./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:43:43,540 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:43:43,658 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:43:43,665 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:43:43,666 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:43:43,704 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:43:43,705 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:43:43,706 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:43:43,707 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:43:43,712 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:43:43,713 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:43:43,713 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:43:43,714 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:43:43,716 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:43:43,717 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:43:43,717 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:43:43,718 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:43:43,718 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:43:43,718 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:43:43,719 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:43:43,719 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:43:43,720 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:43:43,720 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:43:43,721 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:43:43,721 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:43:43,722 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:43:43,722 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:43:43,722 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:43:43,723 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:43:43,723 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:43:43,724 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:43:43,725 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:43:43,725 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:43:43,725 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:43:43,726 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:43:43,726 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:43:43,726 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:43:43,727 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:43:43,727 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 [2023-11-26 11:43:44,055 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:43:44,082 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:43:44,090 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:43:44,092 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:43:44,093 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:43:44,094 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2023-11-26 11:43:47,309 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:43:47,623 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:43:47,626 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2023-11-26 11:43:47,643 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/data/25aadc052/b7fd2124696b4e59aae963f4bcc304a6/FLAGf1affd1ca [2023-11-26 11:43:47,664 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/data/25aadc052/b7fd2124696b4e59aae963f4bcc304a6 [2023-11-26 11:43:47,669 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:43:47,672 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:43:47,676 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:43:47,676 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:43:47,681 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:43:47,682 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:43:47" (1/1) ... [2023-11-26 11:43:47,683 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7472a88e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:47, skipping insertion in model container [2023-11-26 11:43:47,684 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:43:47" (1/1) ... [2023-11-26 11:43:47,753 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:43:48,096 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:43:48,116 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:43:48,199 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:43:48,221 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:43:48,221 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48 WrapperNode [2023-11-26 11:43:48,222 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:43:48,223 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:43:48,223 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:43:48,223 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:43:48,233 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,245 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,334 INFO L138 Inliner]: procedures = 40, calls = 51, calls flagged for inlining = 46, calls inlined = 116, statements flattened = 1679 [2023-11-26 11:43:48,335 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:43:48,336 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:43:48,336 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:43:48,336 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:43:48,350 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,362 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,374 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,435 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 11:43:48,435 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,436 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,480 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,516 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,520 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,547 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,556 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:43:48,557 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:43:48,558 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:43:48,558 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:43:48,577 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (1/1) ... [2023-11-26 11:43:48,583 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:43:48,604 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:43:48,617 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:43:48,662 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:43:48,687 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:43:48,687 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:43:48,688 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:43:48,688 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:43:48,825 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:43:48,828 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:43:50,391 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:43:50,428 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:43:50,428 INFO L309 CfgBuilder]: Removed 9 assume(true) statements. [2023-11-26 11:43:50,430 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:43:50 BoogieIcfgContainer [2023-11-26 11:43:50,431 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:43:50,432 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:43:50,432 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:43:50,436 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:43:50,437 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:43:50,437 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:43:47" (1/3) ... [2023-11-26 11:43:50,439 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4dc2ba6d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:43:50, skipping insertion in model container [2023-11-26 11:43:50,439 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:43:50,440 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:43:48" (2/3) ... [2023-11-26 11:43:50,442 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4dc2ba6d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:43:50, skipping insertion in model container [2023-11-26 11:43:50,442 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:43:50,443 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:43:50" (3/3) ... [2023-11-26 11:43:50,444 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-1.c [2023-11-26 11:43:50,527 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:43:50,527 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:43:50,527 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:43:50,528 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:43:50,528 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:43:50,528 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:43:50,528 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:43:50,529 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:43:50,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:50,621 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 608 [2023-11-26 11:43:50,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:50,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:50,643 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:50,643 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:50,644 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:43:50,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:50,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 608 [2023-11-26 11:43:50,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:50,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:50,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:50,675 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:50,691 INFO L748 eck$LassoCheckResult]: Stem: 199#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 569#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 333#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 564#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 523#L487true assume !(1 == ~m_i~0);~m_st~0 := 2; 129#L487-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 268#L492-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 40#L497-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 149#L502-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 29#L507-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 115#L512-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 540#L517-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222#L696true assume !(0 == ~M_E~0); 534#L696-2true assume !(0 == ~T1_E~0); 537#L701-1true assume !(0 == ~T2_E~0); 567#L706-1true assume !(0 == ~T3_E~0); 305#L711-1true assume !(0 == ~T4_E~0); 151#L716-1true assume !(0 == ~T5_E~0); 587#L721-1true assume !(0 == ~T6_E~0); 273#L726-1true assume 0 == ~E_M~0;~E_M~0 := 1; 476#L731-1true assume !(0 == ~E_1~0); 247#L736-1true assume !(0 == ~E_2~0); 317#L741-1true assume !(0 == ~E_3~0); 626#L746-1true assume !(0 == ~E_4~0); 169#L751-1true assume !(0 == ~E_5~0); 232#L756-1true assume !(0 == ~E_6~0); 148#L761-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51#L346true assume !(1 == ~m_pc~0); 179#L346-2true is_master_triggered_~__retres1~0#1 := 0; 420#L357true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 553#L861true assume !(0 != activate_threads_~tmp~1#1); 475#L861-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69#L365true assume 1 == ~t1_pc~0; 138#L366true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 518#L376true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64#L869true assume !(0 != activate_threads_~tmp___0~0#1); 371#L869-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 502#L384true assume !(1 == ~t2_pc~0); 367#L384-2true is_transmit2_triggered_~__retres1~2#1 := 0; 628#L395true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24#L877true assume !(0 != activate_threads_~tmp___1~0#1); 236#L877-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233#L403true assume 1 == ~t3_pc~0; 152#L404true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 681#L414true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 416#L885true assume !(0 != activate_threads_~tmp___2~0#1); 226#L885-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 524#L422true assume 1 == ~t4_pc~0; 22#L423true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 438#L433true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 451#L893true assume !(0 != activate_threads_~tmp___3~0#1); 291#L893-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30#L441true assume !(1 == ~t5_pc~0); 469#L441-2true is_transmit5_triggered_~__retres1~5#1 := 0; 616#L452true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 181#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 698#L901true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 297#L901-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 424#L460true assume 1 == ~t6_pc~0; 4#L461true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33#L471true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 319#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 421#L909true assume !(0 != activate_threads_~tmp___5~0#1); 550#L909-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280#L774true assume !(1 == ~M_E~0); 592#L774-2true assume !(1 == ~T1_E~0); 442#L779-1true assume !(1 == ~T2_E~0); 210#L784-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 588#L789-1true assume !(1 == ~T4_E~0); 60#L794-1true assume !(1 == ~T5_E~0); 667#L799-1true assume !(1 == ~T6_E~0); 602#L804-1true assume !(1 == ~E_M~0); 659#L809-1true assume !(1 == ~E_1~0); 270#L814-1true assume !(1 == ~E_2~0); 12#L819-1true assume !(1 == ~E_3~0); 325#L824-1true assume 1 == ~E_4~0;~E_4~0 := 2; 649#L829-1true assume !(1 == ~E_5~0); 429#L834-1true assume !(1 == ~E_6~0); 139#L839-1true assume { :end_inline_reset_delta_events } true; 131#L1065-2true [2023-11-26 11:43:50,697 INFO L750 eck$LassoCheckResult]: Loop: 131#L1065-2true assume !false; 341#L1066true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 397#L671-1true assume false; 105#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 489#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163#L696-3true assume 0 == ~M_E~0;~M_E~0 := 1; 582#L696-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 198#L701-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 673#L706-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 548#L711-3true assume !(0 == ~T4_E~0); 535#L716-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 321#L721-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 184#L726-3true assume 0 == ~E_M~0;~E_M~0 := 1; 309#L731-3true assume 0 == ~E_1~0;~E_1~0 := 1; 511#L736-3true assume 0 == ~E_2~0;~E_2~0 := 1; 310#L741-3true assume 0 == ~E_3~0;~E_3~0 := 1; 145#L746-3true assume 0 == ~E_4~0;~E_4~0 := 1; 228#L751-3true assume !(0 == ~E_5~0); 430#L756-3true assume 0 == ~E_6~0;~E_6~0 := 1; 73#L761-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91#L346-24true assume 1 == ~m_pc~0; 413#L347-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 311#L357-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 500#L861-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 439#L861-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111#L365-24true assume 1 == ~t1_pc~0; 322#L366-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 655#L376-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 527#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 392#L869-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 586#L869-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83#L384-24true assume !(1 == ~t2_pc~0); 94#L384-26true is_transmit2_triggered_~__retres1~2#1 := 0; 640#L395-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 675#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 301#L877-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99#L877-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171#L403-24true assume 1 == ~t3_pc~0; 627#L404-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 200#L414-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 370#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 266#L885-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 577#L885-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130#L422-24true assume 1 == ~t4_pc~0; 574#L423-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 104#L433-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 481#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 539#L893-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 448#L893-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 140#L441-24true assume !(1 == ~t5_pc~0); 292#L441-26true is_transmit5_triggered_~__retres1~5#1 := 0; 286#L452-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 243#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65#L901-24true assume !(0 != activate_threads_~tmp___4~0#1); 378#L901-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 374#L460-24true assume 1 == ~t6_pc~0; 590#L461-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 687#L471-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 468#L909-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 368#L909-26true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 636#L774-3true assume !(1 == ~M_E~0); 298#L774-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 183#L779-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 23#L784-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 686#L789-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 13#L794-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 70#L799-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 284#L804-3true assume 1 == ~E_M~0;~E_M~0 := 2; 521#L809-3true assume !(1 == ~E_1~0); 68#L814-3true assume 1 == ~E_2~0;~E_2~0 := 2; 221#L819-3true assume 1 == ~E_3~0;~E_3~0 := 2; 156#L824-3true assume 1 == ~E_4~0;~E_4~0 := 2; 144#L829-3true assume 1 == ~E_5~0;~E_5~0 := 2; 346#L834-3true assume 1 == ~E_6~0;~E_6~0 := 2; 59#L839-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 452#L530-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 109#L567-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 290#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 28#L1084true assume !(0 == start_simulation_~tmp~3#1); 492#L1084-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 167#L530-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80#L567-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 42#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 170#L1039true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76#L1046true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 501#stop_simulation_returnLabel#1true start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 175#L1097true assume !(0 != start_simulation_~tmp___0~1#1); 131#L1065-2true [2023-11-26 11:43:50,705 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:50,705 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2023-11-26 11:43:50,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:50,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019558309] [2023-11-26 11:43:50,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:50,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:50,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:51,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:51,094 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:51,094 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019558309] [2023-11-26 11:43:51,095 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1019558309] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:51,095 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:51,096 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:51,098 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382736847] [2023-11-26 11:43:51,098 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:51,104 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:51,105 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:51,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1343600868, now seen corresponding path program 1 times [2023-11-26 11:43:51,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:51,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129453934] [2023-11-26 11:43:51,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:51,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:51,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:51,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:51,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:51,204 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [129453934] [2023-11-26 11:43:51,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [129453934] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:51,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:51,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:43:51,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004993106] [2023-11-26 11:43:51,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:51,207 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:51,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:51,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:51,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:51,256 INFO L87 Difference]: Start difference. First operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:51,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:51,357 INFO L93 Difference]: Finished difference Result 699 states and 1041 transitions. [2023-11-26 11:43:51,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 699 states and 1041 transitions. [2023-11-26 11:43:51,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:51,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 699 states to 693 states and 1035 transitions. [2023-11-26 11:43:51,398 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-26 11:43:51,401 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-26 11:43:51,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1035 transitions. [2023-11-26 11:43:51,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:51,415 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1035 transitions. [2023-11-26 11:43:51,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1035 transitions. [2023-11-26 11:43:51,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-26 11:43:51,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4935064935064934) internal successors, (1035), 692 states have internal predecessors, (1035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:51,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1035 transitions. [2023-11-26 11:43:51,514 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1035 transitions. [2023-11-26 11:43:51,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:51,519 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1035 transitions. [2023-11-26 11:43:51,520 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:43:51,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1035 transitions. [2023-11-26 11:43:51,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:51,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:51,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:51,534 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:51,535 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:51,535 INFO L748 eck$LassoCheckResult]: Stem: 1771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1931#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1932#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2069#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1668#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1669#L492-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1500#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1501#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1473#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1474#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1642#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1802#L696 assume !(0 == ~M_E~0); 1803#L696-2 assume !(0 == ~T1_E~0); 2072#L701-1 assume !(0 == ~T2_E~0); 2075#L706-1 assume !(0 == ~T3_E~0); 1910#L711-1 assume !(0 == ~T4_E~0); 1703#L716-1 assume !(0 == ~T5_E~0); 1704#L721-1 assume !(0 == ~T6_E~0); 1868#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1869#L731-1 assume !(0 == ~E_1~0); 1838#L736-1 assume !(0 == ~E_2~0); 1839#L741-1 assume !(0 == ~E_3~0); 1919#L746-1 assume !(0 == ~E_4~0); 1728#L751-1 assume !(0 == ~E_5~0); 1729#L756-1 assume !(0 == ~E_6~0); 1700#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1521#L346 assume !(1 == ~m_pc~0); 1522#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1742#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1734#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1735#L861 assume !(0 != activate_threads_~tmp~1#1); 2051#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1554#L365 assume 1 == ~t1_pc~0; 1555#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1689#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1507#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1508#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1543#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1966#L384 assume !(1 == ~t2_pc~0); 1962#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1963#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1937#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1463#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1464#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1818#L403 assume 1 == ~t3_pc~0; 1705#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1706#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1431#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1432#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1813#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1814#L422 assume 1 == ~t4_pc~0; 1458#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1459#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1606#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1607#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1889#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1475#L441 assume !(1 == ~t5_pc~0); 1476#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2048#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1745#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1746#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1899#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1900#L460 assume 1 == ~t6_pc~0; 1419#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1420#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1483#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1921#L909 assume !(0 != activate_threads_~tmp___5~0#1); 2010#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1877#L774 assume !(1 == ~M_E~0); 1878#L774-2 assume !(1 == ~T1_E~0); 2027#L779-1 assume !(1 == ~T2_E~0); 1788#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1789#L789-1 assume !(1 == ~T4_E~0); 1538#L794-1 assume !(1 == ~T5_E~0); 1539#L799-1 assume !(1 == ~T6_E~0); 2092#L804-1 assume !(1 == ~E_M~0); 2093#L809-1 assume !(1 == ~E_1~0); 1866#L814-1 assume !(1 == ~E_2~0); 1437#L819-1 assume !(1 == ~E_3~0); 1438#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1927#L829-1 assume !(1 == ~E_5~0); 2017#L834-1 assume !(1 == ~E_6~0); 1690#L839-1 assume { :end_inline_reset_delta_events } true; 1673#L1065-2 [2023-11-26 11:43:51,536 INFO L750 eck$LassoCheckResult]: Loop: 1673#L1065-2 assume !false; 1674#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1645#L671-1 assume !false; 1995#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1997#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1510#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1524#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1954#L582 assume !(0 != eval_~tmp~0#1); 1622#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1719#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1720#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1767#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1768#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2079#L711-3 assume !(0 == ~T4_E~0); 2073#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1923#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1749#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1750#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1915#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1916#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1697#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1698#L751-3 assume !(0 == ~E_5~0); 1815#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1561#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1562#L346-24 assume 1 == ~m_pc~0; 1600#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1693#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1640#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1641#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2025#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1632#L365-24 assume 1 == ~t1_pc~0; 1633#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1922#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2070#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1986#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1987#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1579#L384-24 assume !(1 == ~t2_pc~0); 1580#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1601#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2100#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1906#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1611#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1612#L403-24 assume 1 == ~t3_pc~0; 1730#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1769#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1770#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1863#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1864#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1670#L422-24 assume 1 == ~t4_pc~0; 1671#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1617#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1618#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2054#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2033#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1686#L441-24 assume !(1 == ~t5_pc~0); 1687#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1882#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1834#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1544#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 1545#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1967#L460-24 assume 1 == ~t6_pc~0; 1968#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2028#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1726#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1727#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1960#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1961#L774-3 assume !(1 == ~M_E~0); 1898#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1748#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1457#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1435#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1436#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1553#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1881#L809-3 assume !(1 == ~E_1~0); 1551#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1552#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1711#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1695#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1696#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1536#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1537#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1534#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1628#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1470#L1084 assume !(0 == start_simulation_~tmp~3#1); 1471#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1724#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1440#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1498#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1499#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1566#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1567#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1736#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1673#L1065-2 [2023-11-26 11:43:51,537 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:51,537 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2023-11-26 11:43:51,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:51,537 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277366243] [2023-11-26 11:43:51,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:51,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:51,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:51,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:51,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:51,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277366243] [2023-11-26 11:43:51,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277366243] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:51,652 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:51,652 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:51,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2092544301] [2023-11-26 11:43:51,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:51,653 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:51,653 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:51,654 INFO L85 PathProgramCache]: Analyzing trace with hash -1334440743, now seen corresponding path program 1 times [2023-11-26 11:43:51,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:51,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734633313] [2023-11-26 11:43:51,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:51,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:51,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:51,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:51,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:51,816 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [734633313] [2023-11-26 11:43:51,817 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [734633313] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:51,817 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:51,817 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:51,817 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906275385] [2023-11-26 11:43:51,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:51,818 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:51,819 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:51,819 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:51,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:51,820 INFO L87 Difference]: Start difference. First operand 693 states and 1035 transitions. cyclomatic complexity: 343 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:51,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:51,856 INFO L93 Difference]: Finished difference Result 693 states and 1034 transitions. [2023-11-26 11:43:51,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1034 transitions. [2023-11-26 11:43:51,866 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:51,876 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1034 transitions. [2023-11-26 11:43:51,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-26 11:43:51,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-26 11:43:51,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1034 transitions. [2023-11-26 11:43:51,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:51,880 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1034 transitions. [2023-11-26 11:43:51,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1034 transitions. [2023-11-26 11:43:51,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-26 11:43:51,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.492063492063492) internal successors, (1034), 692 states have internal predecessors, (1034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:51,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1034 transitions. [2023-11-26 11:43:51,917 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1034 transitions. [2023-11-26 11:43:51,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:51,919 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1034 transitions. [2023-11-26 11:43:51,920 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:43:51,920 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1034 transitions. [2023-11-26 11:43:51,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:51,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:51,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:51,940 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:51,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:51,943 INFO L748 eck$LassoCheckResult]: Stem: 3162#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3325#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3462#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 3061#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3062#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2889#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2890#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2866#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2867#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3035#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3195#L696 assume !(0 == ~M_E~0); 3196#L696-2 assume !(0 == ~T1_E~0); 3465#L701-1 assume !(0 == ~T2_E~0); 3467#L706-1 assume !(0 == ~T3_E~0); 3303#L711-1 assume !(0 == ~T4_E~0); 3096#L716-1 assume !(0 == ~T5_E~0); 3097#L721-1 assume !(0 == ~T6_E~0); 3261#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3262#L731-1 assume !(0 == ~E_1~0); 3231#L736-1 assume !(0 == ~E_2~0); 3232#L741-1 assume !(0 == ~E_3~0); 3312#L746-1 assume !(0 == ~E_4~0); 3121#L751-1 assume !(0 == ~E_5~0); 3122#L756-1 assume !(0 == ~E_6~0); 3093#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2912#L346 assume !(1 == ~m_pc~0); 2913#L346-2 is_master_triggered_~__retres1~0#1 := 0; 3135#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3127#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3128#L861 assume !(0 != activate_threads_~tmp~1#1); 3444#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2946#L365 assume 1 == ~t1_pc~0; 2947#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3079#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2895#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2896#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2936#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3359#L384 assume !(1 == ~t2_pc~0); 3353#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3354#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3326#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2854#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2855#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3210#L403 assume 1 == ~t3_pc~0; 3098#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3099#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2824#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2825#L885 assume !(0 != activate_threads_~tmp___2~0#1); 3203#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3204#L422 assume 1 == ~t4_pc~0; 2849#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2850#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2999#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3000#L893 assume !(0 != activate_threads_~tmp___3~0#1); 3282#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2868#L441 assume !(1 == ~t5_pc~0); 2869#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3440#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3138#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3139#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3291#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3292#L460 assume 1 == ~t6_pc~0; 2809#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2810#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2876#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3314#L909 assume !(0 != activate_threads_~tmp___5~0#1); 3403#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3270#L774 assume !(1 == ~M_E~0); 3271#L774-2 assume !(1 == ~T1_E~0); 3420#L779-1 assume !(1 == ~T2_E~0); 3181#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3182#L789-1 assume !(1 == ~T4_E~0); 2931#L794-1 assume !(1 == ~T5_E~0); 2932#L799-1 assume !(1 == ~T6_E~0); 3485#L804-1 assume !(1 == ~E_M~0); 3486#L809-1 assume !(1 == ~E_1~0); 3258#L814-1 assume !(1 == ~E_2~0); 2828#L819-1 assume !(1 == ~E_3~0); 2829#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3320#L829-1 assume !(1 == ~E_5~0); 3410#L834-1 assume !(1 == ~E_6~0); 3080#L839-1 assume { :end_inline_reset_delta_events } true; 3066#L1065-2 [2023-11-26 11:43:51,944 INFO L750 eck$LassoCheckResult]: Loop: 3066#L1065-2 assume !false; 3067#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3038#L671-1 assume !false; 3385#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3390#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2903#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2917#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3346#L582 assume !(0 != eval_~tmp~0#1); 3013#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3014#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3112#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3113#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3160#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3161#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3472#L711-3 assume !(0 == ~T4_E~0); 3466#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3315#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3142#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3143#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3308#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3309#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3090#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3091#L751-3 assume !(0 == ~E_5~0); 3208#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2954#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2955#L346-24 assume !(1 == ~m_pc~0); 2989#L346-26 is_master_triggered_~__retres1~0#1 := 0; 3086#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3033#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3034#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3418#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3025#L365-24 assume 1 == ~t1_pc~0; 3026#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3316#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3463#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3381#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3382#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2974#L384-24 assume 1 == ~t2_pc~0; 2976#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2996#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3493#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3299#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3005#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3006#L403-24 assume 1 == ~t3_pc~0; 3123#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3164#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3165#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3256#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3257#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3063#L422-24 assume 1 == ~t4_pc~0; 3064#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3011#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3012#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3447#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3426#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3081#L441-24 assume !(1 == ~t5_pc~0); 3082#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 3276#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3227#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2937#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 2938#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3360#L460-24 assume 1 == ~t6_pc~0; 3361#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3421#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3119#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3120#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3355#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3356#L774-3 assume !(1 == ~M_E~0); 3293#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3141#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2852#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2853#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2830#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2831#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2949#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3274#L809-3 assume !(1 == ~E_1~0); 2944#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2945#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3104#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3088#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3089#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2929#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2930#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2927#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3021#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2863#L1084 assume !(0 == start_simulation_~tmp~3#1); 2864#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3117#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2833#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2894#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2960#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2961#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3129#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 3066#L1065-2 [2023-11-26 11:43:51,945 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:51,945 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2023-11-26 11:43:51,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:51,946 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55916500] [2023-11-26 11:43:51,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:51,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:51,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:52,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:52,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:52,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55916500] [2023-11-26 11:43:52,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55916500] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:52,030 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:52,030 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:52,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16520344] [2023-11-26 11:43:52,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:52,031 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:52,031 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:52,032 INFO L85 PathProgramCache]: Analyzing trace with hash -437079207, now seen corresponding path program 1 times [2023-11-26 11:43:52,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:52,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810358042] [2023-11-26 11:43:52,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:52,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:52,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:52,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:52,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:52,164 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810358042] [2023-11-26 11:43:52,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [810358042] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:52,165 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:52,165 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:52,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1726491076] [2023-11-26 11:43:52,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:52,166 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:52,166 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:52,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:52,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:52,167 INFO L87 Difference]: Start difference. First operand 693 states and 1034 transitions. cyclomatic complexity: 342 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:52,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:52,189 INFO L93 Difference]: Finished difference Result 693 states and 1033 transitions. [2023-11-26 11:43:52,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1033 transitions. [2023-11-26 11:43:52,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:52,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1033 transitions. [2023-11-26 11:43:52,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-26 11:43:52,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-26 11:43:52,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1033 transitions. [2023-11-26 11:43:52,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:52,206 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1033 transitions. [2023-11-26 11:43:52,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1033 transitions. [2023-11-26 11:43:52,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-26 11:43:52,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4906204906204905) internal successors, (1033), 692 states have internal predecessors, (1033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:52,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1033 transitions. [2023-11-26 11:43:52,225 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1033 transitions. [2023-11-26 11:43:52,225 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:52,227 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1033 transitions. [2023-11-26 11:43:52,227 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:43:52,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1033 transitions. [2023-11-26 11:43:52,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:52,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:52,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:52,242 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:52,242 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:52,243 INFO L748 eck$LassoCheckResult]: Stem: 4555#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4556#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4717#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4718#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4855#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 4454#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4455#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4284#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4285#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4259#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4260#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4428#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4588#L696 assume !(0 == ~M_E~0); 4589#L696-2 assume !(0 == ~T1_E~0); 4858#L701-1 assume !(0 == ~T2_E~0); 4860#L706-1 assume !(0 == ~T3_E~0); 4696#L711-1 assume !(0 == ~T4_E~0); 4489#L716-1 assume !(0 == ~T5_E~0); 4490#L721-1 assume !(0 == ~T6_E~0); 4654#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4655#L731-1 assume !(0 == ~E_1~0); 4624#L736-1 assume !(0 == ~E_2~0); 4625#L741-1 assume !(0 == ~E_3~0); 4705#L746-1 assume !(0 == ~E_4~0); 4514#L751-1 assume !(0 == ~E_5~0); 4515#L756-1 assume !(0 == ~E_6~0); 4486#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4305#L346 assume !(1 == ~m_pc~0); 4306#L346-2 is_master_triggered_~__retres1~0#1 := 0; 4528#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4520#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4521#L861 assume !(0 != activate_threads_~tmp~1#1); 4837#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4340#L365 assume 1 == ~t1_pc~0; 4341#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4472#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4288#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4289#L869 assume !(0 != activate_threads_~tmp___0~0#1); 4329#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4752#L384 assume !(1 == ~t2_pc~0); 4746#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4747#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4247#L877 assume !(0 != activate_threads_~tmp___1~0#1); 4248#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4603#L403 assume 1 == ~t3_pc~0; 4491#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4492#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4217#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4218#L885 assume !(0 != activate_threads_~tmp___2~0#1); 4596#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4597#L422 assume 1 == ~t4_pc~0; 4244#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4245#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4392#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4393#L893 assume !(0 != activate_threads_~tmp___3~0#1); 4675#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4261#L441 assume !(1 == ~t5_pc~0); 4262#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4833#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4531#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4532#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4684#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4685#L460 assume 1 == ~t6_pc~0; 4202#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4203#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4269#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4707#L909 assume !(0 != activate_threads_~tmp___5~0#1); 4796#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4663#L774 assume !(1 == ~M_E~0); 4664#L774-2 assume !(1 == ~T1_E~0); 4813#L779-1 assume !(1 == ~T2_E~0); 4574#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4575#L789-1 assume !(1 == ~T4_E~0); 4324#L794-1 assume !(1 == ~T5_E~0); 4325#L799-1 assume !(1 == ~T6_E~0); 4878#L804-1 assume !(1 == ~E_M~0); 4879#L809-1 assume !(1 == ~E_1~0); 4651#L814-1 assume !(1 == ~E_2~0); 4223#L819-1 assume !(1 == ~E_3~0); 4224#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4713#L829-1 assume !(1 == ~E_5~0); 4803#L834-1 assume !(1 == ~E_6~0); 4473#L839-1 assume { :end_inline_reset_delta_events } true; 4459#L1065-2 [2023-11-26 11:43:52,243 INFO L750 eck$LassoCheckResult]: Loop: 4459#L1065-2 assume !false; 4460#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4431#L671-1 assume !false; 4778#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4783#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4296#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4310#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4739#L582 assume !(0 != eval_~tmp~0#1); 4406#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4407#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4505#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4506#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4553#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4554#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4865#L711-3 assume !(0 == ~T4_E~0); 4859#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4708#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4535#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4536#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4701#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4702#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4483#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4484#L751-3 assume !(0 == ~E_5~0); 4601#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4347#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4348#L346-24 assume !(1 == ~m_pc~0); 4382#L346-26 is_master_triggered_~__retres1~0#1 := 0; 4479#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4426#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4427#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4811#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4420#L365-24 assume 1 == ~t1_pc~0; 4421#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4709#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4856#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4774#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4775#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4369#L384-24 assume !(1 == ~t2_pc~0); 4370#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 4389#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4886#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4692#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4398#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4399#L403-24 assume 1 == ~t3_pc~0; 4516#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4557#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4558#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4649#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4650#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4456#L422-24 assume 1 == ~t4_pc~0; 4457#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4404#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4405#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4840#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4819#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4474#L441-24 assume !(1 == ~t5_pc~0); 4475#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 4669#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4620#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4330#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 4331#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4753#L460-24 assume 1 == ~t6_pc~0; 4754#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4814#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4512#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4513#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4748#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4749#L774-3 assume !(1 == ~M_E~0); 4686#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4534#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4242#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4243#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4221#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4222#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4339#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4667#L809-3 assume !(1 == ~E_1~0); 4332#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4333#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4495#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4480#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4481#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4322#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4323#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4320#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4414#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4256#L1084 assume !(0 == start_simulation_~tmp~3#1); 4257#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4510#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4226#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4282#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4283#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4349#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4350#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4522#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 4459#L1065-2 [2023-11-26 11:43:52,244 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:52,244 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2023-11-26 11:43:52,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:52,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459687083] [2023-11-26 11:43:52,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:52,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:52,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:52,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:52,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:52,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459687083] [2023-11-26 11:43:52,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1459687083] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:52,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:52,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:52,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819770672] [2023-11-26 11:43:52,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:52,292 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:52,292 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:52,292 INFO L85 PathProgramCache]: Analyzing trace with hash -196811878, now seen corresponding path program 1 times [2023-11-26 11:43:52,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:52,293 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820562281] [2023-11-26 11:43:52,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:52,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:52,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:52,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:52,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:52,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820562281] [2023-11-26 11:43:52,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1820562281] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:52,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:52,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:52,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655682633] [2023-11-26 11:43:52,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:52,379 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:52,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:52,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:52,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:52,380 INFO L87 Difference]: Start difference. First operand 693 states and 1033 transitions. cyclomatic complexity: 341 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:52,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:52,404 INFO L93 Difference]: Finished difference Result 693 states and 1032 transitions. [2023-11-26 11:43:52,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1032 transitions. [2023-11-26 11:43:52,411 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:52,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1032 transitions. [2023-11-26 11:43:52,418 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-26 11:43:52,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-26 11:43:52,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1032 transitions. [2023-11-26 11:43:52,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:52,420 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1032 transitions. [2023-11-26 11:43:52,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1032 transitions. [2023-11-26 11:43:52,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-26 11:43:52,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4891774891774892) internal successors, (1032), 692 states have internal predecessors, (1032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:52,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1032 transitions. [2023-11-26 11:43:52,443 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1032 transitions. [2023-11-26 11:43:52,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:52,445 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1032 transitions. [2023-11-26 11:43:52,446 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:43:52,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1032 transitions. [2023-11-26 11:43:52,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:52,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:52,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:52,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:52,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:52,455 INFO L748 eck$LassoCheckResult]: Stem: 5950#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5951#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6110#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6111#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6248#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 5847#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5848#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5679#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5680#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5652#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5653#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5821#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5981#L696 assume !(0 == ~M_E~0); 5982#L696-2 assume !(0 == ~T1_E~0); 6251#L701-1 assume !(0 == ~T2_E~0); 6254#L706-1 assume !(0 == ~T3_E~0); 6089#L711-1 assume !(0 == ~T4_E~0); 5882#L716-1 assume !(0 == ~T5_E~0); 5883#L721-1 assume !(0 == ~T6_E~0); 6047#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6048#L731-1 assume !(0 == ~E_1~0); 6017#L736-1 assume !(0 == ~E_2~0); 6018#L741-1 assume !(0 == ~E_3~0); 6098#L746-1 assume !(0 == ~E_4~0); 5907#L751-1 assume !(0 == ~E_5~0); 5908#L756-1 assume !(0 == ~E_6~0); 5879#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5700#L346 assume !(1 == ~m_pc~0); 5701#L346-2 is_master_triggered_~__retres1~0#1 := 0; 5921#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5913#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5914#L861 assume !(0 != activate_threads_~tmp~1#1); 6230#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5733#L365 assume 1 == ~t1_pc~0; 5734#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5868#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5686#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5687#L869 assume !(0 != activate_threads_~tmp___0~0#1); 5722#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6145#L384 assume !(1 == ~t2_pc~0); 6141#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6142#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6116#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5642#L877 assume !(0 != activate_threads_~tmp___1~0#1); 5643#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5997#L403 assume 1 == ~t3_pc~0; 5884#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5885#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5610#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5611#L885 assume !(0 != activate_threads_~tmp___2~0#1); 5992#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5993#L422 assume 1 == ~t4_pc~0; 5637#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5638#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5785#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5786#L893 assume !(0 != activate_threads_~tmp___3~0#1); 6068#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5654#L441 assume !(1 == ~t5_pc~0); 5655#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6227#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5925#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5926#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6078#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6079#L460 assume 1 == ~t6_pc~0; 5598#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5599#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5662#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6100#L909 assume !(0 != activate_threads_~tmp___5~0#1); 6189#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6056#L774 assume !(1 == ~M_E~0); 6057#L774-2 assume !(1 == ~T1_E~0); 6206#L779-1 assume !(1 == ~T2_E~0); 5967#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5968#L789-1 assume !(1 == ~T4_E~0); 5717#L794-1 assume !(1 == ~T5_E~0); 5718#L799-1 assume !(1 == ~T6_E~0); 6271#L804-1 assume !(1 == ~E_M~0); 6272#L809-1 assume !(1 == ~E_1~0); 6045#L814-1 assume !(1 == ~E_2~0); 5616#L819-1 assume !(1 == ~E_3~0); 5617#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6106#L829-1 assume !(1 == ~E_5~0); 6196#L834-1 assume !(1 == ~E_6~0); 5869#L839-1 assume { :end_inline_reset_delta_events } true; 5856#L1065-2 [2023-11-26 11:43:52,455 INFO L750 eck$LassoCheckResult]: Loop: 5856#L1065-2 assume !false; 5857#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5824#L671-1 assume !false; 6175#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6176#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5689#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5703#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6133#L582 assume !(0 != eval_~tmp~0#1); 5801#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5802#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5898#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5899#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5946#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5947#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6258#L711-3 assume !(0 == ~T4_E~0); 6252#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6102#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5928#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5929#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6094#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6095#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5876#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5877#L751-3 assume !(0 == ~E_5~0); 5994#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5740#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5741#L346-24 assume 1 == ~m_pc~0; 5776#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5870#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5819#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5820#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6204#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5811#L365-24 assume 1 == ~t1_pc~0; 5812#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6101#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6249#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6167#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6168#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5760#L384-24 assume !(1 == ~t2_pc~0); 5761#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 5782#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6279#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6085#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5791#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5792#L403-24 assume 1 == ~t3_pc~0; 5909#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5948#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5949#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6042#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6043#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5849#L422-24 assume 1 == ~t4_pc~0; 5850#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5796#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5797#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6233#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6212#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5865#L441-24 assume !(1 == ~t5_pc~0); 5866#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 6061#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6013#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5723#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 5724#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6146#L460-24 assume 1 == ~t6_pc~0; 6147#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6207#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5905#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5906#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6139#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6140#L774-3 assume !(1 == ~M_E~0); 6077#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5927#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5635#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5636#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5614#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5615#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5732#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6060#L809-3 assume !(1 == ~E_1~0); 5730#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5731#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5890#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5874#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5875#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5715#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5716#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5713#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5807#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5649#L1084 assume !(0 == start_simulation_~tmp~3#1); 5650#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5903#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5619#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5677#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5678#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5746#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5747#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5915#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 5856#L1065-2 [2023-11-26 11:43:52,456 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:52,456 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2023-11-26 11:43:52,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:52,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341922867] [2023-11-26 11:43:52,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:52,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:52,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:52,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:52,514 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:52,515 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [341922867] [2023-11-26 11:43:52,515 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [341922867] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:52,516 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:52,516 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:52,516 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093674577] [2023-11-26 11:43:52,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:52,517 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:52,517 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:52,517 INFO L85 PathProgramCache]: Analyzing trace with hash -1334440743, now seen corresponding path program 2 times [2023-11-26 11:43:52,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:52,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083142205] [2023-11-26 11:43:52,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:52,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:52,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:52,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:52,578 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:52,578 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083142205] [2023-11-26 11:43:52,578 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2083142205] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:52,579 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:52,579 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:52,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968045569] [2023-11-26 11:43:52,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:52,579 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:52,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:52,580 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:52,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:52,581 INFO L87 Difference]: Start difference. First operand 693 states and 1032 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:52,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:52,603 INFO L93 Difference]: Finished difference Result 693 states and 1031 transitions. [2023-11-26 11:43:52,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1031 transitions. [2023-11-26 11:43:52,610 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:52,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1031 transitions. [2023-11-26 11:43:52,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-26 11:43:52,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-26 11:43:52,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1031 transitions. [2023-11-26 11:43:52,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:52,619 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1031 transitions. [2023-11-26 11:43:52,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1031 transitions. [2023-11-26 11:43:52,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-26 11:43:52,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4877344877344878) internal successors, (1031), 692 states have internal predecessors, (1031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:52,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1031 transitions. [2023-11-26 11:43:52,637 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1031 transitions. [2023-11-26 11:43:52,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:52,640 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1031 transitions. [2023-11-26 11:43:52,641 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:43:52,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1031 transitions. [2023-11-26 11:43:52,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:52,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:52,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:52,647 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:52,648 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:52,648 INFO L748 eck$LassoCheckResult]: Stem: 7341#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7503#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7504#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7641#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 7240#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7241#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7068#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7069#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7045#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7046#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7214#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7374#L696 assume !(0 == ~M_E~0); 7375#L696-2 assume !(0 == ~T1_E~0); 7644#L701-1 assume !(0 == ~T2_E~0); 7646#L706-1 assume !(0 == ~T3_E~0); 7482#L711-1 assume !(0 == ~T4_E~0); 7275#L716-1 assume !(0 == ~T5_E~0); 7276#L721-1 assume !(0 == ~T6_E~0); 7440#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7441#L731-1 assume !(0 == ~E_1~0); 7410#L736-1 assume !(0 == ~E_2~0); 7411#L741-1 assume !(0 == ~E_3~0); 7491#L746-1 assume !(0 == ~E_4~0); 7300#L751-1 assume !(0 == ~E_5~0); 7301#L756-1 assume !(0 == ~E_6~0); 7272#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7091#L346 assume !(1 == ~m_pc~0); 7092#L346-2 is_master_triggered_~__retres1~0#1 := 0; 7314#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7306#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7307#L861 assume !(0 != activate_threads_~tmp~1#1); 7623#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7125#L365 assume 1 == ~t1_pc~0; 7126#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7258#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7074#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7075#L869 assume !(0 != activate_threads_~tmp___0~0#1); 7115#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7538#L384 assume !(1 == ~t2_pc~0); 7532#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7533#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7505#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7033#L877 assume !(0 != activate_threads_~tmp___1~0#1); 7034#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7389#L403 assume 1 == ~t3_pc~0; 7277#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7278#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7003#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7004#L885 assume !(0 != activate_threads_~tmp___2~0#1); 7382#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7383#L422 assume 1 == ~t4_pc~0; 7028#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7029#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7178#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7179#L893 assume !(0 != activate_threads_~tmp___3~0#1); 7461#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7047#L441 assume !(1 == ~t5_pc~0); 7048#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7619#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7317#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7318#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7470#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7471#L460 assume 1 == ~t6_pc~0; 6988#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6989#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7055#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7493#L909 assume !(0 != activate_threads_~tmp___5~0#1); 7582#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7449#L774 assume !(1 == ~M_E~0); 7450#L774-2 assume !(1 == ~T1_E~0); 7599#L779-1 assume !(1 == ~T2_E~0); 7360#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7361#L789-1 assume !(1 == ~T4_E~0); 7110#L794-1 assume !(1 == ~T5_E~0); 7111#L799-1 assume !(1 == ~T6_E~0); 7664#L804-1 assume !(1 == ~E_M~0); 7665#L809-1 assume !(1 == ~E_1~0); 7437#L814-1 assume !(1 == ~E_2~0); 7007#L819-1 assume !(1 == ~E_3~0); 7008#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7499#L829-1 assume !(1 == ~E_5~0); 7589#L834-1 assume !(1 == ~E_6~0); 7259#L839-1 assume { :end_inline_reset_delta_events } true; 7245#L1065-2 [2023-11-26 11:43:52,648 INFO L750 eck$LassoCheckResult]: Loop: 7245#L1065-2 assume !false; 7246#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7217#L671-1 assume !false; 7564#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7569#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7082#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7096#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7525#L582 assume !(0 != eval_~tmp~0#1); 7192#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7193#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7291#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7292#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7339#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7340#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7651#L711-3 assume !(0 == ~T4_E~0); 7645#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7494#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7321#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7322#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7487#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7488#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7269#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7270#L751-3 assume !(0 == ~E_5~0); 7387#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7133#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7134#L346-24 assume !(1 == ~m_pc~0); 7168#L346-26 is_master_triggered_~__retres1~0#1 := 0; 7265#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7212#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7213#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7597#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7204#L365-24 assume 1 == ~t1_pc~0; 7205#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7495#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7642#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7560#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7561#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7153#L384-24 assume !(1 == ~t2_pc~0); 7154#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 7175#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7672#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7478#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7184#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7185#L403-24 assume 1 == ~t3_pc~0; 7302#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7343#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7344#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7435#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7436#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7242#L422-24 assume 1 == ~t4_pc~0; 7243#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7190#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7191#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7626#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7605#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7260#L441-24 assume !(1 == ~t5_pc~0); 7261#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 7455#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7406#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7116#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 7117#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7539#L460-24 assume 1 == ~t6_pc~0; 7540#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7600#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7298#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7299#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7534#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7535#L774-3 assume !(1 == ~M_E~0); 7472#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7320#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7031#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7032#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7009#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7010#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7128#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7453#L809-3 assume !(1 == ~E_1~0); 7123#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7124#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7283#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7267#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7268#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7108#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7109#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7106#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7042#L1084 assume !(0 == start_simulation_~tmp~3#1); 7043#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7296#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7012#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7072#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7073#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7139#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7140#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7308#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 7245#L1065-2 [2023-11-26 11:43:52,649 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:52,649 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2023-11-26 11:43:52,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:52,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553663464] [2023-11-26 11:43:52,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:52,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:52,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:52,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:52,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:52,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553663464] [2023-11-26 11:43:52,727 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1553663464] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:52,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:52,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:52,728 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1632607051] [2023-11-26 11:43:52,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:52,729 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:52,729 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:52,729 INFO L85 PathProgramCache]: Analyzing trace with hash -196811878, now seen corresponding path program 2 times [2023-11-26 11:43:52,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:52,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1044076712] [2023-11-26 11:43:52,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:52,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:52,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:52,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:52,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:52,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1044076712] [2023-11-26 11:43:52,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1044076712] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:52,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:52,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:52,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164264667] [2023-11-26 11:43:52,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:52,792 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:52,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:52,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:52,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:52,793 INFO L87 Difference]: Start difference. First operand 693 states and 1031 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:52,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:52,815 INFO L93 Difference]: Finished difference Result 693 states and 1030 transitions. [2023-11-26 11:43:52,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1030 transitions. [2023-11-26 11:43:52,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:52,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1030 transitions. [2023-11-26 11:43:52,829 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-26 11:43:52,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-26 11:43:52,830 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1030 transitions. [2023-11-26 11:43:52,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:52,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1030 transitions. [2023-11-26 11:43:52,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1030 transitions. [2023-11-26 11:43:52,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-26 11:43:52,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4862914862914862) internal successors, (1030), 692 states have internal predecessors, (1030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:52,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1030 transitions. [2023-11-26 11:43:52,849 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1030 transitions. [2023-11-26 11:43:52,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:52,851 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1030 transitions. [2023-11-26 11:43:52,851 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:43:52,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1030 transitions. [2023-11-26 11:43:52,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-26 11:43:52,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:52,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:52,858 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:52,858 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:52,858 INFO L748 eck$LassoCheckResult]: Stem: 8734#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8896#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8897#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9034#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 8633#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8634#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8465#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8466#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8438#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8439#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8607#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8767#L696 assume !(0 == ~M_E~0); 8768#L696-2 assume !(0 == ~T1_E~0); 9037#L701-1 assume !(0 == ~T2_E~0); 9039#L706-1 assume !(0 == ~T3_E~0); 8875#L711-1 assume !(0 == ~T4_E~0); 8668#L716-1 assume !(0 == ~T5_E~0); 8669#L721-1 assume !(0 == ~T6_E~0); 8833#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8834#L731-1 assume !(0 == ~E_1~0); 8803#L736-1 assume !(0 == ~E_2~0); 8804#L741-1 assume !(0 == ~E_3~0); 8884#L746-1 assume !(0 == ~E_4~0); 8693#L751-1 assume !(0 == ~E_5~0); 8694#L756-1 assume !(0 == ~E_6~0); 8665#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8484#L346 assume !(1 == ~m_pc~0); 8485#L346-2 is_master_triggered_~__retres1~0#1 := 0; 8707#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8699#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8700#L861 assume !(0 != activate_threads_~tmp~1#1); 9016#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8519#L365 assume 1 == ~t1_pc~0; 8520#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8654#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8469#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8470#L869 assume !(0 != activate_threads_~tmp___0~0#1); 8508#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8931#L384 assume !(1 == ~t2_pc~0); 8927#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8928#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8898#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8426#L877 assume !(0 != activate_threads_~tmp___1~0#1); 8427#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8782#L403 assume 1 == ~t3_pc~0; 8670#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8671#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8396#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8397#L885 assume !(0 != activate_threads_~tmp___2~0#1); 8775#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8776#L422 assume 1 == ~t4_pc~0; 8423#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8424#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8571#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8572#L893 assume !(0 != activate_threads_~tmp___3~0#1); 8854#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8440#L441 assume !(1 == ~t5_pc~0); 8441#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9012#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8710#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8711#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8864#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8865#L460 assume 1 == ~t6_pc~0; 8381#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8382#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8448#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8886#L909 assume !(0 != activate_threads_~tmp___5~0#1); 8975#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8842#L774 assume !(1 == ~M_E~0); 8843#L774-2 assume !(1 == ~T1_E~0); 8992#L779-1 assume !(1 == ~T2_E~0); 8753#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8754#L789-1 assume !(1 == ~T4_E~0); 8503#L794-1 assume !(1 == ~T5_E~0); 8504#L799-1 assume !(1 == ~T6_E~0); 9057#L804-1 assume !(1 == ~E_M~0); 9058#L809-1 assume !(1 == ~E_1~0); 8830#L814-1 assume !(1 == ~E_2~0); 8402#L819-1 assume !(1 == ~E_3~0); 8403#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8892#L829-1 assume !(1 == ~E_5~0); 8982#L834-1 assume !(1 == ~E_6~0); 8655#L839-1 assume { :end_inline_reset_delta_events } true; 8638#L1065-2 [2023-11-26 11:43:52,859 INFO L750 eck$LassoCheckResult]: Loop: 8638#L1065-2 assume !false; 8639#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8610#L671-1 assume !false; 8957#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8962#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8475#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8489#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8918#L582 assume !(0 != eval_~tmp~0#1); 8585#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8586#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8684#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8685#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8732#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8733#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9044#L711-3 assume !(0 == ~T4_E~0); 9038#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8887#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8714#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8715#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8880#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8881#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8662#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8663#L751-3 assume !(0 == ~E_5~0); 8780#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8526#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8527#L346-24 assume !(1 == ~m_pc~0); 8561#L346-26 is_master_triggered_~__retres1~0#1 := 0; 8658#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8605#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8606#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8990#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8599#L365-24 assume 1 == ~t1_pc~0; 8600#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8888#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9035#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8953#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8954#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8548#L384-24 assume !(1 == ~t2_pc~0); 8549#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 8568#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9065#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8872#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8577#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8578#L403-24 assume 1 == ~t3_pc~0; 8695#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8736#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8737#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8828#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8829#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8635#L422-24 assume 1 == ~t4_pc~0; 8636#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8582#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8583#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9019#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8998#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8651#L441-24 assume !(1 == ~t5_pc~0); 8652#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 8847#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8799#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8509#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 8510#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8932#L460-24 assume 1 == ~t6_pc~0; 8933#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8993#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8691#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8692#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8925#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8926#L774-3 assume !(1 == ~M_E~0); 8863#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8713#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8421#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8422#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8400#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8401#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8518#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8846#L809-3 assume !(1 == ~E_1~0); 8513#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8514#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8674#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8659#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8660#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8501#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8502#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8499#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8593#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8435#L1084 assume !(0 == start_simulation_~tmp~3#1); 8436#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8689#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8405#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8463#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8464#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8528#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8529#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8701#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 8638#L1065-2 [2023-11-26 11:43:52,859 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:52,860 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2023-11-26 11:43:52,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:52,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391608203] [2023-11-26 11:43:52,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:52,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:52,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:52,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:52,937 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:52,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1391608203] [2023-11-26 11:43:52,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1391608203] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:52,938 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:52,938 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:52,938 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467923002] [2023-11-26 11:43:52,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:52,939 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:52,939 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:52,939 INFO L85 PathProgramCache]: Analyzing trace with hash -196811878, now seen corresponding path program 3 times [2023-11-26 11:43:52,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:52,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305769228] [2023-11-26 11:43:52,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:52,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:52,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:52,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:52,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:52,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305769228] [2023-11-26 11:43:52,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305769228] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:52,986 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:52,986 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:52,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [112643076] [2023-11-26 11:43:52,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:52,987 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:52,987 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:52,988 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:43:52,988 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:43:52,988 INFO L87 Difference]: Start difference. First operand 693 states and 1030 transitions. cyclomatic complexity: 338 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:53,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:53,221 INFO L93 Difference]: Finished difference Result 1194 states and 1770 transitions. [2023-11-26 11:43:53,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1194 states and 1770 transitions. [2023-11-26 11:43:53,233 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1088 [2023-11-26 11:43:53,244 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1194 states to 1194 states and 1770 transitions. [2023-11-26 11:43:53,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1194 [2023-11-26 11:43:53,246 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1194 [2023-11-26 11:43:53,246 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1194 states and 1770 transitions. [2023-11-26 11:43:53,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:53,249 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1194 states and 1770 transitions. [2023-11-26 11:43:53,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1194 states and 1770 transitions. [2023-11-26 11:43:53,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1194 to 1193. [2023-11-26 11:43:53,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1193 states, 1193 states have (on average 1.4828164291701593) internal successors, (1769), 1192 states have internal predecessors, (1769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:53,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1193 states to 1193 states and 1769 transitions. [2023-11-26 11:43:53,284 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1193 states and 1769 transitions. [2023-11-26 11:43:53,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:43:53,285 INFO L428 stractBuchiCegarLoop]: Abstraction has 1193 states and 1769 transitions. [2023-11-26 11:43:53,285 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:43:53,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1193 states and 1769 transitions. [2023-11-26 11:43:53,294 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1088 [2023-11-26 11:43:53,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:53,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:53,296 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:53,296 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:53,296 INFO L748 eck$LassoCheckResult]: Stem: 10636#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10808#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10809#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10976#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 10532#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10533#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10358#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10359#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10335#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10336#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10506#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10671#L696 assume !(0 == ~M_E~0); 10672#L696-2 assume !(0 == ~T1_E~0); 10984#L701-1 assume !(0 == ~T2_E~0); 10986#L706-1 assume !(0 == ~T3_E~0); 10784#L711-1 assume !(0 == ~T4_E~0); 10567#L716-1 assume !(0 == ~T5_E~0); 10568#L721-1 assume !(0 == ~T6_E~0); 10740#L726-1 assume !(0 == ~E_M~0); 10741#L731-1 assume !(0 == ~E_1~0); 10709#L736-1 assume !(0 == ~E_2~0); 10710#L741-1 assume !(0 == ~E_3~0); 10795#L746-1 assume !(0 == ~E_4~0); 10595#L751-1 assume !(0 == ~E_5~0); 10596#L756-1 assume !(0 == ~E_6~0); 10564#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10382#L346 assume !(1 == ~m_pc~0); 10383#L346-2 is_master_triggered_~__retres1~0#1 := 0; 10609#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10601#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10602#L861 assume !(0 != activate_threads_~tmp~1#1); 10953#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10417#L365 assume 1 == ~t1_pc~0; 10418#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10550#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10365#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10366#L869 assume !(0 != activate_threads_~tmp___0~0#1); 10407#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10851#L384 assume !(1 == ~t2_pc~0); 10845#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10846#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10810#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10323#L877 assume !(0 != activate_threads_~tmp___1~0#1); 10324#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10687#L403 assume 1 == ~t3_pc~0; 10569#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10570#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10293#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10294#L885 assume !(0 != activate_threads_~tmp___2~0#1); 10679#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10680#L422 assume 1 == ~t4_pc~0; 10318#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10319#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10470#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10471#L893 assume !(0 != activate_threads_~tmp___3~0#1); 10763#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10337#L441 assume !(1 == ~t5_pc~0); 10338#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10949#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10612#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10613#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10772#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10773#L460 assume 1 == ~t6_pc~0; 10278#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10279#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10797#L909 assume !(0 != activate_threads_~tmp___5~0#1); 10910#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10749#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 10750#L774-2 assume !(1 == ~T1_E~0); 11009#L779-1 assume !(1 == ~T2_E~0); 11072#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11071#L789-1 assume !(1 == ~T4_E~0); 11070#L794-1 assume !(1 == ~T5_E~0); 11069#L799-1 assume !(1 == ~T6_E~0); 11068#L804-1 assume !(1 == ~E_M~0); 11013#L809-1 assume !(1 == ~E_1~0); 10737#L814-1 assume !(1 == ~E_2~0); 10297#L819-1 assume !(1 == ~E_3~0); 10298#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10803#L829-1 assume !(1 == ~E_5~0); 10917#L834-1 assume !(1 == ~E_6~0); 10918#L839-1 assume { :end_inline_reset_delta_events } true; 11055#L1065-2 [2023-11-26 11:43:53,296 INFO L750 eck$LassoCheckResult]: Loop: 11055#L1065-2 assume !false; 10820#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10509#L671-1 assume !false; 11000#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11001#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10387#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10388#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11039#L582 assume !(0 != eval_~tmp~0#1); 11041#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10962#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10963#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11045#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11412#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11411#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11410#L711-3 assume !(0 == ~T4_E~0); 11409#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11408#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11407#L726-3 assume !(0 == ~E_M~0); 11406#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11405#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11404#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11403#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11402#L751-3 assume !(0 == ~E_5~0); 11401#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11400#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11399#L346-24 assume !(1 == ~m_pc~0); 11397#L346-26 is_master_triggered_~__retres1~0#1 := 0; 11396#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11395#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11394#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11393#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11392#L365-24 assume 1 == ~t1_pc~0; 11390#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11389#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11388#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11387#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11386#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11385#L384-24 assume !(1 == ~t2_pc~0); 11383#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 11382#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11381#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11380#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11379#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11378#L403-24 assume 1 == ~t3_pc~0; 11376#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11375#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11374#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11373#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11372#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11371#L422-24 assume !(1 == ~t4_pc~0); 11369#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 11368#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11367#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11366#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11365#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11364#L441-24 assume 1 == ~t5_pc~0; 11362#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11361#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11360#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11359#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 11358#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11357#L460-24 assume 1 == ~t6_pc~0; 11355#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11354#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11353#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11352#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11351#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11350#L774-3 assume !(1 == ~M_E~0); 11026#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11349#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11348#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11347#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11346#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11345#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11344#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10754#L809-3 assume !(1 == ~E_1~0); 11343#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11342#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11341#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11340#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11339#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11338#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11334#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11330#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11329#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11328#L1084 assume !(0 == start_simulation_~tmp~3#1); 10941#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11327#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11320#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11319#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 11318#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11317#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11316#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 11057#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 11055#L1065-2 [2023-11-26 11:43:53,297 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:53,297 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2023-11-26 11:43:53,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:53,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086159115] [2023-11-26 11:43:53,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:53,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:53,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:53,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:53,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:53,411 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086159115] [2023-11-26 11:43:53,411 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086159115] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:53,411 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:53,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:43:53,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994839306] [2023-11-26 11:43:53,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:53,412 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:53,413 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:53,413 INFO L85 PathProgramCache]: Analyzing trace with hash -86295588, now seen corresponding path program 1 times [2023-11-26 11:43:53,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:53,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599801884] [2023-11-26 11:43:53,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:53,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:53,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:53,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:53,475 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:53,475 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1599801884] [2023-11-26 11:43:53,477 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1599801884] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:53,478 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:53,478 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:53,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553529734] [2023-11-26 11:43:53,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:53,479 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:53,479 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:53,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:53,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:53,480 INFO L87 Difference]: Start difference. First operand 1193 states and 1769 transitions. cyclomatic complexity: 578 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:53,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:53,581 INFO L93 Difference]: Finished difference Result 2162 states and 3179 transitions. [2023-11-26 11:43:53,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2162 states and 3179 transitions. [2023-11-26 11:43:53,603 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2054 [2023-11-26 11:43:53,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2162 states to 2162 states and 3179 transitions. [2023-11-26 11:43:53,622 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2162 [2023-11-26 11:43:53,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2162 [2023-11-26 11:43:53,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2162 states and 3179 transitions. [2023-11-26 11:43:53,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:53,629 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2162 states and 3179 transitions. [2023-11-26 11:43:53,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2162 states and 3179 transitions. [2023-11-26 11:43:53,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2162 to 2158. [2023-11-26 11:43:53,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2158 states, 2158 states have (on average 1.4712696941612604) internal successors, (3175), 2157 states have internal predecessors, (3175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:53,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2158 states to 2158 states and 3175 transitions. [2023-11-26 11:43:53,684 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2158 states and 3175 transitions. [2023-11-26 11:43:53,685 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:53,687 INFO L428 stractBuchiCegarLoop]: Abstraction has 2158 states and 3175 transitions. [2023-11-26 11:43:53,687 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 11:43:53,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2158 states and 3175 transitions. [2023-11-26 11:43:53,703 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2050 [2023-11-26 11:43:53,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:53,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:53,706 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:53,706 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:53,707 INFO L748 eck$LassoCheckResult]: Stem: 13994#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 13995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14170#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14171#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14324#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 13889#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13890#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13724#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13725#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13697#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13698#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13863#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14026#L696 assume !(0 == ~M_E~0); 14027#L696-2 assume !(0 == ~T1_E~0); 14332#L701-1 assume !(0 == ~T2_E~0); 14334#L706-1 assume !(0 == ~T3_E~0); 14146#L711-1 assume !(0 == ~T4_E~0); 13924#L716-1 assume !(0 == ~T5_E~0); 13925#L721-1 assume !(0 == ~T6_E~0); 14098#L726-1 assume !(0 == ~E_M~0); 14099#L731-1 assume !(0 == ~E_1~0); 14064#L736-1 assume !(0 == ~E_2~0); 14065#L741-1 assume !(0 == ~E_3~0); 14155#L746-1 assume !(0 == ~E_4~0); 13950#L751-1 assume !(0 == ~E_5~0); 13951#L756-1 assume !(0 == ~E_6~0); 13921#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13745#L346 assume !(1 == ~m_pc~0); 13746#L346-2 is_master_triggered_~__retres1~0#1 := 0; 13965#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13957#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13958#L861 assume !(0 != activate_threads_~tmp~1#1); 14304#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13779#L365 assume !(1 == ~t1_pc~0); 13780#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14315#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13731#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13732#L869 assume !(0 != activate_threads_~tmp___0~0#1); 13768#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14208#L384 assume !(1 == ~t2_pc~0); 14204#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14205#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14176#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13687#L877 assume !(0 != activate_threads_~tmp___1~0#1); 13688#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14044#L403 assume 1 == ~t3_pc~0; 13926#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13927#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13654#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13655#L885 assume !(0 != activate_threads_~tmp___2~0#1); 14039#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14040#L422 assume 1 == ~t4_pc~0; 13682#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13683#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13830#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13831#L893 assume !(0 != activate_threads_~tmp___3~0#1); 14125#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13699#L441 assume !(1 == ~t5_pc~0); 13700#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14301#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13969#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13970#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14135#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14136#L460 assume 1 == ~t6_pc~0; 13643#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13644#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13709#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14158#L909 assume !(0 != activate_threads_~tmp___5~0#1); 14258#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14110#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 14111#L774-2 assume !(1 == ~T1_E~0); 15042#L779-1 assume !(1 == ~T2_E~0); 15039#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14363#L789-1 assume !(1 == ~T4_E~0); 13762#L794-1 assume !(1 == ~T5_E~0); 13763#L799-1 assume !(1 == ~T6_E~0); 14395#L804-1 assume !(1 == ~E_M~0); 14368#L809-1 assume !(1 == ~E_1~0); 14392#L814-1 assume !(1 == ~E_2~0); 14675#L819-1 assume !(1 == ~E_3~0); 14166#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14167#L829-1 assume !(1 == ~E_5~0); 14265#L834-1 assume !(1 == ~E_6~0); 14266#L839-1 assume { :end_inline_reset_delta_events } true; 14587#L1065-2 [2023-11-26 11:43:53,707 INFO L750 eck$LassoCheckResult]: Loop: 14587#L1065-2 assume !false; 14582#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14580#L671-1 assume !false; 14579#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14576#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14570#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14569#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14567#L582 assume !(0 != eval_~tmp~0#1); 14566#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14564#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14561#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14558#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14559#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14552#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14553#L711-3 assume !(0 == ~T4_E~0); 14545#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14546#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14539#L726-3 assume !(0 == ~E_M~0); 14540#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14533#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14534#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14511#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14512#L751-3 assume !(0 == ~E_5~0); 14497#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14498#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14479#L346-24 assume !(1 == ~m_pc~0); 14480#L346-26 is_master_triggered_~__retres1~0#1 := 0; 15051#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15047#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15044#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15041#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15038#L365-24 assume !(1 == ~t1_pc~0); 15036#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15032#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15028#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15025#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15022#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15019#L384-24 assume !(1 == ~t2_pc~0); 15014#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 15011#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15007#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15004#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15000#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14996#L403-24 assume !(1 == ~t3_pc~0); 14992#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 14986#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14981#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14977#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14974#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14970#L422-24 assume !(1 == ~t4_pc~0); 14964#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 14959#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14954#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14950#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14946#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14943#L441-24 assume 1 == ~t5_pc~0; 14937#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14932#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14927#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14923#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 14920#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14917#L460-24 assume 1 == ~t6_pc~0; 14912#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14909#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14904#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14901#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14898#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14894#L774-3 assume !(1 == ~M_E~0); 14889#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14877#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14873#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14870#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14867#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14864#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14861#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14856#L809-3 assume !(1 == ~E_1~0); 14853#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14849#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14846#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14843#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14839#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14836#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14825#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14818#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14813#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 14808#L1084 assume !(0 == start_simulation_~tmp~3#1); 14804#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14682#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14674#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14673#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 14672#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14610#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14600#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 14592#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 14587#L1065-2 [2023-11-26 11:43:53,707 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:53,708 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2023-11-26 11:43:53,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:53,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53776329] [2023-11-26 11:43:53,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:53,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:53,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:53,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:53,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:53,783 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53776329] [2023-11-26 11:43:53,783 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53776329] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:53,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:53,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:43:53,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188827124] [2023-11-26 11:43:53,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:53,784 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:53,784 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:53,785 INFO L85 PathProgramCache]: Analyzing trace with hash -1610208162, now seen corresponding path program 1 times [2023-11-26 11:43:53,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:53,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1979594906] [2023-11-26 11:43:53,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:53,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:53,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:53,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:53,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:53,832 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1979594906] [2023-11-26 11:43:53,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1979594906] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:53,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:53,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:53,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414041544] [2023-11-26 11:43:53,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:53,834 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:53,834 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:53,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:53,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:53,835 INFO L87 Difference]: Start difference. First operand 2158 states and 3175 transitions. cyclomatic complexity: 1021 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:53,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:53,943 INFO L93 Difference]: Finished difference Result 3975 states and 5808 transitions. [2023-11-26 11:43:53,944 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3975 states and 5808 transitions. [2023-11-26 11:43:53,978 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3860 [2023-11-26 11:43:54,010 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3975 states to 3975 states and 5808 transitions. [2023-11-26 11:43:54,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3975 [2023-11-26 11:43:54,015 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3975 [2023-11-26 11:43:54,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3975 states and 5808 transitions. [2023-11-26 11:43:54,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:54,022 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3975 states and 5808 transitions. [2023-11-26 11:43:54,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3975 states and 5808 transitions. [2023-11-26 11:43:54,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3975 to 3967. [2023-11-26 11:43:54,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3967 states, 3967 states have (on average 1.4620620115956642) internal successors, (5800), 3966 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:54,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3967 states to 3967 states and 5800 transitions. [2023-11-26 11:43:54,188 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3967 states and 5800 transitions. [2023-11-26 11:43:54,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:54,189 INFO L428 stractBuchiCegarLoop]: Abstraction has 3967 states and 5800 transitions. [2023-11-26 11:43:54,189 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 11:43:54,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3967 states and 5800 transitions. [2023-11-26 11:43:54,210 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3852 [2023-11-26 11:43:54,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:54,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:54,212 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:54,212 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:54,212 INFO L748 eck$LassoCheckResult]: Stem: 20133#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 20134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 20322#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20323#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20498#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 20028#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20029#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19863#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19864#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19836#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19837#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20006#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20172#L696 assume !(0 == ~M_E~0); 20173#L696-2 assume !(0 == ~T1_E~0); 20503#L701-1 assume !(0 == ~T2_E~0); 20505#L706-1 assume !(0 == ~T3_E~0); 20297#L711-1 assume !(0 == ~T4_E~0); 20065#L716-1 assume !(0 == ~T5_E~0); 20066#L721-1 assume !(0 == ~T6_E~0); 20245#L726-1 assume !(0 == ~E_M~0); 20246#L731-1 assume !(0 == ~E_1~0); 20208#L736-1 assume !(0 == ~E_2~0); 20209#L741-1 assume !(0 == ~E_3~0); 20307#L746-1 assume !(0 == ~E_4~0); 20087#L751-1 assume !(0 == ~E_5~0); 20088#L756-1 assume !(0 == ~E_6~0); 20062#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19883#L346 assume !(1 == ~m_pc~0); 19884#L346-2 is_master_triggered_~__retres1~0#1 := 0; 20106#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20095#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20096#L861 assume !(0 != activate_threads_~tmp~1#1); 20471#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19917#L365 assume !(1 == ~t1_pc~0); 19918#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20486#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19869#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19870#L869 assume !(0 != activate_threads_~tmp___0~0#1); 19906#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20362#L384 assume !(1 == ~t2_pc~0); 20358#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20359#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20328#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19826#L877 assume !(0 != activate_threads_~tmp___1~0#1); 19827#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20187#L403 assume !(1 == ~t3_pc~0); 20188#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20403#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19794#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19795#L885 assume !(0 != activate_threads_~tmp___2~0#1); 20182#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20183#L422 assume 1 == ~t4_pc~0; 19821#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19822#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19968#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19969#L893 assume !(0 != activate_threads_~tmp___3~0#1); 20274#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19838#L441 assume !(1 == ~t5_pc~0); 19839#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20467#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20108#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20109#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20286#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20287#L460 assume 1 == ~t6_pc~0; 19783#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19784#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19848#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20309#L909 assume !(0 != activate_threads_~tmp___5~0#1); 20419#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20257#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 20258#L774-2 assume !(1 == ~T1_E~0); 21809#L779-1 assume !(1 == ~T2_E~0); 21808#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21807#L789-1 assume !(1 == ~T4_E~0); 21806#L794-1 assume !(1 == ~T5_E~0); 21805#L799-1 assume !(1 == ~T6_E~0); 21804#L804-1 assume !(1 == ~E_M~0); 20544#L809-1 assume !(1 == ~E_1~0); 21803#L814-1 assume !(1 == ~E_2~0); 21802#L819-1 assume !(1 == ~E_3~0); 21801#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21800#L829-1 assume !(1 == ~E_5~0); 20427#L834-1 assume !(1 == ~E_6~0); 20428#L839-1 assume { :end_inline_reset_delta_events } true; 21021#L1065-2 [2023-11-26 11:43:54,213 INFO L750 eck$LassoCheckResult]: Loop: 21021#L1065-2 assume !false; 21022#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20856#L671-1 assume !false; 20857#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20783#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20778#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 21773#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21771#L582 assume !(0 != eval_~tmp~0#1); 21769#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21762#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21683#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21684#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22134#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22133#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22132#L711-3 assume !(0 == ~T4_E~0); 22131#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22130#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22129#L726-3 assume !(0 == ~E_M~0); 22128#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22127#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22126#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22125#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22124#L751-3 assume !(0 == ~E_5~0); 22123#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22122#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22121#L346-24 assume !(1 == ~m_pc~0); 22119#L346-26 is_master_triggered_~__retres1~0#1 := 0; 22118#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22117#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22116#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22115#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22114#L365-24 assume !(1 == ~t1_pc~0); 22113#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 22112#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22111#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22110#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22109#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22108#L384-24 assume !(1 == ~t2_pc~0); 22106#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 22105#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22104#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22103#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22102#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22101#L403-24 assume !(1 == ~t3_pc~0); 22100#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 22099#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22098#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22097#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22096#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22095#L422-24 assume !(1 == ~t4_pc~0); 22093#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 22092#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22091#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22090#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22089#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22088#L441-24 assume 1 == ~t5_pc~0; 22086#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22085#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22084#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22083#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 22080#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22078#L460-24 assume 1 == ~t6_pc~0; 22073#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22071#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22069#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22067#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22065#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22063#L774-3 assume !(1 == ~M_E~0); 21268#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21264#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21265#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22054#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22052#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22050#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22047#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21254#L809-3 assume !(1 == ~E_1~0); 22046#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22045#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22044#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22043#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22042#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22041#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 21200#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 21197#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 21192#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 21193#L1084 assume !(0 == start_simulation_~tmp~3#1); 21047#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 21048#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 21035#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 21033#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 21030#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21031#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21795#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 21794#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 21021#L1065-2 [2023-11-26 11:43:54,213 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:54,213 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2023-11-26 11:43:54,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:54,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583512114] [2023-11-26 11:43:54,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:54,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:54,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:54,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:54,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:54,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583512114] [2023-11-26 11:43:54,264 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583512114] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:54,264 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:54,264 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:43:54,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407025477] [2023-11-26 11:43:54,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:54,265 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:54,265 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:54,265 INFO L85 PathProgramCache]: Analyzing trace with hash -1610208162, now seen corresponding path program 2 times [2023-11-26 11:43:54,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:54,266 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96810263] [2023-11-26 11:43:54,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:54,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:54,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:54,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:54,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:54,309 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96810263] [2023-11-26 11:43:54,309 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [96810263] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:54,309 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:54,310 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:54,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [733150540] [2023-11-26 11:43:54,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:54,310 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:54,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:54,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:54,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:54,311 INFO L87 Difference]: Start difference. First operand 3967 states and 5800 transitions. cyclomatic complexity: 1841 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:54,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:54,435 INFO L93 Difference]: Finished difference Result 7374 states and 10725 transitions. [2023-11-26 11:43:54,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7374 states and 10725 transitions. [2023-11-26 11:43:54,489 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7232 [2023-11-26 11:43:54,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7374 states to 7374 states and 10725 transitions. [2023-11-26 11:43:54,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7374 [2023-11-26 11:43:54,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7374 [2023-11-26 11:43:54,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7374 states and 10725 transitions. [2023-11-26 11:43:54,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:54,567 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7374 states and 10725 transitions. [2023-11-26 11:43:54,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7374 states and 10725 transitions. [2023-11-26 11:43:54,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7374 to 7358. [2023-11-26 11:43:54,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7358 states, 7358 states have (on average 1.4554226692035879) internal successors, (10709), 7357 states have internal predecessors, (10709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:54,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7358 states to 7358 states and 10709 transitions. [2023-11-26 11:43:54,864 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7358 states and 10709 transitions. [2023-11-26 11:43:54,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:54,865 INFO L428 stractBuchiCegarLoop]: Abstraction has 7358 states and 10709 transitions. [2023-11-26 11:43:54,865 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 11:43:54,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7358 states and 10709 transitions. [2023-11-26 11:43:54,901 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7216 [2023-11-26 11:43:54,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:54,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:54,903 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:54,903 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:54,904 INFO L748 eck$LassoCheckResult]: Stem: 31472#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 31473#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 31670#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31671#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31841#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 31369#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31370#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31200#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31201#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31177#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31178#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31344#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31511#L696 assume !(0 == ~M_E~0); 31512#L696-2 assume !(0 == ~T1_E~0); 31850#L701-1 assume !(0 == ~T2_E~0); 31853#L706-1 assume !(0 == ~T3_E~0); 31638#L711-1 assume !(0 == ~T4_E~0); 31401#L716-1 assume !(0 == ~T5_E~0); 31402#L721-1 assume !(0 == ~T6_E~0); 31589#L726-1 assume !(0 == ~E_M~0); 31590#L731-1 assume !(0 == ~E_1~0); 31551#L736-1 assume !(0 == ~E_2~0); 31552#L741-1 assume !(0 == ~E_3~0); 31649#L746-1 assume !(0 == ~E_4~0); 31427#L751-1 assume !(0 == ~E_5~0); 31428#L756-1 assume !(0 == ~E_6~0); 31398#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31222#L346 assume !(1 == ~m_pc~0); 31223#L346-2 is_master_triggered_~__retres1~0#1 := 0; 31441#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31433#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31434#L861 assume !(0 != activate_threads_~tmp~1#1); 31812#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31256#L365 assume !(1 == ~t1_pc~0); 31257#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31825#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31207#L869 assume !(0 != activate_threads_~tmp___0~0#1); 31246#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31707#L384 assume !(1 == ~t2_pc~0); 31702#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31703#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31672#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31166#L877 assume !(0 != activate_threads_~tmp___1~0#1); 31167#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31528#L403 assume !(1 == ~t3_pc~0); 31529#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31747#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31141#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31142#L885 assume !(0 != activate_threads_~tmp___2~0#1); 31521#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31522#L422 assume !(1 == ~t4_pc~0); 31668#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31669#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31309#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31310#L893 assume !(0 != activate_threads_~tmp___3~0#1); 31615#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31179#L441 assume !(1 == ~t5_pc~0); 31180#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 31807#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31444#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31445#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31626#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31627#L460 assume 1 == ~t6_pc~0; 31128#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31129#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31187#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31651#L909 assume !(0 != activate_threads_~tmp___5~0#1); 31763#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31599#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 31600#L774-2 assume !(1 == ~T1_E~0); 31780#L779-1 assume !(1 == ~T2_E~0); 31491#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31492#L789-1 assume !(1 == ~T4_E~0); 31241#L794-1 assume !(1 == ~T5_E~0); 31242#L799-1 assume !(1 == ~T6_E~0); 31897#L804-1 assume !(1 == ~E_M~0); 31898#L809-1 assume !(1 == ~E_1~0); 31584#L814-1 assume !(1 == ~E_2~0); 31145#L819-1 assume !(1 == ~E_3~0); 31146#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 31661#L829-1 assume !(1 == ~E_5~0); 31770#L834-1 assume !(1 == ~E_6~0); 31385#L839-1 assume { :end_inline_reset_delta_events } true; 31373#L1065-2 [2023-11-26 11:43:54,904 INFO L750 eck$LassoCheckResult]: Loop: 31373#L1065-2 assume !false; 31374#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31347#L671-1 assume !false; 31742#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31748#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 31213#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31227#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 31694#L582 assume !(0 != eval_~tmp~0#1); 31938#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38123#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38121#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38119#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38117#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38115#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38113#L711-3 assume !(0 == ~T4_E~0); 38111#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38109#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38107#L726-3 assume !(0 == ~E_M~0); 38105#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38103#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38102#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31395#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31396#L751-3 assume !(0 == ~E_5~0); 31526#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31264#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31265#L346-24 assume !(1 == ~m_pc~0); 31298#L346-26 is_master_triggered_~__retres1~0#1 := 0; 31391#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38086#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38084#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38081#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38080#L365-24 assume !(1 == ~t1_pc~0); 38079#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 38078#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38077#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 38076#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38075#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38074#L384-24 assume !(1 == ~t2_pc~0); 38072#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 38071#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38070#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38069#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38068#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38067#L403-24 assume !(1 == ~t3_pc~0); 38066#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 38065#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38064#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38063#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38062#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38061#L422-24 assume !(1 == ~t4_pc~0); 38060#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 38059#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31816#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31817#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31789#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31790#L441-24 assume 1 == ~t5_pc~0; 38057#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31608#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31609#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31247#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 31248#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31715#L460-24 assume 1 == ~t6_pc~0; 38054#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38052#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31425#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31426#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38048#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38046#L774-3 assume !(1 == ~M_E~0); 31628#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31447#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31448#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38040#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31147#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31148#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31604#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31605#L809-3 assume !(1 == ~E_1~0); 31254#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31255#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38036#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31393#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31394#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31682#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31792#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 31237#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31333#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 31174#L1084 assume !(0 == start_simulation_~tmp~3#1); 31175#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31423#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 31150#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31204#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 31205#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31269#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31270#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 31435#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 31373#L1065-2 [2023-11-26 11:43:54,904 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:54,905 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2023-11-26 11:43:54,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:54,905 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393331757] [2023-11-26 11:43:54,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:54,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:54,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:54,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:54,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:54,968 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393331757] [2023-11-26 11:43:54,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [393331757] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:54,969 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:54,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:43:54,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [339334381] [2023-11-26 11:43:54,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:54,969 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:54,970 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:54,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1610208162, now seen corresponding path program 3 times [2023-11-26 11:43:54,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:54,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888557730] [2023-11-26 11:43:54,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:54,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:54,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:55,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:55,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:55,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888557730] [2023-11-26 11:43:55,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1888557730] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:55,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:55,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:55,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277914313] [2023-11-26 11:43:55,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:55,014 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:55,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:55,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:43:55,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:43:55,015 INFO L87 Difference]: Start difference. First operand 7358 states and 10709 transitions. cyclomatic complexity: 3367 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:55,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:55,471 INFO L93 Difference]: Finished difference Result 15182 states and 21862 transitions. [2023-11-26 11:43:55,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15182 states and 21862 transitions. [2023-11-26 11:43:55,570 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14952 [2023-11-26 11:43:55,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15182 states to 15182 states and 21862 transitions. [2023-11-26 11:43:55,646 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15182 [2023-11-26 11:43:55,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15182 [2023-11-26 11:43:55,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15182 states and 21862 transitions. [2023-11-26 11:43:55,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:55,771 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15182 states and 21862 transitions. [2023-11-26 11:43:55,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15182 states and 21862 transitions. [2023-11-26 11:43:55,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15182 to 7673. [2023-11-26 11:43:55,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7673 states, 7673 states have (on average 1.4367261827186237) internal successors, (11024), 7672 states have internal predecessors, (11024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:56,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7673 states to 7673 states and 11024 transitions. [2023-11-26 11:43:56,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7673 states and 11024 transitions. [2023-11-26 11:43:56,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:43:56,026 INFO L428 stractBuchiCegarLoop]: Abstraction has 7673 states and 11024 transitions. [2023-11-26 11:43:56,027 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 11:43:56,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7673 states and 11024 transitions. [2023-11-26 11:43:56,067 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7528 [2023-11-26 11:43:56,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:56,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:56,069 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:56,070 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:56,070 INFO L748 eck$LassoCheckResult]: Stem: 54027#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 54028#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 54209#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54210#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54375#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 53928#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53929#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53755#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53756#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53732#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53733#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53902#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54062#L696 assume !(0 == ~M_E~0); 54063#L696-2 assume !(0 == ~T1_E~0); 54387#L701-1 assume !(0 == ~T2_E~0); 54389#L706-1 assume !(0 == ~T3_E~0); 54186#L711-1 assume !(0 == ~T4_E~0); 53962#L716-1 assume !(0 == ~T5_E~0); 53963#L721-1 assume !(0 == ~T6_E~0); 54139#L726-1 assume !(0 == ~E_M~0); 54140#L731-1 assume !(0 == ~E_1~0); 54103#L736-1 assume !(0 == ~E_2~0); 54104#L741-1 assume !(0 == ~E_3~0); 54195#L746-1 assume !(0 == ~E_4~0); 53985#L751-1 assume !(0 == ~E_5~0); 53986#L756-1 assume !(0 == ~E_6~0); 53959#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53777#L346 assume !(1 == ~m_pc~0); 53778#L346-2 is_master_triggered_~__retres1~0#1 := 0; 53998#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53990#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53991#L861 assume !(0 != activate_threads_~tmp~1#1); 54353#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53813#L365 assume !(1 == ~t1_pc~0); 53814#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54364#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53761#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53762#L869 assume !(0 != activate_threads_~tmp___0~0#1); 53803#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54252#L384 assume !(1 == ~t2_pc~0); 54247#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54248#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54212#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53721#L877 assume !(0 != activate_threads_~tmp___1~0#1); 53722#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54080#L403 assume !(1 == ~t3_pc~0); 54081#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54286#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53694#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53695#L885 assume !(0 != activate_threads_~tmp___2~0#1); 54071#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54072#L422 assume !(1 == ~t4_pc~0); 54207#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54208#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53866#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53867#L893 assume !(0 != activate_threads_~tmp___3~0#1); 54164#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53734#L441 assume !(1 == ~t5_pc~0); 53735#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54348#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54447#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54482#L901 assume !(0 != activate_threads_~tmp___4~0#1); 54174#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54175#L460 assume 1 == ~t6_pc~0; 53681#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53682#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53742#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54197#L909 assume !(0 != activate_threads_~tmp___5~0#1); 54304#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54149#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 54150#L774-2 assume !(1 == ~T1_E~0); 58213#L779-1 assume !(1 == ~T2_E~0); 58212#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58211#L789-1 assume !(1 == ~T4_E~0); 58210#L794-1 assume !(1 == ~T5_E~0); 58209#L799-1 assume !(1 == ~T6_E~0); 58208#L804-1 assume !(1 == ~E_M~0); 54430#L809-1 assume !(1 == ~E_1~0); 58207#L814-1 assume !(1 == ~E_2~0); 58206#L819-1 assume !(1 == ~E_3~0); 58205#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 54463#L829-1 assume !(1 == ~E_5~0); 54311#L834-1 assume !(1 == ~E_6~0); 53945#L839-1 assume { :end_inline_reset_delta_events } true; 53946#L1065-2 [2023-11-26 11:43:56,070 INFO L750 eck$LassoCheckResult]: Loop: 53946#L1065-2 assume !false; 58933#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55912#L671-1 assume !false; 58928#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 58924#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 58917#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 58914#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 58862#L582 assume !(0 != eval_~tmp~0#1); 58863#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59630#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59629#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 59628#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59627#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59626#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59625#L711-3 assume !(0 == ~T4_E~0); 59624#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59623#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59622#L726-3 assume !(0 == ~E_M~0); 59621#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 59620#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59619#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 59618#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59617#L751-3 assume !(0 == ~E_5~0); 59616#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59615#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59614#L346-24 assume !(1 == ~m_pc~0); 59612#L346-26 is_master_triggered_~__retres1~0#1 := 0; 59611#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59610#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 59609#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59608#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59607#L365-24 assume !(1 == ~t1_pc~0); 59606#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 59605#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59604#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 59603#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 59602#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59601#L384-24 assume 1 == ~t2_pc~0; 59600#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59598#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59597#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59596#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59595#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59594#L403-24 assume !(1 == ~t3_pc~0); 59592#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 59589#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59587#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 59585#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59583#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59581#L422-24 assume !(1 == ~t4_pc~0); 59577#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 59569#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59566#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59563#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59558#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59557#L441-24 assume 1 == ~t5_pc~0; 59555#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59554#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59553#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59552#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 59111#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59110#L460-24 assume 1 == ~t6_pc~0; 59108#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59074#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59072#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59070#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59067#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59066#L774-3 assume !(1 == ~M_E~0); 58725#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59065#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59064#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59062#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59060#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 59058#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 59056#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 58692#L809-3 assume !(1 == ~E_1~0); 59053#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59051#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59048#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59045#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59041#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59037#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 59030#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 59020#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 59010#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 59006#L1084 assume !(0 == start_simulation_~tmp~3#1); 58978#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 58976#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 58967#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 58963#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 58957#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 58954#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 58949#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 58944#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 53946#L1065-2 [2023-11-26 11:43:56,071 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:56,071 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2023-11-26 11:43:56,071 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:56,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987434429] [2023-11-26 11:43:56,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:56,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:56,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:56,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:56,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:56,133 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987434429] [2023-11-26 11:43:56,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1987434429] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:56,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:56,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:43:56,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228689051] [2023-11-26 11:43:56,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:56,134 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:56,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:56,135 INFO L85 PathProgramCache]: Analyzing trace with hash -1850475491, now seen corresponding path program 1 times [2023-11-26 11:43:56,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:56,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312829843] [2023-11-26 11:43:56,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:56,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:56,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:56,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:56,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:56,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312829843] [2023-11-26 11:43:56,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312829843] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:56,189 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:56,189 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:56,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1541599742] [2023-11-26 11:43:56,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:56,190 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:56,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:56,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:56,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:56,191 INFO L87 Difference]: Start difference. First operand 7673 states and 11024 transitions. cyclomatic complexity: 3367 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:56,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:56,467 INFO L93 Difference]: Finished difference Result 14708 states and 21001 transitions. [2023-11-26 11:43:56,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14708 states and 21001 transitions. [2023-11-26 11:43:56,550 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14492 [2023-11-26 11:43:56,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14708 states to 14708 states and 21001 transitions. [2023-11-26 11:43:56,611 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14708 [2023-11-26 11:43:56,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14708 [2023-11-26 11:43:56,628 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14708 states and 21001 transitions. [2023-11-26 11:43:56,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:56,644 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14708 states and 21001 transitions. [2023-11-26 11:43:56,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14708 states and 21001 transitions. [2023-11-26 11:43:56,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14708 to 14676. [2023-11-26 11:43:56,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14676 states, 14676 states have (on average 1.4287953120741346) internal successors, (20969), 14675 states have internal predecessors, (20969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:57,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14676 states to 14676 states and 20969 transitions. [2023-11-26 11:43:57,028 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14676 states and 20969 transitions. [2023-11-26 11:43:57,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:57,029 INFO L428 stractBuchiCegarLoop]: Abstraction has 14676 states and 20969 transitions. [2023-11-26 11:43:57,030 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 11:43:57,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14676 states and 20969 transitions. [2023-11-26 11:43:57,087 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14460 [2023-11-26 11:43:57,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:57,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:57,089 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:57,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:57,090 INFO L748 eck$LassoCheckResult]: Stem: 76416#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 76417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 76593#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76594#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76760#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 76312#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76313#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76145#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76146#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76119#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76120#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76289#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76450#L696 assume !(0 == ~M_E~0); 76451#L696-2 assume !(0 == ~T1_E~0); 76767#L701-1 assume !(0 == ~T2_E~0); 76769#L706-1 assume !(0 == ~T3_E~0); 76568#L711-1 assume !(0 == ~T4_E~0); 76348#L716-1 assume !(0 == ~T5_E~0); 76349#L721-1 assume !(0 == ~T6_E~0); 76519#L726-1 assume !(0 == ~E_M~0); 76520#L731-1 assume !(0 == ~E_1~0); 76485#L736-1 assume !(0 == ~E_2~0); 76486#L741-1 assume !(0 == ~E_3~0); 76577#L746-1 assume !(0 == ~E_4~0); 76370#L751-1 assume !(0 == ~E_5~0); 76371#L756-1 assume !(0 == ~E_6~0); 76345#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76165#L346 assume !(1 == ~m_pc~0); 76166#L346-2 is_master_triggered_~__retres1~0#1 := 0; 76387#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76377#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76378#L861 assume !(0 != activate_threads_~tmp~1#1); 76741#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76199#L365 assume !(1 == ~t1_pc~0); 76200#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76752#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76151#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76152#L869 assume !(0 != activate_threads_~tmp___0~0#1); 76188#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76633#L384 assume !(1 == ~t2_pc~0); 76629#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76630#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76598#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76109#L877 assume !(0 != activate_threads_~tmp___1~0#1); 76110#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76465#L403 assume !(1 == ~t3_pc~0); 76466#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76676#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76081#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76082#L885 assume !(0 != activate_threads_~tmp___2~0#1); 76460#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76461#L422 assume !(1 == ~t4_pc~0); 76591#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76592#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76251#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76252#L893 assume !(0 != activate_threads_~tmp___3~0#1); 76546#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76121#L441 assume !(1 == ~t5_pc~0); 76122#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76738#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76389#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76390#L901 assume !(0 != activate_threads_~tmp___4~0#1); 76557#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76558#L460 assume !(1 == ~t6_pc~0); 76700#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76130#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76131#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76579#L909 assume !(0 != activate_threads_~tmp___5~0#1); 76695#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76530#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 76531#L774-2 assume !(1 == ~T1_E~0); 76713#L779-1 assume !(1 == ~T2_E~0); 76433#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76434#L789-1 assume !(1 == ~T4_E~0); 76182#L794-1 assume !(1 == ~T5_E~0); 76183#L799-1 assume !(1 == ~T6_E~0); 76809#L804-1 assume !(1 == ~E_M~0); 76810#L809-1 assume !(1 == ~E_1~0); 76515#L814-1 assume !(1 == ~E_2~0); 76087#L819-1 assume !(1 == ~E_3~0); 76088#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 76585#L829-1 assume !(1 == ~E_5~0); 76703#L834-1 assume !(1 == ~E_6~0); 76333#L839-1 assume { :end_inline_reset_delta_events } true; 76334#L1065-2 [2023-11-26 11:43:57,090 INFO L750 eck$LassoCheckResult]: Loop: 76334#L1065-2 assume !false; 80671#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80583#L671-1 assume !false; 80662#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 80655#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80645#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 80639#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 80630#L582 assume !(0 != eval_~tmp~0#1); 80631#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 80994#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 80993#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 80992#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 80991#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 80990#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 80989#L711-3 assume !(0 == ~T4_E~0); 80988#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 80987#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 80986#L726-3 assume !(0 == ~E_M~0); 80985#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 80984#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 80983#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80982#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 80981#L751-3 assume !(0 == ~E_5~0); 80980#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 80979#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80978#L346-24 assume 1 == ~m_pc~0; 80977#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 80975#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80974#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 80973#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 80972#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80970#L365-24 assume !(1 == ~t1_pc~0); 80967#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 80965#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80963#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 80961#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80959#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80957#L384-24 assume 1 == ~t2_pc~0; 80955#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 80952#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80950#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 80948#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80946#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80944#L403-24 assume !(1 == ~t3_pc~0); 80941#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 80939#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80937#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 80935#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 80933#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80931#L422-24 assume !(1 == ~t4_pc~0); 80929#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 80927#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80925#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 80923#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 80921#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80919#L441-24 assume !(1 == ~t5_pc~0); 80917#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 80914#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80911#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 80901#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 80897#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80894#L460-24 assume !(1 == ~t6_pc~0); 80890#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 80886#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80882#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80878#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 80875#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80872#L774-3 assume !(1 == ~M_E~0); 80419#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 80867#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80864#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 80861#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 80857#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 80854#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 80851#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 80388#L809-3 assume !(1 == ~E_1~0); 80846#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 80843#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 80838#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 80830#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 80826#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 80823#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 80798#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80790#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 80785#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 80780#L1084 assume !(0 == start_simulation_~tmp~3#1); 80775#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 80725#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80714#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 80708#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 80703#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 80697#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80690#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 80683#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 76334#L1065-2 [2023-11-26 11:43:57,091 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:57,091 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2023-11-26 11:43:57,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:57,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050219621] [2023-11-26 11:43:57,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:57,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:57,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:57,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:57,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:57,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050219621] [2023-11-26 11:43:57,159 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050219621] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:57,159 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:57,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:43:57,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805136250] [2023-11-26 11:43:57,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:57,161 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:57,161 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:57,161 INFO L85 PathProgramCache]: Analyzing trace with hash -1226623202, now seen corresponding path program 1 times [2023-11-26 11:43:57,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:57,162 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865136945] [2023-11-26 11:43:57,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:57,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:57,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:57,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:57,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:57,306 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865136945] [2023-11-26 11:43:57,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [865136945] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:57,307 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:57,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:57,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368435831] [2023-11-26 11:43:57,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:57,307 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:57,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:57,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:43:57,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:43:57,309 INFO L87 Difference]: Start difference. First operand 14676 states and 20969 transitions. cyclomatic complexity: 6325 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:57,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:57,443 INFO L93 Difference]: Finished difference Result 21861 states and 31258 transitions. [2023-11-26 11:43:57,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21861 states and 31258 transitions. [2023-11-26 11:43:57,556 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21596 [2023-11-26 11:43:57,857 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21861 states to 21861 states and 31258 transitions. [2023-11-26 11:43:57,857 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21861 [2023-11-26 11:43:57,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21861 [2023-11-26 11:43:57,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21861 states and 31258 transitions. [2023-11-26 11:43:57,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:57,937 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21861 states and 31258 transitions. [2023-11-26 11:43:57,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21861 states and 31258 transitions. [2023-11-26 11:43:58,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21861 to 15306. [2023-11-26 11:43:58,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15306 states, 15306 states have (on average 1.4321834574676597) internal successors, (21921), 15305 states have internal predecessors, (21921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:58,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15306 states to 15306 states and 21921 transitions. [2023-11-26 11:43:58,629 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15306 states and 21921 transitions. [2023-11-26 11:43:58,630 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:43:58,631 INFO L428 stractBuchiCegarLoop]: Abstraction has 15306 states and 21921 transitions. [2023-11-26 11:43:58,632 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 11:43:58,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15306 states and 21921 transitions. [2023-11-26 11:43:58,741 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15104 [2023-11-26 11:43:58,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:58,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:58,743 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:58,743 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:58,744 INFO L748 eck$LassoCheckResult]: Stem: 112956#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 112957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 113132#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113133#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 113302#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 112854#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112855#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112689#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112690#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112662#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112663#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 112832#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112991#L696 assume !(0 == ~M_E~0); 112992#L696-2 assume !(0 == ~T1_E~0); 113309#L701-1 assume !(0 == ~T2_E~0); 113312#L706-1 assume !(0 == ~T3_E~0); 113106#L711-1 assume !(0 == ~T4_E~0); 112888#L716-1 assume !(0 == ~T5_E~0); 112889#L721-1 assume !(0 == ~T6_E~0); 113060#L726-1 assume !(0 == ~E_M~0); 113061#L731-1 assume !(0 == ~E_1~0); 113027#L736-1 assume !(0 == ~E_2~0); 113028#L741-1 assume !(0 == ~E_3~0); 113116#L746-1 assume !(0 == ~E_4~0); 112912#L751-1 assume !(0 == ~E_5~0); 112913#L756-1 assume !(0 == ~E_6~0); 112885#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112710#L346 assume !(1 == ~m_pc~0); 112711#L346-2 is_master_triggered_~__retres1~0#1 := 0; 112927#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112917#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 112918#L861 assume !(0 != activate_threads_~tmp~1#1); 113274#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112743#L365 assume !(1 == ~t1_pc~0); 112744#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 113290#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112696#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112697#L869 assume !(0 != activate_threads_~tmp___0~0#1); 112732#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113174#L384 assume !(1 == ~t2_pc~0); 113170#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 113171#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113139#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 112653#L877 assume !(0 != activate_threads_~tmp___1~0#1); 112654#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 113006#L403 assume !(1 == ~t3_pc~0); 113007#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 113206#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112624#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 112625#L885 assume !(0 != activate_threads_~tmp___2~0#1); 113001#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113002#L422 assume !(1 == ~t4_pc~0); 113130#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 113131#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112796#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 112797#L893 assume !(0 != activate_threads_~tmp___3~0#1); 113083#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112664#L441 assume !(1 == ~t5_pc~0); 112665#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 113269#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112929#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 112930#L901 assume !(0 != activate_threads_~tmp___4~0#1); 113095#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113096#L460 assume !(1 == ~t6_pc~0); 113224#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 112673#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112674#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 113118#L909 assume !(0 != activate_threads_~tmp___5~0#1); 113219#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 113070#L774 assume !(1 == ~M_E~0); 113071#L774-2 assume !(1 == ~T1_E~0); 113241#L779-1 assume !(1 == ~T2_E~0); 112973#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112974#L789-1 assume !(1 == ~T4_E~0); 112727#L794-1 assume !(1 == ~T5_E~0); 112728#L799-1 assume !(1 == ~T6_E~0); 113355#L804-1 assume !(1 == ~E_M~0); 113356#L809-1 assume !(1 == ~E_1~0); 113058#L814-1 assume !(1 == ~E_2~0); 112630#L819-1 assume !(1 == ~E_3~0); 112631#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 113126#L829-1 assume !(1 == ~E_5~0); 113227#L834-1 assume !(1 == ~E_6~0); 112874#L839-1 assume { :end_inline_reset_delta_events } true; 112875#L1065-2 [2023-11-26 11:43:58,744 INFO L750 eck$LassoCheckResult]: Loop: 112875#L1065-2 assume !false; 121942#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 121940#L671-1 assume !false; 121939#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 120483#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 120476#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 120474#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 120472#L582 assume !(0 != eval_~tmp~0#1); 120471#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 120463#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 120461#L696-3 assume !(0 == ~M_E~0); 120459#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 120456#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 120454#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 120452#L711-3 assume !(0 == ~T4_E~0); 120450#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 120448#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 120446#L726-3 assume !(0 == ~E_M~0); 120444#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 120442#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 120440#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 120438#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 120436#L751-3 assume !(0 == ~E_5~0); 120434#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 120432#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 120430#L346-24 assume !(1 == ~m_pc~0); 120427#L346-26 is_master_triggered_~__retres1~0#1 := 0; 120425#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 120423#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 120421#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 120419#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 120416#L365-24 assume !(1 == ~t1_pc~0); 120414#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 120412#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120410#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 120408#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 120406#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 120404#L384-24 assume !(1 == ~t2_pc~0); 120401#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 120399#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 120397#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 120395#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 120393#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 120390#L403-24 assume !(1 == ~t3_pc~0); 120388#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 120386#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120384#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 120382#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 120380#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120378#L422-24 assume !(1 == ~t4_pc~0); 120376#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 120374#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 120372#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 120370#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 120368#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 120365#L441-24 assume !(1 == ~t5_pc~0); 120363#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 124309#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124307#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 120355#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 120353#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 120350#L460-24 assume !(1 == ~t6_pc~0); 120348#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 120346#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 120343#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 120341#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 120339#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 120336#L774-3 assume !(1 == ~M_E~0); 117833#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 120333#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 120331#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 120329#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 120327#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 120326#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 120324#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 120322#L809-3 assume !(1 == ~E_1~0); 120320#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 120318#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 120316#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 120314#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 120312#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 120310#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 120292#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 120287#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 120285#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 118036#L1084 assume !(0 == start_simulation_~tmp~3#1); 118037#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 121974#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 121965#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 121961#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 121957#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 121953#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 121952#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 121951#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 112875#L1065-2 [2023-11-26 11:43:58,744 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:58,745 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2023-11-26 11:43:58,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:58,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140000273] [2023-11-26 11:43:58,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:58,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:58,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:58,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:58,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:58,813 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140000273] [2023-11-26 11:43:58,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140000273] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:58,814 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:58,814 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:58,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112089560] [2023-11-26 11:43:58,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:58,817 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:43:58,817 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:58,817 INFO L85 PathProgramCache]: Analyzing trace with hash -1727857954, now seen corresponding path program 1 times [2023-11-26 11:43:58,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:58,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473362454] [2023-11-26 11:43:58,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:58,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:58,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:43:58,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:43:58,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:43:58,864 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [473362454] [2023-11-26 11:43:58,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [473362454] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:43:58,865 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:43:58,865 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:43:58,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783549237] [2023-11-26 11:43:58,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:43:58,866 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:43:58,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:43:58,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:43:58,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:43:58,867 INFO L87 Difference]: Start difference. First operand 15306 states and 21921 transitions. cyclomatic complexity: 6631 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:59,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:43:59,024 INFO L93 Difference]: Finished difference Result 24428 states and 34861 transitions. [2023-11-26 11:43:59,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24428 states and 34861 transitions. [2023-11-26 11:43:59,155 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24096 [2023-11-26 11:43:59,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24428 states to 24428 states and 34861 transitions. [2023-11-26 11:43:59,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24428 [2023-11-26 11:43:59,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24428 [2023-11-26 11:43:59,415 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24428 states and 34861 transitions. [2023-11-26 11:43:59,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:43:59,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24428 states and 34861 transitions. [2023-11-26 11:43:59,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24428 states and 34861 transitions. [2023-11-26 11:43:59,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24428 to 17449. [2023-11-26 11:43:59,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17449 states, 17449 states have (on average 1.4309129463006476) internal successors, (24968), 17448 states have internal predecessors, (24968), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:43:59,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17449 states to 17449 states and 24968 transitions. [2023-11-26 11:43:59,894 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17449 states and 24968 transitions. [2023-11-26 11:43:59,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:43:59,895 INFO L428 stractBuchiCegarLoop]: Abstraction has 17449 states and 24968 transitions. [2023-11-26 11:43:59,895 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 11:43:59,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17449 states and 24968 transitions. [2023-11-26 11:43:59,967 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17184 [2023-11-26 11:43:59,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:43:59,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:43:59,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:59,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:43:59,970 INFO L748 eck$LassoCheckResult]: Stem: 152700#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 152701#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 152875#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 152876#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153031#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 152600#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 152601#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 152434#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 152435#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 152407#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 152408#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 152577#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 152733#L696 assume !(0 == ~M_E~0); 152734#L696-2 assume !(0 == ~T1_E~0); 153038#L701-1 assume !(0 == ~T2_E~0); 153040#L706-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 153064#L711-1 assume !(0 == ~T4_E~0); 153158#L716-1 assume !(0 == ~T5_E~0); 153073#L721-1 assume !(0 == ~T6_E~0); 153074#L726-1 assume !(0 == ~E_M~0); 153157#L731-1 assume !(0 == ~E_1~0); 153156#L736-1 assume !(0 == ~E_2~0); 152860#L741-1 assume !(0 == ~E_3~0); 152861#L746-1 assume !(0 == ~E_4~0); 152658#L751-1 assume !(0 == ~E_5~0); 152659#L756-1 assume !(0 == ~E_6~0); 152748#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153154#L346 assume !(1 == ~m_pc~0); 153152#L346-2 is_master_triggered_~__retres1~0#1 := 0; 153151#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153150#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 153056#L861 assume !(0 != activate_threads_~tmp~1#1); 153007#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153008#L365 assume !(1 == ~t1_pc~0); 153148#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 153147#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152440#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 152441#L869 assume !(0 != activate_threads_~tmp___0~0#1); 152476#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152914#L384 assume !(1 == ~t2_pc~0); 152910#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 152911#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152881#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 152397#L877 assume !(0 != activate_threads_~tmp___1~0#1); 152398#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152749#L403 assume !(1 == ~t3_pc~0); 152750#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 152948#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152369#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 152370#L885 assume !(0 != activate_threads_~tmp___2~0#1); 152743#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152744#L422 assume !(1 == ~t4_pc~0); 152873#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 152874#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152539#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152540#L893 assume !(0 != activate_threads_~tmp___3~0#1); 152991#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 153130#L441 assume !(1 == ~t5_pc~0); 153047#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 153129#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 153127#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 153124#L901 assume !(0 != activate_threads_~tmp___4~0#1); 152838#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152839#L460 assume !(1 == ~t6_pc~0); 152969#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 153121#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 153120#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 153119#L909 assume !(0 != activate_threads_~tmp___5~0#1); 153051#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153052#L774 assume !(1 == ~M_E~0); 153118#L774-2 assume !(1 == ~T1_E~0); 153117#L779-1 assume !(1 == ~T2_E~0); 153116#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 152718#L789-1 assume !(1 == ~T4_E~0); 152471#L794-1 assume !(1 == ~T5_E~0); 152472#L799-1 assume !(1 == ~T6_E~0); 153076#L804-1 assume !(1 == ~E_M~0); 153077#L809-1 assume !(1 == ~E_1~0); 152800#L814-1 assume !(1 == ~E_2~0); 152375#L819-1 assume !(1 == ~E_3~0); 152376#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 152869#L829-1 assume !(1 == ~E_5~0); 152972#L834-1 assume !(1 == ~E_6~0); 152620#L839-1 assume { :end_inline_reset_delta_events } true; 152621#L1065-2 [2023-11-26 11:43:59,971 INFO L750 eck$LassoCheckResult]: Loop: 152621#L1065-2 assume !false; 159937#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 159705#L671-1 assume !false; 159704#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 158456#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158449#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 158446#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 158443#L582 assume !(0 != eval_~tmp~0#1); 158441#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 158439#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 158437#L696-3 assume !(0 == ~M_E~0); 158435#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 158434#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 158431#L706-3 assume !(0 == ~T3_E~0); 158432#L711-3 assume !(0 == ~T4_E~0); 158586#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 158583#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 158581#L726-3 assume !(0 == ~E_M~0); 158579#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 158577#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 158575#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 158573#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 158570#L751-3 assume !(0 == ~E_5~0); 158568#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 158566#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 158564#L346-24 assume 1 == ~m_pc~0; 158562#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 158559#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 158558#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 158555#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 158553#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158551#L365-24 assume !(1 == ~t1_pc~0); 158549#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 158547#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 158545#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 158543#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 158541#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158539#L384-24 assume !(1 == ~t2_pc~0); 158536#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 158534#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 158532#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 158529#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 158527#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158525#L403-24 assume !(1 == ~t3_pc~0); 158522#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 158520#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 158518#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 158516#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 158514#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 158512#L422-24 assume !(1 == ~t4_pc~0); 158510#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 158508#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158504#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 158502#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 158500#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 158499#L441-24 assume !(1 == ~t5_pc~0); 158498#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 158496#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158494#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 158491#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 158488#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 158487#L460-24 assume !(1 == ~t6_pc~0); 158483#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 158479#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158478#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 158476#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 158472#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158468#L774-3 assume !(1 == ~M_E~0); 156583#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 158463#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 158371#L784-3 assume !(1 == ~T3_E~0); 158368#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 158366#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 158363#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 158361#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 158359#L809-3 assume !(1 == ~E_1~0); 158357#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 158355#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 158353#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 157696#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 157695#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 157694#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 157690#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 157686#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 157685#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 156764#L1084 assume !(0 == start_simulation_~tmp~3#1); 156765#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 160067#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 160059#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 160057#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 160055#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 160053#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 160052#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 160051#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 152621#L1065-2 [2023-11-26 11:43:59,971 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:43:59,972 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2023-11-26 11:43:59,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:43:59,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744566172] [2023-11-26 11:43:59,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:43:59,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:43:59,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:00,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:00,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:00,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744566172] [2023-11-26 11:44:00,049 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744566172] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:00,049 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:00,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:44:00,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254175103] [2023-11-26 11:44:00,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:00,050 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:44:00,051 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:00,051 INFO L85 PathProgramCache]: Analyzing trace with hash 237628893, now seen corresponding path program 1 times [2023-11-26 11:44:00,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:00,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786898146] [2023-11-26 11:44:00,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:00,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:00,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:00,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:00,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:00,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786898146] [2023-11-26 11:44:00,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786898146] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:00,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:00,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:44:00,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944852297] [2023-11-26 11:44:00,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:00,104 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:00,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:00,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:44:00,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:44:00,105 INFO L87 Difference]: Start difference. First operand 17449 states and 24968 transitions. cyclomatic complexity: 7535 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:00,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:00,368 INFO L93 Difference]: Finished difference Result 22274 states and 31679 transitions. [2023-11-26 11:44:00,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22274 states and 31679 transitions. [2023-11-26 11:44:00,458 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22016 [2023-11-26 11:44:00,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22274 states to 22274 states and 31679 transitions. [2023-11-26 11:44:00,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22274 [2023-11-26 11:44:00,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22274 [2023-11-26 11:44:00,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22274 states and 31679 transitions. [2023-11-26 11:44:00,553 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:00,553 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22274 states and 31679 transitions. [2023-11-26 11:44:00,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22274 states and 31679 transitions. [2023-11-26 11:44:00,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22274 to 15306. [2023-11-26 11:44:00,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15306 states, 15306 states have (on average 1.42578073957925) internal successors, (21823), 15305 states have internal predecessors, (21823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:00,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15306 states to 15306 states and 21823 transitions. [2023-11-26 11:44:00,913 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15306 states and 21823 transitions. [2023-11-26 11:44:00,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:44:00,914 INFO L428 stractBuchiCegarLoop]: Abstraction has 15306 states and 21823 transitions. [2023-11-26 11:44:00,914 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 11:44:00,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15306 states and 21823 transitions. [2023-11-26 11:44:00,962 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15104 [2023-11-26 11:44:00,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:00,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:00,964 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:00,964 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:00,964 INFO L748 eck$LassoCheckResult]: Stem: 192430#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 192431#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 192618#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 192619#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 192801#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 192327#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 192328#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 192160#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 192161#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 192137#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 192138#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 192302#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 192467#L696 assume !(0 == ~M_E~0); 192468#L696-2 assume !(0 == ~T1_E~0); 192807#L701-1 assume !(0 == ~T2_E~0); 192809#L706-1 assume !(0 == ~T3_E~0); 192590#L711-1 assume !(0 == ~T4_E~0); 192362#L716-1 assume !(0 == ~T5_E~0); 192363#L721-1 assume !(0 == ~T6_E~0); 192538#L726-1 assume !(0 == ~E_M~0); 192539#L731-1 assume !(0 == ~E_1~0); 192506#L736-1 assume !(0 == ~E_2~0); 192507#L741-1 assume !(0 == ~E_3~0); 192599#L746-1 assume !(0 == ~E_4~0); 192387#L751-1 assume !(0 == ~E_5~0); 192388#L756-1 assume !(0 == ~E_6~0); 192359#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 192183#L346 assume !(1 == ~m_pc~0); 192184#L346-2 is_master_triggered_~__retres1~0#1 := 0; 192401#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192393#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 192394#L861 assume !(0 != activate_threads_~tmp~1#1); 192775#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192217#L365 assume !(1 == ~t1_pc~0); 192218#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 192790#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 192166#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 192167#L869 assume !(0 != activate_threads_~tmp___0~0#1); 192207#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 192660#L384 assume !(1 == ~t2_pc~0); 192655#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 192656#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192622#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 192126#L877 assume !(0 != activate_threads_~tmp___1~0#1); 192127#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192484#L403 assume !(1 == ~t3_pc~0); 192485#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 192704#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 192101#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 192102#L885 assume !(0 != activate_threads_~tmp___2~0#1); 192477#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192478#L422 assume !(1 == ~t4_pc~0); 192616#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 192617#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 192269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 192270#L893 assume !(0 != activate_threads_~tmp___3~0#1); 192564#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 192139#L441 assume !(1 == ~t5_pc~0); 192140#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 192769#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 192404#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 192405#L901 assume !(0 != activate_threads_~tmp___4~0#1); 192576#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 192577#L460 assume !(1 == ~t6_pc~0); 192724#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 192146#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 192147#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 192602#L909 assume !(0 != activate_threads_~tmp___5~0#1); 192721#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192548#L774 assume !(1 == ~M_E~0); 192549#L774-2 assume !(1 == ~T1_E~0); 192742#L779-1 assume !(1 == ~T2_E~0); 192449#L784-1 assume !(1 == ~T3_E~0); 192450#L789-1 assume !(1 == ~T4_E~0); 192202#L794-1 assume !(1 == ~T5_E~0); 192203#L799-1 assume !(1 == ~T6_E~0); 192865#L804-1 assume !(1 == ~E_M~0); 192866#L809-1 assume !(1 == ~E_1~0); 192534#L814-1 assume !(1 == ~E_2~0); 192105#L819-1 assume !(1 == ~E_3~0); 192106#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 192610#L829-1 assume !(1 == ~E_5~0); 192731#L834-1 assume !(1 == ~E_6~0); 192345#L839-1 assume { :end_inline_reset_delta_events } true; 192346#L1065-2 [2023-11-26 11:44:00,965 INFO L750 eck$LassoCheckResult]: Loop: 192346#L1065-2 assume !false; 201926#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 201923#L671-1 assume !false; 201921#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 201916#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 201909#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 201907#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 201904#L582 assume !(0 != eval_~tmp~0#1); 201902#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 201900#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 201898#L696-3 assume !(0 == ~M_E~0); 201896#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 201893#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 201891#L706-3 assume !(0 == ~T3_E~0); 201889#L711-3 assume !(0 == ~T4_E~0); 201887#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 201885#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 201883#L726-3 assume !(0 == ~E_M~0); 201880#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 201878#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 201876#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 201874#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 201872#L751-3 assume !(0 == ~E_5~0); 201870#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 201867#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 201865#L346-24 assume 1 == ~m_pc~0; 201863#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 201860#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 201858#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 201856#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 201854#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 201852#L365-24 assume !(1 == ~t1_pc~0); 201850#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 201848#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201846#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 201844#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 201841#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 201839#L384-24 assume 1 == ~t2_pc~0; 201837#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 201834#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 201832#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 201830#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 201827#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 201825#L403-24 assume !(1 == ~t3_pc~0); 201823#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 201820#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 201818#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 201816#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 201813#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 201811#L422-24 assume !(1 == ~t4_pc~0); 201809#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 201807#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 201805#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 201803#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 201802#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 201800#L441-24 assume !(1 == ~t5_pc~0); 201798#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 206936#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 206859#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 201790#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 201788#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 201786#L460-24 assume !(1 == ~t6_pc~0); 201784#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 201783#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 201782#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 201780#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 201779#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 201778#L774-3 assume !(1 == ~M_E~0); 196065#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 201777#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 201776#L784-3 assume !(1 == ~T3_E~0); 201775#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 201773#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 201771#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 201770#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 201769#L809-3 assume !(1 == ~E_1~0); 201768#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 201766#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 201765#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 201326#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 201323#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 201321#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 201104#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 201086#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 201067#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 196216#L1084 assume !(0 == start_simulation_~tmp~3#1); 196217#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 205005#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 204997#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 204995#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 204993#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 204991#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 204989#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 204987#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 192346#L1065-2 [2023-11-26 11:44:00,965 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:00,965 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2023-11-26 11:44:00,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:00,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677439893] [2023-11-26 11:44:00,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:00,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:00,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:01,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:01,037 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:01,037 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [677439893] [2023-11-26 11:44:01,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [677439893] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:01,039 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:01,039 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:44:01,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982088141] [2023-11-26 11:44:01,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:01,040 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:44:01,040 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:01,040 INFO L85 PathProgramCache]: Analyzing trace with hash -2638436, now seen corresponding path program 1 times [2023-11-26 11:44:01,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:01,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245514067] [2023-11-26 11:44:01,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:01,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:01,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:01,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:01,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:01,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245514067] [2023-11-26 11:44:01,093 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1245514067] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:01,093 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:01,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:44:01,094 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150510678] [2023-11-26 11:44:01,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:01,094 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:01,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:01,095 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:44:01,095 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:44:01,096 INFO L87 Difference]: Start difference. First operand 15306 states and 21823 transitions. cyclomatic complexity: 6533 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:01,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:01,299 INFO L93 Difference]: Finished difference Result 24188 states and 34235 transitions. [2023-11-26 11:44:01,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24188 states and 34235 transitions. [2023-11-26 11:44:01,648 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23856 [2023-11-26 11:44:01,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24188 states to 24188 states and 34235 transitions. [2023-11-26 11:44:01,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24188 [2023-11-26 11:44:01,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24188 [2023-11-26 11:44:01,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24188 states and 34235 transitions. [2023-11-26 11:44:01,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:01,775 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24188 states and 34235 transitions. [2023-11-26 11:44:01,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24188 states and 34235 transitions. [2023-11-26 11:44:02,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24188 to 17449. [2023-11-26 11:44:02,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17449 states, 17449 states have (on average 1.41933635165339) internal successors, (24766), 17448 states have internal predecessors, (24766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:02,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17449 states to 17449 states and 24766 transitions. [2023-11-26 11:44:02,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17449 states and 24766 transitions. [2023-11-26 11:44:02,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:44:02,154 INFO L428 stractBuchiCegarLoop]: Abstraction has 17449 states and 24766 transitions. [2023-11-26 11:44:02,154 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 11:44:02,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17449 states and 24766 transitions. [2023-11-26 11:44:02,229 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17184 [2023-11-26 11:44:02,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:02,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:02,232 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:02,232 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:02,233 INFO L748 eck$LassoCheckResult]: Stem: 231947#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 231948#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 232142#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 232143#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 232337#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 231839#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 231840#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 231668#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 231669#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 231642#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 231643#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 231814#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 231982#L696 assume !(0 == ~M_E~0); 231983#L696-2 assume !(0 == ~T1_E~0); 232345#L701-1 assume !(0 == ~T2_E~0); 232348#L706-1 assume !(0 == ~T3_E~0); 232107#L711-1 assume !(0 == ~T4_E~0); 231877#L716-1 assume !(0 == ~T5_E~0); 231878#L721-1 assume !(0 == ~T6_E~0); 232058#L726-1 assume !(0 == ~E_M~0); 232059#L731-1 assume !(0 == ~E_1~0); 232021#L736-1 assume !(0 == ~E_2~0); 232022#L741-1 assume !(0 == ~E_3~0); 232118#L746-1 assume 0 == ~E_4~0;~E_4~0 := 1; 232423#L751-1 assume !(0 == ~E_5~0); 232499#L756-1 assume !(0 == ~E_6~0); 231873#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 231874#L346 assume !(1 == ~m_pc~0); 231914#L346-2 is_master_triggered_~__retres1~0#1 := 0; 231915#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 232245#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 232367#L861 assume !(0 != activate_threads_~tmp~1#1); 232304#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 232305#L365 assume !(1 == ~t1_pc~0); 232496#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 232495#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 231674#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 231675#L869 assume !(0 != activate_threads_~tmp___0~0#1); 231714#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 232493#L384 assume !(1 == ~t2_pc~0); 232491#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 232424#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 232425#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 231630#L877 assume !(0 != activate_threads_~tmp___1~0#1); 231631#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 232000#L403 assume !(1 == ~t3_pc~0); 232001#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 232229#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 231604#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 231605#L885 assume !(0 != activate_threads_~tmp___2~0#1); 231994#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 231995#L422 assume !(1 == ~t4_pc~0); 232338#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 232482#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 232481#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 232480#L893 assume !(0 != activate_threads_~tmp___3~0#1); 232085#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 231644#L441 assume !(1 == ~t5_pc~0); 231645#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 232301#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 231918#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 231919#L901 assume !(0 != activate_threads_~tmp___4~0#1); 232464#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 232471#L460 assume !(1 == ~t6_pc~0); 232343#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 231651#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 231652#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 232469#L909 assume !(0 != activate_threads_~tmp___5~0#1); 232362#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 232363#L774 assume !(1 == ~M_E~0); 232397#L774-2 assume !(1 == ~T1_E~0); 232267#L779-1 assume !(1 == ~T2_E~0); 231967#L784-1 assume !(1 == ~T3_E~0); 231968#L789-1 assume !(1 == ~T4_E~0); 232466#L794-1 assume !(1 == ~T5_E~0); 232446#L799-1 assume !(1 == ~T6_E~0); 232447#L804-1 assume !(1 == ~E_M~0); 232441#L809-1 assume !(1 == ~E_1~0); 232442#L814-1 assume !(1 == ~E_2~0); 231610#L819-1 assume !(1 == ~E_3~0); 231611#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 232133#L829-1 assume !(1 == ~E_5~0); 232255#L834-1 assume !(1 == ~E_6~0); 231859#L839-1 assume { :end_inline_reset_delta_events } true; 231860#L1065-2 [2023-11-26 11:44:02,233 INFO L750 eck$LassoCheckResult]: Loop: 231860#L1065-2 assume !false; 236082#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 235829#L671-1 assume !false; 236074#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 235513#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 235507#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 235504#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 235503#L582 assume !(0 != eval_~tmp~0#1); 231794#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231795#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 232316#L696-3 assume !(0 == ~M_E~0); 247802#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 247800#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 247798#L706-3 assume !(0 == ~T3_E~0); 247796#L711-3 assume !(0 == ~T4_E~0); 247794#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 247790#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 247788#L726-3 assume !(0 == ~E_M~0); 247786#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 247784#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 247773#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 247772#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 247771#L751-3 assume !(0 == ~E_5~0); 247770#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 247769#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247768#L346-24 assume 1 == ~m_pc~0; 247767#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 247765#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247764#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 247763#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 247762#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247761#L365-24 assume !(1 == ~t1_pc~0); 247760#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 247759#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247758#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 247757#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 247756#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247755#L384-24 assume 1 == ~t2_pc~0; 247754#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 247752#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247751#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 247750#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 247749#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247748#L403-24 assume !(1 == ~t3_pc~0); 247747#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 247746#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247745#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 247744#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 247743#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247742#L422-24 assume !(1 == ~t4_pc~0); 247741#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 247740#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247739#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 247738#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 247737#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247736#L441-24 assume !(1 == ~t5_pc~0); 247735#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 247775#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247774#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 247730#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 247729#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 247728#L460-24 assume !(1 == ~t6_pc~0); 247727#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 247726#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247725#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 247724#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 247723#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 247722#L774-3 assume !(1 == ~M_E~0); 234355#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 247721#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 247720#L784-3 assume !(1 == ~T3_E~0); 247719#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 247718#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 247717#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 247716#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 247715#L809-3 assume !(1 == ~E_1~0); 247714#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 247713#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 247711#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 247710#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 247232#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 246629#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 236549#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 232805#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 232806#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 234465#L1084 assume !(0 == start_simulation_~tmp~3#1); 234466#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 236135#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 236123#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 236116#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 236110#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 236104#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 236097#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 236092#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 231860#L1065-2 [2023-11-26 11:44:02,234 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:02,234 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2023-11-26 11:44:02,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:02,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167678064] [2023-11-26 11:44:02,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:02,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:02,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:02,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:02,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:02,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [167678064] [2023-11-26 11:44:02,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [167678064] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:02,303 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:02,303 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:44:02,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095994743] [2023-11-26 11:44:02,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:02,304 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:44:02,304 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:02,304 INFO L85 PathProgramCache]: Analyzing trace with hash -2638436, now seen corresponding path program 2 times [2023-11-26 11:44:02,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:02,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898591409] [2023-11-26 11:44:02,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:02,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:02,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:02,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:02,355 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:02,355 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898591409] [2023-11-26 11:44:02,355 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1898591409] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:02,355 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:02,356 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:44:02,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1286482787] [2023-11-26 11:44:02,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:02,356 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:02,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:02,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:44:02,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:44:02,357 INFO L87 Difference]: Start difference. First operand 17449 states and 24766 transitions. cyclomatic complexity: 7333 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:02,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:02,543 INFO L93 Difference]: Finished difference Result 21862 states and 30841 transitions. [2023-11-26 11:44:02,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21862 states and 30841 transitions. [2023-11-26 11:44:02,661 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21596 [2023-11-26 11:44:02,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21862 states to 21862 states and 30841 transitions. [2023-11-26 11:44:02,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21862 [2023-11-26 11:44:02,767 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21862 [2023-11-26 11:44:02,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21862 states and 30841 transitions. [2023-11-26 11:44:02,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:02,786 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21862 states and 30841 transitions. [2023-11-26 11:44:02,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21862 states and 30841 transitions. [2023-11-26 11:44:03,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21862 to 15306. [2023-11-26 11:44:03,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15306 states, 15306 states have (on average 1.4125833006664053) internal successors, (21621), 15305 states have internal predecessors, (21621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:03,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15306 states to 15306 states and 21621 transitions. [2023-11-26 11:44:03,316 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15306 states and 21621 transitions. [2023-11-26 11:44:03,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:44:03,317 INFO L428 stractBuchiCegarLoop]: Abstraction has 15306 states and 21621 transitions. [2023-11-26 11:44:03,317 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 11:44:03,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15306 states and 21621 transitions. [2023-11-26 11:44:03,368 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15104 [2023-11-26 11:44:03,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:03,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:03,370 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:03,370 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:03,370 INFO L748 eck$LassoCheckResult]: Stem: 271258#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 271259#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 271436#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 271437#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 271599#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 271159#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 271160#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 270989#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 270990#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 270964#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 270965#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 271137#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 271290#L696 assume !(0 == ~M_E~0); 271291#L696-2 assume !(0 == ~T1_E~0); 271603#L701-1 assume !(0 == ~T2_E~0); 271605#L706-1 assume !(0 == ~T3_E~0); 271408#L711-1 assume !(0 == ~T4_E~0); 271194#L716-1 assume !(0 == ~T5_E~0); 271195#L721-1 assume !(0 == ~T6_E~0); 271360#L726-1 assume !(0 == ~E_M~0); 271361#L731-1 assume !(0 == ~E_1~0); 271327#L736-1 assume !(0 == ~E_2~0); 271328#L741-1 assume !(0 == ~E_3~0); 271417#L746-1 assume !(0 == ~E_4~0); 271216#L751-1 assume !(0 == ~E_5~0); 271217#L756-1 assume !(0 == ~E_6~0); 271191#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 271011#L346 assume !(1 == ~m_pc~0); 271012#L346-2 is_master_triggered_~__retres1~0#1 := 0; 271231#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 271221#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 271222#L861 assume !(0 != activate_threads_~tmp~1#1); 271574#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 271045#L365 assume !(1 == ~t1_pc~0); 271046#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 271587#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 270997#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 270998#L869 assume !(0 != activate_threads_~tmp___0~0#1); 271034#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 271472#L384 assume !(1 == ~t2_pc~0); 271468#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 271469#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 271441#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270954#L877 assume !(0 != activate_threads_~tmp___1~0#1); 270955#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 271306#L403 assume !(1 == ~t3_pc~0); 271307#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 271508#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 270927#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270928#L885 assume !(0 != activate_threads_~tmp___2~0#1); 271300#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 271301#L422 assume !(1 == ~t4_pc~0); 271434#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 271435#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 271098#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 271099#L893 assume !(0 != activate_threads_~tmp___3~0#1); 271384#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 270966#L441 assume !(1 == ~t5_pc~0); 270967#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 271570#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 271233#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 271234#L901 assume !(0 != activate_threads_~tmp___4~0#1); 271396#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 271397#L460 assume !(1 == ~t6_pc~0); 271529#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 270975#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 270976#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 271419#L909 assume !(0 != activate_threads_~tmp___5~0#1); 271524#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 271371#L774 assume !(1 == ~M_E~0); 271372#L774-2 assume !(1 == ~T1_E~0); 271544#L779-1 assume !(1 == ~T2_E~0); 271275#L784-1 assume !(1 == ~T3_E~0); 271276#L789-1 assume !(1 == ~T4_E~0); 271028#L794-1 assume !(1 == ~T5_E~0); 271029#L799-1 assume !(1 == ~T6_E~0); 271638#L804-1 assume !(1 == ~E_M~0); 271639#L809-1 assume !(1 == ~E_1~0); 271356#L814-1 assume !(1 == ~E_2~0); 270933#L819-1 assume !(1 == ~E_3~0); 270934#L824-1 assume !(1 == ~E_4~0); 271427#L829-1 assume !(1 == ~E_5~0); 271533#L834-1 assume !(1 == ~E_6~0); 271179#L839-1 assume { :end_inline_reset_delta_events } true; 271180#L1065-2 [2023-11-26 11:44:03,371 INFO L750 eck$LassoCheckResult]: Loop: 271180#L1065-2 assume !false; 277902#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 277895#L671-1 assume !false; 277890#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 277742#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 277729#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 277723#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 277591#L582 assume !(0 != eval_~tmp~0#1); 277592#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 278880#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 278879#L696-3 assume !(0 == ~M_E~0); 278878#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 278877#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 278876#L706-3 assume !(0 == ~T3_E~0); 278875#L711-3 assume !(0 == ~T4_E~0); 278874#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 278873#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 278872#L726-3 assume !(0 == ~E_M~0); 278871#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 278870#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 278869#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 278868#L746-3 assume !(0 == ~E_4~0); 278867#L751-3 assume !(0 == ~E_5~0); 278866#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 278865#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 278864#L346-24 assume !(1 == ~m_pc~0); 278862#L346-26 is_master_triggered_~__retres1~0#1 := 0; 278861#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 278860#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 278859#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 278858#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 278857#L365-24 assume !(1 == ~t1_pc~0); 278856#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 278855#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278854#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 278853#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 278852#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278851#L384-24 assume !(1 == ~t2_pc~0); 278849#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 278848#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 278847#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 278846#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 278845#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278844#L403-24 assume !(1 == ~t3_pc~0); 278843#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 278842#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 278841#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 278840#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 278839#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278838#L422-24 assume !(1 == ~t4_pc~0); 278837#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 278836#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 278835#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 278834#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 278833#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 278832#L441-24 assume 1 == ~t5_pc~0; 278830#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 278829#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 278828#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 278827#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 278825#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 278824#L460-24 assume !(1 == ~t6_pc~0); 278823#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 278822#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 278821#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 278820#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 278819#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 278818#L774-3 assume !(1 == ~M_E~0); 273893#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 278817#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 278816#L784-3 assume !(1 == ~T3_E~0); 278815#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 278814#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 278813#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 278812#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 278811#L809-3 assume !(1 == ~E_1~0); 278810#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 278809#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 278808#L824-3 assume !(1 == ~E_4~0); 278806#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 278804#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 278802#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 278796#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 278791#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 278789#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 274694#L1084 assume !(0 == start_simulation_~tmp~3#1); 274695#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 277997#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 277989#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 277987#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 277985#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 277939#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 277929#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 277918#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 271180#L1065-2 [2023-11-26 11:44:03,371 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:03,372 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2023-11-26 11:44:03,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:03,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682307578] [2023-11-26 11:44:03,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:03,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:03,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:03,387 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:03,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:03,457 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:03,459 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:03,459 INFO L85 PathProgramCache]: Analyzing trace with hash -599924771, now seen corresponding path program 1 times [2023-11-26 11:44:03,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:03,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [650416151] [2023-11-26 11:44:03,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:03,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:03,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:03,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:03,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:03,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [650416151] [2023-11-26 11:44:03,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [650416151] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:03,504 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:03,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:44:03,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1617294784] [2023-11-26 11:44:03,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:03,506 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:03,506 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:03,506 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:44:03,506 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:44:03,507 INFO L87 Difference]: Start difference. First operand 15306 states and 21621 transitions. cyclomatic complexity: 6331 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:03,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:03,649 INFO L93 Difference]: Finished difference Result 22965 states and 32247 transitions. [2023-11-26 11:44:03,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22965 states and 32247 transitions. [2023-11-26 11:44:03,752 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22660 [2023-11-26 11:44:03,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22965 states to 22965 states and 32247 transitions. [2023-11-26 11:44:03,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22965 [2023-11-26 11:44:03,847 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22965 [2023-11-26 11:44:03,847 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22965 states and 32247 transitions. [2023-11-26 11:44:03,862 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:03,862 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22965 states and 32247 transitions. [2023-11-26 11:44:03,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22965 states and 32247 transitions. [2023-11-26 11:44:04,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22965 to 22805. [2023-11-26 11:44:04,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22805 states, 22805 states have (on average 1.4028064021048017) internal successors, (31991), 22804 states have internal predecessors, (31991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:04,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22805 states to 22805 states and 31991 transitions. [2023-11-26 11:44:04,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22805 states and 31991 transitions. [2023-11-26 11:44:04,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:44:04,367 INFO L428 stractBuchiCegarLoop]: Abstraction has 22805 states and 31991 transitions. [2023-11-26 11:44:04,367 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 11:44:04,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22805 states and 31991 transitions. [2023-11-26 11:44:04,439 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22500 [2023-11-26 11:44:04,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:04,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:04,441 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:04,441 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:04,442 INFO L748 eck$LassoCheckResult]: Stem: 309534#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 309535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 309713#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 309714#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 309896#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 309431#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 309432#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 309267#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 309268#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 309240#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 309241#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 309410#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 309568#L696 assume !(0 == ~M_E~0); 309569#L696-2 assume !(0 == ~T1_E~0); 309906#L701-1 assume !(0 == ~T2_E~0); 309909#L706-1 assume !(0 == ~T3_E~0); 309687#L711-1 assume !(0 == ~T4_E~0); 309469#L716-1 assume !(0 == ~T5_E~0); 309470#L721-1 assume !(0 == ~T6_E~0); 309640#L726-1 assume !(0 == ~E_M~0); 309641#L731-1 assume 0 == ~E_1~0;~E_1~0 := 1; 309866#L736-1 assume !(0 == ~E_2~0); 309697#L741-1 assume !(0 == ~E_3~0); 309698#L746-1 assume !(0 == ~E_4~0); 309491#L751-1 assume !(0 == ~E_5~0); 309492#L756-1 assume !(0 == ~E_6~0); 309583#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 309287#L346 assume !(1 == ~m_pc~0); 309288#L346-2 is_master_triggered_~__retres1~0#1 := 0; 310048#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 309496#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 309497#L861 assume !(0 != activate_threads_~tmp~1#1); 310047#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 309320#L365 assume !(1 == ~t1_pc~0); 309321#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 309881#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 309892#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 310044#L869 assume !(0 != activate_threads_~tmp___0~0#1); 309756#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 309757#L384 assume !(1 == ~t2_pc~0); 309883#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 309980#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 309981#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 309230#L877 assume !(0 != activate_threads_~tmp___1~0#1); 309231#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 309584#L403 assume !(1 == ~t3_pc~0); 309585#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 309796#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 309202#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 309203#L885 assume !(0 != activate_threads_~tmp___2~0#1); 309578#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 309579#L422 assume !(1 == ~t4_pc~0); 309711#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 309712#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 309372#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 309373#L893 assume !(0 != activate_threads_~tmp___3~0#1); 309844#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 310034#L441 assume !(1 == ~t5_pc~0); 309917#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 309970#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 309509#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 309510#L901 assume !(0 != activate_threads_~tmp___4~0#1); 310013#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 310027#L460 assume !(1 == ~t6_pc~0); 310026#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 310025#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 309700#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 309701#L909 assume !(0 != activate_threads_~tmp___5~0#1); 309813#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309651#L774 assume !(1 == ~M_E~0); 309652#L774-2 assume !(1 == ~T1_E~0); 309832#L779-1 assume !(1 == ~T2_E~0); 309552#L784-1 assume !(1 == ~T3_E~0); 309553#L789-1 assume !(1 == ~T4_E~0); 309304#L794-1 assume !(1 == ~T5_E~0); 309305#L799-1 assume !(1 == ~T6_E~0); 309957#L804-1 assume !(1 == ~E_M~0); 309958#L809-1 assume 1 == ~E_1~0;~E_1~0 := 2; 309636#L814-1 assume !(1 == ~E_2~0); 309208#L819-1 assume !(1 == ~E_3~0); 309209#L824-1 assume !(1 == ~E_4~0); 309707#L829-1 assume !(1 == ~E_5~0); 309822#L834-1 assume !(1 == ~E_6~0); 309452#L839-1 assume { :end_inline_reset_delta_events } true; 309453#L1065-2 [2023-11-26 11:44:04,442 INFO L750 eck$LassoCheckResult]: Loop: 309453#L1065-2 assume !false; 314255#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 314252#L671-1 assume !false; 314250#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 314245#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 314236#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 314234#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 314231#L582 assume !(0 != eval_~tmp~0#1); 314229#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 314226#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 314224#L696-3 assume !(0 == ~M_E~0); 314222#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 314220#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 314218#L706-3 assume !(0 == ~T3_E~0); 314216#L711-3 assume !(0 == ~T4_E~0); 314214#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 314212#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 314211#L726-3 assume !(0 == ~E_M~0); 314206#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 314204#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 314202#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 314201#L746-3 assume !(0 == ~E_4~0); 314198#L751-3 assume !(0 == ~E_5~0); 314197#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 314196#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 314195#L346-24 assume !(1 == ~m_pc~0); 314193#L346-26 is_master_triggered_~__retres1~0#1 := 0; 314191#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 314188#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 314184#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 314180#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 314178#L365-24 assume !(1 == ~t1_pc~0); 314176#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 314175#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 314174#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 314173#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 314172#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 314171#L384-24 assume !(1 == ~t2_pc~0); 314169#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 314168#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 314166#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 314165#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 314162#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 314160#L403-24 assume !(1 == ~t3_pc~0); 314158#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 314156#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 314154#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 314152#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 314149#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 314148#L422-24 assume !(1 == ~t4_pc~0); 314146#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 314144#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 314142#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 314140#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 314137#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 314135#L441-24 assume !(1 == ~t5_pc~0); 314132#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 314130#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 314128#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 314120#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 314118#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 314116#L460-24 assume !(1 == ~t6_pc~0); 314114#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 314112#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314110#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 314108#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 314106#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 314104#L774-3 assume !(1 == ~M_E~0); 313685#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 314099#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 314097#L784-3 assume !(1 == ~T3_E~0); 314095#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 314093#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 314092#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 314089#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 314087#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 314059#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 314054#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 314046#L824-3 assume !(1 == ~E_4~0); 314040#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 314034#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 314029#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 314014#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 314005#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 313997#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 313986#L1084 assume !(0 == start_simulation_~tmp~3#1); 313987#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 314582#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 314574#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 314573#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 314572#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 314570#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 314568#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 314566#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 309453#L1065-2 [2023-11-26 11:44:04,442 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:04,443 INFO L85 PathProgramCache]: Analyzing trace with hash 1678656137, now seen corresponding path program 1 times [2023-11-26 11:44:04,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:04,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061578448] [2023-11-26 11:44:04,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:04,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:04,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:04,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:04,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:04,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061578448] [2023-11-26 11:44:04,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061578448] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:04,504 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:04,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:44:04,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025427311] [2023-11-26 11:44:04,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:04,506 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:44:04,507 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:04,507 INFO L85 PathProgramCache]: Analyzing trace with hash 132090588, now seen corresponding path program 1 times [2023-11-26 11:44:04,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:04,507 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048504616] [2023-11-26 11:44:04,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:04,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:04,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:04,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:04,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:04,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048504616] [2023-11-26 11:44:04,597 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1048504616] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:04,597 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:04,597 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:44:04,597 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1063361234] [2023-11-26 11:44:04,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:04,598 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:04,601 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:04,601 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:44:04,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:44:04,602 INFO L87 Difference]: Start difference. First operand 22805 states and 31991 transitions. cyclomatic complexity: 9202 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:04,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:04,814 INFO L93 Difference]: Finished difference Result 30824 states and 43184 transitions. [2023-11-26 11:44:04,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30824 states and 43184 transitions. [2023-11-26 11:44:04,963 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 29728 [2023-11-26 11:44:05,335 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30824 states to 30824 states and 43184 transitions. [2023-11-26 11:44:05,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30824 [2023-11-26 11:44:05,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30824 [2023-11-26 11:44:05,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30824 states and 43184 transitions. [2023-11-26 11:44:05,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:05,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30824 states and 43184 transitions. [2023-11-26 11:44:05,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30824 states and 43184 transitions. [2023-11-26 11:44:05,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30824 to 21710. [2023-11-26 11:44:05,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21710 states, 21710 states have (on average 1.4013818516812528) internal successors, (30424), 21709 states have internal predecessors, (30424), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:05,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21710 states to 21710 states and 30424 transitions. [2023-11-26 11:44:05,703 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21710 states and 30424 transitions. [2023-11-26 11:44:05,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:44:05,704 INFO L428 stractBuchiCegarLoop]: Abstraction has 21710 states and 30424 transitions. [2023-11-26 11:44:05,705 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 11:44:05,705 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21710 states and 30424 transitions. [2023-11-26 11:44:05,777 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21468 [2023-11-26 11:44:05,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:05,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:05,780 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:05,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:05,780 INFO L748 eck$LassoCheckResult]: Stem: 363179#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 363180#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 363368#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 363369#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 363563#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 363074#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 363075#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 362904#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 362905#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 362881#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 362882#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 363049#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 363216#L696 assume !(0 == ~M_E~0); 363217#L696-2 assume !(0 == ~T1_E~0); 363569#L701-1 assume !(0 == ~T2_E~0); 363571#L706-1 assume !(0 == ~T3_E~0); 363336#L711-1 assume !(0 == ~T4_E~0); 363109#L716-1 assume !(0 == ~T5_E~0); 363110#L721-1 assume !(0 == ~T6_E~0); 363287#L726-1 assume !(0 == ~E_M~0); 363288#L731-1 assume !(0 == ~E_1~0); 363254#L736-1 assume !(0 == ~E_2~0); 363255#L741-1 assume !(0 == ~E_3~0); 363349#L746-1 assume !(0 == ~E_4~0); 363137#L751-1 assume !(0 == ~E_5~0); 363138#L756-1 assume !(0 == ~E_6~0); 363106#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 362926#L346 assume !(1 == ~m_pc~0); 362927#L346-2 is_master_triggered_~__retres1~0#1 := 0; 363150#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 363142#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 363143#L861 assume !(0 != activate_threads_~tmp~1#1); 363529#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 362960#L365 assume !(1 == ~t1_pc~0); 362961#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 363551#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 362910#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 362911#L869 assume !(0 != activate_threads_~tmp___0~0#1); 362950#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 363417#L384 assume !(1 == ~t2_pc~0); 363411#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 363412#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 363372#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 362869#L877 assume !(0 != activate_threads_~tmp___1~0#1); 362870#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 363232#L403 assume !(1 == ~t3_pc~0); 363233#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 363455#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 362844#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 362845#L885 assume !(0 != activate_threads_~tmp___2~0#1); 363225#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 363226#L422 assume !(1 == ~t4_pc~0); 363366#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 363367#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 363012#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 363013#L893 assume !(0 != activate_threads_~tmp___3~0#1); 363314#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 362883#L441 assume !(1 == ~t5_pc~0); 362884#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 363525#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 363153#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 363154#L901 assume !(0 != activate_threads_~tmp___4~0#1); 363323#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 363324#L460 assume !(1 == ~t6_pc~0); 363479#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 362890#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 362891#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 363351#L909 assume !(0 != activate_threads_~tmp___5~0#1); 363475#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363299#L774 assume !(1 == ~M_E~0); 363300#L774-2 assume !(1 == ~T1_E~0); 363496#L779-1 assume !(1 == ~T2_E~0); 363200#L784-1 assume !(1 == ~T3_E~0); 363201#L789-1 assume !(1 == ~T4_E~0); 362945#L794-1 assume !(1 == ~T5_E~0); 362946#L799-1 assume !(1 == ~T6_E~0); 363624#L804-1 assume !(1 == ~E_M~0); 363625#L809-1 assume !(1 == ~E_1~0); 363282#L814-1 assume !(1 == ~E_2~0); 362848#L819-1 assume !(1 == ~E_3~0); 362849#L824-1 assume !(1 == ~E_4~0); 363359#L829-1 assume !(1 == ~E_5~0); 363485#L834-1 assume !(1 == ~E_6~0); 363090#L839-1 assume { :end_inline_reset_delta_events } true; 363091#L1065-2 [2023-11-26 11:44:05,781 INFO L750 eck$LassoCheckResult]: Loop: 363091#L1065-2 assume !false; 369531#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 369528#L671-1 assume !false; 369525#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 369520#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 369513#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 369511#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 369508#L582 assume !(0 != eval_~tmp~0#1); 369506#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 369504#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 369502#L696-3 assume !(0 == ~M_E~0); 369499#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 369495#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 369491#L706-3 assume !(0 == ~T3_E~0); 369480#L711-3 assume !(0 == ~T4_E~0); 368279#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 367869#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 367866#L726-3 assume !(0 == ~E_M~0); 367864#L731-3 assume !(0 == ~E_1~0); 367862#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 367860#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 367858#L746-3 assume !(0 == ~E_4~0); 367856#L751-3 assume !(0 == ~E_5~0); 367854#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 367852#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 367850#L346-24 assume !(1 == ~m_pc~0); 367847#L346-26 is_master_triggered_~__retres1~0#1 := 0; 367845#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 367842#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 367840#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 367838#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 367836#L365-24 assume !(1 == ~t1_pc~0); 367834#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 367821#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 367815#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 367809#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 367804#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 367803#L384-24 assume !(1 == ~t2_pc~0); 367799#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 367797#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 367795#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 367793#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 367791#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 367788#L403-24 assume !(1 == ~t3_pc~0); 367786#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 367784#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 367778#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 367773#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 367768#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 367762#L422-24 assume !(1 == ~t4_pc~0); 367757#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 367752#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 367747#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 367742#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 367737#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 367734#L441-24 assume !(1 == ~t5_pc~0); 367729#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 367724#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 367718#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 367712#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 367710#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 367707#L460-24 assume !(1 == ~t6_pc~0); 367705#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 367703#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 367700#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 367698#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 367696#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 367694#L774-3 assume !(1 == ~M_E~0); 366366#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 367691#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 367689#L784-3 assume !(1 == ~T3_E~0); 367687#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 367685#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 367684#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 367682#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 367680#L809-3 assume !(1 == ~E_1~0); 367678#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 367676#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 367674#L824-3 assume !(1 == ~E_4~0); 367664#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 367651#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 367636#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 367628#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 367499#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 367496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 366510#L1084 assume !(0 == start_simulation_~tmp~3#1); 366511#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 369646#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 369638#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 369636#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 369634#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 369631#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 369629#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 369627#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 363091#L1065-2 [2023-11-26 11:44:05,784 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:05,785 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2023-11-26 11:44:05,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:05,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517111526] [2023-11-26 11:44:05,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:05,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:05,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:05,799 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:05,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:05,853 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:05,854 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:05,854 INFO L85 PathProgramCache]: Analyzing trace with hash 660777244, now seen corresponding path program 1 times [2023-11-26 11:44:05,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:05,855 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423657376] [2023-11-26 11:44:05,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:05,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:05,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:05,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:05,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:05,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423657376] [2023-11-26 11:44:05,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1423657376] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:05,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:05,928 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:44:05,928 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [426483707] [2023-11-26 11:44:05,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:05,929 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:05,929 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:05,930 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:44:05,930 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:44:05,931 INFO L87 Difference]: Start difference. First operand 21710 states and 30424 transitions. cyclomatic complexity: 8730 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:06,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:06,466 INFO L93 Difference]: Finished difference Result 39290 states and 54468 transitions. [2023-11-26 11:44:06,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39290 states and 54468 transitions. [2023-11-26 11:44:06,698 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 38896 [2023-11-26 11:44:06,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39290 states to 39290 states and 54468 transitions. [2023-11-26 11:44:06,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39290 [2023-11-26 11:44:06,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39290 [2023-11-26 11:44:06,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39290 states and 54468 transitions. [2023-11-26 11:44:06,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:06,899 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39290 states and 54468 transitions. [2023-11-26 11:44:06,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39290 states and 54468 transitions. [2023-11-26 11:44:07,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39290 to 21854. [2023-11-26 11:44:07,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21854 states, 21854 states have (on average 1.3987370733046582) internal successors, (30568), 21853 states have internal predecessors, (30568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:07,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21854 states to 21854 states and 30568 transitions. [2023-11-26 11:44:07,336 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21854 states and 30568 transitions. [2023-11-26 11:44:07,336 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 11:44:07,337 INFO L428 stractBuchiCegarLoop]: Abstraction has 21854 states and 30568 transitions. [2023-11-26 11:44:07,337 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 11:44:07,337 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21854 states and 30568 transitions. [2023-11-26 11:44:07,428 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21612 [2023-11-26 11:44:07,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:07,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:07,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:07,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:07,431 INFO L748 eck$LassoCheckResult]: Stem: 424195#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 424196#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 424381#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 424382#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 424566#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 424092#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 424093#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 423924#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 423925#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 423897#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 423898#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 424071#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 424231#L696 assume !(0 == ~M_E~0); 424232#L696-2 assume !(0 == ~T1_E~0); 424573#L701-1 assume !(0 == ~T2_E~0); 424575#L706-1 assume !(0 == ~T3_E~0); 424350#L711-1 assume !(0 == ~T4_E~0); 424127#L716-1 assume !(0 == ~T5_E~0); 424128#L721-1 assume !(0 == ~T6_E~0); 424302#L726-1 assume !(0 == ~E_M~0); 424303#L731-1 assume !(0 == ~E_1~0); 424268#L736-1 assume !(0 == ~E_2~0); 424269#L741-1 assume !(0 == ~E_3~0); 424363#L746-1 assume !(0 == ~E_4~0); 424149#L751-1 assume !(0 == ~E_5~0); 424150#L756-1 assume !(0 == ~E_6~0); 424124#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 423944#L346 assume !(1 == ~m_pc~0); 423945#L346-2 is_master_triggered_~__retres1~0#1 := 0; 424167#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 424157#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 424158#L861 assume !(0 != activate_threads_~tmp~1#1); 424535#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 423978#L365 assume !(1 == ~t1_pc~0); 423979#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 424550#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 423930#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 423931#L869 assume !(0 != activate_threads_~tmp___0~0#1); 423967#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 424424#L384 assume !(1 == ~t2_pc~0); 424419#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 424420#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 424386#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 423888#L877 assume !(0 != activate_threads_~tmp___1~0#1); 423889#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 424247#L403 assume !(1 == ~t3_pc~0); 424248#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 424466#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 423861#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 423862#L885 assume !(0 != activate_threads_~tmp___2~0#1); 424241#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 424242#L422 assume !(1 == ~t4_pc~0); 424379#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 424380#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 424033#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 424034#L893 assume !(0 != activate_threads_~tmp___3~0#1); 424327#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 423899#L441 assume !(1 == ~t5_pc~0); 423900#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 424531#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 424169#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 424170#L901 assume !(0 != activate_threads_~tmp___4~0#1); 424339#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 424340#L460 assume !(1 == ~t6_pc~0); 424485#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 423908#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 423909#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 424365#L909 assume !(0 != activate_threads_~tmp___5~0#1); 424480#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 424312#L774 assume !(1 == ~M_E~0); 424313#L774-2 assume !(1 == ~T1_E~0); 424501#L779-1 assume !(1 == ~T2_E~0); 424213#L784-1 assume !(1 == ~T3_E~0); 424214#L789-1 assume !(1 == ~T4_E~0); 423962#L794-1 assume !(1 == ~T5_E~0); 423963#L799-1 assume !(1 == ~T6_E~0); 424625#L804-1 assume !(1 == ~E_M~0); 424626#L809-1 assume !(1 == ~E_1~0); 424298#L814-1 assume !(1 == ~E_2~0); 423867#L819-1 assume !(1 == ~E_3~0); 423868#L824-1 assume !(1 == ~E_4~0); 424373#L829-1 assume !(1 == ~E_5~0); 424489#L834-1 assume !(1 == ~E_6~0); 424112#L839-1 assume { :end_inline_reset_delta_events } true; 424113#L1065-2 [2023-11-26 11:44:07,431 INFO L750 eck$LassoCheckResult]: Loop: 424113#L1065-2 assume !false; 438403#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 438397#L671-1 assume !false; 437916#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 437913#L530 assume !(0 == ~m_st~0); 437914#L534 assume !(0 == ~t1_st~0); 437909#L538 assume !(0 == ~t2_st~0); 437910#L542 assume !(0 == ~t3_st~0); 437912#L546 assume !(0 == ~t4_st~0); 437907#L550 assume !(0 == ~t5_st~0); 437908#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 437911#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 432944#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 432945#L582 assume !(0 != eval_~tmp~0#1); 437901#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 437900#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 437899#L696-3 assume !(0 == ~M_E~0); 437898#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 437897#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 437896#L706-3 assume !(0 == ~T3_E~0); 437895#L711-3 assume !(0 == ~T4_E~0); 437894#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 437893#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 437892#L726-3 assume !(0 == ~E_M~0); 437891#L731-3 assume !(0 == ~E_1~0); 437890#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 437889#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 437888#L746-3 assume !(0 == ~E_4~0); 437887#L751-3 assume !(0 == ~E_5~0); 437886#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 437885#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 437884#L346-24 assume !(1 == ~m_pc~0); 437882#L346-26 is_master_triggered_~__retres1~0#1 := 0; 437881#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 437880#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 437879#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 437878#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 437877#L365-24 assume !(1 == ~t1_pc~0); 437876#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 437875#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 437874#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 437873#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 437872#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 437871#L384-24 assume 1 == ~t2_pc~0; 437870#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 437868#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 437867#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 437866#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 437865#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 437864#L403-24 assume !(1 == ~t3_pc~0); 437863#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 437862#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 437861#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 437860#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 437859#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 437858#L422-24 assume !(1 == ~t4_pc~0); 437857#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 437856#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 437855#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 437854#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 437853#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 437852#L441-24 assume !(1 == ~t5_pc~0); 437850#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 437848#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 437846#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 437843#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 437842#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 437841#L460-24 assume !(1 == ~t6_pc~0); 437840#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 437839#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 437838#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 437837#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 437836#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 437835#L774-3 assume !(1 == ~M_E~0); 437538#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 437834#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 437833#L784-3 assume !(1 == ~T3_E~0); 437832#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 437831#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 437830#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 437829#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 437828#L809-3 assume !(1 == ~E_1~0); 437827#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 437826#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 437825#L824-3 assume !(1 == ~E_4~0); 437824#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 437823#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 437822#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 437818#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 437813#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 437811#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 437808#L1084 assume !(0 == start_simulation_~tmp~3#1); 437809#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 438546#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 438536#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 438533#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 438528#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 438525#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 438522#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 438517#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 424113#L1065-2 [2023-11-26 11:44:07,434 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:07,434 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2023-11-26 11:44:07,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:07,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548047592] [2023-11-26 11:44:07,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:07,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:07,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:07,451 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:07,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:07,487 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:07,488 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:07,488 INFO L85 PathProgramCache]: Analyzing trace with hash -1847581078, now seen corresponding path program 1 times [2023-11-26 11:44:07,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:07,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778907446] [2023-11-26 11:44:07,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:07,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:07,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:07,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:07,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:07,601 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1778907446] [2023-11-26 11:44:07,601 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1778907446] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:07,601 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:07,601 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:44:07,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464766924] [2023-11-26 11:44:07,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:07,602 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:07,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:07,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:44:07,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:44:07,604 INFO L87 Difference]: Start difference. First operand 21854 states and 30568 transitions. cyclomatic complexity: 8730 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:08,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:08,118 INFO L93 Difference]: Finished difference Result 56268 states and 76973 transitions. [2023-11-26 11:44:08,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56268 states and 76973 transitions. [2023-11-26 11:44:08,702 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 55772 [2023-11-26 11:44:08,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56268 states to 56268 states and 76973 transitions. [2023-11-26 11:44:08,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56268 [2023-11-26 11:44:08,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56268 [2023-11-26 11:44:08,910 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56268 states and 76973 transitions. [2023-11-26 11:44:08,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:08,970 INFO L218 hiAutomatonCegarLoop]: Abstraction has 56268 states and 76973 transitions. [2023-11-26 11:44:09,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56268 states and 76973 transitions. [2023-11-26 11:44:09,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56268 to 22745. [2023-11-26 11:44:09,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22745 states, 22745 states have (on average 1.3831171686084853) internal successors, (31459), 22744 states have internal predecessors, (31459), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:09,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22745 states to 22745 states and 31459 transitions. [2023-11-26 11:44:09,348 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22745 states and 31459 transitions. [2023-11-26 11:44:09,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:44:09,349 INFO L428 stractBuchiCegarLoop]: Abstraction has 22745 states and 31459 transitions. [2023-11-26 11:44:09,350 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 11:44:09,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22745 states and 31459 transitions. [2023-11-26 11:44:09,425 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22500 [2023-11-26 11:44:09,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:09,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:09,429 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:09,429 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:09,430 INFO L748 eck$LassoCheckResult]: Stem: 502332#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 502333#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 502512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 502513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 502710#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 502230#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 502231#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 502056#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 502057#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 502033#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 502034#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 502205#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 502366#L696 assume !(0 == ~M_E~0); 502367#L696-2 assume !(0 == ~T1_E~0); 502717#L701-1 assume !(0 == ~T2_E~0); 502719#L706-1 assume !(0 == ~T3_E~0); 502484#L711-1 assume !(0 == ~T4_E~0); 502266#L716-1 assume !(0 == ~T5_E~0); 502267#L721-1 assume !(0 == ~T6_E~0); 502438#L726-1 assume !(0 == ~E_M~0); 502439#L731-1 assume !(0 == ~E_1~0); 502404#L736-1 assume !(0 == ~E_2~0); 502405#L741-1 assume !(0 == ~E_3~0); 502494#L746-1 assume !(0 == ~E_4~0); 502288#L751-1 assume !(0 == ~E_5~0); 502289#L756-1 assume !(0 == ~E_6~0); 502263#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 502077#L346 assume !(1 == ~m_pc~0); 502078#L346-2 is_master_triggered_~__retres1~0#1 := 0; 502304#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 502623#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 502734#L861 assume !(0 != activate_threads_~tmp~1#1); 502683#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 502112#L365 assume !(1 == ~t1_pc~0); 502113#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 502696#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 502061#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 502062#L869 assume !(0 != activate_threads_~tmp___0~0#1); 502102#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 502561#L384 assume !(1 == ~t2_pc~0); 502555#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 502556#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 502516#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 502021#L877 assume !(0 != activate_threads_~tmp___1~0#1); 502022#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 502382#L403 assume !(1 == ~t3_pc~0); 502383#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 502603#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 501996#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 501997#L885 assume !(0 != activate_threads_~tmp___2~0#1); 502375#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 502376#L422 assume !(1 == ~t4_pc~0); 502510#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 502511#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 502167#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 502168#L893 assume !(0 != activate_threads_~tmp___3~0#1); 502461#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 502035#L441 assume !(1 == ~t5_pc~0); 502036#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 502676#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 502307#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 502308#L901 assume !(0 != activate_threads_~tmp___4~0#1); 502471#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 502472#L460 assume !(1 == ~t6_pc~0); 502627#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 502042#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 502043#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 502496#L909 assume !(0 != activate_threads_~tmp___5~0#1); 502624#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 502448#L774 assume !(1 == ~M_E~0); 502449#L774-2 assume !(1 == ~T1_E~0); 502648#L779-1 assume !(1 == ~T2_E~0); 502351#L784-1 assume !(1 == ~T3_E~0); 502352#L789-1 assume !(1 == ~T4_E~0); 502097#L794-1 assume !(1 == ~T5_E~0); 502098#L799-1 assume !(1 == ~T6_E~0); 502768#L804-1 assume !(1 == ~E_M~0); 502769#L809-1 assume !(1 == ~E_1~0); 502433#L814-1 assume !(1 == ~E_2~0); 502000#L819-1 assume !(1 == ~E_3~0); 502001#L824-1 assume !(1 == ~E_4~0); 502502#L829-1 assume !(1 == ~E_5~0); 502633#L834-1 assume !(1 == ~E_6~0); 502247#L839-1 assume { :end_inline_reset_delta_events } true; 502248#L1065-2 [2023-11-26 11:44:09,430 INFO L750 eck$LassoCheckResult]: Loop: 502248#L1065-2 assume !false; 505800#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 504961#L671-1 assume !false; 505799#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 505797#L530 assume !(0 == ~m_st~0); 505798#L534 assume !(0 == ~t1_st~0); 505793#L538 assume !(0 == ~t2_st~0); 505794#L542 assume !(0 == ~t3_st~0); 505796#L546 assume !(0 == ~t4_st~0); 505791#L550 assume !(0 == ~t5_st~0); 505792#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 505795#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 505698#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 505699#L582 assume !(0 != eval_~tmp~0#1); 506043#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 506042#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 506041#L696-3 assume !(0 == ~M_E~0); 506040#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 506039#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 506038#L706-3 assume !(0 == ~T3_E~0); 506037#L711-3 assume !(0 == ~T4_E~0); 506036#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 506035#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 506034#L726-3 assume !(0 == ~E_M~0); 506033#L731-3 assume !(0 == ~E_1~0); 506032#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 506031#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 506030#L746-3 assume !(0 == ~E_4~0); 506029#L751-3 assume !(0 == ~E_5~0); 506028#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 506027#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 506026#L346-24 assume !(1 == ~m_pc~0); 506025#L346-26 is_master_triggered_~__retres1~0#1 := 0; 506023#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 506021#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 506019#L861-24 assume !(0 != activate_threads_~tmp~1#1); 505983#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 505980#L365-24 assume !(1 == ~t1_pc~0); 505977#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 505974#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 505971#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 505968#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 505965#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505962#L384-24 assume 1 == ~t2_pc~0; 505958#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 505953#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 505950#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 505947#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 505944#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 505941#L403-24 assume !(1 == ~t3_pc~0); 505938#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 505935#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 505932#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 505929#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 505926#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 505923#L422-24 assume !(1 == ~t4_pc~0); 505920#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 505917#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 505914#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 505911#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 505908#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 505905#L441-24 assume !(1 == ~t5_pc~0); 505901#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 505895#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 505889#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 505883#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 505878#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 505875#L460-24 assume !(1 == ~t6_pc~0); 505872#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 505869#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 505866#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 505863#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 505860#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 505857#L774-3 assume !(1 == ~M_E~0); 505856#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 505855#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 505854#L784-3 assume !(1 == ~T3_E~0); 505852#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 505849#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 505847#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 505845#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 505843#L809-3 assume !(1 == ~E_1~0); 505841#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 505839#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 505837#L824-3 assume !(1 == ~E_4~0); 505835#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 505833#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 505831#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 505826#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 505821#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 505819#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 505816#L1084 assume !(0 == start_simulation_~tmp~3#1); 505814#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 505813#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 505806#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 505805#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 505804#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 505803#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 505802#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 505801#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 502248#L1065-2 [2023-11-26 11:44:09,431 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:09,431 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2023-11-26 11:44:09,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:09,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273238977] [2023-11-26 11:44:09,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:09,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:09,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:09,451 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:09,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:09,484 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:09,485 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:09,485 INFO L85 PathProgramCache]: Analyzing trace with hash 761206380, now seen corresponding path program 1 times [2023-11-26 11:44:09,486 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:09,486 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075958633] [2023-11-26 11:44:09,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:09,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:09,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:09,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:09,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:09,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075958633] [2023-11-26 11:44:09,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075958633] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:09,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:09,531 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:44:09,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891970619] [2023-11-26 11:44:09,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:09,531 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:09,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:09,532 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:44:09,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:44:09,532 INFO L87 Difference]: Start difference. First operand 22745 states and 31459 transitions. cyclomatic complexity: 8730 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:09,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:09,704 INFO L93 Difference]: Finished difference Result 42629 states and 58207 transitions. [2023-11-26 11:44:09,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42629 states and 58207 transitions. [2023-11-26 11:44:09,898 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42232 [2023-11-26 11:44:10,347 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42629 states to 42629 states and 58207 transitions. [2023-11-26 11:44:10,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42629 [2023-11-26 11:44:10,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42629 [2023-11-26 11:44:10,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42629 states and 58207 transitions. [2023-11-26 11:44:10,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:10,391 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42629 states and 58207 transitions. [2023-11-26 11:44:10,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42629 states and 58207 transitions. [2023-11-26 11:44:10,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42629 to 41189. [2023-11-26 11:44:10,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41189 states, 41189 states have (on average 1.3681079899973294) internal successors, (56351), 41188 states have internal predecessors, (56351), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:10,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41189 states to 41189 states and 56351 transitions. [2023-11-26 11:44:10,964 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41189 states and 56351 transitions. [2023-11-26 11:44:10,965 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:44:10,965 INFO L428 stractBuchiCegarLoop]: Abstraction has 41189 states and 56351 transitions. [2023-11-26 11:44:10,965 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-26 11:44:10,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41189 states and 56351 transitions. [2023-11-26 11:44:11,109 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 40792 [2023-11-26 11:44:11,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:11,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:11,110 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:11,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:11,111 INFO L748 eck$LassoCheckResult]: Stem: 567723#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 567724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 567910#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 567911#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 568085#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 567613#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 567614#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 567437#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 567438#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 567414#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 567415#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 567589#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 567757#L696 assume !(0 == ~M_E~0); 567758#L696-2 assume !(0 == ~T1_E~0); 568089#L701-1 assume !(0 == ~T2_E~0); 568092#L706-1 assume !(0 == ~T3_E~0); 567880#L711-1 assume !(0 == ~T4_E~0); 567653#L716-1 assume !(0 == ~T5_E~0); 567654#L721-1 assume !(0 == ~T6_E~0); 567830#L726-1 assume !(0 == ~E_M~0); 567831#L731-1 assume !(0 == ~E_1~0); 567795#L736-1 assume !(0 == ~E_2~0); 567796#L741-1 assume !(0 == ~E_3~0); 567893#L746-1 assume !(0 == ~E_4~0); 567675#L751-1 assume !(0 == ~E_5~0); 567676#L756-1 assume !(0 == ~E_6~0); 567650#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567460#L346 assume !(1 == ~m_pc~0); 567461#L346-2 is_master_triggered_~__retres1~0#1 := 0; 567689#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 568174#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 568105#L861 assume !(0 != activate_threads_~tmp~1#1); 568055#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567496#L365 assume !(1 == ~t1_pc~0); 567497#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 568068#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567443#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 567444#L869 assume !(0 != activate_threads_~tmp___0~0#1); 567486#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567954#L384 assume !(1 == ~t2_pc~0); 567948#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 567949#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567913#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567402#L877 assume !(0 != activate_threads_~tmp___1~0#1); 567403#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567772#L403 assume !(1 == ~t3_pc~0); 567773#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 567990#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567376#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 567377#L885 assume !(0 != activate_threads_~tmp___2~0#1); 567765#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567766#L422 assume !(1 == ~t4_pc~0); 567908#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 567909#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567551#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 567552#L893 assume !(0 != activate_threads_~tmp___3~0#1); 567857#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 567416#L441 assume !(1 == ~t5_pc~0); 567417#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 568051#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567692#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 567693#L901 assume !(0 != activate_threads_~tmp___4~0#1); 567867#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 567868#L460 assume !(1 == ~t6_pc~0); 568010#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 567423#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 567424#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 567895#L909 assume !(0 != activate_threads_~tmp___5~0#1); 568007#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 567841#L774 assume !(1 == ~M_E~0); 567842#L774-2 assume !(1 == ~T1_E~0); 568027#L779-1 assume !(1 == ~T2_E~0); 567742#L784-1 assume !(1 == ~T3_E~0); 567743#L789-1 assume !(1 == ~T4_E~0); 567480#L794-1 assume !(1 == ~T5_E~0); 567481#L799-1 assume !(1 == ~T6_E~0); 568129#L804-1 assume !(1 == ~E_M~0); 568130#L809-1 assume !(1 == ~E_1~0); 567825#L814-1 assume !(1 == ~E_2~0); 567380#L819-1 assume !(1 == ~E_3~0); 567381#L824-1 assume !(1 == ~E_4~0); 567901#L829-1 assume !(1 == ~E_5~0); 568016#L834-1 assume !(1 == ~E_6~0); 567631#L839-1 assume { :end_inline_reset_delta_events } true; 567632#L1065-2 [2023-11-26 11:44:11,111 INFO L750 eck$LassoCheckResult]: Loop: 567632#L1065-2 assume !false; 571143#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 571140#L671-1 assume !false; 571138#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 571135#L530 assume !(0 == ~m_st~0); 571136#L534 assume !(0 == ~t1_st~0); 573401#L538 assume !(0 == ~t2_st~0); 573399#L542 assume !(0 == ~t3_st~0); 573397#L546 assume !(0 == ~t4_st~0); 573395#L550 assume !(0 == ~t5_st~0); 573392#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 573390#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 573388#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 573386#L582 assume !(0 != eval_~tmp~0#1); 573384#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 573381#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 573379#L696-3 assume !(0 == ~M_E~0); 573377#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 573374#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 573372#L706-3 assume !(0 == ~T3_E~0); 573370#L711-3 assume !(0 == ~T4_E~0); 573368#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 573366#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 573364#L726-3 assume !(0 == ~E_M~0); 573362#L731-3 assume !(0 == ~E_1~0); 573360#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 573356#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 573354#L746-3 assume !(0 == ~E_4~0); 573352#L751-3 assume !(0 == ~E_5~0); 573350#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 573348#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 573346#L346-24 assume 1 == ~m_pc~0; 573343#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 573341#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 573338#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 573335#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 573333#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 573331#L365-24 assume !(1 == ~t1_pc~0); 573329#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 573327#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 573325#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 573322#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 573320#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 573318#L384-24 assume !(1 == ~t2_pc~0); 573313#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 573311#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 573308#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 573306#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 573303#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 573299#L403-24 assume !(1 == ~t3_pc~0); 573298#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 573296#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 573292#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 573288#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 573286#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 573284#L422-24 assume !(1 == ~t4_pc~0); 573282#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 573277#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 573275#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 573273#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 573271#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 573269#L441-24 assume 1 == ~t5_pc~0; 573266#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 573264#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 573262#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 573260#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 573256#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 573254#L460-24 assume !(1 == ~t6_pc~0); 573252#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 573250#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 573248#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 573246#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 573244#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 573235#L774-3 assume !(1 == ~M_E~0); 573233#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 573231#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 573229#L784-3 assume !(1 == ~T3_E~0); 573227#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 573224#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 573222#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 573220#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 573218#L809-3 assume !(1 == ~E_1~0); 573207#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 573200#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 573191#L824-3 assume !(1 == ~E_4~0); 573182#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 573174#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 573111#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 573107#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 573105#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 573103#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 573057#L1084 assume !(0 == start_simulation_~tmp~3#1); 573054#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 573045#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 573010#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 573009#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 572999#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 572991#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 572984#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 572976#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 567632#L1065-2 [2023-11-26 11:44:11,112 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:11,112 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2023-11-26 11:44:11,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:11,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760423590] [2023-11-26 11:44:11,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:11,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:11,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:11,125 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:11,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:11,158 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:11,158 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:11,159 INFO L85 PathProgramCache]: Analyzing trace with hash -1788014231, now seen corresponding path program 1 times [2023-11-26 11:44:11,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:11,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272350474] [2023-11-26 11:44:11,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:11,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:11,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:11,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:11,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:11,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272350474] [2023-11-26 11:44:11,230 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272350474] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:11,230 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:11,230 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:44:11,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145591430] [2023-11-26 11:44:11,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:11,231 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:11,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:11,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:44:11,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:44:11,232 INFO L87 Difference]: Start difference. First operand 41189 states and 56351 transitions. cyclomatic complexity: 15178 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:12,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:12,050 INFO L93 Difference]: Finished difference Result 77123 states and 105120 transitions. [2023-11-26 11:44:12,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77123 states and 105120 transitions. [2023-11-26 11:44:12,339 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 76400 [2023-11-26 11:44:12,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77123 states to 77123 states and 105120 transitions. [2023-11-26 11:44:12,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77123 [2023-11-26 11:44:12,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77123 [2023-11-26 11:44:12,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77123 states and 105120 transitions. [2023-11-26 11:44:12,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:12,592 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77123 states and 105120 transitions. [2023-11-26 11:44:12,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77123 states and 105120 transitions. [2023-11-26 11:44:13,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77123 to 41189. [2023-11-26 11:44:13,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41189 states, 41189 states have (on average 1.3540993954696643) internal successors, (55774), 41188 states have internal predecessors, (55774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:13,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41189 states to 41189 states and 55774 transitions. [2023-11-26 11:44:13,645 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41189 states and 55774 transitions. [2023-11-26 11:44:13,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-26 11:44:13,646 INFO L428 stractBuchiCegarLoop]: Abstraction has 41189 states and 55774 transitions. [2023-11-26 11:44:13,646 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-26 11:44:13,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41189 states and 55774 transitions. [2023-11-26 11:44:13,775 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 40792 [2023-11-26 11:44:13,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:13,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:13,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:13,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:13,778 INFO L748 eck$LassoCheckResult]: Stem: 686039#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 686040#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 686225#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 686226#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 686403#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 685932#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 685933#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 685761#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 685762#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 685736#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 685737#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 685910#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 686075#L696 assume !(0 == ~M_E~0); 686076#L696-2 assume !(0 == ~T1_E~0); 686413#L701-1 assume !(0 == ~T2_E~0); 686415#L706-1 assume !(0 == ~T3_E~0); 686196#L711-1 assume !(0 == ~T4_E~0); 685968#L716-1 assume !(0 == ~T5_E~0); 685969#L721-1 assume !(0 == ~T6_E~0); 686148#L726-1 assume !(0 == ~E_M~0); 686149#L731-1 assume !(0 == ~E_1~0); 686112#L736-1 assume !(0 == ~E_2~0); 686113#L741-1 assume !(0 == ~E_3~0); 686206#L746-1 assume !(0 == ~E_4~0); 685992#L751-1 assume !(0 == ~E_5~0); 685993#L756-1 assume !(0 == ~E_6~0); 685965#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 685783#L346 assume !(1 == ~m_pc~0); 685784#L346-2 is_master_triggered_~__retres1~0#1 := 0; 686007#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 685997#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 685998#L861 assume !(0 != activate_threads_~tmp~1#1); 686377#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 685816#L365 assume !(1 == ~t1_pc~0); 685817#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 686391#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 685769#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 685770#L869 assume !(0 != activate_threads_~tmp___0~0#1); 685805#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 686272#L384 assume !(1 == ~t2_pc~0); 686268#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 686269#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 686232#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 685727#L877 assume !(0 != activate_threads_~tmp___1~0#1); 685728#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 686090#L403 assume !(1 == ~t3_pc~0); 686091#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 686307#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 685699#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 685700#L885 assume !(0 != activate_threads_~tmp___2~0#1); 686085#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 686086#L422 assume !(1 == ~t4_pc~0); 686223#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 686224#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 685867#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 685868#L893 assume !(0 != activate_threads_~tmp___3~0#1); 686172#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 685738#L441 assume !(1 == ~t5_pc~0); 685739#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 686373#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 686518#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 686517#L901 assume !(0 != activate_threads_~tmp___4~0#1); 686182#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 686183#L460 assume !(1 == ~t6_pc~0); 686329#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 685747#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 685748#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 686208#L909 assume !(0 != activate_threads_~tmp___5~0#1); 686324#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 686158#L774 assume !(1 == ~M_E~0); 686159#L774-2 assume !(1 == ~T1_E~0); 686342#L779-1 assume !(1 == ~T2_E~0); 686057#L784-1 assume !(1 == ~T3_E~0); 686058#L789-1 assume !(1 == ~T4_E~0); 685800#L794-1 assume !(1 == ~T5_E~0); 685801#L799-1 assume !(1 == ~T6_E~0); 686458#L804-1 assume !(1 == ~E_M~0); 686459#L809-1 assume !(1 == ~E_1~0); 686144#L814-1 assume !(1 == ~E_2~0); 685705#L819-1 assume !(1 == ~E_3~0); 685706#L824-1 assume !(1 == ~E_4~0); 686215#L829-1 assume !(1 == ~E_5~0); 686332#L834-1 assume !(1 == ~E_6~0); 685951#L839-1 assume { :end_inline_reset_delta_events } true; 685952#L1065-2 [2023-11-26 11:44:13,779 INFO L750 eck$LassoCheckResult]: Loop: 685952#L1065-2 assume !false; 688294#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 688291#L671-1 assume !false; 688289#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 688286#L530 assume !(0 == ~m_st~0); 688287#L534 assume !(0 == ~t1_st~0); 688808#L538 assume !(0 == ~t2_st~0); 688806#L542 assume !(0 == ~t3_st~0); 688804#L546 assume !(0 == ~t4_st~0); 688802#L550 assume !(0 == ~t5_st~0); 688799#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 688797#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 688795#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 688793#L582 assume !(0 != eval_~tmp~0#1); 688791#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 688789#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 688787#L696-3 assume !(0 == ~M_E~0); 688785#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 688783#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 688780#L706-3 assume !(0 == ~T3_E~0); 688778#L711-3 assume !(0 == ~T4_E~0); 688776#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 688773#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 688772#L726-3 assume !(0 == ~E_M~0); 688770#L731-3 assume !(0 == ~E_1~0); 688767#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 688765#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 688763#L746-3 assume !(0 == ~E_4~0); 688758#L751-3 assume !(0 == ~E_5~0); 688756#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 688754#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 688752#L346-24 assume 1 == ~m_pc~0; 688749#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 688676#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 688674#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 688671#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 688669#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 688667#L365-24 assume !(1 == ~t1_pc~0); 688665#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 688663#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 688661#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 688658#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 688656#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 688654#L384-24 assume !(1 == ~t2_pc~0); 688651#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 688649#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 688647#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 688645#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 688643#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 688641#L403-24 assume !(1 == ~t3_pc~0); 688639#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 688637#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 688635#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 688633#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 688631#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 688630#L422-24 assume !(1 == ~t4_pc~0); 688629#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 688628#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 688626#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 688625#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 688624#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 688623#L441-24 assume 1 == ~t5_pc~0; 688622#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 688620#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 688618#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 688616#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 688613#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 688611#L460-24 assume !(1 == ~t6_pc~0); 688609#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 688607#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 688605#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 688603#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 688600#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 688519#L774-3 assume !(1 == ~M_E~0); 688517#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 688513#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 688511#L784-3 assume !(1 == ~T3_E~0); 688509#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 688507#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 688504#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 688502#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 688500#L809-3 assume !(1 == ~E_1~0); 688498#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 688496#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 688494#L824-3 assume !(1 == ~E_4~0); 688492#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 688490#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 688488#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 688484#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 688482#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 688480#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 688477#L1084 assume !(0 == start_simulation_~tmp~3#1); 688474#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 688471#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 688469#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 688467#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 688465#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 688463#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 688461#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 688459#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 685952#L1065-2 [2023-11-26 11:44:13,779 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:13,780 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 6 times [2023-11-26 11:44:13,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:13,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824151006] [2023-11-26 11:44:13,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:13,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:13,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:13,797 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:13,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:13,826 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:13,827 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:13,827 INFO L85 PathProgramCache]: Analyzing trace with hash -944008729, now seen corresponding path program 1 times [2023-11-26 11:44:13,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:13,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [276482605] [2023-11-26 11:44:13,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:13,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:13,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:13,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:13,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:13,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [276482605] [2023-11-26 11:44:13,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [276482605] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:13,924 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:13,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:44:13,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [748579705] [2023-11-26 11:44:13,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:13,925 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:13,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:13,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:44:13,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:44:13,926 INFO L87 Difference]: Start difference. First operand 41189 states and 55774 transitions. cyclomatic complexity: 14601 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:14,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:14,418 INFO L93 Difference]: Finished difference Result 66429 states and 88877 transitions. [2023-11-26 11:44:14,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66429 states and 88877 transitions. [2023-11-26 11:44:14,716 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65872 [2023-11-26 11:44:14,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66429 states to 66429 states and 88877 transitions. [2023-11-26 11:44:14,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66429 [2023-11-26 11:44:14,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66429 [2023-11-26 11:44:14,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66429 states and 88877 transitions. [2023-11-26 11:44:14,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:14,963 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66429 states and 88877 transitions. [2023-11-26 11:44:15,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66429 states and 88877 transitions. [2023-11-26 11:44:15,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66429 to 41765. [2023-11-26 11:44:15,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41765 states, 41765 states have (on average 1.3403807015443554) internal successors, (55981), 41764 states have internal predecessors, (55981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:16,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41765 states to 41765 states and 55981 transitions. [2023-11-26 11:44:16,029 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41765 states and 55981 transitions. [2023-11-26 11:44:16,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:44:16,030 INFO L428 stractBuchiCegarLoop]: Abstraction has 41765 states and 55981 transitions. [2023-11-26 11:44:16,030 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-26 11:44:16,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41765 states and 55981 transitions. [2023-11-26 11:44:16,162 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41368 [2023-11-26 11:44:16,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:16,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:16,164 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:16,164 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:16,164 INFO L748 eck$LassoCheckResult]: Stem: 793668#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 793669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 793854#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 793855#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 794035#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 793562#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 793563#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 793393#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 793394#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 793368#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 793369#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 793540#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 793703#L696 assume !(0 == ~M_E~0); 793704#L696-2 assume !(0 == ~T1_E~0); 794042#L701-1 assume !(0 == ~T2_E~0); 794044#L706-1 assume !(0 == ~T3_E~0); 793826#L711-1 assume !(0 == ~T4_E~0); 793598#L716-1 assume !(0 == ~T5_E~0); 793599#L721-1 assume !(0 == ~T6_E~0); 793776#L726-1 assume !(0 == ~E_M~0); 793777#L731-1 assume !(0 == ~E_1~0); 793740#L736-1 assume !(0 == ~E_2~0); 793741#L741-1 assume !(0 == ~E_3~0); 793838#L746-1 assume !(0 == ~E_4~0); 793620#L751-1 assume !(0 == ~E_5~0); 793621#L756-1 assume !(0 == ~E_6~0); 793595#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 793415#L346 assume !(1 == ~m_pc~0); 793416#L346-2 is_master_triggered_~__retres1~0#1 := 0; 793637#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 794136#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 794057#L861 assume !(0 != activate_threads_~tmp~1#1); 794004#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 793449#L365 assume !(1 == ~t1_pc~0); 793450#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 794020#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 793401#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 793402#L869 assume !(0 != activate_threads_~tmp___0~0#1); 793438#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 793896#L384 assume !(1 == ~t2_pc~0); 793893#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 793894#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 793860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 793358#L877 assume !(0 != activate_threads_~tmp___1~0#1); 793359#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 793719#L403 assume !(1 == ~t3_pc~0); 793720#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 793931#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 793330#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 793331#L885 assume !(0 != activate_threads_~tmp___2~0#1); 793710#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 793711#L422 assume !(1 == ~t4_pc~0); 793852#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 793853#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 793501#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 793502#L893 assume !(0 != activate_threads_~tmp___3~0#1); 793802#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 793370#L441 assume !(1 == ~t5_pc~0); 793371#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 794000#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 794135#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 794134#L901 assume !(0 != activate_threads_~tmp___4~0#1); 793813#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 793814#L460 assume !(1 == ~t6_pc~0); 793954#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 793377#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 793378#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 793840#L909 assume !(0 != activate_threads_~tmp___5~0#1); 793949#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 793788#L774 assume !(1 == ~M_E~0); 793789#L774-2 assume !(1 == ~T1_E~0); 793970#L779-1 assume !(1 == ~T2_E~0); 793686#L784-1 assume !(1 == ~T3_E~0); 793687#L789-1 assume !(1 == ~T4_E~0); 793433#L794-1 assume !(1 == ~T5_E~0); 793434#L799-1 assume !(1 == ~T6_E~0); 794087#L804-1 assume !(1 == ~E_M~0); 794088#L809-1 assume !(1 == ~E_1~0); 793772#L814-1 assume !(1 == ~E_2~0); 793336#L819-1 assume !(1 == ~E_3~0); 793337#L824-1 assume !(1 == ~E_4~0); 793846#L829-1 assume !(1 == ~E_5~0); 793958#L834-1 assume !(1 == ~E_6~0); 793582#L839-1 assume { :end_inline_reset_delta_events } true; 793583#L1065-2 [2023-11-26 11:44:16,165 INFO L750 eck$LassoCheckResult]: Loop: 793583#L1065-2 assume !false; 798451#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 798361#L671-1 assume !false; 798435#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 798425#L530 assume !(0 == ~m_st~0); 798426#L534 assume !(0 == ~t1_st~0); 798702#L538 assume !(0 == ~t2_st~0); 798700#L542 assume !(0 == ~t3_st~0); 798698#L546 assume !(0 == ~t4_st~0); 798696#L550 assume !(0 == ~t5_st~0); 798693#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 798691#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 798689#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 798687#L582 assume !(0 != eval_~tmp~0#1); 798685#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 798682#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 798680#L696-3 assume !(0 == ~M_E~0); 798678#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 798675#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 798673#L706-3 assume !(0 == ~T3_E~0); 798671#L711-3 assume !(0 == ~T4_E~0); 798669#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 798667#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 798651#L726-3 assume !(0 == ~E_M~0); 798645#L731-3 assume !(0 == ~E_1~0); 798639#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 798631#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 798623#L746-3 assume !(0 == ~E_4~0); 798612#L751-3 assume !(0 == ~E_5~0); 798607#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 797576#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 797572#L346-24 assume 1 == ~m_pc~0; 797569#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 797567#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 797564#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 797561#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 797559#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 797557#L365-24 assume !(1 == ~t1_pc~0); 797555#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 797553#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 797551#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 797548#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 797546#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 797544#L384-24 assume !(1 == ~t2_pc~0); 797541#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 797539#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 797537#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 797535#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 797533#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 797531#L403-24 assume !(1 == ~t3_pc~0); 797529#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 797527#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 797525#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 797523#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 797521#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 797519#L422-24 assume !(1 == ~t4_pc~0); 797517#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 797515#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 797513#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 797511#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 797509#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 797508#L441-24 assume 1 == ~t5_pc~0; 797502#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 797500#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 797498#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 797496#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 797494#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 797492#L460-24 assume !(1 == ~t6_pc~0); 797490#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 797488#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 797486#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 797483#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 797481#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 797479#L774-3 assume !(1 == ~M_E~0); 797344#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 797475#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 797473#L784-3 assume !(1 == ~T3_E~0); 797471#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 797469#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 797467#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 797465#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 797463#L809-3 assume !(1 == ~E_1~0); 797461#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 797459#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 797457#L824-3 assume !(1 == ~E_4~0); 797455#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 797453#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 797451#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 797448#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 797446#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 797444#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 797441#L1084 assume !(0 == start_simulation_~tmp~3#1); 797442#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 798477#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 798475#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 798473#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 798471#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 798470#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 798468#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 798466#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 793583#L1065-2 [2023-11-26 11:44:16,165 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:16,165 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 7 times [2023-11-26 11:44:16,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:16,166 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422164459] [2023-11-26 11:44:16,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:16,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:16,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:16,178 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:16,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:16,202 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:16,202 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:16,202 INFO L85 PathProgramCache]: Analyzing trace with hash -383308951, now seen corresponding path program 1 times [2023-11-26 11:44:16,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:16,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290649081] [2023-11-26 11:44:16,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:16,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:16,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:16,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:16,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:16,280 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290649081] [2023-11-26 11:44:16,280 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290649081] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:16,280 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:16,280 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:44:16,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694872662] [2023-11-26 11:44:16,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:16,281 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:16,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:16,282 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:44:16,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:44:16,283 INFO L87 Difference]: Start difference. First operand 41765 states and 55981 transitions. cyclomatic complexity: 14232 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:16,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:16,775 INFO L93 Difference]: Finished difference Result 99425 states and 130582 transitions. [2023-11-26 11:44:16,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99425 states and 130582 transitions. [2023-11-26 11:44:17,191 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 98648 [2023-11-26 11:44:18,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99425 states to 99425 states and 130582 transitions. [2023-11-26 11:44:18,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99425 [2023-11-26 11:44:18,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99425 [2023-11-26 11:44:18,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99425 states and 130582 transitions. [2023-11-26 11:44:18,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:18,123 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99425 states and 130582 transitions. [2023-11-26 11:44:18,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99425 states and 130582 transitions. [2023-11-26 11:44:18,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99425 to 43496. [2023-11-26 11:44:18,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43496 states, 43496 states have (on average 1.3268346514622034) internal successors, (57712), 43495 states have internal predecessors, (57712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:18,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43496 states to 43496 states and 57712 transitions. [2023-11-26 11:44:18,606 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43496 states and 57712 transitions. [2023-11-26 11:44:18,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:44:18,606 INFO L428 stractBuchiCegarLoop]: Abstraction has 43496 states and 57712 transitions. [2023-11-26 11:44:18,607 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-26 11:44:18,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43496 states and 57712 transitions. [2023-11-26 11:44:18,718 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43096 [2023-11-26 11:44:18,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:18,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:18,719 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:18,720 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:18,720 INFO L748 eck$LassoCheckResult]: Stem: 934879#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 934880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 935065#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 935066#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 935268#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 934774#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 934775#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 934594#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 934595#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 934571#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 934572#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 934748#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 934914#L696 assume !(0 == ~M_E~0); 934915#L696-2 assume !(0 == ~T1_E~0); 935273#L701-1 assume !(0 == ~T2_E~0); 935275#L706-1 assume !(0 == ~T3_E~0); 935037#L711-1 assume !(0 == ~T4_E~0); 934810#L716-1 assume !(0 == ~T5_E~0); 934811#L721-1 assume !(0 == ~T6_E~0); 934986#L726-1 assume !(0 == ~E_M~0); 934987#L731-1 assume !(0 == ~E_1~0); 934953#L736-1 assume !(0 == ~E_2~0); 934954#L741-1 assume !(0 == ~E_3~0); 935048#L746-1 assume !(0 == ~E_4~0); 934835#L751-1 assume !(0 == ~E_5~0); 934836#L756-1 assume !(0 == ~E_6~0); 934807#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 934616#L346 assume !(1 == ~m_pc~0); 934617#L346-2 is_master_triggered_~__retres1~0#1 := 0; 934850#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 934842#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 934843#L861 assume !(0 != activate_threads_~tmp~1#1); 935239#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 934652#L365 assume !(1 == ~t1_pc~0); 934653#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 935255#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 934599#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 934600#L869 assume !(0 != activate_threads_~tmp___0~0#1); 934642#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 935120#L384 assume !(1 == ~t2_pc~0); 935115#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 935116#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 935339#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 934559#L877 assume !(0 != activate_threads_~tmp___1~0#1); 934560#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 934931#L403 assume !(1 == ~t3_pc~0); 934932#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 935166#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 934532#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 934533#L885 assume !(0 != activate_threads_~tmp___2~0#1); 934923#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 934924#L422 assume !(1 == ~t4_pc~0); 935063#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 935064#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 934709#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 934710#L893 assume !(0 != activate_threads_~tmp___3~0#1); 935015#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 934573#L441 assume !(1 == ~t5_pc~0); 934574#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 935234#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 935385#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 935384#L901 assume !(0 != activate_threads_~tmp___4~0#1); 935024#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 935025#L460 assume !(1 == ~t6_pc~0); 935192#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 934580#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 934581#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 935050#L909 assume !(0 != activate_threads_~tmp___5~0#1); 935189#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 934999#L774 assume !(1 == ~M_E~0); 935000#L774-2 assume !(1 == ~T1_E~0); 935208#L779-1 assume !(1 == ~T2_E~0); 934898#L784-1 assume !(1 == ~T3_E~0); 934899#L789-1 assume !(1 == ~T4_E~0); 934635#L794-1 assume !(1 == ~T5_E~0); 934636#L799-1 assume !(1 == ~T6_E~0); 935322#L804-1 assume !(1 == ~E_M~0); 935323#L809-1 assume !(1 == ~E_1~0); 934983#L814-1 assume !(1 == ~E_2~0); 934536#L819-1 assume !(1 == ~E_3~0); 934537#L824-1 assume !(1 == ~E_4~0); 935058#L829-1 assume !(1 == ~E_5~0); 935198#L834-1 assume !(1 == ~E_6~0); 934792#L839-1 assume { :end_inline_reset_delta_events } true; 934793#L1065-2 [2023-11-26 11:44:18,720 INFO L750 eck$LassoCheckResult]: Loop: 934793#L1065-2 assume !false; 937771#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 937767#L671-1 assume !false; 937765#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 937760#L530 assume !(0 == ~m_st~0); 937761#L534 assume !(0 == ~t1_st~0); 937859#L538 assume !(0 == ~t2_st~0); 937858#L542 assume !(0 == ~t3_st~0); 937857#L546 assume !(0 == ~t4_st~0); 937856#L550 assume !(0 == ~t5_st~0); 937854#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 937853#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 937852#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 937850#L582 assume !(0 != eval_~tmp~0#1); 937848#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 937846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 937844#L696-3 assume !(0 == ~M_E~0); 937842#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 937840#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 937838#L706-3 assume !(0 == ~T3_E~0); 937836#L711-3 assume !(0 == ~T4_E~0); 937834#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 937832#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 937830#L726-3 assume !(0 == ~E_M~0); 937828#L731-3 assume !(0 == ~E_1~0); 937826#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 937824#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 937818#L746-3 assume !(0 == ~E_4~0); 937815#L751-3 assume !(0 == ~E_5~0); 937810#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 937800#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 937793#L346-24 assume 1 == ~m_pc~0; 937786#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 937779#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 937774#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 937768#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 937766#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 937762#L365-24 assume !(1 == ~t1_pc~0); 937758#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 937755#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 937751#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 937748#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 937745#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 937744#L384-24 assume 1 == ~t2_pc~0; 937742#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 937740#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 937738#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 937736#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 937734#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 937732#L403-24 assume !(1 == ~t3_pc~0); 937730#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 937728#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 937726#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 937724#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 937722#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 937684#L422-24 assume !(1 == ~t4_pc~0); 937682#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 937680#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 937678#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 937676#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 937674#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 937672#L441-24 assume !(1 == ~t5_pc~0); 937670#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 938626#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 938625#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 937662#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 937660#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 937658#L460-24 assume !(1 == ~t6_pc~0); 937656#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 937652#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 937650#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 937648#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 937646#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 937645#L774-3 assume !(1 == ~M_E~0); 937442#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 937644#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 937643#L784-3 assume !(1 == ~T3_E~0); 937642#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 937641#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 937640#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 937639#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 937638#L809-3 assume !(1 == ~E_1~0); 937637#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 937636#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 937635#L824-3 assume !(1 == ~E_4~0); 937634#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 937633#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 937632#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 937630#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 937629#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 937628#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 937626#L1084 assume !(0 == start_simulation_~tmp~3#1); 937627#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 937819#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 937816#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 937811#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 937801#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 937794#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 937788#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 937780#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 934793#L1065-2 [2023-11-26 11:44:18,721 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:18,721 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 8 times [2023-11-26 11:44:18,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:18,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626042637] [2023-11-26 11:44:18,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:18,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:18,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:18,738 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:18,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:18,762 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:18,763 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:18,763 INFO L85 PathProgramCache]: Analyzing trace with hash 1870457131, now seen corresponding path program 1 times [2023-11-26 11:44:18,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:18,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848635659] [2023-11-26 11:44:18,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:18,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:18,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:18,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:18,843 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:18,843 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1848635659] [2023-11-26 11:44:18,843 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1848635659] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:18,843 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:18,844 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:44:18,844 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1030963710] [2023-11-26 11:44:18,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:18,845 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:18,845 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:18,845 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:44:18,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:44:18,846 INFO L87 Difference]: Start difference. First operand 43496 states and 57712 transitions. cyclomatic complexity: 14232 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:19,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:19,222 INFO L93 Difference]: Finished difference Result 73432 states and 96019 transitions. [2023-11-26 11:44:19,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73432 states and 96019 transitions. [2023-11-26 11:44:20,011 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 72904 [2023-11-26 11:44:20,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73432 states to 73432 states and 96019 transitions. [2023-11-26 11:44:20,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73432 [2023-11-26 11:44:20,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73432 [2023-11-26 11:44:20,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73432 states and 96019 transitions. [2023-11-26 11:44:20,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:20,194 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73432 states and 96019 transitions. [2023-11-26 11:44:20,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73432 states and 96019 transitions. [2023-11-26 11:44:20,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73432 to 44432. [2023-11-26 11:44:20,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44432 states, 44432 states have (on average 1.3139854159164566) internal successors, (58383), 44431 states have internal predecessors, (58383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:20,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44432 states to 44432 states and 58383 transitions. [2023-11-26 11:44:20,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44432 states and 58383 transitions. [2023-11-26 11:44:20,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:44:20,609 INFO L428 stractBuchiCegarLoop]: Abstraction has 44432 states and 58383 transitions. [2023-11-26 11:44:20,609 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-26 11:44:20,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44432 states and 58383 transitions. [2023-11-26 11:44:20,722 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 44032 [2023-11-26 11:44:20,722 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:20,722 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:20,723 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:20,723 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:20,724 INFO L748 eck$LassoCheckResult]: Stem: 1051816#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1051817#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1052015#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1052016#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1052202#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1051707#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1051708#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1051532#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1051533#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1051509#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1051510#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1051685#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1051854#L696 assume !(0 == ~M_E~0); 1051855#L696-2 assume !(0 == ~T1_E~0); 1052210#L701-1 assume !(0 == ~T2_E~0); 1052211#L706-1 assume !(0 == ~T3_E~0); 1051983#L711-1 assume !(0 == ~T4_E~0); 1051744#L716-1 assume !(0 == ~T5_E~0); 1051745#L721-1 assume !(0 == ~T6_E~0); 1051927#L726-1 assume !(0 == ~E_M~0); 1051928#L731-1 assume !(0 == ~E_1~0); 1051890#L736-1 assume !(0 == ~E_2~0); 1051891#L741-1 assume !(0 == ~E_3~0); 1051995#L746-1 assume !(0 == ~E_4~0); 1051770#L751-1 assume !(0 == ~E_5~0); 1051771#L756-1 assume !(0 == ~E_6~0); 1051741#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1051554#L346 assume !(1 == ~m_pc~0); 1051555#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1051786#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1052316#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1052224#L861 assume !(0 != activate_threads_~tmp~1#1); 1052170#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1051592#L365 assume !(1 == ~t1_pc~0); 1051593#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1052187#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1051538#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1051539#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1051581#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1052059#L384 assume !(1 == ~t2_pc~0); 1052053#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1052054#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1052017#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1051498#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1051499#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1051868#L403 assume !(1 == ~t3_pc~0); 1051869#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1052095#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1051472#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1051473#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1051861#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1051862#L422 assume !(1 == ~t4_pc~0); 1052013#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1052014#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1051644#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1051645#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1051955#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1051511#L441 assume !(1 == ~t5_pc~0); 1051512#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1052165#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1052314#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1052313#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1051967#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1051968#L460 assume !(1 == ~t6_pc~0); 1052116#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1051518#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1051519#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1051997#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1052113#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1051940#L774 assume !(1 == ~M_E~0); 1051941#L774-2 assume !(1 == ~T1_E~0); 1052135#L779-1 assume !(1 == ~T2_E~0); 1051836#L784-1 assume !(1 == ~T3_E~0); 1051837#L789-1 assume !(1 == ~T4_E~0); 1051575#L794-1 assume !(1 == ~T5_E~0); 1051576#L799-1 assume !(1 == ~T6_E~0); 1052256#L804-1 assume !(1 == ~E_M~0); 1052257#L809-1 assume !(1 == ~E_1~0); 1051922#L814-1 assume !(1 == ~E_2~0); 1051478#L819-1 assume !(1 == ~E_3~0); 1051479#L824-1 assume !(1 == ~E_4~0); 1052006#L829-1 assume !(1 == ~E_5~0); 1052122#L834-1 assume !(1 == ~E_6~0); 1051723#L839-1 assume { :end_inline_reset_delta_events } true; 1051724#L1065-2 [2023-11-26 11:44:20,724 INFO L750 eck$LassoCheckResult]: Loop: 1051724#L1065-2 assume !false; 1053796#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1053792#L671-1 assume !false; 1053790#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1053787#L530 assume !(0 == ~m_st~0); 1053788#L534 assume !(0 == ~t1_st~0); 1054281#L538 assume !(0 == ~t2_st~0); 1054282#L542 assume !(0 == ~t3_st~0); 1054283#L546 assume !(0 == ~t4_st~0); 1054279#L550 assume !(0 == ~t5_st~0); 1054280#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1054278#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1054274#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1054270#L582 assume !(0 != eval_~tmp~0#1); 1054265#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1054261#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1054257#L696-3 assume !(0 == ~M_E~0); 1054249#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1054248#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1054247#L706-3 assume !(0 == ~T3_E~0); 1054246#L711-3 assume !(0 == ~T4_E~0); 1054245#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1054243#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1054242#L726-3 assume !(0 == ~E_M~0); 1054241#L731-3 assume !(0 == ~E_1~0); 1054239#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1054238#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1054237#L746-3 assume !(0 == ~E_4~0); 1054236#L751-3 assume !(0 == ~E_5~0); 1054234#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1054232#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1054231#L346-24 assume 1 == ~m_pc~0; 1054229#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1054228#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1054226#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1054223#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1054222#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1054221#L365-24 assume !(1 == ~t1_pc~0); 1054219#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1054218#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1054217#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1054215#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 1054213#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1054209#L384-24 assume 1 == ~t2_pc~0; 1054210#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1054211#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1054220#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1054200#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1054198#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1054196#L403-24 assume !(1 == ~t3_pc~0); 1054194#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1054191#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1054189#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1054187#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 1054184#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1054182#L422-24 assume !(1 == ~t4_pc~0); 1054180#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1054178#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1054176#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1054174#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1054172#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1054170#L441-24 assume 1 == ~t5_pc~0; 1054166#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1054164#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1054162#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1054160#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1054157#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1054155#L460-24 assume !(1 == ~t6_pc~0); 1054151#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1054149#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1054147#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1054145#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1054142#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1053962#L774-3 assume !(1 == ~M_E~0); 1053960#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1053958#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1053956#L784-3 assume !(1 == ~T3_E~0); 1053953#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1053951#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1053949#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1053947#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1053945#L809-3 assume !(1 == ~E_1~0); 1053943#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1053941#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1053939#L824-3 assume !(1 == ~E_4~0); 1053937#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1053935#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1053933#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1053930#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1053928#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1053926#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1053924#L1084 assume !(0 == start_simulation_~tmp~3#1); 1053922#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1053919#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1053916#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1053914#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1053911#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1053909#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1053907#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1053904#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1051724#L1065-2 [2023-11-26 11:44:20,725 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:20,725 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 9 times [2023-11-26 11:44:20,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:20,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723458572] [2023-11-26 11:44:20,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:20,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:20,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:20,738 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:20,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:20,763 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:20,763 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:20,764 INFO L85 PathProgramCache]: Analyzing trace with hash -976664662, now seen corresponding path program 1 times [2023-11-26 11:44:20,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:20,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145632153] [2023-11-26 11:44:20,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:20,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:20,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:20,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:20,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:20,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145632153] [2023-11-26 11:44:20,839 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2145632153] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:20,839 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:20,839 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:44:20,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133485329] [2023-11-26 11:44:20,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:20,840 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:20,840 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:20,840 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:44:20,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:44:20,840 INFO L87 Difference]: Start difference. First operand 44432 states and 58383 transitions. cyclomatic complexity: 13967 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:21,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:21,584 INFO L93 Difference]: Finished difference Result 52952 states and 68964 transitions. [2023-11-26 11:44:21,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52952 states and 68964 transitions. [2023-11-26 11:44:21,890 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 52512 [2023-11-26 11:44:22,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52952 states to 52952 states and 68964 transitions. [2023-11-26 11:44:22,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52952 [2023-11-26 11:44:22,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52952 [2023-11-26 11:44:22,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52952 states and 68964 transitions. [2023-11-26 11:44:22,088 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:22,088 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52952 states and 68964 transitions. [2023-11-26 11:44:22,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52952 states and 68964 transitions. [2023-11-26 11:44:22,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52952 to 44504. [2023-11-26 11:44:22,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44504 states, 44504 states have (on average 1.3010515908682365) internal successors, (57902), 44503 states have internal predecessors, (57902), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:22,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44504 states to 44504 states and 57902 transitions. [2023-11-26 11:44:22,703 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44504 states and 57902 transitions. [2023-11-26 11:44:22,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:44:22,704 INFO L428 stractBuchiCegarLoop]: Abstraction has 44504 states and 57902 transitions. [2023-11-26 11:44:22,704 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-26 11:44:22,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44504 states and 57902 transitions. [2023-11-26 11:44:22,858 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 44104 [2023-11-26 11:44:22,858 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:22,858 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:22,860 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:22,860 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:22,861 INFO L748 eck$LassoCheckResult]: Stem: 1149219#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1149220#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1149410#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1149411#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1149631#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1149110#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1149111#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1148931#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1148932#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1148908#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1148909#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1149084#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1149254#L696 assume !(0 == ~M_E~0); 1149255#L696-2 assume !(0 == ~T1_E~0); 1149639#L701-1 assume !(0 == ~T2_E~0); 1149642#L706-1 assume !(0 == ~T3_E~0); 1149383#L711-1 assume !(0 == ~T4_E~0); 1149147#L716-1 assume !(0 == ~T5_E~0); 1149148#L721-1 assume !(0 == ~T6_E~0); 1149326#L726-1 assume !(0 == ~E_M~0); 1149327#L731-1 assume !(0 == ~E_1~0); 1149293#L736-1 assume !(0 == ~E_2~0); 1149294#L741-1 assume !(0 == ~E_3~0); 1149393#L746-1 assume !(0 == ~E_4~0); 1149173#L751-1 assume !(0 == ~E_5~0); 1149174#L756-1 assume !(0 == ~E_6~0); 1149144#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1148955#L346 assume !(1 == ~m_pc~0); 1148956#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1149188#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1149776#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1149660#L861 assume !(0 != activate_threads_~tmp~1#1); 1149591#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1148990#L365 assume !(1 == ~t1_pc~0); 1148991#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1149613#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1148937#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1148938#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1148980#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1149458#L384 assume !(1 == ~t2_pc~0); 1149453#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1149454#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1149412#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1148896#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1148897#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1149270#L403 assume !(1 == ~t3_pc~0); 1149271#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1149502#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1148868#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1148869#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1149263#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1149264#L422 assume !(1 == ~t4_pc~0); 1149408#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1149409#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1149045#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1149046#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1149358#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1148910#L441 assume !(1 == ~t5_pc~0); 1148911#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1149582#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1149774#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1149773#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1149369#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1149370#L460 assume !(1 == ~t6_pc~0); 1149528#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1148917#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1148918#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1149395#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1149525#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1149341#L774 assume !(1 == ~M_E~0); 1149342#L774-2 assume !(1 == ~T1_E~0); 1149551#L779-1 assume !(1 == ~T2_E~0); 1149238#L784-1 assume !(1 == ~T3_E~0); 1149239#L789-1 assume !(1 == ~T4_E~0); 1148975#L794-1 assume !(1 == ~T5_E~0); 1148976#L799-1 assume !(1 == ~T6_E~0); 1149708#L804-1 assume !(1 == ~E_M~0); 1149709#L809-1 assume !(1 == ~E_1~0); 1149322#L814-1 assume !(1 == ~E_2~0); 1148872#L819-1 assume !(1 == ~E_3~0); 1148873#L824-1 assume !(1 == ~E_4~0); 1149403#L829-1 assume !(1 == ~E_5~0); 1149535#L834-1 assume !(1 == ~E_6~0); 1149128#L839-1 assume { :end_inline_reset_delta_events } true; 1149129#L1065-2 [2023-11-26 11:44:22,862 INFO L750 eck$LassoCheckResult]: Loop: 1149129#L1065-2 assume !false; 1159156#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1159153#L671-1 assume !false; 1159152#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1159150#L530 assume !(0 == ~m_st~0); 1159151#L534 assume !(0 == ~t1_st~0); 1159467#L538 assume !(0 == ~t2_st~0); 1159465#L542 assume !(0 == ~t3_st~0); 1159463#L546 assume !(0 == ~t4_st~0); 1159459#L550 assume !(0 == ~t5_st~0); 1159456#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1159454#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1159452#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1159449#L582 assume !(0 != eval_~tmp~0#1); 1159447#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1159445#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1159443#L696-3 assume !(0 == ~M_E~0); 1159441#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1159439#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1159437#L706-3 assume !(0 == ~T3_E~0); 1159435#L711-3 assume !(0 == ~T4_E~0); 1159432#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1159430#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1159428#L726-3 assume !(0 == ~E_M~0); 1159426#L731-3 assume !(0 == ~E_1~0); 1159424#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1159422#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1159420#L746-3 assume !(0 == ~E_4~0); 1159418#L751-3 assume !(0 == ~E_5~0); 1159416#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1159414#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1159412#L346-24 assume 1 == ~m_pc~0; 1159409#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1159407#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1159405#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1159403#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1159402#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1159401#L365-24 assume !(1 == ~t1_pc~0); 1159399#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1159398#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1159397#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1159395#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 1159393#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1159390#L384-24 assume !(1 == ~t2_pc~0); 1159388#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1159387#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1159385#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1159383#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1159380#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1159378#L403-24 assume !(1 == ~t3_pc~0); 1159376#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1159374#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1159372#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1159369#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 1159367#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1159365#L422-24 assume !(1 == ~t4_pc~0); 1159362#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1159360#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1159358#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1159356#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 1159354#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1159352#L441-24 assume 1 == ~t5_pc~0; 1159349#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1159347#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1159345#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1159343#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1159340#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1159338#L460-24 assume !(1 == ~t6_pc~0); 1159336#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1159334#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1159332#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1159330#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1159328#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1159232#L774-3 assume !(1 == ~M_E~0); 1159229#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1159227#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1159225#L784-3 assume !(1 == ~T3_E~0); 1159223#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1159221#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1159219#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1159217#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1159215#L809-3 assume !(1 == ~E_1~0); 1159213#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1159211#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1159209#L824-3 assume !(1 == ~E_4~0); 1159207#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1159205#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1159203#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1159198#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1159196#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1159194#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1159191#L1084 assume !(0 == start_simulation_~tmp~3#1); 1159187#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1159184#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1159182#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1159180#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1159178#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1159176#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1159174#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1159172#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1149129#L1065-2 [2023-11-26 11:44:22,862 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:22,863 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 10 times [2023-11-26 11:44:22,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:22,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835369643] [2023-11-26 11:44:22,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:22,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:22,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:22,882 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:22,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:22,915 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:22,915 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:22,915 INFO L85 PathProgramCache]: Analyzing trace with hash 131150063, now seen corresponding path program 1 times [2023-11-26 11:44:22,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:22,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376299837] [2023-11-26 11:44:22,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:22,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:22,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:23,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:23,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:23,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [376299837] [2023-11-26 11:44:23,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [376299837] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:23,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:23,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:44:23,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [5791671] [2023-11-26 11:44:23,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:23,010 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:44:23,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:44:23,010 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:44:23,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:44:23,011 INFO L87 Difference]: Start difference. First operand 44504 states and 57902 transitions. cyclomatic complexity: 13414 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:23,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:44:23,969 INFO L93 Difference]: Finished difference Result 67756 states and 87269 transitions. [2023-11-26 11:44:23,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67756 states and 87269 transitions. [2023-11-26 11:44:24,227 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 67252 [2023-11-26 11:44:24,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67756 states to 67756 states and 87269 transitions. [2023-11-26 11:44:24,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67756 [2023-11-26 11:44:24,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67756 [2023-11-26 11:44:24,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67756 states and 87269 transitions. [2023-11-26 11:44:24,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:44:24,423 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67756 states and 87269 transitions. [2023-11-26 11:44:24,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67756 states and 87269 transitions. [2023-11-26 11:44:24,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67756 to 45440. [2023-11-26 11:44:24,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45440 states, 45440 states have (on average 1.289018485915493) internal successors, (58573), 45439 states have internal predecessors, (58573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:44:24,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45440 states to 45440 states and 58573 transitions. [2023-11-26 11:44:24,893 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45440 states and 58573 transitions. [2023-11-26 11:44:24,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:44:24,894 INFO L428 stractBuchiCegarLoop]: Abstraction has 45440 states and 58573 transitions. [2023-11-26 11:44:24,895 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-26 11:44:24,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45440 states and 58573 transitions. [2023-11-26 11:44:25,018 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 45040 [2023-11-26 11:44:25,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:44:25,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:44:25,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:25,020 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:44:25,021 INFO L748 eck$LassoCheckResult]: Stem: 1261482#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1261483#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1261671#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1261672#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1261864#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1261378#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1261379#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1261201#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1261202#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1261178#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1261179#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1261352#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1261516#L696 assume !(0 == ~M_E~0); 1261517#L696-2 assume !(0 == ~T1_E~0); 1261870#L701-1 assume !(0 == ~T2_E~0); 1261872#L706-1 assume !(0 == ~T3_E~0); 1261642#L711-1 assume !(0 == ~T4_E~0); 1261415#L716-1 assume !(0 == ~T5_E~0); 1261416#L721-1 assume !(0 == ~T6_E~0); 1261593#L726-1 assume !(0 == ~E_M~0); 1261594#L731-1 assume !(0 == ~E_1~0); 1261556#L736-1 assume !(0 == ~E_2~0); 1261557#L741-1 assume !(0 == ~E_3~0); 1261653#L746-1 assume !(0 == ~E_4~0); 1261439#L751-1 assume !(0 == ~E_5~0); 1261440#L756-1 assume !(0 == ~E_6~0); 1261412#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1261224#L346 assume !(1 == ~m_pc~0); 1261225#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1261452#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1261968#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1261884#L861 assume !(0 != activate_threads_~tmp~1#1); 1261834#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1261258#L365 assume !(1 == ~t1_pc~0); 1261259#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1261849#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1261208#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1261209#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1261248#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1261716#L384 assume !(1 == ~t2_pc~0); 1261711#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1261712#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1261673#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1261166#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1261167#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1261532#L403 assume !(1 == ~t3_pc~0); 1261533#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1261756#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1261140#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1261141#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1261525#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1261526#L422 assume !(1 == ~t4_pc~0); 1261669#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1261670#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1261313#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1261314#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1261619#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1261180#L441 assume !(1 == ~t5_pc~0); 1261181#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1261828#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1261966#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1261965#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1261629#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1261630#L460 assume !(1 == ~t6_pc~0); 1261779#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1261187#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1261188#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1261655#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1261776#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1261605#L774 assume !(1 == ~M_E~0); 1261606#L774-2 assume !(1 == ~T1_E~0); 1261797#L779-1 assume !(1 == ~T2_E~0); 1261501#L784-1 assume !(1 == ~T3_E~0); 1261502#L789-1 assume !(1 == ~T4_E~0); 1261243#L794-1 assume !(1 == ~T5_E~0); 1261244#L799-1 assume !(1 == ~T6_E~0); 1261917#L804-1 assume !(1 == ~E_M~0); 1261918#L809-1 assume !(1 == ~E_1~0); 1261588#L814-1 assume !(1 == ~E_2~0); 1261144#L819-1 assume !(1 == ~E_3~0); 1261145#L824-1 assume !(1 == ~E_4~0); 1261663#L829-1 assume !(1 == ~E_5~0); 1261785#L834-1 assume !(1 == ~E_6~0); 1261395#L839-1 assume { :end_inline_reset_delta_events } true; 1261396#L1065-2 [2023-11-26 11:44:25,021 INFO L750 eck$LassoCheckResult]: Loop: 1261396#L1065-2 assume !false; 1265212#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1265209#L671-1 assume !false; 1265207#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1265203#L530 assume !(0 == ~m_st~0); 1265204#L534 assume !(0 == ~t1_st~0); 1268152#L538 assume !(0 == ~t2_st~0); 1268147#L542 assume !(0 == ~t3_st~0); 1268143#L546 assume !(0 == ~t4_st~0); 1268139#L550 assume !(0 == ~t5_st~0); 1268135#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1268132#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1268128#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1268125#L582 assume !(0 != eval_~tmp~0#1); 1268121#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1268117#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1268113#L696-3 assume !(0 == ~M_E~0); 1268109#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1268106#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1268102#L706-3 assume !(0 == ~T3_E~0); 1268098#L711-3 assume !(0 == ~T4_E~0); 1268096#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1268093#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1268089#L726-3 assume !(0 == ~E_M~0); 1268087#L731-3 assume !(0 == ~E_1~0); 1268085#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1268075#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1268072#L746-3 assume !(0 == ~E_4~0); 1268066#L751-3 assume !(0 == ~E_5~0); 1268004#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1267904#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1267903#L346-24 assume 1 == ~m_pc~0; 1267901#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1267899#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1267898#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1267896#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1267894#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1267892#L365-24 assume !(1 == ~t1_pc~0); 1267890#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1267889#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1267887#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1267885#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 1267883#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1267872#L384-24 assume 1 == ~t2_pc~0; 1267873#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1267874#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1267900#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1267862#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1267860#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1267859#L403-24 assume !(1 == ~t3_pc~0); 1267852#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1267735#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1267725#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1265319#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 1265316#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1265314#L422-24 assume !(1 == ~t4_pc~0); 1265312#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1265310#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1265308#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1265306#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 1265304#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1265302#L441-24 assume 1 == ~t5_pc~0; 1265299#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1265297#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1265295#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1265293#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1265290#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1265288#L460-24 assume !(1 == ~t6_pc~0); 1265285#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1265283#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1265281#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1265279#L909-24 assume !(0 != activate_threads_~tmp___5~0#1); 1265277#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1265275#L774-3 assume !(1 == ~M_E~0); 1263571#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1265271#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1265269#L784-3 assume !(1 == ~T3_E~0); 1265267#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1265264#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1265262#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1265260#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1265258#L809-3 assume !(1 == ~E_1~0); 1265256#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1265254#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1265252#L824-3 assume !(1 == ~E_4~0); 1265250#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1265247#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1265245#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1265242#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1265240#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1265238#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1265236#L1084 assume !(0 == start_simulation_~tmp~3#1); 1265233#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1265230#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1265228#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1265226#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1265224#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1265222#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1265220#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1265218#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1261396#L1065-2 [2023-11-26 11:44:25,021 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:25,021 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 11 times [2023-11-26 11:44:25,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:25,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986094368] [2023-11-26 11:44:25,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:25,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:25,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:25,036 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:25,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:25,066 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:25,070 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:25,071 INFO L85 PathProgramCache]: Analyzing trace with hash 833185454, now seen corresponding path program 1 times [2023-11-26 11:44:25,071 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:25,071 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941635208] [2023-11-26 11:44:25,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:25,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:25,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:25,086 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:44:25,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:44:25,117 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:44:25,118 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:44:25,118 INFO L85 PathProgramCache]: Analyzing trace with hash 129573750, now seen corresponding path program 1 times [2023-11-26 11:44:25,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:44:25,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528477325] [2023-11-26 11:44:25,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:44:25,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:44:25,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:44:25,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:44:25,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:44:25,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [528477325] [2023-11-26 11:44:25,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [528477325] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:44:25,196 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:44:25,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:44:25,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571097900] [2023-11-26 11:44:25,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:44:27,582 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 11:44:27,583 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 11:44:27,583 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 11:44:27,583 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 11:44:27,583 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-26 11:44:27,583 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:27,583 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 11:44:27,584 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 11:44:27,584 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-1.c_Iteration29_Loop [2023-11-26 11:44:27,584 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 11:44:27,584 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 11:44:27,622 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,632 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,638 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,643 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,647 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,652 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,657 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,660 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,663 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,665 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,668 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,688 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,697 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,699 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,702 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,714 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,731 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,742 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,748 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,751 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,773 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,783 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,788 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,793 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,809 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,811 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,827 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,829 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,832 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,834 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,844 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,849 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,853 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,857 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,859 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,863 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,868 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,871 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,876 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,881 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,886 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,892 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:27,897 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:44:28,616 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 11:44:28,620 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-26 11:44:28,623 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:28,623 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:28,630 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:28,642 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-26 11:44:28,643 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:28,644 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:28,663 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:28,663 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:28,675 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2023-11-26 11:44:28,678 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:28,679 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:28,680 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:28,682 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-26 11:44:28,684 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:28,684 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:28,763 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:28,763 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:28,771 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:28,771 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:28,771 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:28,773 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:28,778 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:28,778 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:28,790 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-26 11:44:28,802 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:28,802 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:28,811 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:28,811 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:28,811 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:28,813 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:28,824 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:28,825 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:28,840 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-26 11:44:28,847 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:28,847 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:28,858 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:28,858 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:28,858 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:28,860 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:28,870 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:28,870 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:28,885 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-26 11:44:28,895 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:28,895 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:28,905 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:28,906 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:28,906 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:28,907 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:28,918 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:28,918 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:28,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-26 11:44:28,946 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:28,946 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:28,956 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:28,957 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:28,957 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:28,958 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:28,968 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:28,968 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:28,983 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-26 11:44:28,992 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:28,993 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,002 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,002 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,002 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,004 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,016 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,016 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,030 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-26 11:44:29,041 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,041 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,051 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,051 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,052 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,053 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,063 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,063 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,078 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-26 11:44:29,090 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,090 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_4~0=-8} Honda state: {~E_4~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,100 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,101 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,101 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,102 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,116 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,116 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,132 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-26 11:44:29,147 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,147 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,156 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,157 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,157 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,158 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,168 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,168 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,182 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-26 11:44:29,199 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,199 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,204 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,204 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,205 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,215 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-26 11:44:29,216 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,216 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,239 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,239 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,248 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,248 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,248 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,250 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,262 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-26 11:44:29,263 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,263 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,295 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,295 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,305 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,305 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,305 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,307 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,312 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,312 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,326 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-26 11:44:29,339 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,339 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,349 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,349 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,349 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,351 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,358 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-26 11:44:29,358 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,358 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,382 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,382 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,386 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,387 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,387 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,388 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,398 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,398 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,413 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-26 11:44:29,431 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,431 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=1} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,435 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,435 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,436 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,437 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,452 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,452 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,467 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-26 11:44:29,483 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,483 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_1~0=-1} Honda state: {~E_1~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,493 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,493 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,494 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,495 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,512 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,512 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-26 11:44:29,543 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,543 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,548 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,548 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,549 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,555 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-26 11:44:29,556 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,556 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,591 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,591 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___4~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___4~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,597 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,597 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,598 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,599 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,611 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-26 11:44:29,611 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,612 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,624 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,624 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Honda state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,628 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2023-11-26 11:44:29,629 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,629 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,630 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,639 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,639 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,639 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-26 11:44:29,651 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,651 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___2~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,653 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2023-11-26 11:44:29,654 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,654 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,655 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,656 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2023-11-26 11:44:29,657 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,657 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,669 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,669 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,672 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2023-11-26 11:44:29,672 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,673 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,674 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,676 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,676 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,686 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2023-11-26 11:44:29,690 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,691 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,693 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,694 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,694 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,695 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,696 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2023-11-26 11:44:29,697 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,697 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,709 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,710 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,712 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2023-11-26 11:44:29,712 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,712 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,713 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,715 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-26 11:44:29,718 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,718 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,731 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,731 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,734 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2023-11-26 11:44:29,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,734 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,735 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,736 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-26 11:44:29,738 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,738 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,750 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,751 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,753 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2023-11-26 11:44:29,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,754 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,754 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,756 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2023-11-26 11:44:29,757 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,757 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,770 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,770 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,772 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2023-11-26 11:44:29,773 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,773 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,774 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,775 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2023-11-26 11:44:29,776 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,777 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,789 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,789 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,791 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,791 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,792 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,792 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,799 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2023-11-26 11:44:29,800 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,800 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,822 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:44:29,822 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet10#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:44:29,825 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,825 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,825 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,826 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:44:29,832 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:44:29,832 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:44:29,838 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2023-11-26 11:44:29,856 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2023-11-26 11:44:29,856 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:44:29,857 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:44:29,857 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac412adb-8708-408d-9e51-b65f8310a6d5/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)