./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 10:42:36,928 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 10:42:37,055 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 10:42:37,069 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 10:42:37,070 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 10:42:37,112 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 10:42:37,112 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 10:42:37,113 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 10:42:37,114 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 10:42:37,115 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 10:42:37,116 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 10:42:37,116 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 10:42:37,117 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 10:42:37,117 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 10:42:37,118 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 10:42:37,119 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 10:42:37,119 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 10:42:37,120 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 10:42:37,120 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 10:42:37,121 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 10:42:37,122 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 10:42:37,122 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 10:42:37,123 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 10:42:37,123 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 10:42:37,124 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 10:42:37,124 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 10:42:37,125 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 10:42:37,125 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 10:42:37,125 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 10:42:37,126 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 10:42:37,126 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 10:42:37,127 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 10:42:37,127 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 10:42:37,127 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 10:42:37,128 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 10:42:37,128 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 10:42:37,128 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 10:42:37,129 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 10:42:37,129 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 [2023-11-26 10:42:37,439 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 10:42:37,463 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 10:42:37,467 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 10:42:37,468 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 10:42:37,469 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 10:42:37,470 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2023-11-26 10:42:40,705 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 10:42:41,058 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 10:42:41,058 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2023-11-26 10:42:41,089 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/data/b762aaa48/2494b795c42540a794aadea5f4489e86/FLAGd20c25730 [2023-11-26 10:42:41,110 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/data/b762aaa48/2494b795c42540a794aadea5f4489e86 [2023-11-26 10:42:41,112 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 10:42:41,114 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 10:42:41,117 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 10:42:41,117 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 10:42:41,123 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 10:42:41,125 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,126 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7dd8a9f0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41, skipping insertion in model container [2023-11-26 10:42:41,126 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,202 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 10:42:41,466 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:42:41,484 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 10:42:41,575 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:42:41,602 INFO L206 MainTranslator]: Completed translation [2023-11-26 10:42:41,603 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41 WrapperNode [2023-11-26 10:42:41,603 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 10:42:41,604 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 10:42:41,604 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 10:42:41,604 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 10:42:41,613 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,627 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,742 INFO L138 Inliner]: procedures = 44, calls = 57, calls flagged for inlining = 52, calls inlined = 160, statements flattened = 2391 [2023-11-26 10:42:41,743 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 10:42:41,744 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 10:42:41,745 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 10:42:41,745 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 10:42:41,757 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,758 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,772 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,810 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 10:42:41,811 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,811 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,850 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,879 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,884 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,893 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,906 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 10:42:41,907 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 10:42:41,907 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 10:42:41,907 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 10:42:41,908 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (1/1) ... [2023-11-26 10:42:41,919 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:42:41,946 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:42:41,982 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:42:41,999 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56d5aacf-1bb3-421a-acb4-d23883445660/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 10:42:42,027 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 10:42:42,028 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 10:42:42,028 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 10:42:42,028 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 10:42:42,189 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 10:42:42,191 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 10:42:43,818 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 10:42:43,856 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 10:42:43,857 INFO L309 CfgBuilder]: Removed 11 assume(true) statements. [2023-11-26 10:42:43,859 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:42:43 BoogieIcfgContainer [2023-11-26 10:42:43,859 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 10:42:43,860 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 10:42:43,861 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 10:42:43,864 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 10:42:43,865 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:42:43,865 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 10:42:41" (1/3) ... [2023-11-26 10:42:43,866 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@49ba5701 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:42:43, skipping insertion in model container [2023-11-26 10:42:43,867 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:42:43,868 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:42:41" (2/3) ... [2023-11-26 10:42:43,870 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@49ba5701 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:42:43, skipping insertion in model container [2023-11-26 10:42:43,870 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:42:43,871 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:42:43" (3/3) ... [2023-11-26 10:42:43,872 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-2.c [2023-11-26 10:42:43,949 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 10:42:43,949 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 10:42:43,950 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 10:42:43,950 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 10:42:43,950 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 10:42:43,950 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 10:42:43,950 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 10:42:43,950 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 10:42:43,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1017 states, 1016 states have (on average 1.5098425196850394) internal successors, (1534), 1016 states have internal predecessors, (1534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:44,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 898 [2023-11-26 10:42:44,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:44,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:44,052 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:44,052 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:44,052 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 10:42:44,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1017 states, 1016 states have (on average 1.5098425196850394) internal successors, (1534), 1016 states have internal predecessors, (1534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:44,072 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 898 [2023-11-26 10:42:44,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:44,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:44,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:44,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:44,091 INFO L748 eck$LassoCheckResult]: Stem: 124#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 936#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 760#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 934#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 318#L609true assume !(1 == ~m_i~0);~m_st~0 := 2; 1016#L609-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 59#L614-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 104#L619-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 735#L624-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 978#L629-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 43#L634-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 289#L639-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 874#L644-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 310#L649-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 107#L866true assume !(0 == ~M_E~0); 982#L866-2true assume !(0 == ~T1_E~0); 457#L871-1true assume !(0 == ~T2_E~0); 857#L876-1true assume !(0 == ~T3_E~0); 850#L881-1true assume !(0 == ~T4_E~0); 472#L886-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 283#L891-1true assume !(0 == ~T6_E~0); 462#L896-1true assume !(0 == ~T7_E~0); 595#L901-1true assume !(0 == ~T8_E~0); 485#L906-1true assume !(0 == ~E_M~0); 871#L911-1true assume !(0 == ~E_1~0); 316#L916-1true assume !(0 == ~E_2~0); 597#L921-1true assume !(0 == ~E_3~0); 756#L926-1true assume 0 == ~E_4~0;~E_4~0 := 1; 878#L931-1true assume !(0 == ~E_5~0); 903#L936-1true assume !(0 == ~E_6~0); 992#L941-1true assume !(0 == ~E_7~0); 319#L946-1true assume !(0 == ~E_8~0); 796#L951-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 907#L430true assume !(1 == ~m_pc~0); 699#L430-2true is_master_triggered_~__retres1~0#1 := 0; 16#L441true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 651#is_master_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 405#L1073true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 833#L1073-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 575#L449true assume 1 == ~t1_pc~0; 600#L450true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 828#L460true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 912#L1081true assume !(0 != activate_threads_~tmp___0~0#1); 497#L1081-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 358#L468true assume !(1 == ~t2_pc~0); 228#L468-2true is_transmit2_triggered_~__retres1~2#1 := 0; 445#L479true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220#L1089true assume !(0 != activate_threads_~tmp___1~0#1); 17#L1089-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 905#L487true assume 1 == ~t3_pc~0; 836#L488true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62#L498true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 654#L1097true assume !(0 != activate_threads_~tmp___2~0#1); 271#L1097-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 354#L506true assume !(1 == ~t4_pc~0); 867#L506-2true is_transmit4_triggered_~__retres1~4#1 := 0; 983#L517true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 837#L1105true assume !(0 != activate_threads_~tmp___3~0#1); 348#L1105-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 229#L525true assume 1 == ~t5_pc~0; 185#L526true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 721#L536true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 656#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 969#L1113true assume !(0 != activate_threads_~tmp___4~0#1); 141#L1113-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 346#L544true assume !(1 == ~t6_pc~0); 230#L544-2true is_transmit6_triggered_~__retres1~6#1 := 0; 512#L555true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 211#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26#L1121true assume !(0 != activate_threads_~tmp___5~0#1); 810#L1121-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 715#L563true assume 1 == ~t7_pc~0; 528#L564true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38#L574true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 950#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 284#L1129true assume !(0 != activate_threads_~tmp___6~0#1); 113#L1129-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 513#L582true assume 1 == ~t8_pc~0; 71#L583true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 840#L593true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 583#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 262#L1137true assume !(0 != activate_threads_~tmp___7~0#1); 187#L1137-2true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 579#L964true assume 1 == ~M_E~0;~M_E~0 := 2; 832#L964-2true assume !(1 == ~T1_E~0); 142#L969-1true assume !(1 == ~T2_E~0); 766#L974-1true assume !(1 == ~T3_E~0); 623#L979-1true assume !(1 == ~T4_E~0); 964#L984-1true assume !(1 == ~T5_E~0); 233#L989-1true assume !(1 == ~T6_E~0); 466#L994-1true assume !(1 == ~T7_E~0); 160#L999-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 584#L1004-1true assume !(1 == ~E_M~0); 27#L1009-1true assume !(1 == ~E_1~0); 154#L1014-1true assume !(1 == ~E_2~0); 565#L1019-1true assume !(1 == ~E_3~0); 809#L1024-1true assume !(1 == ~E_4~0); 122#L1029-1true assume !(1 == ~E_5~0); 169#L1034-1true assume !(1 == ~E_6~0); 994#L1039-1true assume 1 == ~E_7~0;~E_7~0 := 2; 781#L1044-1true assume !(1 == ~E_8~0); 295#L1049-1true assume { :end_inline_reset_delta_events } true; 103#L1315-2true [2023-11-26 10:42:44,095 INFO L750 eck$LassoCheckResult]: Loop: 103#L1315-2true assume !false; 885#L1316true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 608#L841-1true assume !true; 593#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 355#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19#L866-3true assume 0 == ~M_E~0;~M_E~0 := 1; 845#L866-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 173#L871-3true assume !(0 == ~T2_E~0); 274#L876-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 182#L881-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 688#L886-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 335#L891-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 469#L896-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 245#L901-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 337#L906-3true assume 0 == ~E_M~0;~E_M~0 := 1; 609#L911-3true assume !(0 == ~E_1~0); 520#L916-3true assume 0 == ~E_2~0;~E_2~0 := 1; 196#L921-3true assume 0 == ~E_3~0;~E_3~0 := 1; 504#L926-3true assume 0 == ~E_4~0;~E_4~0 := 1; 603#L931-3true assume 0 == ~E_5~0;~E_5~0 := 1; 251#L936-3true assume 0 == ~E_6~0;~E_6~0 := 1; 347#L941-3true assume 0 == ~E_7~0;~E_7~0 := 1; 606#L946-3true assume 0 == ~E_8~0;~E_8~0 := 1; 174#L951-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 879#L430-30true assume !(1 == ~m_pc~0); 648#L430-32true is_master_triggered_~__retres1~0#1 := 0; 259#L441-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 236#is_master_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 545#L1073-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 927#L1073-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 555#L449-30true assume 1 == ~t1_pc~0; 189#L450-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25#L460-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 387#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 232#L1081-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68#L1081-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 397#L468-30true assume 1 == ~t2_pc~0; 120#L469-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 617#L479-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 330#L1089-30true assume !(0 != activate_threads_~tmp___1~0#1); 795#L1089-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224#L487-30true assume !(1 == ~t3_pc~0); 106#L487-32true is_transmit3_triggered_~__retres1~3#1 := 0; 862#L498-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 375#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 821#L1097-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 573#L1097-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 280#L506-30true assume !(1 == ~t4_pc~0); 535#L506-32true is_transmit4_triggered_~__retres1~4#1 := 0; 297#L517-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 849#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 638#L1105-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 225#L1105-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 985#L525-30true assume 1 == ~t5_pc~0; 709#L526-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 930#L536-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 477#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 694#L1113-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 227#L1113-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94#L544-30true assume 1 == ~t6_pc~0; 4#L545-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 881#L555-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 723#L1121-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1004#L1121-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 685#L563-30true assume !(1 == ~t7_pc~0); 162#L563-32true is_transmit7_triggered_~__retres1~7#1 := 0; 88#L574-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 540#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 290#L1129-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 920#L1129-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 666#L582-30true assume !(1 == ~t8_pc~0); 135#L582-32true is_transmit8_triggered_~__retres1~8#1 := 0; 281#L593-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 989#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1002#L1137-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 914#L1137-32true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32#L964-3true assume 1 == ~M_E~0;~M_E~0 := 2; 101#L964-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 208#L969-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 96#L974-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 932#L979-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 363#L984-3true assume !(1 == ~T5_E~0); 996#L989-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 125#L994-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 843#L999-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 494#L1004-3true assume 1 == ~E_M~0;~E_M~0 := 2; 51#L1009-3true assume 1 == ~E_1~0;~E_1~0 := 2; 558#L1014-3true assume 1 == ~E_2~0;~E_2~0 := 2; 343#L1019-3true assume 1 == ~E_3~0;~E_3~0 := 2; 980#L1024-3true assume !(1 == ~E_4~0); 331#L1029-3true assume 1 == ~E_5~0;~E_5~0 := 2; 313#L1034-3true assume 1 == ~E_6~0;~E_6~0 := 2; 564#L1039-3true assume 1 == ~E_7~0;~E_7~0 := 2; 598#L1044-3true assume 1 == ~E_8~0;~E_8~0 := 2; 119#L1049-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 470#L662-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 706#L709-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 190#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 138#L1334true assume !(0 == start_simulation_~tmp~3#1); 827#L1334-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 144#L662-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2#L709-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 28#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 928#L1289true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 758#L1296true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 371#stop_simulation_returnLabel#1true start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 734#L1347true assume !(0 != start_simulation_~tmp___0~1#1); 103#L1315-2true [2023-11-26 10:42:44,102 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:44,103 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2023-11-26 10:42:44,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:44,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635628795] [2023-11-26 10:42:44,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:44,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:44,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:44,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:44,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:44,513 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635628795] [2023-11-26 10:42:44,514 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1635628795] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:44,514 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:44,515 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:44,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517179680] [2023-11-26 10:42:44,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:44,522 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:44,523 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:44,523 INFO L85 PathProgramCache]: Analyzing trace with hash -1219078109, now seen corresponding path program 1 times [2023-11-26 10:42:44,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:44,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493553502] [2023-11-26 10:42:44,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:44,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:44,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:44,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:44,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:44,584 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [493553502] [2023-11-26 10:42:44,585 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [493553502] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:44,585 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:44,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:42:44,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292154703] [2023-11-26 10:42:44,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:44,587 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:44,588 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:44,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:44,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:44,632 INFO L87 Difference]: Start difference. First operand has 1017 states, 1016 states have (on average 1.5098425196850394) internal successors, (1534), 1016 states have internal predecessors, (1534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:44,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:44,747 INFO L93 Difference]: Finished difference Result 1013 states and 1505 transitions. [2023-11-26 10:42:44,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1013 states and 1505 transitions. [2023-11-26 10:42:44,764 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:44,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1013 states to 1007 states and 1499 transitions. [2023-11-26 10:42:44,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-26 10:42:44,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-26 10:42:44,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1499 transitions. [2023-11-26 10:42:44,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:44,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1499 transitions. [2023-11-26 10:42:44,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1499 transitions. [2023-11-26 10:42:44,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-26 10:42:44,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4885799404170805) internal successors, (1499), 1006 states have internal predecessors, (1499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:44,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1499 transitions. [2023-11-26 10:42:44,885 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1499 transitions. [2023-11-26 10:42:44,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:44,891 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1499 transitions. [2023-11-26 10:42:44,891 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 10:42:44,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1499 transitions. [2023-11-26 10:42:44,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:44,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:44,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:44,905 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:44,906 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:44,906 INFO L748 eck$LassoCheckResult]: Stem: 2287#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2288#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3001#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3002#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2601#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2602#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2159#L614-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2160#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2251#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2987#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2127#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2128#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2556#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2588#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2255#L866 assume !(0 == ~M_E~0); 2256#L866-2 assume !(0 == ~T1_E~0); 2786#L871-1 assume !(0 == ~T2_E~0); 2787#L876-1 assume !(0 == ~T3_E~0); 3027#L881-1 assume !(0 == ~T4_E~0); 2800#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2545#L891-1 assume !(0 == ~T6_E~0); 2546#L896-1 assume !(0 == ~T7_E~0); 2794#L901-1 assume !(0 == ~T8_E~0); 2815#L906-1 assume !(0 == ~E_M~0); 2816#L911-1 assume !(0 == ~E_1~0); 2598#L916-1 assume !(0 == ~E_2~0); 2599#L921-1 assume !(0 == ~E_3~0); 2908#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2998#L931-1 assume !(0 == ~E_5~0); 3030#L936-1 assume !(0 == ~E_6~0); 3034#L941-1 assume !(0 == ~E_7~0); 2603#L946-1 assume !(0 == ~E_8~0); 2604#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3015#L430 assume !(1 == ~m_pc~0); 2445#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2074#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2075#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2720#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2721#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2889#L449 assume 1 == ~t1_pc~0; 2890#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2262#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2101#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2102#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2830#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2660#L468 assume !(1 == ~t2_pc~0); 2062#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2061#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2455#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2450#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2076#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2077#L487 assume 1 == ~t3_pc~0; 3025#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2165#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2058#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2059#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2523#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2524#L506 assume !(1 == ~t4_pc~0); 2655#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2705#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2151#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2152#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2649#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2462#L525 assume 1 == ~t5_pc~0; 2396#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2115#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2946#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2947#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2319#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2320#L544 assume !(1 == ~t6_pc~0); 2463#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2464#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2435#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2096#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2097#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2979#L563 assume 1 == ~t7_pc~0; 2853#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2119#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2120#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2547#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2263#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2264#L582 assume 1 == ~t8_pc~0; 2183#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2184#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2895#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2511#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2400#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2401#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 2893#L964-2 assume !(1 == ~T1_E~0); 2321#L969-1 assume !(1 == ~T2_E~0); 2322#L974-1 assume !(1 == ~T3_E~0); 2926#L979-1 assume !(1 == ~T4_E~0); 2927#L984-1 assume !(1 == ~T5_E~0); 2469#L989-1 assume !(1 == ~T6_E~0); 2470#L994-1 assume !(1 == ~T7_E~0); 2352#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2353#L1004-1 assume !(1 == ~E_M~0); 2098#L1009-1 assume !(1 == ~E_1~0); 2099#L1014-1 assume !(1 == ~E_2~0); 2341#L1019-1 assume !(1 == ~E_3~0); 2881#L1024-1 assume !(1 == ~E_4~0); 2284#L1029-1 assume !(1 == ~E_5~0); 2285#L1034-1 assume !(1 == ~E_6~0); 2368#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3011#L1044-1 assume !(1 == ~E_8~0); 2567#L1049-1 assume { :end_inline_reset_delta_events } true; 2249#L1315-2 [2023-11-26 10:42:44,908 INFO L750 eck$LassoCheckResult]: Loop: 2249#L1315-2 assume !false; 2250#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2663#L841-1 assume !false; 2917#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2314#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2315#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2496#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2071#L724 assume !(0 != eval_~tmp~0#1); 2073#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2657#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2080#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2081#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2373#L871-3 assume !(0 == ~T2_E~0); 2374#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2390#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2391#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2631#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2632#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2489#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2490#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2633#L911-3 assume !(0 == ~E_1~0); 2847#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2417#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2418#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2836#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2497#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2498#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2648#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2375#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2376#L430-30 assume 1 == ~m_pc~0; 2402#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2403#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2474#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2475#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2864#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2870#L449-30 assume 1 == ~t1_pc~0; 2405#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2094#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2095#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2468#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2179#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2180#L468-30 assume 1 == ~t2_pc~0; 2279#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2280#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2371#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2372#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 2623#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2456#L487-30 assume 1 == ~t3_pc~0; 2434#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2254#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2685#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2686#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2888#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2540#L506-30 assume !(1 == ~t4_pc~0); 2541#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2570#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2571#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2934#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2457#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2458#L525-30 assume !(1 == ~t5_pc~0); 2977#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2976#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2804#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2805#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2461#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2231#L544-30 assume 1 == ~t6_pc~0; 2043#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2044#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2157#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2158#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2982#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2965#L563-30 assume 1 == ~t7_pc~0; 2198#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2199#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2220#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2557#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2558#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2955#L582-30 assume 1 == ~t8_pc~0; 2915#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2308#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2543#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3045#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3035#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2106#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2107#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2245#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2234#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2235#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2669#L984-3 assume !(1 == ~T5_E~0); 2670#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2289#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2290#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2828#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2142#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2143#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2645#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2646#L1024-3 assume !(1 == ~E_4~0); 2624#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2593#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2594#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2880#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2277#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2278#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2398#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2407#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2311#L1334 assume !(0 == start_simulation_~tmp~3#1); 2312#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2325#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2039#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2040#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2100#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3000#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2679#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2680#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2249#L1315-2 [2023-11-26 10:42:44,909 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:44,909 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2023-11-26 10:42:44,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:44,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444741879] [2023-11-26 10:42:44,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:44,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:44,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:45,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:45,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:45,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [444741879] [2023-11-26 10:42:45,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [444741879] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:45,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:45,020 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:45,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606391343] [2023-11-26 10:42:45,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:45,021 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:45,021 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:45,021 INFO L85 PathProgramCache]: Analyzing trace with hash 13135423, now seen corresponding path program 1 times [2023-11-26 10:42:45,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:45,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005870510] [2023-11-26 10:42:45,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:45,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:45,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:45,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:45,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:45,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005870510] [2023-11-26 10:42:45,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005870510] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:45,145 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:45,145 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:45,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [966826892] [2023-11-26 10:42:45,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:45,146 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:45,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:45,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:45,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:45,147 INFO L87 Difference]: Start difference. First operand 1007 states and 1499 transitions. cyclomatic complexity: 493 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:45,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:45,184 INFO L93 Difference]: Finished difference Result 1007 states and 1498 transitions. [2023-11-26 10:42:45,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1498 transitions. [2023-11-26 10:42:45,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:45,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1498 transitions. [2023-11-26 10:42:45,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-26 10:42:45,210 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-26 10:42:45,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1498 transitions. [2023-11-26 10:42:45,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:45,213 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1498 transitions. [2023-11-26 10:42:45,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1498 transitions. [2023-11-26 10:42:45,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-26 10:42:45,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4875868917576962) internal successors, (1498), 1006 states have internal predecessors, (1498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:45,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1498 transitions. [2023-11-26 10:42:45,249 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1498 transitions. [2023-11-26 10:42:45,249 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:45,252 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1498 transitions. [2023-11-26 10:42:45,253 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 10:42:45,253 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1498 transitions. [2023-11-26 10:42:45,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:45,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:45,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:45,273 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:45,273 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:45,275 INFO L748 eck$LassoCheckResult]: Stem: 4308#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4309#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4622#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 4623#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4180#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4181#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4272#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5008#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4148#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4149#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4577#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4609#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4276#L866 assume !(0 == ~M_E~0); 4277#L866-2 assume !(0 == ~T1_E~0); 4807#L871-1 assume !(0 == ~T2_E~0); 4808#L876-1 assume !(0 == ~T3_E~0); 5048#L881-1 assume !(0 == ~T4_E~0); 4821#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4566#L891-1 assume !(0 == ~T6_E~0); 4567#L896-1 assume !(0 == ~T7_E~0); 4815#L901-1 assume !(0 == ~T8_E~0); 4836#L906-1 assume !(0 == ~E_M~0); 4837#L911-1 assume !(0 == ~E_1~0); 4619#L916-1 assume !(0 == ~E_2~0); 4620#L921-1 assume !(0 == ~E_3~0); 4929#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5019#L931-1 assume !(0 == ~E_5~0); 5051#L936-1 assume !(0 == ~E_6~0); 5055#L941-1 assume !(0 == ~E_7~0); 4624#L946-1 assume !(0 == ~E_8~0); 4625#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5036#L430 assume !(1 == ~m_pc~0); 4466#L430-2 is_master_triggered_~__retres1~0#1 := 0; 4095#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4096#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4741#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4742#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4910#L449 assume 1 == ~t1_pc~0; 4911#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4283#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4122#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4123#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 4851#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4681#L468 assume !(1 == ~t2_pc~0); 4083#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4082#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4476#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4471#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 4097#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4098#L487 assume 1 == ~t3_pc~0; 5046#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4186#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4079#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4080#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 4544#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4545#L506 assume !(1 == ~t4_pc~0); 4676#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4726#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4172#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4173#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 4670#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4483#L525 assume 1 == ~t5_pc~0; 4417#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4136#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4967#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4968#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 4340#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4341#L544 assume !(1 == ~t6_pc~0); 4484#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4485#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4456#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4117#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 4118#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5000#L563 assume 1 == ~t7_pc~0; 4874#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4140#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4141#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4568#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 4284#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4285#L582 assume 1 == ~t8_pc~0; 4204#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4205#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4916#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4532#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 4421#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4422#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 4914#L964-2 assume !(1 == ~T1_E~0); 4342#L969-1 assume !(1 == ~T2_E~0); 4343#L974-1 assume !(1 == ~T3_E~0); 4947#L979-1 assume !(1 == ~T4_E~0); 4948#L984-1 assume !(1 == ~T5_E~0); 4490#L989-1 assume !(1 == ~T6_E~0); 4491#L994-1 assume !(1 == ~T7_E~0); 4373#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4374#L1004-1 assume !(1 == ~E_M~0); 4119#L1009-1 assume !(1 == ~E_1~0); 4120#L1014-1 assume !(1 == ~E_2~0); 4362#L1019-1 assume !(1 == ~E_3~0); 4902#L1024-1 assume !(1 == ~E_4~0); 4305#L1029-1 assume !(1 == ~E_5~0); 4306#L1034-1 assume !(1 == ~E_6~0); 4389#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5032#L1044-1 assume !(1 == ~E_8~0); 4588#L1049-1 assume { :end_inline_reset_delta_events } true; 4270#L1315-2 [2023-11-26 10:42:45,276 INFO L750 eck$LassoCheckResult]: Loop: 4270#L1315-2 assume !false; 4271#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4684#L841-1 assume !false; 4938#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4335#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4336#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4517#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4092#L724 assume !(0 != eval_~tmp~0#1); 4094#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4678#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4101#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4102#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4394#L871-3 assume !(0 == ~T2_E~0); 4395#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4411#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4412#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4652#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4653#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4510#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4511#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4654#L911-3 assume !(0 == ~E_1~0); 4868#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4438#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4439#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4857#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4518#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4519#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4669#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4396#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4397#L430-30 assume 1 == ~m_pc~0; 4423#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4424#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4495#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4496#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4885#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4891#L449-30 assume 1 == ~t1_pc~0; 4426#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4115#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4116#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4489#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4200#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4201#L468-30 assume 1 == ~t2_pc~0; 4300#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4301#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4392#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4393#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 4644#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4477#L487-30 assume !(1 == ~t3_pc~0); 4274#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4275#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4706#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4707#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4909#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4561#L506-30 assume !(1 == ~t4_pc~0); 4562#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4591#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4592#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4955#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4478#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4479#L525-30 assume 1 == ~t5_pc~0; 4996#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4997#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4825#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4826#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4482#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4252#L544-30 assume 1 == ~t6_pc~0; 4064#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4065#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4178#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4179#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5003#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4986#L563-30 assume 1 == ~t7_pc~0; 4219#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4220#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4241#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4578#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4579#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4976#L582-30 assume 1 == ~t8_pc~0; 4936#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4329#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4564#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5066#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5056#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4127#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4128#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4266#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4255#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4256#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4690#L984-3 assume !(1 == ~T5_E~0); 4691#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4310#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4311#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4849#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4163#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4164#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4666#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4667#L1024-3 assume !(1 == ~E_4~0); 4645#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4614#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4615#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4901#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4298#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4299#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4419#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4428#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4332#L1334 assume !(0 == start_simulation_~tmp~3#1); 4333#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4346#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4060#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4061#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4121#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5021#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4700#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4701#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 4270#L1315-2 [2023-11-26 10:42:45,277 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:45,277 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2023-11-26 10:42:45,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:45,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869683255] [2023-11-26 10:42:45,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:45,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:45,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:45,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:45,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:45,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [869683255] [2023-11-26 10:42:45,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [869683255] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:45,407 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:45,407 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:45,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1718827298] [2023-11-26 10:42:45,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:45,408 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:45,412 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:45,413 INFO L85 PathProgramCache]: Analyzing trace with hash -1036208961, now seen corresponding path program 1 times [2023-11-26 10:42:45,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:45,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248924219] [2023-11-26 10:42:45,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:45,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:45,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:45,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:45,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:45,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248924219] [2023-11-26 10:42:45,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248924219] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:45,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:45,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:45,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044643808] [2023-11-26 10:42:45,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:45,555 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:45,555 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:45,556 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:45,556 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:45,556 INFO L87 Difference]: Start difference. First operand 1007 states and 1498 transitions. cyclomatic complexity: 492 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:45,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:45,587 INFO L93 Difference]: Finished difference Result 1007 states and 1497 transitions. [2023-11-26 10:42:45,587 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1497 transitions. [2023-11-26 10:42:45,597 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:45,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1497 transitions. [2023-11-26 10:42:45,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-26 10:42:45,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-26 10:42:45,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1497 transitions. [2023-11-26 10:42:45,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:45,611 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1497 transitions. [2023-11-26 10:42:45,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1497 transitions. [2023-11-26 10:42:45,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-26 10:42:45,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4865938430983119) internal successors, (1497), 1006 states have internal predecessors, (1497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:45,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1497 transitions. [2023-11-26 10:42:45,689 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1497 transitions. [2023-11-26 10:42:45,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:45,692 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1497 transitions. [2023-11-26 10:42:45,692 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 10:42:45,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1497 transitions. [2023-11-26 10:42:45,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:45,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:45,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:45,707 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:45,707 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:45,707 INFO L748 eck$LassoCheckResult]: Stem: 6329#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 7043#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7044#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6643#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 6644#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6201#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6202#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6293#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7029#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6169#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6170#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6598#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6630#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6297#L866 assume !(0 == ~M_E~0); 6298#L866-2 assume !(0 == ~T1_E~0); 6828#L871-1 assume !(0 == ~T2_E~0); 6829#L876-1 assume !(0 == ~T3_E~0); 7069#L881-1 assume !(0 == ~T4_E~0); 6842#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6587#L891-1 assume !(0 == ~T6_E~0); 6588#L896-1 assume !(0 == ~T7_E~0); 6836#L901-1 assume !(0 == ~T8_E~0); 6857#L906-1 assume !(0 == ~E_M~0); 6858#L911-1 assume !(0 == ~E_1~0); 6640#L916-1 assume !(0 == ~E_2~0); 6641#L921-1 assume !(0 == ~E_3~0); 6950#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7040#L931-1 assume !(0 == ~E_5~0); 7072#L936-1 assume !(0 == ~E_6~0); 7076#L941-1 assume !(0 == ~E_7~0); 6645#L946-1 assume !(0 == ~E_8~0); 6646#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7057#L430 assume !(1 == ~m_pc~0); 6487#L430-2 is_master_triggered_~__retres1~0#1 := 0; 6116#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6117#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6762#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6763#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6931#L449 assume 1 == ~t1_pc~0; 6932#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6304#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6144#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 6872#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6702#L468 assume !(1 == ~t2_pc~0); 6104#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6103#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6497#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6492#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 6118#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6119#L487 assume 1 == ~t3_pc~0; 7067#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6207#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6100#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6101#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 6565#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6566#L506 assume !(1 == ~t4_pc~0); 6697#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6747#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6193#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6194#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 6691#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6504#L525 assume 1 == ~t5_pc~0; 6438#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6157#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6988#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6989#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 6361#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6362#L544 assume !(1 == ~t6_pc~0); 6505#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6506#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6477#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6138#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 6139#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7021#L563 assume 1 == ~t7_pc~0; 6895#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6161#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6162#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6589#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 6305#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6306#L582 assume 1 == ~t8_pc~0; 6225#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6226#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6937#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6553#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 6442#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6443#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 6935#L964-2 assume !(1 == ~T1_E~0); 6363#L969-1 assume !(1 == ~T2_E~0); 6364#L974-1 assume !(1 == ~T3_E~0); 6968#L979-1 assume !(1 == ~T4_E~0); 6969#L984-1 assume !(1 == ~T5_E~0); 6511#L989-1 assume !(1 == ~T6_E~0); 6512#L994-1 assume !(1 == ~T7_E~0); 6394#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6395#L1004-1 assume !(1 == ~E_M~0); 6140#L1009-1 assume !(1 == ~E_1~0); 6141#L1014-1 assume !(1 == ~E_2~0); 6383#L1019-1 assume !(1 == ~E_3~0); 6923#L1024-1 assume !(1 == ~E_4~0); 6326#L1029-1 assume !(1 == ~E_5~0); 6327#L1034-1 assume !(1 == ~E_6~0); 6410#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7053#L1044-1 assume !(1 == ~E_8~0); 6609#L1049-1 assume { :end_inline_reset_delta_events } true; 6291#L1315-2 [2023-11-26 10:42:45,708 INFO L750 eck$LassoCheckResult]: Loop: 6291#L1315-2 assume !false; 6292#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6705#L841-1 assume !false; 6959#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6356#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6357#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6538#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6113#L724 assume !(0 != eval_~tmp~0#1); 6115#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6699#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6122#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6123#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6415#L871-3 assume !(0 == ~T2_E~0); 6416#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6432#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6433#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6673#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6674#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6531#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6532#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6675#L911-3 assume !(0 == ~E_1~0); 6889#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6459#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6460#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6878#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6539#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6540#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6690#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6417#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6418#L430-30 assume 1 == ~m_pc~0; 6444#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6445#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6516#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6517#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6906#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6912#L449-30 assume !(1 == ~t1_pc~0); 6448#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 6136#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6137#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6510#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6221#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6222#L468-30 assume 1 == ~t2_pc~0; 6321#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6322#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6413#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6414#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 6665#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6498#L487-30 assume !(1 == ~t3_pc~0); 6295#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 6296#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6727#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6728#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6930#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6582#L506-30 assume !(1 == ~t4_pc~0); 6583#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 6612#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6613#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6976#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6499#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6500#L525-30 assume 1 == ~t5_pc~0; 7017#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7018#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6846#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6847#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6503#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6273#L544-30 assume 1 == ~t6_pc~0; 6085#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6086#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6199#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6200#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7024#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7007#L563-30 assume 1 == ~t7_pc~0; 6240#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6241#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6262#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6599#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6600#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6997#L582-30 assume 1 == ~t8_pc~0; 6957#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6350#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6585#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7087#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7077#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6148#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6149#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6287#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6276#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6277#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6711#L984-3 assume !(1 == ~T5_E~0); 6712#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6331#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6332#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6870#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6184#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6185#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6687#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6688#L1024-3 assume !(1 == ~E_4~0); 6666#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6635#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6636#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6922#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6319#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6320#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6440#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6449#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6353#L1334 assume !(0 == start_simulation_~tmp~3#1); 6354#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6367#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6081#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6082#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6142#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7042#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6721#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6722#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 6291#L1315-2 [2023-11-26 10:42:45,710 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:45,710 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2023-11-26 10:42:45,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:45,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795140751] [2023-11-26 10:42:45,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:45,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:45,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:45,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:45,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:45,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795140751] [2023-11-26 10:42:45,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [795140751] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:45,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:45,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:45,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911549592] [2023-11-26 10:42:45,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:45,777 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:45,778 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:45,778 INFO L85 PathProgramCache]: Analyzing trace with hash -1973236160, now seen corresponding path program 1 times [2023-11-26 10:42:45,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:45,778 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144352161] [2023-11-26 10:42:45,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:45,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:45,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:45,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:45,839 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:45,839 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144352161] [2023-11-26 10:42:45,839 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144352161] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:45,839 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:45,840 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:45,840 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104450057] [2023-11-26 10:42:45,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:45,841 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:45,841 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:45,841 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:45,841 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:45,842 INFO L87 Difference]: Start difference. First operand 1007 states and 1497 transitions. cyclomatic complexity: 491 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:45,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:45,868 INFO L93 Difference]: Finished difference Result 1007 states and 1496 transitions. [2023-11-26 10:42:45,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1496 transitions. [2023-11-26 10:42:45,878 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:45,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1496 transitions. [2023-11-26 10:42:45,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-26 10:42:45,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-26 10:42:45,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1496 transitions. [2023-11-26 10:42:45,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:45,891 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1496 transitions. [2023-11-26 10:42:45,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1496 transitions. [2023-11-26 10:42:45,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-26 10:42:45,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4856007944389276) internal successors, (1496), 1006 states have internal predecessors, (1496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:45,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1496 transitions. [2023-11-26 10:42:45,917 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1496 transitions. [2023-11-26 10:42:45,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:45,918 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1496 transitions. [2023-11-26 10:42:45,918 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 10:42:45,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1496 transitions. [2023-11-26 10:42:45,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:45,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:45,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:45,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:45,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:45,929 INFO L748 eck$LassoCheckResult]: Stem: 8350#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8351#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9064#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9065#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8664#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 8665#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8222#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8223#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8314#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9050#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8190#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8191#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8619#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8651#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8318#L866 assume !(0 == ~M_E~0); 8319#L866-2 assume !(0 == ~T1_E~0); 8849#L871-1 assume !(0 == ~T2_E~0); 8850#L876-1 assume !(0 == ~T3_E~0); 9090#L881-1 assume !(0 == ~T4_E~0); 8863#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8608#L891-1 assume !(0 == ~T6_E~0); 8609#L896-1 assume !(0 == ~T7_E~0); 8857#L901-1 assume !(0 == ~T8_E~0); 8878#L906-1 assume !(0 == ~E_M~0); 8879#L911-1 assume !(0 == ~E_1~0); 8661#L916-1 assume !(0 == ~E_2~0); 8662#L921-1 assume !(0 == ~E_3~0); 8971#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 9061#L931-1 assume !(0 == ~E_5~0); 9093#L936-1 assume !(0 == ~E_6~0); 9097#L941-1 assume !(0 == ~E_7~0); 8666#L946-1 assume !(0 == ~E_8~0); 8667#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9078#L430 assume !(1 == ~m_pc~0); 8508#L430-2 is_master_triggered_~__retres1~0#1 := 0; 8137#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8138#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8783#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8784#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8952#L449 assume 1 == ~t1_pc~0; 8953#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8325#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8164#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8165#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 8893#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8723#L468 assume !(1 == ~t2_pc~0); 8125#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8124#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8513#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 8139#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8140#L487 assume 1 == ~t3_pc~0; 9088#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8228#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8121#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8122#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 8586#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8587#L506 assume !(1 == ~t4_pc~0); 8718#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8768#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8214#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8215#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 8712#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8525#L525 assume 1 == ~t5_pc~0; 8459#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8178#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9009#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9010#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 8382#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8383#L544 assume !(1 == ~t6_pc~0); 8526#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8527#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8498#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8159#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 8160#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9042#L563 assume 1 == ~t7_pc~0; 8916#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8182#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8183#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8610#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 8326#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8327#L582 assume 1 == ~t8_pc~0; 8246#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8247#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8958#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8574#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 8463#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8464#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 8956#L964-2 assume !(1 == ~T1_E~0); 8384#L969-1 assume !(1 == ~T2_E~0); 8385#L974-1 assume !(1 == ~T3_E~0); 8989#L979-1 assume !(1 == ~T4_E~0); 8990#L984-1 assume !(1 == ~T5_E~0); 8532#L989-1 assume !(1 == ~T6_E~0); 8533#L994-1 assume !(1 == ~T7_E~0); 8415#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8416#L1004-1 assume !(1 == ~E_M~0); 8161#L1009-1 assume !(1 == ~E_1~0); 8162#L1014-1 assume !(1 == ~E_2~0); 8404#L1019-1 assume !(1 == ~E_3~0); 8944#L1024-1 assume !(1 == ~E_4~0); 8347#L1029-1 assume !(1 == ~E_5~0); 8348#L1034-1 assume !(1 == ~E_6~0); 8431#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9074#L1044-1 assume !(1 == ~E_8~0); 8630#L1049-1 assume { :end_inline_reset_delta_events } true; 8312#L1315-2 [2023-11-26 10:42:45,930 INFO L750 eck$LassoCheckResult]: Loop: 8312#L1315-2 assume !false; 8313#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8726#L841-1 assume !false; 8980#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8377#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8378#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8559#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8134#L724 assume !(0 != eval_~tmp~0#1); 8136#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8720#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8143#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8144#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8436#L871-3 assume !(0 == ~T2_E~0); 8437#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8453#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8454#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8694#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8695#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8552#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8553#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8696#L911-3 assume !(0 == ~E_1~0); 8910#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8480#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8481#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8899#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8560#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8561#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8711#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8438#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8439#L430-30 assume 1 == ~m_pc~0; 8465#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8466#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8537#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8538#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8927#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8933#L449-30 assume 1 == ~t1_pc~0; 8468#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8157#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8158#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8531#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8242#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8243#L468-30 assume 1 == ~t2_pc~0; 8342#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8343#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8434#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8435#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 8686#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8519#L487-30 assume 1 == ~t3_pc~0; 8497#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8317#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8748#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8749#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8951#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8603#L506-30 assume !(1 == ~t4_pc~0); 8604#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 8633#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8634#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8997#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8520#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8521#L525-30 assume !(1 == ~t5_pc~0); 9040#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 9039#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8867#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8868#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8524#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8294#L544-30 assume 1 == ~t6_pc~0; 8106#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8107#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8220#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8221#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9045#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9028#L563-30 assume 1 == ~t7_pc~0; 8261#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8262#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8283#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8620#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8621#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9018#L582-30 assume 1 == ~t8_pc~0; 8978#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8371#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8606#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9108#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9098#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8169#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8170#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8308#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8297#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8298#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8732#L984-3 assume !(1 == ~T5_E~0); 8733#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8352#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8353#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8891#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8205#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8206#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8708#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8709#L1024-3 assume !(1 == ~E_4~0); 8687#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8656#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8657#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8943#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8340#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8341#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8461#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8470#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8374#L1334 assume !(0 == start_simulation_~tmp~3#1); 8375#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8388#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8102#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8103#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 8163#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9063#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8742#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 8743#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 8312#L1315-2 [2023-11-26 10:42:45,930 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:45,931 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2023-11-26 10:42:45,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:45,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648548988] [2023-11-26 10:42:45,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:45,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:45,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:45,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:45,991 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:45,991 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648548988] [2023-11-26 10:42:45,992 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [648548988] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:45,992 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:45,992 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:45,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117484655] [2023-11-26 10:42:45,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:45,993 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:45,993 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:45,993 INFO L85 PathProgramCache]: Analyzing trace with hash 13135423, now seen corresponding path program 2 times [2023-11-26 10:42:45,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:45,994 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2066786445] [2023-11-26 10:42:45,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:45,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:46,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:46,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:46,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:46,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2066786445] [2023-11-26 10:42:46,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2066786445] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:46,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:46,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:46,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503309857] [2023-11-26 10:42:46,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:46,063 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:46,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:46,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:46,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:46,065 INFO L87 Difference]: Start difference. First operand 1007 states and 1496 transitions. cyclomatic complexity: 490 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:46,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:46,095 INFO L93 Difference]: Finished difference Result 1007 states and 1495 transitions. [2023-11-26 10:42:46,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1495 transitions. [2023-11-26 10:42:46,105 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:46,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1495 transitions. [2023-11-26 10:42:46,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-26 10:42:46,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-26 10:42:46,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1495 transitions. [2023-11-26 10:42:46,117 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:46,117 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1495 transitions. [2023-11-26 10:42:46,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1495 transitions. [2023-11-26 10:42:46,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-26 10:42:46,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4846077457795432) internal successors, (1495), 1006 states have internal predecessors, (1495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:46,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1495 transitions. [2023-11-26 10:42:46,143 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1495 transitions. [2023-11-26 10:42:46,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:46,149 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1495 transitions. [2023-11-26 10:42:46,149 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 10:42:46,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1495 transitions. [2023-11-26 10:42:46,156 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:46,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:46,157 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:46,158 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:46,159 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:46,159 INFO L748 eck$LassoCheckResult]: Stem: 10371#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10372#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 11085#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11086#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10685#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 10686#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10243#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10244#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10335#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11071#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10211#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10212#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10640#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10672#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10339#L866 assume !(0 == ~M_E~0); 10340#L866-2 assume !(0 == ~T1_E~0); 10870#L871-1 assume !(0 == ~T2_E~0); 10871#L876-1 assume !(0 == ~T3_E~0); 11111#L881-1 assume !(0 == ~T4_E~0); 10884#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10629#L891-1 assume !(0 == ~T6_E~0); 10630#L896-1 assume !(0 == ~T7_E~0); 10878#L901-1 assume !(0 == ~T8_E~0); 10899#L906-1 assume !(0 == ~E_M~0); 10900#L911-1 assume !(0 == ~E_1~0); 10682#L916-1 assume !(0 == ~E_2~0); 10683#L921-1 assume !(0 == ~E_3~0); 10992#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 11082#L931-1 assume !(0 == ~E_5~0); 11114#L936-1 assume !(0 == ~E_6~0); 11118#L941-1 assume !(0 == ~E_7~0); 10687#L946-1 assume !(0 == ~E_8~0); 10688#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11099#L430 assume !(1 == ~m_pc~0); 10529#L430-2 is_master_triggered_~__retres1~0#1 := 0; 10158#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10159#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10804#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10805#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10973#L449 assume 1 == ~t1_pc~0; 10974#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10346#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10185#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10186#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 10914#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10744#L468 assume !(1 == ~t2_pc~0); 10146#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10145#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10539#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10534#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 10160#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10161#L487 assume 1 == ~t3_pc~0; 11109#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10249#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10142#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10143#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 10607#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10608#L506 assume !(1 == ~t4_pc~0); 10739#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10789#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10235#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10236#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 10733#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10546#L525 assume 1 == ~t5_pc~0; 10480#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10199#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11030#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11031#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 10403#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10404#L544 assume !(1 == ~t6_pc~0); 10547#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10548#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10519#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10180#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 10181#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11063#L563 assume 1 == ~t7_pc~0; 10937#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10203#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10204#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10631#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 10347#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10348#L582 assume 1 == ~t8_pc~0; 10267#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10268#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10979#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10595#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 10484#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10485#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 10977#L964-2 assume !(1 == ~T1_E~0); 10405#L969-1 assume !(1 == ~T2_E~0); 10406#L974-1 assume !(1 == ~T3_E~0); 11010#L979-1 assume !(1 == ~T4_E~0); 11011#L984-1 assume !(1 == ~T5_E~0); 10553#L989-1 assume !(1 == ~T6_E~0); 10554#L994-1 assume !(1 == ~T7_E~0); 10436#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10437#L1004-1 assume !(1 == ~E_M~0); 10182#L1009-1 assume !(1 == ~E_1~0); 10183#L1014-1 assume !(1 == ~E_2~0); 10425#L1019-1 assume !(1 == ~E_3~0); 10965#L1024-1 assume !(1 == ~E_4~0); 10368#L1029-1 assume !(1 == ~E_5~0); 10369#L1034-1 assume !(1 == ~E_6~0); 10452#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11095#L1044-1 assume !(1 == ~E_8~0); 10651#L1049-1 assume { :end_inline_reset_delta_events } true; 10333#L1315-2 [2023-11-26 10:42:46,160 INFO L750 eck$LassoCheckResult]: Loop: 10333#L1315-2 assume !false; 10334#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10747#L841-1 assume !false; 11001#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10398#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10399#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10580#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10155#L724 assume !(0 != eval_~tmp~0#1); 10157#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10741#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10164#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10165#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10457#L871-3 assume !(0 == ~T2_E~0); 10458#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10474#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10475#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10715#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10716#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10573#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10574#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10717#L911-3 assume !(0 == ~E_1~0); 10931#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10501#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10502#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10920#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10581#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10582#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10732#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10459#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10460#L430-30 assume 1 == ~m_pc~0; 10486#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10487#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10558#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10559#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10948#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10954#L449-30 assume 1 == ~t1_pc~0; 10489#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10178#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10179#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10552#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10263#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10264#L468-30 assume 1 == ~t2_pc~0; 10363#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10364#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10455#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10456#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 10707#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10540#L487-30 assume !(1 == ~t3_pc~0); 10337#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 10338#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10769#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10770#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10972#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10624#L506-30 assume !(1 == ~t4_pc~0); 10625#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10654#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10655#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11018#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10541#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10542#L525-30 assume 1 == ~t5_pc~0; 11059#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11060#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10888#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10889#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10545#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10315#L544-30 assume !(1 == ~t6_pc~0); 10129#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10128#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10241#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10242#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11066#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11049#L563-30 assume 1 == ~t7_pc~0; 10282#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10283#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10304#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10641#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10642#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11039#L582-30 assume 1 == ~t8_pc~0; 10999#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10392#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10627#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11129#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11119#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10190#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10191#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10329#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10318#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10319#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10753#L984-3 assume !(1 == ~T5_E~0); 10754#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10373#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10374#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10912#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10226#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10227#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10729#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10730#L1024-3 assume !(1 == ~E_4~0); 10708#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10677#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10678#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10964#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10361#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10362#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10482#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10491#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10395#L1334 assume !(0 == start_simulation_~tmp~3#1); 10396#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10409#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10123#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10124#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 10184#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11084#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10763#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 10764#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 10333#L1315-2 [2023-11-26 10:42:46,160 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:46,161 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2023-11-26 10:42:46,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:46,161 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542792411] [2023-11-26 10:42:46,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:46,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:46,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:46,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:46,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:46,206 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542792411] [2023-11-26 10:42:46,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542792411] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:46,211 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:46,211 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:46,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963969237] [2023-11-26 10:42:46,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:46,211 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:46,212 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:46,212 INFO L85 PathProgramCache]: Analyzing trace with hash 431994368, now seen corresponding path program 1 times [2023-11-26 10:42:46,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:46,213 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045723844] [2023-11-26 10:42:46,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:46,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:46,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:46,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:46,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:46,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045723844] [2023-11-26 10:42:46,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1045723844] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:46,275 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:46,276 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:46,276 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786096969] [2023-11-26 10:42:46,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:46,277 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:46,277 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:46,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:46,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:46,278 INFO L87 Difference]: Start difference. First operand 1007 states and 1495 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:46,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:46,309 INFO L93 Difference]: Finished difference Result 1007 states and 1494 transitions. [2023-11-26 10:42:46,309 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1494 transitions. [2023-11-26 10:42:46,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:46,328 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1494 transitions. [2023-11-26 10:42:46,328 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-26 10:42:46,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-26 10:42:46,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1494 transitions. [2023-11-26 10:42:46,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:46,333 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1494 transitions. [2023-11-26 10:42:46,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1494 transitions. [2023-11-26 10:42:46,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-26 10:42:46,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.483614697120159) internal successors, (1494), 1006 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:46,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1494 transitions. [2023-11-26 10:42:46,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1494 transitions. [2023-11-26 10:42:46,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:46,362 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1494 transitions. [2023-11-26 10:42:46,362 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 10:42:46,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1494 transitions. [2023-11-26 10:42:46,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:46,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:46,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:46,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:46,372 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:46,372 INFO L748 eck$LassoCheckResult]: Stem: 12392#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13106#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13107#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12706#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 12707#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12264#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12265#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12356#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13092#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12232#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12233#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12661#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12693#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12360#L866 assume !(0 == ~M_E~0); 12361#L866-2 assume !(0 == ~T1_E~0); 12891#L871-1 assume !(0 == ~T2_E~0); 12892#L876-1 assume !(0 == ~T3_E~0); 13132#L881-1 assume !(0 == ~T4_E~0); 12905#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12650#L891-1 assume !(0 == ~T6_E~0); 12651#L896-1 assume !(0 == ~T7_E~0); 12899#L901-1 assume !(0 == ~T8_E~0); 12920#L906-1 assume !(0 == ~E_M~0); 12921#L911-1 assume !(0 == ~E_1~0); 12703#L916-1 assume !(0 == ~E_2~0); 12704#L921-1 assume !(0 == ~E_3~0); 13013#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 13103#L931-1 assume !(0 == ~E_5~0); 13135#L936-1 assume !(0 == ~E_6~0); 13139#L941-1 assume !(0 == ~E_7~0); 12708#L946-1 assume !(0 == ~E_8~0); 12709#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13120#L430 assume !(1 == ~m_pc~0); 12550#L430-2 is_master_triggered_~__retres1~0#1 := 0; 12179#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12180#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12825#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12826#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12994#L449 assume 1 == ~t1_pc~0; 12995#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12367#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12207#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 12935#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12765#L468 assume !(1 == ~t2_pc~0); 12167#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12166#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12560#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12555#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 12181#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12182#L487 assume 1 == ~t3_pc~0; 13130#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12270#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12163#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12164#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 12628#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12629#L506 assume !(1 == ~t4_pc~0); 12760#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12810#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12256#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12257#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 12754#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12567#L525 assume 1 == ~t5_pc~0; 12501#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12220#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13051#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13052#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 12424#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12425#L544 assume !(1 == ~t6_pc~0); 12568#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12569#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12540#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12201#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 12202#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13084#L563 assume 1 == ~t7_pc~0; 12958#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12224#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12652#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 12368#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12369#L582 assume 1 == ~t8_pc~0; 12288#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12289#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13000#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12616#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 12505#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12506#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 12998#L964-2 assume !(1 == ~T1_E~0); 12426#L969-1 assume !(1 == ~T2_E~0); 12427#L974-1 assume !(1 == ~T3_E~0); 13031#L979-1 assume !(1 == ~T4_E~0); 13032#L984-1 assume !(1 == ~T5_E~0); 12574#L989-1 assume !(1 == ~T6_E~0); 12575#L994-1 assume !(1 == ~T7_E~0); 12457#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12458#L1004-1 assume !(1 == ~E_M~0); 12203#L1009-1 assume !(1 == ~E_1~0); 12204#L1014-1 assume !(1 == ~E_2~0); 12446#L1019-1 assume !(1 == ~E_3~0); 12986#L1024-1 assume !(1 == ~E_4~0); 12389#L1029-1 assume !(1 == ~E_5~0); 12390#L1034-1 assume !(1 == ~E_6~0); 12473#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 13116#L1044-1 assume !(1 == ~E_8~0); 12672#L1049-1 assume { :end_inline_reset_delta_events } true; 12354#L1315-2 [2023-11-26 10:42:46,373 INFO L750 eck$LassoCheckResult]: Loop: 12354#L1315-2 assume !false; 12355#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12768#L841-1 assume !false; 13022#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12419#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12420#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12601#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12176#L724 assume !(0 != eval_~tmp~0#1); 12178#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12762#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12185#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12186#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12478#L871-3 assume !(0 == ~T2_E~0); 12479#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12495#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12496#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12736#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12737#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12594#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12595#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12738#L911-3 assume !(0 == ~E_1~0); 12952#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12522#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12523#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12941#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12602#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12603#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12753#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12480#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12481#L430-30 assume 1 == ~m_pc~0; 12507#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12508#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12579#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12580#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12969#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12975#L449-30 assume 1 == ~t1_pc~0; 12510#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12199#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12200#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12573#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12284#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12285#L468-30 assume 1 == ~t2_pc~0; 12384#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12385#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12476#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12477#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 12728#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12561#L487-30 assume !(1 == ~t3_pc~0); 12358#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 12359#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12790#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12791#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12993#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12645#L506-30 assume !(1 == ~t4_pc~0); 12646#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 12675#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12676#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13039#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12562#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12563#L525-30 assume 1 == ~t5_pc~0; 13080#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13081#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12909#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12910#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12566#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12336#L544-30 assume 1 == ~t6_pc~0; 12148#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12149#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12262#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12263#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13087#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13070#L563-30 assume !(1 == ~t7_pc~0); 12305#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 12304#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12325#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12662#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12663#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13060#L582-30 assume 1 == ~t8_pc~0; 13020#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12413#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12648#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13150#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13140#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12211#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12212#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12350#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12339#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12340#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12774#L984-3 assume !(1 == ~T5_E~0); 12775#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12394#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12395#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12933#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12247#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12248#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12750#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12751#L1024-3 assume !(1 == ~E_4~0); 12729#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12698#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12699#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12985#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12382#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12383#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12503#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12512#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12416#L1334 assume !(0 == start_simulation_~tmp~3#1); 12417#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12430#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12144#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12145#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 12205#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13105#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12784#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12785#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 12354#L1315-2 [2023-11-26 10:42:46,373 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:46,374 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2023-11-26 10:42:46,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:46,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543470981] [2023-11-26 10:42:46,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:46,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:46,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:46,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:46,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:46,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1543470981] [2023-11-26 10:42:46,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1543470981] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:46,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:46,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:46,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418467462] [2023-11-26 10:42:46,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:46,423 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:46,423 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:46,424 INFO L85 PathProgramCache]: Analyzing trace with hash 862321344, now seen corresponding path program 1 times [2023-11-26 10:42:46,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:46,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364004303] [2023-11-26 10:42:46,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:46,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:46,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:46,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:46,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:46,529 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364004303] [2023-11-26 10:42:46,529 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364004303] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:46,529 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:46,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:46,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845290463] [2023-11-26 10:42:46,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:46,530 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:46,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:46,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:46,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:46,531 INFO L87 Difference]: Start difference. First operand 1007 states and 1494 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:46,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:46,559 INFO L93 Difference]: Finished difference Result 1007 states and 1493 transitions. [2023-11-26 10:42:46,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1493 transitions. [2023-11-26 10:42:46,569 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:46,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1493 transitions. [2023-11-26 10:42:46,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-26 10:42:46,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-26 10:42:46,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1493 transitions. [2023-11-26 10:42:46,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:46,581 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1493 transitions. [2023-11-26 10:42:46,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1493 transitions. [2023-11-26 10:42:46,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-26 10:42:46,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4826216484607746) internal successors, (1493), 1006 states have internal predecessors, (1493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:46,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1493 transitions. [2023-11-26 10:42:46,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1493 transitions. [2023-11-26 10:42:46,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:46,610 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1493 transitions. [2023-11-26 10:42:46,610 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 10:42:46,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1493 transitions. [2023-11-26 10:42:46,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:46,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:46,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:46,620 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:46,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:46,620 INFO L748 eck$LassoCheckResult]: Stem: 14413#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15127#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15128#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14727#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 14728#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14285#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14286#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14377#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15113#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14253#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14254#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14682#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14714#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14381#L866 assume !(0 == ~M_E~0); 14382#L866-2 assume !(0 == ~T1_E~0); 14912#L871-1 assume !(0 == ~T2_E~0); 14913#L876-1 assume !(0 == ~T3_E~0); 15153#L881-1 assume !(0 == ~T4_E~0); 14926#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14671#L891-1 assume !(0 == ~T6_E~0); 14672#L896-1 assume !(0 == ~T7_E~0); 14920#L901-1 assume !(0 == ~T8_E~0); 14941#L906-1 assume !(0 == ~E_M~0); 14942#L911-1 assume !(0 == ~E_1~0); 14724#L916-1 assume !(0 == ~E_2~0); 14725#L921-1 assume !(0 == ~E_3~0); 15034#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 15124#L931-1 assume !(0 == ~E_5~0); 15156#L936-1 assume !(0 == ~E_6~0); 15160#L941-1 assume !(0 == ~E_7~0); 14729#L946-1 assume !(0 == ~E_8~0); 14730#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15141#L430 assume !(1 == ~m_pc~0); 14571#L430-2 is_master_triggered_~__retres1~0#1 := 0; 14200#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14201#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14846#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14847#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15015#L449 assume 1 == ~t1_pc~0; 15016#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14388#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14227#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14228#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 14956#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14786#L468 assume !(1 == ~t2_pc~0); 14188#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14187#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14581#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14576#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 14202#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14203#L487 assume 1 == ~t3_pc~0; 15151#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14291#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14184#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14185#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 14649#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14650#L506 assume !(1 == ~t4_pc~0); 14781#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14831#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14277#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14278#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 14775#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14588#L525 assume 1 == ~t5_pc~0; 14522#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14241#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15072#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15073#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 14445#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14446#L544 assume !(1 == ~t6_pc~0); 14589#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14590#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14561#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14222#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 14223#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15105#L563 assume 1 == ~t7_pc~0; 14979#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14245#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14246#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14673#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 14389#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14390#L582 assume 1 == ~t8_pc~0; 14309#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14310#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15021#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14637#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 14526#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14527#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 15019#L964-2 assume !(1 == ~T1_E~0); 14447#L969-1 assume !(1 == ~T2_E~0); 14448#L974-1 assume !(1 == ~T3_E~0); 15052#L979-1 assume !(1 == ~T4_E~0); 15053#L984-1 assume !(1 == ~T5_E~0); 14595#L989-1 assume !(1 == ~T6_E~0); 14596#L994-1 assume !(1 == ~T7_E~0); 14478#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14479#L1004-1 assume !(1 == ~E_M~0); 14224#L1009-1 assume !(1 == ~E_1~0); 14225#L1014-1 assume !(1 == ~E_2~0); 14467#L1019-1 assume !(1 == ~E_3~0); 15007#L1024-1 assume !(1 == ~E_4~0); 14410#L1029-1 assume !(1 == ~E_5~0); 14411#L1034-1 assume !(1 == ~E_6~0); 14494#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15137#L1044-1 assume !(1 == ~E_8~0); 14693#L1049-1 assume { :end_inline_reset_delta_events } true; 14375#L1315-2 [2023-11-26 10:42:46,621 INFO L750 eck$LassoCheckResult]: Loop: 14375#L1315-2 assume !false; 14376#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14789#L841-1 assume !false; 15043#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14440#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14441#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14622#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14197#L724 assume !(0 != eval_~tmp~0#1); 14199#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14783#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14206#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14207#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14499#L871-3 assume !(0 == ~T2_E~0); 14500#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14516#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14517#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14757#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14758#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14615#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14616#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14759#L911-3 assume !(0 == ~E_1~0); 14973#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14543#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14544#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14962#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14623#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14624#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14774#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14501#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14502#L430-30 assume 1 == ~m_pc~0; 14528#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14529#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14600#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14601#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14990#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14996#L449-30 assume 1 == ~t1_pc~0; 14531#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14220#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14221#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14594#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14305#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14306#L468-30 assume 1 == ~t2_pc~0; 14405#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14406#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14497#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14498#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 14749#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14582#L487-30 assume 1 == ~t3_pc~0; 14560#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14380#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14811#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14812#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15014#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14666#L506-30 assume !(1 == ~t4_pc~0); 14667#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14696#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14697#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15060#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14583#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14584#L525-30 assume 1 == ~t5_pc~0; 15101#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15102#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14930#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14931#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14587#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14357#L544-30 assume 1 == ~t6_pc~0; 14169#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14170#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14283#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14284#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15108#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15091#L563-30 assume 1 == ~t7_pc~0; 14324#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14325#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14346#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14683#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14684#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15081#L582-30 assume 1 == ~t8_pc~0; 15041#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14434#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14669#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15171#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15161#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14232#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14233#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14371#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14360#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14361#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14795#L984-3 assume !(1 == ~T5_E~0); 14796#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14415#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14416#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14954#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14268#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14269#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14771#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14772#L1024-3 assume !(1 == ~E_4~0); 14750#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14719#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14720#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15006#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14403#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14404#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14524#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14533#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14437#L1334 assume !(0 == start_simulation_~tmp~3#1); 14438#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14451#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14165#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14166#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 14226#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15126#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14805#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14806#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 14375#L1315-2 [2023-11-26 10:42:46,621 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:46,622 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2023-11-26 10:42:46,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:46,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549786023] [2023-11-26 10:42:46,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:46,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:46,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:46,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:46,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:46,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549786023] [2023-11-26 10:42:46,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549786023] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:46,685 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:46,685 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:46,689 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1682544497] [2023-11-26 10:42:46,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:46,690 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:46,690 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:46,690 INFO L85 PathProgramCache]: Analyzing trace with hash 1121264062, now seen corresponding path program 1 times [2023-11-26 10:42:46,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:46,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964733717] [2023-11-26 10:42:46,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:46,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:46,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:46,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:46,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:46,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964733717] [2023-11-26 10:42:46,778 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964733717] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:46,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:46,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:46,779 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845187289] [2023-11-26 10:42:46,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:46,780 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:46,780 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:46,781 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:46,781 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:46,781 INFO L87 Difference]: Start difference. First operand 1007 states and 1493 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:46,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:46,808 INFO L93 Difference]: Finished difference Result 1007 states and 1492 transitions. [2023-11-26 10:42:46,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1492 transitions. [2023-11-26 10:42:46,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:46,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1492 transitions. [2023-11-26 10:42:46,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2023-11-26 10:42:46,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2023-11-26 10:42:46,830 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1492 transitions. [2023-11-26 10:42:46,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:46,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1492 transitions. [2023-11-26 10:42:46,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1492 transitions. [2023-11-26 10:42:46,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2023-11-26 10:42:46,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.4816285998013903) internal successors, (1492), 1006 states have internal predecessors, (1492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:46,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1492 transitions. [2023-11-26 10:42:46,860 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1492 transitions. [2023-11-26 10:42:46,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:46,862 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007 states and 1492 transitions. [2023-11-26 10:42:46,863 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 10:42:46,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1492 transitions. [2023-11-26 10:42:46,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 892 [2023-11-26 10:42:46,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:46,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:46,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:46,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:46,873 INFO L748 eck$LassoCheckResult]: Stem: 16434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17148#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17149#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16748#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 16749#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16306#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16307#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16398#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17134#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16274#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16275#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16703#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16735#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16402#L866 assume !(0 == ~M_E~0); 16403#L866-2 assume !(0 == ~T1_E~0); 16933#L871-1 assume !(0 == ~T2_E~0); 16934#L876-1 assume !(0 == ~T3_E~0); 17174#L881-1 assume !(0 == ~T4_E~0); 16947#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16692#L891-1 assume !(0 == ~T6_E~0); 16693#L896-1 assume !(0 == ~T7_E~0); 16941#L901-1 assume !(0 == ~T8_E~0); 16962#L906-1 assume !(0 == ~E_M~0); 16963#L911-1 assume !(0 == ~E_1~0); 16745#L916-1 assume !(0 == ~E_2~0); 16746#L921-1 assume !(0 == ~E_3~0); 17055#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 17145#L931-1 assume !(0 == ~E_5~0); 17177#L936-1 assume !(0 == ~E_6~0); 17181#L941-1 assume !(0 == ~E_7~0); 16750#L946-1 assume !(0 == ~E_8~0); 16751#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17162#L430 assume !(1 == ~m_pc~0); 16592#L430-2 is_master_triggered_~__retres1~0#1 := 0; 16221#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16222#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16867#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16868#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17036#L449 assume 1 == ~t1_pc~0; 17037#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16409#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16249#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 16977#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16807#L468 assume !(1 == ~t2_pc~0); 16209#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16208#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16602#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16597#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 16223#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16224#L487 assume 1 == ~t3_pc~0; 17172#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16312#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16205#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16206#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 16670#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16671#L506 assume !(1 == ~t4_pc~0); 16802#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16852#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16298#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16299#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 16796#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16609#L525 assume 1 == ~t5_pc~0; 16543#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16262#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17093#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17094#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 16466#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16467#L544 assume !(1 == ~t6_pc~0); 16610#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16611#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16582#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16243#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 16244#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17126#L563 assume 1 == ~t7_pc~0; 17000#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16266#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16694#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 16410#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16411#L582 assume 1 == ~t8_pc~0; 16330#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16331#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17042#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16658#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 16547#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16548#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 17040#L964-2 assume !(1 == ~T1_E~0); 16468#L969-1 assume !(1 == ~T2_E~0); 16469#L974-1 assume !(1 == ~T3_E~0); 17073#L979-1 assume !(1 == ~T4_E~0); 17074#L984-1 assume !(1 == ~T5_E~0); 16616#L989-1 assume !(1 == ~T6_E~0); 16617#L994-1 assume !(1 == ~T7_E~0); 16499#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16500#L1004-1 assume !(1 == ~E_M~0); 16245#L1009-1 assume !(1 == ~E_1~0); 16246#L1014-1 assume !(1 == ~E_2~0); 16488#L1019-1 assume !(1 == ~E_3~0); 17028#L1024-1 assume !(1 == ~E_4~0); 16431#L1029-1 assume !(1 == ~E_5~0); 16432#L1034-1 assume !(1 == ~E_6~0); 16515#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17158#L1044-1 assume !(1 == ~E_8~0); 16714#L1049-1 assume { :end_inline_reset_delta_events } true; 16396#L1315-2 [2023-11-26 10:42:46,873 INFO L750 eck$LassoCheckResult]: Loop: 16396#L1315-2 assume !false; 16397#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16810#L841-1 assume !false; 17064#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16461#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16462#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16643#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16218#L724 assume !(0 != eval_~tmp~0#1); 16220#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16804#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16227#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16228#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16520#L871-3 assume !(0 == ~T2_E~0); 16521#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16537#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16538#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16778#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16779#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16636#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16637#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16780#L911-3 assume !(0 == ~E_1~0); 16994#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16564#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16565#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16983#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16644#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16645#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16795#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16522#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16523#L430-30 assume 1 == ~m_pc~0; 16549#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16550#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16621#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16622#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17011#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17017#L449-30 assume 1 == ~t1_pc~0; 16552#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16241#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16242#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16615#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16326#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16327#L468-30 assume 1 == ~t2_pc~0; 16426#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16427#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16518#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16519#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 16770#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16603#L487-30 assume !(1 == ~t3_pc~0); 16400#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 16401#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16832#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16833#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17035#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16687#L506-30 assume !(1 == ~t4_pc~0); 16688#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 16717#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16718#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17081#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16604#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16605#L525-30 assume 1 == ~t5_pc~0; 17122#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17123#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16951#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16952#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16608#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16378#L544-30 assume !(1 == ~t6_pc~0); 16192#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 16191#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16304#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16305#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17129#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17112#L563-30 assume 1 == ~t7_pc~0; 16345#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16346#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16367#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16704#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16705#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17102#L582-30 assume 1 == ~t8_pc~0; 17062#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16455#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16690#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17192#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17182#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16253#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16254#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16392#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16381#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16382#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16816#L984-3 assume !(1 == ~T5_E~0); 16817#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16436#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16437#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16975#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16289#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16290#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16792#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16793#L1024-3 assume !(1 == ~E_4~0); 16771#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16740#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16741#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17027#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16424#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16425#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16545#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16554#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16458#L1334 assume !(0 == start_simulation_~tmp~3#1); 16459#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16472#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16186#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16187#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 16247#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17147#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16826#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 16827#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 16396#L1315-2 [2023-11-26 10:42:46,874 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:46,874 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2023-11-26 10:42:46,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:46,874 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569576826] [2023-11-26 10:42:46,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:46,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:46,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:46,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:46,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:46,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569576826] [2023-11-26 10:42:46,981 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1569576826] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:46,981 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:46,981 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:46,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377935435] [2023-11-26 10:42:46,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:46,982 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:46,982 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:46,982 INFO L85 PathProgramCache]: Analyzing trace with hash 431994368, now seen corresponding path program 2 times [2023-11-26 10:42:46,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:46,983 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293170216] [2023-11-26 10:42:46,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:46,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:47,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:47,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:47,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:47,051 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293170216] [2023-11-26 10:42:47,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1293170216] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:47,051 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:47,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:47,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553352575] [2023-11-26 10:42:47,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:47,052 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:47,052 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:47,053 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:42:47,053 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:42:47,053 INFO L87 Difference]: Start difference. First operand 1007 states and 1492 transitions. cyclomatic complexity: 486 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:47,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:47,207 INFO L93 Difference]: Finished difference Result 1834 states and 2707 transitions. [2023-11-26 10:42:47,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1834 states and 2707 transitions. [2023-11-26 10:42:47,224 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1701 [2023-11-26 10:42:47,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1834 states to 1834 states and 2707 transitions. [2023-11-26 10:42:47,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1834 [2023-11-26 10:42:47,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1834 [2023-11-26 10:42:47,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1834 states and 2707 transitions. [2023-11-26 10:42:47,246 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:47,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1834 states and 2707 transitions. [2023-11-26 10:42:47,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1834 states and 2707 transitions. [2023-11-26 10:42:47,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1834 to 1834. [2023-11-26 10:42:47,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1834 states, 1834 states have (on average 1.4760087241003272) internal successors, (2707), 1833 states have internal predecessors, (2707), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:47,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1834 states to 1834 states and 2707 transitions. [2023-11-26 10:42:47,301 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1834 states and 2707 transitions. [2023-11-26 10:42:47,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:42:47,302 INFO L428 stractBuchiCegarLoop]: Abstraction has 1834 states and 2707 transitions. [2023-11-26 10:42:47,302 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 10:42:47,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1834 states and 2707 transitions. [2023-11-26 10:42:47,313 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1701 [2023-11-26 10:42:47,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:47,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:47,315 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:47,315 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:47,315 INFO L748 eck$LassoCheckResult]: Stem: 19286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 20088#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20089#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19617#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 19618#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19157#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19158#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19250#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20066#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19125#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19126#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19570#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19604#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19254#L866 assume !(0 == ~M_E~0); 19255#L866-2 assume !(0 == ~T1_E~0); 19816#L871-1 assume !(0 == ~T2_E~0); 19817#L876-1 assume !(0 == ~T3_E~0); 20138#L881-1 assume !(0 == ~T4_E~0); 19830#L886-1 assume !(0 == ~T5_E~0); 19559#L891-1 assume !(0 == ~T6_E~0); 19560#L896-1 assume !(0 == ~T7_E~0); 19824#L901-1 assume !(0 == ~T8_E~0); 19845#L906-1 assume !(0 == ~E_M~0); 19846#L911-1 assume !(0 == ~E_1~0); 19614#L916-1 assume !(0 == ~E_2~0); 19615#L921-1 assume !(0 == ~E_3~0); 19955#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 20084#L931-1 assume !(0 == ~E_5~0); 20144#L936-1 assume !(0 == ~E_6~0); 20156#L941-1 assume !(0 == ~E_7~0); 19619#L946-1 assume !(0 == ~E_8~0); 19620#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20111#L430 assume !(1 == ~m_pc~0); 19455#L430-2 is_master_triggered_~__retres1~0#1 := 0; 19072#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19073#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19745#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19746#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19931#L449 assume 1 == ~t1_pc~0; 19932#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19261#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19099#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19100#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 19862#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19679#L468 assume !(1 == ~t2_pc~0); 19060#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19059#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19465#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19460#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 19074#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19075#L487 assume 1 == ~t3_pc~0; 20133#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19163#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19056#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19057#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 19537#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19538#L506 assume !(1 == ~t4_pc~0); 19673#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19729#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19149#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19150#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 19666#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19472#L525 assume 1 == ~t5_pc~0; 19403#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19113#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20006#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20007#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 19319#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19320#L544 assume !(1 == ~t6_pc~0); 19473#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19474#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19444#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19094#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 19095#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20054#L563 assume 1 == ~t7_pc~0; 19888#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19117#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19118#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19561#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 19262#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19263#L582 assume 1 == ~t8_pc~0; 19181#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19182#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19939#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19523#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 19407#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19408#L964 assume !(1 == ~M_E~0); 19935#L964-2 assume !(1 == ~T1_E~0); 19321#L969-1 assume !(1 == ~T2_E~0); 19322#L974-1 assume !(1 == ~T3_E~0); 19977#L979-1 assume !(1 == ~T4_E~0); 19978#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20176#L989-1 assume !(1 == ~T6_E~0); 20723#L994-1 assume !(1 == ~T7_E~0); 20722#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20721#L1004-1 assume !(1 == ~E_M~0); 20720#L1009-1 assume !(1 == ~E_1~0); 20719#L1014-1 assume !(1 == ~E_2~0); 20718#L1019-1 assume !(1 == ~E_3~0); 20717#L1024-1 assume !(1 == ~E_4~0); 19283#L1029-1 assume !(1 == ~E_5~0); 19284#L1034-1 assume !(1 == ~E_6~0); 19371#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 20180#L1044-1 assume !(1 == ~E_8~0); 19581#L1049-1 assume { :end_inline_reset_delta_events } true; 19248#L1315-2 [2023-11-26 10:42:47,316 INFO L750 eck$LassoCheckResult]: Loop: 19248#L1315-2 assume !false; 19249#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19682#L841-1 assume !false; 20113#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20114#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19980#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19507#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19069#L724 assume !(0 != eval_~tmp~0#1); 19071#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19675#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19676#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20136#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19377#L871-3 assume !(0 == ~T2_E~0); 19378#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19397#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19398#L886-3 assume !(0 == ~T5_E~0); 19648#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19649#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19500#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19501#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19650#L911-3 assume !(0 == ~E_1~0); 19881#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19424#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19425#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19869#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19508#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19509#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19665#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19379#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19380#L430-30 assume 1 == ~m_pc~0; 19409#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19410#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19484#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19485#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19903#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19911#L449-30 assume 1 == ~t1_pc~0; 19412#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19092#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19093#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19478#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19177#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19178#L468-30 assume !(1 == ~t2_pc~0); 19280#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 19279#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19375#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19376#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 19640#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19466#L487-30 assume 1 == ~t3_pc~0; 19443#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19253#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19705#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19706#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19930#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19554#L506-30 assume !(1 == ~t4_pc~0); 19555#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 19584#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19585#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19991#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19467#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19468#L525-30 assume 1 == ~t5_pc~0; 20049#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20050#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19834#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19835#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19471#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19229#L544-30 assume 1 == ~t6_pc~0; 19041#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19042#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19155#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19156#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20059#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20033#L563-30 assume 1 == ~t7_pc~0; 19196#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19197#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19218#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19571#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19572#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20017#L582-30 assume 1 == ~t8_pc~0; 19962#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19308#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19557#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20179#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20158#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19104#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19105#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19244#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19232#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19233#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19689#L984-3 assume !(1 == ~T5_E~0); 19690#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19288#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19289#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19860#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19140#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19141#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19662#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19663#L1024-3 assume !(1 == ~E_4~0); 19641#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19609#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19610#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19922#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19276#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19277#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19405#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20762#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 20761#L1334 assume !(0 == start_simulation_~tmp~3#1); 20027#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20758#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20751#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20750#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 20749#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20086#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20087#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 20065#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 19248#L1315-2 [2023-11-26 10:42:47,317 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:47,317 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2023-11-26 10:42:47,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:47,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718127047] [2023-11-26 10:42:47,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:47,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:47,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:47,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:47,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:47,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [718127047] [2023-11-26 10:42:47,432 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [718127047] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:47,432 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:47,433 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:47,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [910086243] [2023-11-26 10:42:47,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:47,434 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:47,435 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:47,435 INFO L85 PathProgramCache]: Analyzing trace with hash -10674303, now seen corresponding path program 1 times [2023-11-26 10:42:47,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:47,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275207903] [2023-11-26 10:42:47,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:47,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:47,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:47,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:47,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:47,496 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275207903] [2023-11-26 10:42:47,496 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275207903] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:47,496 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:47,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:47,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458544474] [2023-11-26 10:42:47,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:47,497 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:47,498 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:47,498 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:42:47,498 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:42:47,499 INFO L87 Difference]: Start difference. First operand 1834 states and 2707 transitions. cyclomatic complexity: 875 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:47,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:47,719 INFO L93 Difference]: Finished difference Result 3342 states and 4920 transitions. [2023-11-26 10:42:47,720 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3342 states and 4920 transitions. [2023-11-26 10:42:47,749 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3189 [2023-11-26 10:42:47,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3342 states to 3342 states and 4920 transitions. [2023-11-26 10:42:47,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3342 [2023-11-26 10:42:47,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3342 [2023-11-26 10:42:47,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3342 states and 4920 transitions. [2023-11-26 10:42:47,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:47,794 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3342 states and 4920 transitions. [2023-11-26 10:42:47,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3342 states and 4920 transitions. [2023-11-26 10:42:47,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3342 to 3340. [2023-11-26 10:42:47,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3340 states, 3340 states have (on average 1.4724550898203592) internal successors, (4918), 3339 states have internal predecessors, (4918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:47,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3340 states to 3340 states and 4918 transitions. [2023-11-26 10:42:47,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3340 states and 4918 transitions. [2023-11-26 10:42:47,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:42:47,949 INFO L428 stractBuchiCegarLoop]: Abstraction has 3340 states and 4918 transitions. [2023-11-26 10:42:47,949 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 10:42:47,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3340 states and 4918 transitions. [2023-11-26 10:42:47,968 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3189 [2023-11-26 10:42:47,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:47,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:47,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:47,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:47,971 INFO L748 eck$LassoCheckResult]: Stem: 24475#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25231#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25232#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24799#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 24800#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24345#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24346#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24439#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25214#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24312#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24313#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24753#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24786#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24443#L866 assume !(0 == ~M_E~0); 24444#L866-2 assume !(0 == ~T1_E~0); 24993#L871-1 assume !(0 == ~T2_E~0); 24994#L876-1 assume !(0 == ~T3_E~0); 25272#L881-1 assume !(0 == ~T4_E~0); 25008#L886-1 assume !(0 == ~T5_E~0); 24742#L891-1 assume !(0 == ~T6_E~0); 24743#L896-1 assume !(0 == ~T7_E~0); 25001#L901-1 assume !(0 == ~T8_E~0); 25024#L906-1 assume !(0 == ~E_M~0); 25025#L911-1 assume !(0 == ~E_1~0); 24796#L916-1 assume !(0 == ~E_2~0); 24797#L921-1 assume !(0 == ~E_3~0); 25125#L926-1 assume !(0 == ~E_4~0); 25228#L931-1 assume !(0 == ~E_5~0); 25280#L936-1 assume !(0 == ~E_6~0); 25286#L941-1 assume !(0 == ~E_7~0); 24801#L946-1 assume !(0 == ~E_8~0); 24802#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25252#L430 assume !(1 == ~m_pc~0); 24640#L430-2 is_master_triggered_~__retres1~0#1 := 0; 24258#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24259#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24925#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24926#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25101#L449 assume 1 == ~t1_pc~0; 25102#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24450#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24285#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24286#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 25039#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24863#L468 assume !(1 == ~t2_pc~0); 24246#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24245#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24645#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 24260#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24261#L487 assume 1 == ~t3_pc~0; 25269#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24351#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24242#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24243#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 24720#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24721#L506 assume !(1 == ~t4_pc~0); 24858#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24910#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24337#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24338#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 24850#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24657#L525 assume 1 == ~t5_pc~0; 24586#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24300#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25166#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25167#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 24507#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24508#L544 assume !(1 == ~t6_pc~0); 24658#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24659#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24629#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24280#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 24281#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25203#L563 assume 1 == ~t7_pc~0; 25064#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24304#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24305#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24744#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 24451#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24452#L582 assume 1 == ~t8_pc~0; 24369#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24370#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25108#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24707#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 24590#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24591#L964 assume !(1 == ~M_E~0); 25105#L964-2 assume !(1 == ~T1_E~0); 25488#L969-1 assume !(1 == ~T2_E~0); 25486#L974-1 assume !(1 == ~T3_E~0); 25143#L979-1 assume !(1 == ~T4_E~0); 25144#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25300#L989-1 assume !(1 == ~T6_E~0); 25439#L994-1 assume !(1 == ~T7_E~0); 25437#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25435#L1004-1 assume !(1 == ~E_M~0); 24282#L1009-1 assume !(1 == ~E_1~0); 24283#L1014-1 assume !(1 == ~E_2~0); 25405#L1019-1 assume !(1 == ~E_3~0); 25383#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25381#L1029-1 assume !(1 == ~E_5~0); 25380#L1034-1 assume !(1 == ~E_6~0); 25360#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25351#L1044-1 assume !(1 == ~E_8~0); 25343#L1049-1 assume { :end_inline_reset_delta_events } true; 25336#L1315-2 [2023-11-26 10:42:47,971 INFO L750 eck$LassoCheckResult]: Loop: 25336#L1315-2 assume !false; 25332#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25331#L841-1 assume !false; 25330#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25325#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25320#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25319#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25317#L724 assume !(0 != eval_~tmp~0#1); 25316#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25315#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25313#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25314#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25881#L871-3 assume !(0 == ~T2_E~0); 25878#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25876#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25874#L886-3 assume !(0 == ~T5_E~0); 25872#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25870#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25868#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25865#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25863#L911-3 assume !(0 == ~E_1~0); 25861#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25859#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25858#L926-3 assume !(0 == ~E_4~0); 25857#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25855#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25852#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25850#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25848#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25846#L430-30 assume 1 == ~m_pc~0; 25842#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25839#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25837#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25835#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25833#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25831#L449-30 assume !(1 == ~t1_pc~0); 25828#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 25825#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25823#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25821#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25819#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25817#L468-30 assume 1 == ~t2_pc~0; 25814#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25811#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25809#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25807#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 25805#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25803#L487-30 assume 1 == ~t3_pc~0; 25800#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25797#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25795#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25793#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25791#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25789#L506-30 assume !(1 == ~t4_pc~0); 25786#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 25783#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25781#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25780#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25779#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25778#L525-30 assume 1 == ~t5_pc~0; 25776#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25775#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25774#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25773#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25772#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25771#L544-30 assume !(1 == ~t6_pc~0); 25769#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 25768#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25767#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25766#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25765#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25764#L563-30 assume 1 == ~t7_pc~0; 25760#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25758#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25756#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25755#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25754#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25753#L582-30 assume !(1 == ~t8_pc~0); 25731#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 25704#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25701#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25699#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25697#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25696#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24291#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25662#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25661#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25659#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25641#L984-3 assume !(1 == ~T5_E~0); 25640#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25637#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25635#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25634#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25609#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25597#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25593#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25582#L1024-3 assume !(1 == ~E_4~0); 25549#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25523#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25513#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25507#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25506#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25474#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25465#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25464#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25460#L1334 assume !(0 == start_simulation_~tmp~3#1); 25185#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25430#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25397#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25379#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 25375#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25359#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25350#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 25342#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 25336#L1315-2 [2023-11-26 10:42:47,972 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:47,972 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2023-11-26 10:42:47,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:47,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498666384] [2023-11-26 10:42:47,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:47,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:48,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:48,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:48,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:48,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498666384] [2023-11-26 10:42:48,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498666384] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:48,076 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:48,076 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:42:48,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992883566] [2023-11-26 10:42:48,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:48,077 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:48,077 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:48,078 INFO L85 PathProgramCache]: Analyzing trace with hash 1868159045, now seen corresponding path program 1 times [2023-11-26 10:42:48,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:48,078 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834578336] [2023-11-26 10:42:48,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:48,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:48,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:48,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:48,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:48,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834578336] [2023-11-26 10:42:48,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834578336] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:48,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:48,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:42:48,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1839789133] [2023-11-26 10:42:48,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:48,178 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:48,179 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:48,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:42:48,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:42:48,180 INFO L87 Difference]: Start difference. First operand 3340 states and 4918 transitions. cyclomatic complexity: 1582 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:48,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:48,659 INFO L93 Difference]: Finished difference Result 8807 states and 12787 transitions. [2023-11-26 10:42:48,660 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8807 states and 12787 transitions. [2023-11-26 10:42:48,733 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8484 [2023-11-26 10:42:48,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8807 states to 8807 states and 12787 transitions. [2023-11-26 10:42:48,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8807 [2023-11-26 10:42:48,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8807 [2023-11-26 10:42:48,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8807 states and 12787 transitions. [2023-11-26 10:42:48,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:48,821 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8807 states and 12787 transitions. [2023-11-26 10:42:48,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8807 states and 12787 transitions. [2023-11-26 10:42:48,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8807 to 3460. [2023-11-26 10:42:48,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3460 states, 3460 states have (on average 1.4560693641618496) internal successors, (5038), 3459 states have internal predecessors, (5038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:48,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 5038 transitions. [2023-11-26 10:42:48,961 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3460 states and 5038 transitions. [2023-11-26 10:42:48,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 10:42:48,962 INFO L428 stractBuchiCegarLoop]: Abstraction has 3460 states and 5038 transitions. [2023-11-26 10:42:48,962 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 10:42:48,963 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3460 states and 5038 transitions. [2023-11-26 10:42:48,983 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3306 [2023-11-26 10:42:48,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:48,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:48,985 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:48,986 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:48,986 INFO L748 eck$LassoCheckResult]: Stem: 36635#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 36636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 37419#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37420#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36958#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 36959#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36508#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36509#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36599#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37401#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36474#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36475#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36915#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36945#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36604#L866 assume !(0 == ~M_E~0); 36605#L866-2 assume !(0 == ~T1_E~0); 37157#L871-1 assume !(0 == ~T2_E~0); 37158#L876-1 assume !(0 == ~T3_E~0); 37463#L881-1 assume !(0 == ~T4_E~0); 37172#L886-1 assume !(0 == ~T5_E~0); 36902#L891-1 assume !(0 == ~T6_E~0); 36903#L896-1 assume !(0 == ~T7_E~0); 37165#L901-1 assume !(0 == ~T8_E~0); 37188#L906-1 assume !(0 == ~E_M~0); 37189#L911-1 assume !(0 == ~E_1~0); 36955#L916-1 assume !(0 == ~E_2~0); 36956#L921-1 assume !(0 == ~E_3~0); 37296#L926-1 assume !(0 == ~E_4~0); 37416#L931-1 assume !(0 == ~E_5~0); 37468#L936-1 assume !(0 == ~E_6~0); 37481#L941-1 assume !(0 == ~E_7~0); 36961#L946-1 assume !(0 == ~E_8~0); 36962#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37445#L430 assume !(1 == ~m_pc~0); 36802#L430-2 is_master_triggered_~__retres1~0#1 := 0; 36422#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36423#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37088#L1073 assume !(0 != activate_threads_~tmp~1#1); 37089#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37274#L449 assume 1 == ~t1_pc~0; 37275#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36610#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36450#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36451#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 37203#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37024#L468 assume !(1 == ~t2_pc~0); 36408#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36407#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36810#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36807#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 36424#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36425#L487 assume 1 == ~t3_pc~0; 37461#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36512#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36404#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36405#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 36880#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36881#L506 assume !(1 == ~t4_pc~0); 37017#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37071#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36498#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36499#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 37010#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36817#L525 assume 1 == ~t5_pc~0; 36752#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36462#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37349#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37350#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 36667#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36668#L544 assume !(1 == ~t6_pc~0); 36818#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36819#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36788#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36442#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 36443#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37390#L563 assume 1 == ~t7_pc~0; 37228#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36466#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36467#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36906#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 36613#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36614#L582 assume 1 == ~t8_pc~0; 36530#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36531#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37281#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36867#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 36753#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36754#L964 assume !(1 == ~M_E~0); 37279#L964-2 assume !(1 == ~T1_E~0); 36669#L969-1 assume !(1 == ~T2_E~0); 36670#L974-1 assume !(1 == ~T3_E~0); 37320#L979-1 assume !(1 == ~T4_E~0); 37321#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37650#L989-1 assume !(1 == ~T6_E~0); 37648#L994-1 assume !(1 == ~T7_E~0); 37643#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37642#L1004-1 assume !(1 == ~E_M~0); 37631#L1009-1 assume !(1 == ~E_1~0); 36693#L1014-1 assume !(1 == ~E_2~0); 36694#L1019-1 assume !(1 == ~E_3~0); 37594#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 37579#L1029-1 assume !(1 == ~E_5~0); 37577#L1034-1 assume !(1 == ~E_6~0); 37565#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37556#L1044-1 assume !(1 == ~E_8~0); 37548#L1049-1 assume { :end_inline_reset_delta_events } true; 37541#L1315-2 [2023-11-26 10:42:48,987 INFO L750 eck$LassoCheckResult]: Loop: 37541#L1315-2 assume !false; 37537#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37536#L841-1 assume !false; 37535#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37530#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37525#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37524#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37522#L724 assume !(0 != eval_~tmp~0#1); 37521#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37520#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37518#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37519#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38307#L871-3 assume !(0 == ~T2_E~0); 38306#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38305#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38304#L886-3 assume !(0 == ~T5_E~0); 38303#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38302#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38301#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38300#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38299#L911-3 assume !(0 == ~E_1~0); 38298#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38297#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38296#L926-3 assume !(0 == ~E_4~0); 38295#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38294#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38293#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38292#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38291#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38290#L430-30 assume 1 == ~m_pc~0; 38288#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 38286#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38284#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38282#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38280#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38278#L449-30 assume !(1 == ~t1_pc~0); 38275#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 38273#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38270#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38268#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38266#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38264#L468-30 assume 1 == ~t2_pc~0; 38261#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38259#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38256#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38254#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 38252#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38250#L487-30 assume 1 == ~t3_pc~0; 38247#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38245#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38244#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38241#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38239#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38237#L506-30 assume !(1 == ~t4_pc~0); 38234#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 38232#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38229#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38227#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38225#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38223#L525-30 assume 1 == ~t5_pc~0; 38220#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38218#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38215#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38213#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38211#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38209#L544-30 assume !(1 == ~t6_pc~0); 38206#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 38204#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38201#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38199#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38197#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37854#L563-30 assume 1 == ~t7_pc~0; 37852#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37850#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37849#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37848#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37752#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37749#L582-30 assume !(1 == ~t8_pc~0); 37746#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 37744#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37742#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37740#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37726#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37723#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36448#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37718#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37715#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37712#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37709#L984-3 assume !(1 == ~T5_E~0); 37708#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37706#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37704#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37702#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37700#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37698#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37696#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37693#L1024-3 assume !(1 == ~E_4~0); 37692#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37691#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37690#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37689#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37688#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37687#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37665#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37664#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 37659#L1334 assume !(0 == start_simulation_~tmp~3#1); 37365#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37602#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37580#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37578#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 37576#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37564#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37555#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 37547#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 37541#L1315-2 [2023-11-26 10:42:48,988 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:48,988 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2023-11-26 10:42:48,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:48,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687594182] [2023-11-26 10:42:48,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:48,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:49,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:49,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:49,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:49,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687594182] [2023-11-26 10:42:49,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687594182] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:49,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:49,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:42:49,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493761215] [2023-11-26 10:42:49,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:49,054 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:49,055 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:49,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1868159045, now seen corresponding path program 2 times [2023-11-26 10:42:49,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:49,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816932331] [2023-11-26 10:42:49,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:49,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:49,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:49,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:49,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:49,138 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816932331] [2023-11-26 10:42:49,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816932331] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:49,138 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:49,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:42:49,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1882079148] [2023-11-26 10:42:49,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:49,139 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:49,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:49,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:49,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:49,140 INFO L87 Difference]: Start difference. First operand 3460 states and 5038 transitions. cyclomatic complexity: 1582 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:49,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:49,283 INFO L93 Difference]: Finished difference Result 6454 states and 9332 transitions. [2023-11-26 10:42:49,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6454 states and 9332 transitions. [2023-11-26 10:42:49,329 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6293 [2023-11-26 10:42:49,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6454 states to 6454 states and 9332 transitions. [2023-11-26 10:42:49,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6454 [2023-11-26 10:42:49,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6454 [2023-11-26 10:42:49,381 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6454 states and 9332 transitions. [2023-11-26 10:42:49,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:49,391 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6454 states and 9332 transitions. [2023-11-26 10:42:49,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6454 states and 9332 transitions. [2023-11-26 10:42:49,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6454 to 6446. [2023-11-26 10:42:49,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6446 states, 6446 states have (on average 1.4464784362395284) internal successors, (9324), 6445 states have internal predecessors, (9324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:49,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6446 states to 6446 states and 9324 transitions. [2023-11-26 10:42:49,665 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6446 states and 9324 transitions. [2023-11-26 10:42:49,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:49,666 INFO L428 stractBuchiCegarLoop]: Abstraction has 6446 states and 9324 transitions. [2023-11-26 10:42:49,666 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 10:42:49,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6446 states and 9324 transitions. [2023-11-26 10:42:49,698 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6285 [2023-11-26 10:42:49,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:49,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:49,700 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:49,700 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:49,701 INFO L748 eck$LassoCheckResult]: Stem: 46559#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 46560#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 47356#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47357#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46886#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 46887#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46431#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46432#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46523#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47337#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46397#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46398#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46840#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46873#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46527#L866 assume !(0 == ~M_E~0); 46528#L866-2 assume !(0 == ~T1_E~0); 47089#L871-1 assume !(0 == ~T2_E~0); 47090#L876-1 assume !(0 == ~T3_E~0); 47399#L881-1 assume !(0 == ~T4_E~0); 47104#L886-1 assume !(0 == ~T5_E~0); 46828#L891-1 assume !(0 == ~T6_E~0); 46829#L896-1 assume !(0 == ~T7_E~0); 47097#L901-1 assume !(0 == ~T8_E~0); 47122#L906-1 assume !(0 == ~E_M~0); 47123#L911-1 assume !(0 == ~E_1~0); 46883#L916-1 assume !(0 == ~E_2~0); 46884#L921-1 assume !(0 == ~E_3~0); 47233#L926-1 assume !(0 == ~E_4~0); 47351#L931-1 assume !(0 == ~E_5~0); 47406#L936-1 assume !(0 == ~E_6~0); 47415#L941-1 assume !(0 == ~E_7~0); 46888#L946-1 assume !(0 == ~E_8~0); 46889#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47382#L430 assume !(1 == ~m_pc~0); 46728#L430-2 is_master_triggered_~__retres1~0#1 := 0; 46343#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46344#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47016#L1073 assume !(0 != activate_threads_~tmp~1#1); 47017#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47212#L449 assume !(1 == ~t1_pc~0); 46533#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46534#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46370#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46371#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 47137#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46950#L468 assume !(1 == ~t2_pc~0); 46331#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46330#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46738#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46733#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 46345#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46346#L487 assume 1 == ~t3_pc~0; 47397#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46437#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46327#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46328#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 46807#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46808#L506 assume !(1 == ~t4_pc~0); 46944#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46997#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46423#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46424#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 46937#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46745#L525 assume 1 == ~t5_pc~0; 46673#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46385#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47282#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47283#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 46591#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46592#L544 assume !(1 == ~t6_pc~0); 46746#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46747#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46716#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46365#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 46366#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47322#L563 assume 1 == ~t7_pc~0; 47164#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46389#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46390#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46830#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 46535#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46536#L582 assume 1 == ~t8_pc~0; 46455#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46456#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47218#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46795#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 46677#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46678#L964 assume !(1 == ~M_E~0); 47215#L964-2 assume !(1 == ~T1_E~0); 46593#L969-1 assume !(1 == ~T2_E~0); 46594#L974-1 assume !(1 == ~T3_E~0); 47255#L979-1 assume !(1 == ~T4_E~0); 47256#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50660#L989-1 assume !(1 == ~T6_E~0); 51869#L994-1 assume !(1 == ~T7_E~0); 51867#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51865#L1004-1 assume !(1 == ~E_M~0); 51863#L1009-1 assume !(1 == ~E_1~0); 51861#L1014-1 assume !(1 == ~E_2~0); 51859#L1019-1 assume !(1 == ~E_3~0); 51856#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 46556#L1029-1 assume !(1 == ~E_5~0); 46557#L1034-1 assume !(1 == ~E_6~0); 51682#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 51672#L1044-1 assume !(1 == ~E_8~0); 51663#L1049-1 assume { :end_inline_reset_delta_events } true; 51655#L1315-2 [2023-11-26 10:42:49,702 INFO L750 eck$LassoCheckResult]: Loop: 51655#L1315-2 assume !false; 51650#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51648#L841-1 assume !false; 51646#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 51639#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 51633#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 51631#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 51629#L724 assume !(0 != eval_~tmp~0#1); 47229#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46946#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46947#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 52306#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52580#L871-3 assume !(0 == ~T2_E~0); 52579#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52578#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52577#L886-3 assume !(0 == ~T5_E~0); 52576#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52575#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52574#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52573#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 52572#L911-3 assume !(0 == ~E_1~0); 52571#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52570#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52569#L926-3 assume !(0 == ~E_4~0); 52568#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52567#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52566#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 52565#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 52564#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52563#L430-30 assume !(1 == ~m_pc~0); 52561#L430-32 is_master_triggered_~__retres1~0#1 := 0; 52559#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52557#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52556#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 52554#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52553#L449-30 assume !(1 == ~t1_pc~0); 52552#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 52551#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52550#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52549#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52548#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52547#L468-30 assume 1 == ~t2_pc~0; 52545#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52544#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52543#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52542#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 52541#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52540#L487-30 assume 1 == ~t3_pc~0; 52538#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52537#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52536#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52535#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52534#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52533#L506-30 assume !(1 == ~t4_pc~0); 52531#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 52530#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52529#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52528#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52527#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52526#L525-30 assume 1 == ~t5_pc~0; 52524#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 52523#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52522#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52521#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 52520#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52519#L544-30 assume !(1 == ~t6_pc~0); 52517#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 52516#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52515#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52514#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 52513#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52512#L563-30 assume 1 == ~t7_pc~0; 52510#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52509#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52508#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52507#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52506#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52505#L582-30 assume !(1 == ~t8_pc~0); 52503#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 52502#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52501#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52500#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52499#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52498#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46376#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52497#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52496#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52495#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46959#L984-3 assume !(1 == ~T5_E~0); 46960#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46561#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46562#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47135#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46413#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46414#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46933#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46934#L1024-3 assume !(1 == ~E_4~0); 46910#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46911#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52321#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47234#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47235#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 52085#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 52063#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 52054#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 52047#L1334 assume !(0 == start_simulation_~tmp~3#1); 47301#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 52033#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 51999#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 51976#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 51705#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51681#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51671#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 51662#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 51655#L1315-2 [2023-11-26 10:42:49,702 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:49,703 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2023-11-26 10:42:49,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:49,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721859427] [2023-11-26 10:42:49,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:49,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:49,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:49,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:49,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:49,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1721859427] [2023-11-26 10:42:49,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1721859427] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:49,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:49,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:42:49,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450838384] [2023-11-26 10:42:49,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:49,771 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:49,771 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:49,772 INFO L85 PathProgramCache]: Analyzing trace with hash -406865656, now seen corresponding path program 1 times [2023-11-26 10:42:49,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:49,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47440820] [2023-11-26 10:42:49,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:49,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:49,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:49,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:49,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:49,848 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [47440820] [2023-11-26 10:42:49,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [47440820] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:49,848 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:49,848 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:42:49,849 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047473189] [2023-11-26 10:42:49,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:49,849 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:49,849 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:49,850 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:49,850 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:49,851 INFO L87 Difference]: Start difference. First operand 6446 states and 9324 transitions. cyclomatic complexity: 2886 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:50,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:50,023 INFO L93 Difference]: Finished difference Result 12382 states and 17784 transitions. [2023-11-26 10:42:50,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12382 states and 17784 transitions. [2023-11-26 10:42:50,107 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12206 [2023-11-26 10:42:50,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12382 states to 12382 states and 17784 transitions. [2023-11-26 10:42:50,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12382 [2023-11-26 10:42:50,179 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12382 [2023-11-26 10:42:50,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12382 states and 17784 transitions. [2023-11-26 10:42:50,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:50,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12382 states and 17784 transitions. [2023-11-26 10:42:50,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12382 states and 17784 transitions. [2023-11-26 10:42:50,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12382 to 12366. [2023-11-26 10:42:50,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12366 states, 12366 states have (on average 1.4368429564936116) internal successors, (17768), 12365 states have internal predecessors, (17768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:50,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12366 states to 12366 states and 17768 transitions. [2023-11-26 10:42:50,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12366 states and 17768 transitions. [2023-11-26 10:42:50,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:50,720 INFO L428 stractBuchiCegarLoop]: Abstraction has 12366 states and 17768 transitions. [2023-11-26 10:42:50,720 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 10:42:50,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12366 states and 17768 transitions. [2023-11-26 10:42:50,769 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12190 [2023-11-26 10:42:50,769 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:50,769 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:50,771 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:50,771 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:50,772 INFO L748 eck$LassoCheckResult]: Stem: 65399#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 65400#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 66270#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66271#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65735#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 65736#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65267#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65268#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65361#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66248#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65234#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65235#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65687#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65722#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65367#L866 assume !(0 == ~M_E~0); 65368#L866-2 assume !(0 == ~T1_E~0); 65959#L871-1 assume !(0 == ~T2_E~0); 65960#L876-1 assume !(0 == ~T3_E~0); 66327#L881-1 assume !(0 == ~T4_E~0); 65974#L886-1 assume !(0 == ~T5_E~0); 65675#L891-1 assume !(0 == ~T6_E~0); 65676#L896-1 assume !(0 == ~T7_E~0); 65967#L901-1 assume !(0 == ~T8_E~0); 65991#L906-1 assume !(0 == ~E_M~0); 65992#L911-1 assume !(0 == ~E_1~0); 65732#L916-1 assume !(0 == ~E_2~0); 65733#L921-1 assume !(0 == ~E_3~0); 66121#L926-1 assume !(0 == ~E_4~0); 66264#L931-1 assume !(0 == ~E_5~0); 66343#L936-1 assume !(0 == ~E_6~0); 66355#L941-1 assume !(0 == ~E_7~0); 65737#L946-1 assume !(0 == ~E_8~0); 65738#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66301#L430 assume !(1 == ~m_pc~0); 65571#L430-2 is_master_triggered_~__retres1~0#1 := 0; 66213#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66404#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 65873#L1073 assume !(0 != activate_threads_~tmp~1#1); 65874#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66093#L449 assume !(1 == ~t1_pc~0); 65373#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65374#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65207#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 65208#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 66007#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65797#L468 assume !(1 == ~t2_pc~0); 65168#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 65167#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65581#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65576#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 65182#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65183#L487 assume !(1 == ~t3_pc~0); 65302#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 65273#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65164#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65165#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 65654#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65655#L506 assume !(1 == ~t4_pc~0); 65792#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 65851#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65259#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65260#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 65786#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65589#L525 assume 1 == ~t5_pc~0; 65515#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65222#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66177#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66178#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 65431#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65432#L544 assume !(1 == ~t6_pc~0); 65590#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 65591#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65559#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65202#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 65203#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66227#L563 assume 1 == ~t7_pc~0; 66041#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65226#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65227#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65677#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 65375#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65376#L582 assume 1 == ~t8_pc~0; 65291#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65292#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66101#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65641#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 65519#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65520#L964 assume !(1 == ~M_E~0); 66097#L964-2 assume !(1 == ~T1_E~0); 68987#L969-1 assume !(1 == ~T2_E~0); 68986#L974-1 assume !(1 == ~T3_E~0); 68985#L979-1 assume !(1 == ~T4_E~0); 68983#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 68934#L989-1 assume !(1 == ~T6_E~0); 68932#L994-1 assume !(1 == ~T7_E~0); 68930#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66102#L1004-1 assume !(1 == ~E_M~0); 66103#L1009-1 assume !(1 == ~E_1~0); 68879#L1014-1 assume !(1 == ~E_2~0); 68877#L1019-1 assume !(1 == ~E_3~0); 68829#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 68825#L1029-1 assume !(1 == ~E_5~0); 68823#L1034-1 assume !(1 == ~E_6~0); 68782#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 68748#L1044-1 assume !(1 == ~E_8~0); 68719#L1049-1 assume { :end_inline_reset_delta_events } true; 68687#L1315-2 [2023-11-26 10:42:50,772 INFO L750 eck$LassoCheckResult]: Loop: 68687#L1315-2 assume !false; 68663#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68661#L841-1 assume !false; 68629#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 65426#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 65427#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 65625#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65177#L724 assume !(0 != eval_~tmp~0#1); 65179#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72975#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 72973#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 72971#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 72969#L871-3 assume !(0 == ~T2_E~0); 72967#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72964#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72962#L886-3 assume !(0 == ~T5_E~0); 72960#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 72958#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 72956#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 72954#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 72951#L911-3 assume !(0 == ~E_1~0); 72949#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 72947#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 72945#L926-3 assume !(0 == ~E_4~0); 72943#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 72941#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 72938#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 72937#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 72936#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72935#L430-30 assume 1 == ~m_pc~0; 72931#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 72930#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72924#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 72922#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72921#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72919#L449-30 assume !(1 == ~t1_pc~0); 72918#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 72917#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72916#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 72915#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72914#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72913#L468-30 assume !(1 == ~t2_pc~0); 72912#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 72910#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72908#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 72905#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 72902#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72899#L487-30 assume !(1 == ~t3_pc~0); 72896#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 72894#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72892#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 72890#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 72888#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 72886#L506-30 assume 1 == ~t4_pc~0; 72883#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 72878#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72874#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72869#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 72865#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 72862#L525-30 assume !(1 == ~t5_pc~0); 72859#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 72855#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 72852#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72849#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 72846#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72843#L544-30 assume !(1 == ~t6_pc~0); 72839#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 72835#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72832#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 72828#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 72826#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72825#L563-30 assume 1 == ~t7_pc~0; 72823#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72821#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72820#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 72802#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 72801#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 72800#L582-30 assume 1 == ~t8_pc~0; 72799#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 72797#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 72796#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 72795#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 72794#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72793#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 70580#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72777#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72776#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 72775#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 72774#L984-3 assume !(1 == ~T5_E~0); 70571#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 72772#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72332#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 69377#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69376#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69374#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69373#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69286#L1024-3 assume !(1 == ~E_4~0); 69284#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69282#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69280#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 69277#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 69276#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 69199#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 69107#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 69039#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 68976#L1334 assume !(0 == start_simulation_~tmp~3#1); 66201#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 68872#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 68864#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 68824#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 68783#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68781#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68747#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 68718#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 68687#L1315-2 [2023-11-26 10:42:50,773 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:50,773 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2023-11-26 10:42:50,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:50,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261810522] [2023-11-26 10:42:50,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:50,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:50,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:50,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:50,851 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:50,852 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261810522] [2023-11-26 10:42:50,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1261810522] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:50,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:50,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:42:50,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [695210722] [2023-11-26 10:42:50,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:50,856 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:50,857 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:50,857 INFO L85 PathProgramCache]: Analyzing trace with hash -1419246714, now seen corresponding path program 1 times [2023-11-26 10:42:50,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:50,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962663477] [2023-11-26 10:42:50,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:50,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:50,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:50,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:50,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:50,918 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962663477] [2023-11-26 10:42:50,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962663477] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:50,918 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:50,918 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:50,919 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928948278] [2023-11-26 10:42:50,919 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:50,920 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:50,920 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:50,921 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:50,921 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:50,922 INFO L87 Difference]: Start difference. First operand 12366 states and 17768 transitions. cyclomatic complexity: 5418 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:51,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:51,243 INFO L93 Difference]: Finished difference Result 23363 states and 33403 transitions. [2023-11-26 10:42:51,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23363 states and 33403 transitions. [2023-11-26 10:42:51,380 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23132 [2023-11-26 10:42:51,482 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23363 states to 23363 states and 33403 transitions. [2023-11-26 10:42:51,482 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23363 [2023-11-26 10:42:51,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23363 [2023-11-26 10:42:51,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23363 states and 33403 transitions. [2023-11-26 10:42:51,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:51,545 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23363 states and 33403 transitions. [2023-11-26 10:42:51,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23363 states and 33403 transitions. [2023-11-26 10:42:52,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23363 to 23331. [2023-11-26 10:42:52,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23331 states, 23331 states have (on average 1.4303287471604302) internal successors, (33371), 23330 states have internal predecessors, (33371), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:52,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23331 states to 23331 states and 33371 transitions. [2023-11-26 10:42:52,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23331 states and 33371 transitions. [2023-11-26 10:42:52,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:52,268 INFO L428 stractBuchiCegarLoop]: Abstraction has 23331 states and 33371 transitions. [2023-11-26 10:42:52,269 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 10:42:52,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23331 states and 33371 transitions. [2023-11-26 10:42:52,360 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23100 [2023-11-26 10:42:52,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:52,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:52,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:52,363 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:52,363 INFO L748 eck$LassoCheckResult]: Stem: 101132#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 101133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 101946#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101947#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 101459#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 101460#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 101004#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 101005#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101094#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 101928#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100971#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 100972#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 101416#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 101446#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 101100#L866 assume !(0 == ~M_E~0); 101101#L866-2 assume !(0 == ~T1_E~0); 101668#L871-1 assume !(0 == ~T2_E~0); 101669#L876-1 assume !(0 == ~T3_E~0); 102002#L881-1 assume !(0 == ~T4_E~0); 101686#L886-1 assume !(0 == ~T5_E~0); 101403#L891-1 assume !(0 == ~T6_E~0); 101404#L896-1 assume !(0 == ~T7_E~0); 101677#L901-1 assume !(0 == ~T8_E~0); 101701#L906-1 assume !(0 == ~E_M~0); 101702#L911-1 assume !(0 == ~E_1~0); 101456#L916-1 assume !(0 == ~E_2~0); 101457#L921-1 assume !(0 == ~E_3~0); 101816#L926-1 assume !(0 == ~E_4~0); 101943#L931-1 assume !(0 == ~E_5~0); 102010#L936-1 assume !(0 == ~E_6~0); 102017#L941-1 assume !(0 == ~E_7~0); 101462#L946-1 assume !(0 == ~E_8~0); 101463#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101980#L430 assume !(1 == ~m_pc~0); 101303#L430-2 is_master_triggered_~__retres1~0#1 := 0; 101905#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102058#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 101594#L1073 assume !(0 != activate_threads_~tmp~1#1); 101595#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101794#L449 assume !(1 == ~t1_pc~0); 101106#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 101107#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100946#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100947#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 101716#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101524#L468 assume !(1 == ~t2_pc~0); 100904#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 100903#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101313#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 101308#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 100918#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100919#L487 assume !(1 == ~t3_pc~0); 101037#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101008#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100900#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 100901#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 101383#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101384#L506 assume !(1 == ~t4_pc~0); 101519#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 101578#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100994#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100995#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 101509#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101320#L525 assume !(1 == ~t5_pc~0); 100957#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 100958#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101871#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101872#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 101167#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101168#L544 assume !(1 == ~t6_pc~0); 101321#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 101322#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101293#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100938#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 100939#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101917#L563 assume 1 == ~t7_pc~0; 101745#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 100962#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100963#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 101405#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 101110#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 101111#L582 assume 1 == ~t8_pc~0; 101026#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 101027#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101802#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 101370#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 101255#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101256#L964 assume !(1 == ~M_E~0); 101799#L964-2 assume !(1 == ~T1_E~0); 101169#L969-1 assume !(1 == ~T2_E~0); 101170#L974-1 assume !(1 == ~T3_E~0); 101838#L979-1 assume !(1 == ~T4_E~0); 101839#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 102042#L989-1 assume !(1 == ~T6_E~0); 108562#L994-1 assume !(1 == ~T7_E~0); 108560#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 108558#L1004-1 assume !(1 == ~E_M~0); 108556#L1009-1 assume !(1 == ~E_1~0); 108554#L1014-1 assume !(1 == ~E_2~0); 108552#L1019-1 assume !(1 == ~E_3~0); 107686#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 107684#L1029-1 assume !(1 == ~E_5~0); 107682#L1034-1 assume !(1 == ~E_6~0); 107680#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 107678#L1044-1 assume !(1 == ~E_8~0); 107677#L1049-1 assume { :end_inline_reset_delta_events } true; 107675#L1315-2 [2023-11-26 10:42:52,364 INFO L750 eck$LassoCheckResult]: Loop: 107675#L1315-2 assume !false; 107217#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 107216#L841-1 assume !false; 107215#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 104376#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 104370#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 104368#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 104365#L724 assume !(0 != eval_~tmp~0#1); 104366#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 108609#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 108608#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 108607#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 108606#L871-3 assume !(0 == ~T2_E~0); 108605#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 108604#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 108603#L886-3 assume !(0 == ~T5_E~0); 108602#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 108601#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 108600#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 108599#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 108598#L911-3 assume !(0 == ~E_1~0); 108597#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 108596#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 108595#L926-3 assume !(0 == ~E_4~0); 108594#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 108593#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 108592#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 108591#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 108590#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108589#L430-30 assume !(1 == ~m_pc~0); 108587#L430-32 is_master_triggered_~__retres1~0#1 := 0; 108585#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108583#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 108582#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 108580#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108578#L449-30 assume !(1 == ~t1_pc~0); 108576#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 108574#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108572#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 108571#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 108570#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108569#L468-30 assume 1 == ~t2_pc~0; 108567#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 108566#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108565#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 108564#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 108563#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108561#L487-30 assume !(1 == ~t3_pc~0); 108559#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 108557#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108555#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 108553#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 108551#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108550#L506-30 assume 1 == ~t4_pc~0; 108549#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 108547#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108546#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 108544#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 108542#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108541#L525-30 assume !(1 == ~t5_pc~0); 108540#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 108539#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108538#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 108537#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 108536#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 108535#L544-30 assume !(1 == ~t6_pc~0); 108533#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 108532#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 108531#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 108530#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 108529#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 108528#L563-30 assume !(1 == ~t7_pc~0); 108527#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 108524#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 108523#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 108522#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 108521#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 108520#L582-30 assume !(1 == ~t8_pc~0); 108515#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 108513#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 108511#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 108509#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 108506#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108504#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 107921#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 108501#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 108499#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 108497#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 108115#L984-3 assume !(1 == ~T5_E~0); 108113#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 108111#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 108109#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 108107#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 108105#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 108103#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 108101#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 107890#L1024-3 assume !(1 == ~E_4~0); 107888#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107886#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107884#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107882#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 107880#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 107878#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107868#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 107866#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 107863#L1334 assume !(0 == start_simulation_~tmp~3#1); 107862#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 107697#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107689#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 107685#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 107683#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 107681#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 107679#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 107676#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 107675#L1315-2 [2023-11-26 10:42:52,365 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:52,365 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2023-11-26 10:42:52,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:52,365 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403954870] [2023-11-26 10:42:52,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:52,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:52,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:52,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:52,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:52,464 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403954870] [2023-11-26 10:42:52,464 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403954870] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:52,465 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:52,465 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:52,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1679138937] [2023-11-26 10:42:52,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:52,466 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:52,466 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:52,466 INFO L85 PathProgramCache]: Analyzing trace with hash 1492498122, now seen corresponding path program 1 times [2023-11-26 10:42:52,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:52,467 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076107506] [2023-11-26 10:42:52,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:52,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:52,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:52,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:52,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:52,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076107506] [2023-11-26 10:42:52,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2076107506] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:52,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:52,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:52,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988637286] [2023-11-26 10:42:52,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:52,538 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:52,539 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:52,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:42:52,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:42:52,540 INFO L87 Difference]: Start difference. First operand 23331 states and 33371 transitions. cyclomatic complexity: 10072 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:53,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:53,197 INFO L93 Difference]: Finished difference Result 54594 states and 77544 transitions. [2023-11-26 10:42:53,197 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54594 states and 77544 transitions. [2023-11-26 10:42:53,676 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 54140 [2023-11-26 10:42:54,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54594 states to 54594 states and 77544 transitions. [2023-11-26 10:42:54,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54594 [2023-11-26 10:42:54,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54594 [2023-11-26 10:42:54,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54594 states and 77544 transitions. [2023-11-26 10:42:54,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:54,176 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54594 states and 77544 transitions. [2023-11-26 10:42:54,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54594 states and 77544 transitions. [2023-11-26 10:42:54,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54594 to 44046. [2023-11-26 10:42:54,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44046 states, 44046 states have (on average 1.424783181219634) internal successors, (62756), 44045 states have internal predecessors, (62756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:55,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44046 states to 44046 states and 62756 transitions. [2023-11-26 10:42:55,097 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44046 states and 62756 transitions. [2023-11-26 10:42:55,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:42:55,099 INFO L428 stractBuchiCegarLoop]: Abstraction has 44046 states and 62756 transitions. [2023-11-26 10:42:55,099 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 10:42:55,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44046 states and 62756 transitions. [2023-11-26 10:42:55,427 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43736 [2023-11-26 10:42:55,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:55,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:55,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:55,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:55,430 INFO L748 eck$LassoCheckResult]: Stem: 179066#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 179067#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 179858#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 179859#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 179387#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 179388#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 178937#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 178938#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 179028#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 179842#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 178905#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 178906#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 179344#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 179374#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 179035#L866 assume !(0 == ~M_E~0); 179036#L866-2 assume !(0 == ~T1_E~0); 179581#L871-1 assume !(0 == ~T2_E~0); 179582#L876-1 assume !(0 == ~T3_E~0); 179900#L881-1 assume !(0 == ~T4_E~0); 179597#L886-1 assume !(0 == ~T5_E~0); 179331#L891-1 assume !(0 == ~T6_E~0); 179332#L896-1 assume !(0 == ~T7_E~0); 179589#L901-1 assume !(0 == ~T8_E~0); 179617#L906-1 assume !(0 == ~E_M~0); 179618#L911-1 assume !(0 == ~E_1~0); 179384#L916-1 assume !(0 == ~E_2~0); 179385#L921-1 assume !(0 == ~E_3~0); 179726#L926-1 assume !(0 == ~E_4~0); 179855#L931-1 assume !(0 == ~E_5~0); 179906#L936-1 assume !(0 == ~E_6~0); 179919#L941-1 assume !(0 == ~E_7~0); 179390#L946-1 assume !(0 == ~E_8~0); 179391#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 179885#L430 assume !(1 == ~m_pc~0); 179234#L430-2 is_master_triggered_~__retres1~0#1 := 0; 179821#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 179948#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 179515#L1073 assume !(0 != activate_threads_~tmp~1#1); 179516#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 179705#L449 assume !(1 == ~t1_pc~0); 179040#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 179041#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 178884#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 178885#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 179631#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 179454#L468 assume !(1 == ~t2_pc~0); 178839#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 178838#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 179241#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 179237#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 178855#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 178856#L487 assume !(1 == ~t3_pc~0); 178970#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 178941#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 178835#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 178836#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 179311#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 179312#L506 assume !(1 == ~t4_pc~0); 179445#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 179501#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 178927#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 178928#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 179440#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 179247#L525 assume !(1 == ~t5_pc~0); 178891#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 178892#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 179781#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 179782#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 179099#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 179100#L544 assume !(1 == ~t6_pc~0); 179248#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 179249#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 179221#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 178873#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 178874#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 179833#L563 assume !(1 == ~t7_pc~0); 179643#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 178896#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 178897#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 179338#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 179044#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 179045#L582 assume 1 == ~t8_pc~0; 178959#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 178960#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 179712#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 179300#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 179184#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 179185#L964 assume !(1 == ~M_E~0); 179709#L964-2 assume !(1 == ~T1_E~0); 179897#L969-1 assume !(1 == ~T2_E~0); 179863#L974-1 assume !(1 == ~T3_E~0); 179864#L979-1 assume !(1 == ~T4_E~0); 198843#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 179254#L989-1 assume !(1 == ~T6_E~0); 179255#L994-1 assume !(1 == ~T7_E~0); 179592#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 202625#L1004-1 assume !(1 == ~E_M~0); 202624#L1009-1 assume !(1 == ~E_1~0); 179124#L1014-1 assume !(1 == ~E_2~0); 179125#L1019-1 assume !(1 == ~E_3~0); 179697#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 179063#L1029-1 assume !(1 == ~E_5~0); 179064#L1034-1 assume !(1 == ~E_6~0); 179150#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 179876#L1044-1 assume !(1 == ~E_8~0); 179877#L1049-1 assume { :end_inline_reset_delta_events } true; 216508#L1315-2 [2023-11-26 10:42:55,431 INFO L750 eck$LassoCheckResult]: Loop: 216508#L1315-2 assume !false; 216341#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 216338#L841-1 assume !false; 216336#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 216180#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 216172#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 216171#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 216169#L724 assume !(0 != eval_~tmp~0#1); 216170#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 220405#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 220403#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 220401#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 220399#L871-3 assume !(0 == ~T2_E~0); 220397#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 220394#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 220392#L886-3 assume !(0 == ~T5_E~0); 220390#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 220388#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 220386#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 220384#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 220382#L911-3 assume !(0 == ~E_1~0); 220380#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 220378#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 220376#L926-3 assume !(0 == ~E_4~0); 220374#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 220372#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 220369#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 220367#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 220365#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220363#L430-30 assume !(1 == ~m_pc~0); 220359#L430-32 is_master_triggered_~__retres1~0#1 := 0; 220357#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 220354#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 220352#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 220349#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 219899#L449-30 assume !(1 == ~t1_pc~0); 219441#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 219299#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 219260#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 219250#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 219248#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 219246#L468-30 assume !(1 == ~t2_pc~0); 219243#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 216690#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216687#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 216685#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 216683#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216681#L487-30 assume !(1 == ~t3_pc~0); 216679#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 216677#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216675#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 216673#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 216671#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216668#L506-30 assume 1 == ~t4_pc~0; 216666#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 216663#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 216661#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 216659#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 216657#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216655#L525-30 assume !(1 == ~t5_pc~0); 216653#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 216651#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216649#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 216647#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 216645#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 216644#L544-30 assume 1 == ~t6_pc~0; 216641#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 216638#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 216636#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 216634#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 216632#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 216630#L563-30 assume !(1 == ~t7_pc~0); 189125#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 216627#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 216625#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 216623#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 216621#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 216619#L582-30 assume !(1 == ~t8_pc~0); 216615#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 216613#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 216611#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 216609#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 216607#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216605#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 199022#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 216601#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 216599#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 216597#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 216578#L984-3 assume !(1 == ~T5_E~0); 216576#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 216574#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 216572#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 216570#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 216568#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 216566#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 216564#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 216562#L1024-3 assume !(1 == ~E_4~0); 203652#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 216559#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 216557#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 216555#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 216553#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 216551#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 216541#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 216539#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 216536#L1334 assume !(0 == start_simulation_~tmp~3#1); 216535#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 216532#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 216522#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 216520#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 216518#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 216517#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 216514#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 216510#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 216508#L1315-2 [2023-11-26 10:42:55,431 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:55,432 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2023-11-26 10:42:55,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:55,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612174155] [2023-11-26 10:42:55,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:55,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:55,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:55,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:55,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:55,492 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612174155] [2023-11-26 10:42:55,492 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [612174155] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:55,492 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:55,492 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:42:55,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170017766] [2023-11-26 10:42:55,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:55,493 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:55,493 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:55,494 INFO L85 PathProgramCache]: Analyzing trace with hash -2138684470, now seen corresponding path program 1 times [2023-11-26 10:42:55,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:55,494 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001776363] [2023-11-26 10:42:55,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:55,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:55,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:55,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:55,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:55,540 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001776363] [2023-11-26 10:42:55,540 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001776363] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:55,541 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:55,541 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:55,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953830608] [2023-11-26 10:42:55,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:55,542 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:55,542 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:55,542 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:42:55,542 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:42:55,543 INFO L87 Difference]: Start difference. First operand 44046 states and 62756 transitions. cyclomatic complexity: 18742 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:56,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:42:56,181 INFO L93 Difference]: Finished difference Result 83205 states and 118105 transitions. [2023-11-26 10:42:56,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83205 states and 118105 transitions. [2023-11-26 10:42:56,770 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 82608 [2023-11-26 10:42:57,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83205 states to 83205 states and 118105 transitions. [2023-11-26 10:42:57,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83205 [2023-11-26 10:42:57,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83205 [2023-11-26 10:42:57,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83205 states and 118105 transitions. [2023-11-26 10:42:57,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:42:57,476 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83205 states and 118105 transitions. [2023-11-26 10:42:57,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83205 states and 118105 transitions. [2023-11-26 10:42:58,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83205 to 83077. [2023-11-26 10:42:58,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83077 states, 83077 states have (on average 1.4200922036183299) internal successors, (117977), 83076 states have internal predecessors, (117977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:42:59,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83077 states to 83077 states and 117977 transitions. [2023-11-26 10:42:59,237 INFO L240 hiAutomatonCegarLoop]: Abstraction has 83077 states and 117977 transitions. [2023-11-26 10:42:59,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:42:59,238 INFO L428 stractBuchiCegarLoop]: Abstraction has 83077 states and 117977 transitions. [2023-11-26 10:42:59,238 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 10:42:59,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83077 states and 117977 transitions. [2023-11-26 10:42:59,545 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 82480 [2023-11-26 10:42:59,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:42:59,545 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:42:59,548 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:59,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:42:59,549 INFO L748 eck$LassoCheckResult]: Stem: 306323#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 306324#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 307170#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 307171#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 306643#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 306644#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 306197#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 306198#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 306287#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 307147#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 306164#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 306165#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 306600#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 306630#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 306292#L866 assume !(0 == ~M_E~0); 306293#L866-2 assume !(0 == ~T1_E~0); 306850#L871-1 assume !(0 == ~T2_E~0); 306851#L876-1 assume !(0 == ~T3_E~0); 307226#L881-1 assume !(0 == ~T4_E~0); 306867#L886-1 assume !(0 == ~T5_E~0); 306587#L891-1 assume !(0 == ~T6_E~0); 306588#L896-1 assume !(0 == ~T7_E~0); 306858#L901-1 assume !(0 == ~T8_E~0); 306887#L906-1 assume !(0 == ~E_M~0); 306888#L911-1 assume !(0 == ~E_1~0); 306640#L916-1 assume !(0 == ~E_2~0); 306641#L921-1 assume !(0 == ~E_3~0); 307010#L926-1 assume !(0 == ~E_4~0); 307166#L931-1 assume !(0 == ~E_5~0); 307240#L936-1 assume !(0 == ~E_6~0); 307257#L941-1 assume !(0 == ~E_7~0); 306646#L946-1 assume !(0 == ~E_8~0); 306647#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 307200#L430 assume !(1 == ~m_pc~0); 306486#L430-2 is_master_triggered_~__retres1~0#1 := 0; 307123#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 307306#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 306783#L1073 assume !(0 != activate_threads_~tmp~1#1); 306784#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 306980#L449 assume !(1 == ~t1_pc~0); 306297#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 306298#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 306141#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 306142#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 306901#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 306711#L468 assume !(1 == ~t2_pc~0); 306097#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 306096#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 306493#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 306489#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 306113#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 306114#L487 assume !(1 == ~t3_pc~0); 306227#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 306201#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 306093#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 306094#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 306566#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 306567#L506 assume !(1 == ~t4_pc~0); 306703#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 306763#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 306187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 306188#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 306697#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 306500#L525 assume !(1 == ~t5_pc~0); 306149#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 306150#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 307072#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 307073#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 306355#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 306356#L544 assume !(1 == ~t6_pc~0); 306501#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 306502#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 306471#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 306131#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 306132#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 307136#L563 assume !(1 == ~t7_pc~0); 306914#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 306155#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 306156#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 306594#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 306301#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 306302#L582 assume !(1 == ~t8_pc~0); 306917#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 307221#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 306991#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 306555#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 306434#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306435#L964 assume !(1 == ~M_E~0); 306987#L964-2 assume !(1 == ~T1_E~0); 307219#L969-1 assume !(1 == ~T2_E~0); 307175#L974-1 assume !(1 == ~T3_E~0); 307176#L979-1 assume !(1 == ~T4_E~0); 311302#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 311300#L989-1 assume !(1 == ~T6_E~0); 311161#L994-1 assume !(1 == ~T7_E~0); 311159#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 311157#L1004-1 assume !(1 == ~E_M~0); 311156#L1009-1 assume !(1 == ~E_1~0); 311155#L1014-1 assume !(1 == ~E_2~0); 311153#L1019-1 assume !(1 == ~E_3~0); 311149#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 311148#L1029-1 assume !(1 == ~E_5~0); 311147#L1034-1 assume !(1 == ~E_6~0); 311146#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 311145#L1044-1 assume !(1 == ~E_8~0); 311144#L1049-1 assume { :end_inline_reset_delta_events } true; 311142#L1315-2 [2023-11-26 10:42:59,550 INFO L750 eck$LassoCheckResult]: Loop: 311142#L1315-2 assume !false; 311135#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 311133#L841-1 assume !false; 311131#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 311012#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 311003#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 310997#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 310987#L724 assume !(0 != eval_~tmp~0#1); 310988#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 312854#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 312852#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 312850#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 312848#L871-3 assume !(0 == ~T2_E~0); 312846#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 312844#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 312842#L886-3 assume !(0 == ~T5_E~0); 312840#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 312838#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 312835#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 312833#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 312831#L911-3 assume !(0 == ~E_1~0); 312829#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 312827#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 312825#L926-3 assume !(0 == ~E_4~0); 312823#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 312821#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 312820#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 312805#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 312798#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 312792#L430-30 assume 1 == ~m_pc~0; 312784#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 312775#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 312612#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 312606#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 312604#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 312602#L449-30 assume !(1 == ~t1_pc~0); 312598#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 312596#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 312594#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 312592#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 312590#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 312588#L468-30 assume 1 == ~t2_pc~0; 312585#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 312583#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 312581#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 312579#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 312577#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 312575#L487-30 assume !(1 == ~t3_pc~0); 312574#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 312573#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312569#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 312567#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 312565#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 312564#L506-30 assume !(1 == ~t4_pc~0); 312562#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 312561#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 312559#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 312557#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 312555#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 312553#L525-30 assume !(1 == ~t5_pc~0); 312551#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 312549#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 312548#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 312531#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 312523#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 312479#L544-30 assume !(1 == ~t6_pc~0); 312468#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 312461#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 312071#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 312068#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 312066#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 312064#L563-30 assume !(1 == ~t7_pc~0); 310761#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 312061#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 312059#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 312057#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 312055#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 312053#L582-30 assume !(1 == ~t8_pc~0); 312051#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 312049#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 312047#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 312009#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 311997#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311988#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 311537#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 311531#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 311515#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 311500#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 311488#L984-3 assume !(1 == ~T5_E~0); 311479#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 311471#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 311463#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 311455#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 311447#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 311440#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 311415#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 311405#L1024-3 assume !(1 == ~E_4~0); 311397#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 311391#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 311384#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 311378#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 311312#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 311311#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 311301#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 311299#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 311216#L1334 assume !(0 == start_simulation_~tmp~3#1); 311214#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 311208#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 311200#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 311198#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 311196#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 311194#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 311192#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 311143#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 311142#L1315-2 [2023-11-26 10:42:59,551 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:59,551 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2023-11-26 10:42:59,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:59,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872599118] [2023-11-26 10:42:59,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:59,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:59,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:59,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:59,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:59,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872599118] [2023-11-26 10:42:59,652 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872599118] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:59,652 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:59,652 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:42:59,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7039057] [2023-11-26 10:42:59,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:59,653 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:42:59,653 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:42:59,654 INFO L85 PathProgramCache]: Analyzing trace with hash 501087688, now seen corresponding path program 1 times [2023-11-26 10:42:59,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:42:59,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398656944] [2023-11-26 10:42:59,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:42:59,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:42:59,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:42:59,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:42:59,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:42:59,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398656944] [2023-11-26 10:42:59,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [398656944] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:42:59,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:42:59,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:42:59,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962709732] [2023-11-26 10:42:59,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:42:59,738 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:42:59,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:42:59,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:42:59,738 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:42:59,739 INFO L87 Difference]: Start difference. First operand 83077 states and 117977 transitions. cyclomatic complexity: 34964 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:00,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:00,505 INFO L93 Difference]: Finished difference Result 63510 states and 89995 transitions. [2023-11-26 10:43:00,505 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63510 states and 89995 transitions. [2023-11-26 10:43:00,792 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 63056 [2023-11-26 10:43:00,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63510 states to 63510 states and 89995 transitions. [2023-11-26 10:43:00,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63510 [2023-11-26 10:43:01,020 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63510 [2023-11-26 10:43:01,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63510 states and 89995 transitions. [2023-11-26 10:43:01,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:01,075 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63510 states and 89995 transitions. [2023-11-26 10:43:01,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63510 states and 89995 transitions. [2023-11-26 10:43:01,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63510 to 43969. [2023-11-26 10:43:01,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43969 states, 43969 states have (on average 1.4174077190748027) internal successors, (62322), 43968 states have internal predecessors, (62322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:02,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43969 states to 43969 states and 62322 transitions. [2023-11-26 10:43:02,045 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43969 states and 62322 transitions. [2023-11-26 10:43:02,046 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:43:02,047 INFO L428 stractBuchiCegarLoop]: Abstraction has 43969 states and 62322 transitions. [2023-11-26 10:43:02,047 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 10:43:02,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43969 states and 62322 transitions. [2023-11-26 10:43:02,176 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43632 [2023-11-26 10:43:02,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:02,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:02,179 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:02,179 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:02,180 INFO L748 eck$LassoCheckResult]: Stem: 452922#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 452923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 453732#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 453733#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 453246#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 453247#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 452794#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 452795#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 452884#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 453714#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 452761#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 452762#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 453200#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 453233#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 452891#L866 assume !(0 == ~M_E~0); 452892#L866-2 assume !(0 == ~T1_E~0); 453453#L871-1 assume !(0 == ~T2_E~0); 453454#L876-1 assume !(0 == ~T3_E~0); 453787#L881-1 assume !(0 == ~T4_E~0); 453468#L886-1 assume !(0 == ~T5_E~0); 453187#L891-1 assume !(0 == ~T6_E~0); 453188#L896-1 assume !(0 == ~T7_E~0); 453461#L901-1 assume !(0 == ~T8_E~0); 453486#L906-1 assume !(0 == ~E_M~0); 453487#L911-1 assume !(0 == ~E_1~0); 453243#L916-1 assume !(0 == ~E_2~0); 453244#L921-1 assume !(0 == ~E_3~0); 453605#L926-1 assume !(0 == ~E_4~0); 453729#L931-1 assume !(0 == ~E_5~0); 453799#L936-1 assume !(0 == ~E_6~0); 453807#L941-1 assume !(0 == ~E_7~0); 453249#L946-1 assume !(0 == ~E_8~0); 453250#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 453762#L430 assume !(1 == ~m_pc~0); 453090#L430-2 is_master_triggered_~__retres1~0#1 := 0; 452710#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 452711#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 453379#L1073 assume !(0 != activate_threads_~tmp~1#1); 453380#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 453581#L449 assume !(1 == ~t1_pc~0); 452896#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 452897#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 452741#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 452742#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 453500#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 453314#L468 assume !(1 == ~t2_pc~0); 452696#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 452695#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453097#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 453093#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 452712#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 452713#L487 assume !(1 == ~t3_pc~0); 452824#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 452798#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 452692#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 452693#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 453167#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 453168#L506 assume !(1 == ~t4_pc~0); 453304#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 453360#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 452784#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 452785#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 453299#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 453103#L525 assume !(1 == ~t5_pc~0); 452748#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 452749#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 453657#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 453658#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 452956#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 452957#L544 assume !(1 == ~t6_pc~0); 453104#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 453105#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 453074#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 452730#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 452731#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 453703#L563 assume !(1 == ~t7_pc~0); 453513#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 452753#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 452754#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 453194#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 452900#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 452901#L582 assume !(1 == ~t8_pc~0); 453517#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 453781#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 453589#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 453156#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 453036#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 453037#L964 assume !(1 == ~M_E~0); 453586#L964-2 assume !(1 == ~T1_E~0); 452958#L969-1 assume !(1 == ~T2_E~0); 452959#L974-1 assume !(1 == ~T3_E~0); 453627#L979-1 assume !(1 == ~T4_E~0); 453628#L984-1 assume !(1 == ~T5_E~0); 453110#L989-1 assume !(1 == ~T6_E~0); 453111#L994-1 assume !(1 == ~T7_E~0); 452992#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 452993#L1004-1 assume !(1 == ~E_M~0); 452733#L1009-1 assume !(1 == ~E_1~0); 452734#L1014-1 assume !(1 == ~E_2~0); 452980#L1019-1 assume !(1 == ~E_3~0); 453573#L1024-1 assume !(1 == ~E_4~0); 452919#L1029-1 assume !(1 == ~E_5~0); 452920#L1034-1 assume !(1 == ~E_6~0); 453004#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 453749#L1044-1 assume !(1 == ~E_8~0); 453211#L1049-1 assume { :end_inline_reset_delta_events } true; 453212#L1315-2 [2023-11-26 10:43:02,180 INFO L750 eck$LassoCheckResult]: Loop: 453212#L1315-2 assume !false; 467196#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 467194#L841-1 assume !false; 467192#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 467180#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 467174#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 467173#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 467169#L724 assume !(0 != eval_~tmp~0#1); 467170#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 470105#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 470104#L866-3 assume !(0 == ~M_E~0); 470103#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 470102#L871-3 assume !(0 == ~T2_E~0); 470100#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 470098#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 470094#L886-3 assume !(0 == ~T5_E~0); 470092#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 470090#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 470088#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 470085#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 470083#L911-3 assume !(0 == ~E_1~0); 470081#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 470079#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 470077#L926-3 assume !(0 == ~E_4~0); 470075#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 470073#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 470071#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 470069#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 470066#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 470064#L430-30 assume 1 == ~m_pc~0; 470062#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 470063#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 470107#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 470053#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 470051#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 470049#L449-30 assume !(1 == ~t1_pc~0); 470047#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 470045#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 470043#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 470041#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 470038#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 470036#L468-30 assume !(1 == ~t2_pc~0); 470034#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 470031#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 470029#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 470027#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 470025#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 470023#L487-30 assume !(1 == ~t3_pc~0); 470021#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 470019#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 470017#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 470015#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 470012#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 470010#L506-30 assume !(1 == ~t4_pc~0); 470007#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 470005#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 470003#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 470001#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 469998#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 469996#L525-30 assume !(1 == ~t5_pc~0); 469994#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 469992#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 469990#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 469988#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 469986#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 469984#L544-30 assume 1 == ~t6_pc~0; 469982#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 469979#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 469977#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 469976#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 469975#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 469973#L563-30 assume !(1 == ~t7_pc~0); 463591#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 469970#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 469968#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 469966#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 469964#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 469962#L582-30 assume !(1 == ~t8_pc~0); 469960#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 469958#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 469956#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 469954#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 469952#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 469950#L964-3 assume !(1 == ~M_E~0); 469948#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 469946#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 469944#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 469942#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 469940#L984-3 assume !(1 == ~T5_E~0); 469938#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 469866#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 469860#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 469853#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 469846#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 469840#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 469834#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 469827#L1024-3 assume !(1 == ~E_4~0); 469820#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 469811#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 469804#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 469798#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 469793#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 466740#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 466730#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 466132#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 459015#L1334 assume !(0 == start_simulation_~tmp~3#1); 459016#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 467349#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 467341#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 467339#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 467337#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 467336#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 467335#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 467334#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 453212#L1315-2 [2023-11-26 10:43:02,181 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:02,181 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2023-11-26 10:43:02,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:02,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837661360] [2023-11-26 10:43:02,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:02,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:02,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:02,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:02,265 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:02,265 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837661360] [2023-11-26 10:43:02,265 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837661360] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:02,266 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:02,266 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:43:02,266 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785779984] [2023-11-26 10:43:02,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:02,266 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:43:02,267 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:02,267 INFO L85 PathProgramCache]: Analyzing trace with hash -1039201016, now seen corresponding path program 1 times [2023-11-26 10:43:02,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:02,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198361632] [2023-11-26 10:43:02,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:02,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:02,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:02,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:02,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:02,341 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [198361632] [2023-11-26 10:43:02,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [198361632] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:02,342 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:02,342 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:43:02,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [165608252] [2023-11-26 10:43:02,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:02,343 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:43:02,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:02,344 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:43:02,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:43:02,344 INFO L87 Difference]: Start difference. First operand 43969 states and 62322 transitions. cyclomatic complexity: 18385 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:02,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:02,732 INFO L93 Difference]: Finished difference Result 69931 states and 99092 transitions. [2023-11-26 10:43:02,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69931 states and 99092 transitions. [2023-11-26 10:43:03,463 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 69392 [2023-11-26 10:43:03,720 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69931 states to 69931 states and 99092 transitions. [2023-11-26 10:43:03,721 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69931 [2023-11-26 10:43:03,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69931 [2023-11-26 10:43:03,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69931 states and 99092 transitions. [2023-11-26 10:43:03,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:03,810 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69931 states and 99092 transitions. [2023-11-26 10:43:03,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69931 states and 99092 transitions. [2023-11-26 10:43:04,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69931 to 49329. [2023-11-26 10:43:04,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49329 states, 49329 states have (on average 1.419388189503132) internal successors, (70017), 49328 states have internal predecessors, (70017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:05,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49329 states to 49329 states and 70017 transitions. [2023-11-26 10:43:05,070 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49329 states and 70017 transitions. [2023-11-26 10:43:05,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:43:05,075 INFO L428 stractBuchiCegarLoop]: Abstraction has 49329 states and 70017 transitions. [2023-11-26 10:43:05,076 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 10:43:05,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49329 states and 70017 transitions. [2023-11-26 10:43:05,260 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48912 [2023-11-26 10:43:05,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:05,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:05,264 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:05,264 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:05,265 INFO L748 eck$LassoCheckResult]: Stem: 566835#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 566836#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 567657#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 567658#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 567170#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 567171#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 566707#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 566708#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 566797#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 567639#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 566674#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 566675#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 567126#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 567156#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 566804#L866 assume !(0 == ~M_E~0); 566805#L866-2 assume !(0 == ~T1_E~0); 567384#L871-1 assume !(0 == ~T2_E~0); 567385#L876-1 assume !(0 == ~T3_E~0); 567710#L881-1 assume !(0 == ~T4_E~0); 567399#L886-1 assume !(0 == ~T5_E~0); 567113#L891-1 assume !(0 == ~T6_E~0); 567114#L896-1 assume !(0 == ~T7_E~0); 567392#L901-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 567526#L906-1 assume !(0 == ~E_M~0); 567718#L911-1 assume !(0 == ~E_1~0); 567719#L916-1 assume !(0 == ~E_2~0); 567529#L921-1 assume !(0 == ~E_3~0); 567530#L926-1 assume !(0 == ~E_4~0); 567721#L931-1 assume !(0 == ~E_5~0); 567722#L936-1 assume !(0 == ~E_6~0); 567805#L941-1 assume !(0 == ~E_7~0); 567173#L946-1 assume !(0 == ~E_8~0); 567174#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567738#L430 assume !(1 == ~m_pc~0); 567739#L430-2 is_master_triggered_~__retres1~0#1 := 0; 567802#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567803#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567312#L1073 assume !(0 != activate_threads_~tmp~1#1); 567313#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567504#L449 assume !(1 == ~t1_pc~0); 567505#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 567699#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567700#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 567742#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 567432#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567433#L468 assume !(1 == ~t2_pc~0); 566608#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 566607#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567015#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 567016#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 566624#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 566625#L487 assume !(1 == ~t3_pc~0); 566738#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 566739#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 566604#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 566605#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 567090#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567091#L506 assume !(1 == ~t4_pc~0); 567292#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 567293#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567798#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 567797#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 567796#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 567795#L525 assume !(1 == ~t5_pc~0); 566659#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 566660#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567584#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 567585#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 567758#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 567791#L544 assume !(1 == ~t6_pc~0); 567789#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 567788#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 567787#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 566642#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 566643#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 567628#L563 assume !(1 == ~t7_pc~0); 567445#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 567446#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 567783#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 567120#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 566813#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 566814#L582 assume !(1 == ~t8_pc~0); 567450#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 567706#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 567707#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 567778#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 567777#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 567510#L964 assume !(1 == ~M_E~0); 567511#L964-2 assume !(1 == ~T1_E~0); 567701#L969-1 assume !(1 == ~T2_E~0); 567775#L974-1 assume !(1 == ~T3_E~0); 567774#L979-1 assume !(1 == ~T4_E~0); 567773#L984-1 assume !(1 == ~T5_E~0); 567772#L989-1 assume !(1 == ~T6_E~0); 567771#L994-1 assume !(1 == ~T7_E~0); 567770#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 566907#L1004-1 assume !(1 == ~E_M~0); 566645#L1009-1 assume !(1 == ~E_1~0); 566646#L1014-1 assume !(1 == ~E_2~0); 566893#L1019-1 assume !(1 == ~E_3~0); 567496#L1024-1 assume !(1 == ~E_4~0); 566832#L1029-1 assume !(1 == ~E_5~0); 566833#L1034-1 assume !(1 == ~E_6~0); 566918#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 567671#L1044-1 assume !(1 == ~E_8~0); 567136#L1049-1 assume { :end_inline_reset_delta_events } true; 567137#L1315-2 [2023-11-26 10:43:05,266 INFO L750 eck$LassoCheckResult]: Loop: 567137#L1315-2 assume !false; 582039#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 582037#L841-1 assume !false; 582035#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 581997#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 581989#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 581987#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 581984#L724 assume !(0 != eval_~tmp~0#1); 581985#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 587754#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 587752#L866-3 assume !(0 == ~M_E~0); 587750#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 587748#L871-3 assume !(0 == ~T2_E~0); 587746#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 587744#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 587742#L886-3 assume !(0 == ~T5_E~0); 587740#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 587738#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 587573#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 587571#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 587569#L911-3 assume !(0 == ~E_1~0); 587567#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 587565#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 587563#L926-3 assume !(0 == ~E_4~0); 587561#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 587559#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 587557#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 587555#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 587553#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 585407#L430-30 assume 1 == ~m_pc~0; 585408#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 585418#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 585419#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 585392#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 585393#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 585386#L449-30 assume !(1 == ~t1_pc~0); 585387#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 585380#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 585381#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 585374#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 585375#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 585366#L468-30 assume 1 == ~t2_pc~0; 585368#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 585356#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 585357#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 585350#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 585351#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 585344#L487-30 assume !(1 == ~t3_pc~0); 585345#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 585338#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 585339#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 585332#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 585333#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 585325#L506-30 assume !(1 == ~t4_pc~0); 585326#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 585318#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 585319#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 585312#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 585313#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 585306#L525-30 assume !(1 == ~t5_pc~0); 585307#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 585242#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 585243#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 585236#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 585237#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 585229#L544-30 assume !(1 == ~t6_pc~0); 585230#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 585222#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 585223#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 585216#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 585217#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 585212#L563-30 assume !(1 == ~t7_pc~0); 585211#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 585210#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 585209#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 585208#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 585207#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 585206#L582-30 assume !(1 == ~t8_pc~0); 585205#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 585204#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 585203#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 585202#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 585201#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 585200#L964-3 assume !(1 == ~M_E~0); 585199#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 585198#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 585197#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 585196#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 585195#L984-3 assume !(1 == ~T5_E~0); 585194#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 585193#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 585191#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 585189#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 585179#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 585177#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 585176#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 585166#L1024-3 assume !(1 == ~E_4~0); 585164#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 585162#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 585159#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 585157#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 585155#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 585153#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 584620#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 572271#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 571403#L1334 assume !(0 == start_simulation_~tmp~3#1); 571404#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 582186#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 582178#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 582176#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 582174#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 582172#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 582170#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 582168#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 567137#L1315-2 [2023-11-26 10:43:05,267 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:05,267 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2023-11-26 10:43:05,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:05,268 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171694697] [2023-11-26 10:43:05,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:05,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:05,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:05,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:05,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:05,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171694697] [2023-11-26 10:43:05,359 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [171694697] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:05,359 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:05,359 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:43:05,360 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685836187] [2023-11-26 10:43:05,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:05,361 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:43:05,361 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:05,361 INFO L85 PathProgramCache]: Analyzing trace with hash -1702985720, now seen corresponding path program 1 times [2023-11-26 10:43:05,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:05,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722462888] [2023-11-26 10:43:05,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:05,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:05,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:05,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:05,463 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:05,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722462888] [2023-11-26 10:43:05,464 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1722462888] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:05,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:05,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:43:05,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868662701] [2023-11-26 10:43:05,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:05,465 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:43:05,466 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:05,466 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:43:05,466 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:43:05,467 INFO L87 Difference]: Start difference. First operand 49329 states and 70017 transitions. cyclomatic complexity: 20720 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:05,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:05,794 INFO L93 Difference]: Finished difference Result 43969 states and 62160 transitions. [2023-11-26 10:43:05,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43969 states and 62160 transitions. [2023-11-26 10:43:06,037 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43632 [2023-11-26 10:43:06,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43969 states to 43969 states and 62160 transitions. [2023-11-26 10:43:06,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43969 [2023-11-26 10:43:06,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43969 [2023-11-26 10:43:06,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43969 states and 62160 transitions. [2023-11-26 10:43:06,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:06,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43969 states and 62160 transitions. [2023-11-26 10:43:06,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43969 states and 62160 transitions. [2023-11-26 10:43:07,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43969 to 43969. [2023-11-26 10:43:07,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43969 states, 43969 states have (on average 1.4137233050558349) internal successors, (62160), 43968 states have internal predecessors, (62160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:07,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43969 states to 43969 states and 62160 transitions. [2023-11-26 10:43:07,481 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43969 states and 62160 transitions. [2023-11-26 10:43:07,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:43:07,482 INFO L428 stractBuchiCegarLoop]: Abstraction has 43969 states and 62160 transitions. [2023-11-26 10:43:07,482 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 10:43:07,482 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43969 states and 62160 transitions. [2023-11-26 10:43:07,594 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43632 [2023-11-26 10:43:07,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:07,594 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:07,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:07,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:07,597 INFO L748 eck$LassoCheckResult]: Stem: 660139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 660140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 660931#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 660932#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 660460#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 660461#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 660014#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 660015#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 660103#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 660914#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 659983#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 659984#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 660417#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 660447#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 660108#L866 assume !(0 == ~M_E~0); 660109#L866-2 assume !(0 == ~T1_E~0); 660662#L871-1 assume !(0 == ~T2_E~0); 660663#L876-1 assume !(0 == ~T3_E~0); 660978#L881-1 assume !(0 == ~T4_E~0); 660676#L886-1 assume !(0 == ~T5_E~0); 660404#L891-1 assume !(0 == ~T6_E~0); 660405#L896-1 assume !(0 == ~T7_E~0); 660670#L901-1 assume !(0 == ~T8_E~0); 660693#L906-1 assume !(0 == ~E_M~0); 660694#L911-1 assume !(0 == ~E_1~0); 660457#L916-1 assume !(0 == ~E_2~0); 660458#L921-1 assume !(0 == ~E_3~0); 660804#L926-1 assume !(0 == ~E_4~0); 660928#L931-1 assume !(0 == ~E_5~0); 660986#L936-1 assume !(0 == ~E_6~0); 661002#L941-1 assume !(0 == ~E_7~0); 660462#L946-1 assume !(0 == ~E_8~0); 660463#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 660955#L430 assume !(1 == ~m_pc~0); 660301#L430-2 is_master_triggered_~__retres1~0#1 := 0; 660893#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 661026#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 660587#L1073 assume !(0 != activate_threads_~tmp~1#1); 660588#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 660780#L449 assume !(1 == ~t1_pc~0); 660113#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 660114#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 659959#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 659960#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 660707#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 660524#L468 assume !(1 == ~t2_pc~0); 659918#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 659917#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 660311#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 660306#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 659934#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 659935#L487 assume !(1 == ~t3_pc~0); 660046#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 660020#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 659914#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 659915#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 660383#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 660384#L506 assume !(1 == ~t4_pc~0); 660516#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 660571#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 660006#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 660007#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 660511#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 660317#L525 assume !(1 == ~t5_pc~0); 659969#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 659970#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 660856#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 660857#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 660171#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 660172#L544 assume !(1 == ~t6_pc~0); 660318#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 660319#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 660290#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 659952#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 659953#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 660904#L563 assume !(1 == ~t7_pc~0); 660718#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 659974#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 659975#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 660411#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 660117#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 660118#L582 assume !(1 == ~t8_pc~0); 660721#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 660970#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 660788#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 660370#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 660256#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 660257#L964 assume !(1 == ~M_E~0); 660784#L964-2 assume !(1 == ~T1_E~0); 660173#L969-1 assume !(1 == ~T2_E~0); 660174#L974-1 assume !(1 == ~T3_E~0); 660825#L979-1 assume !(1 == ~T4_E~0); 660826#L984-1 assume !(1 == ~T5_E~0); 660324#L989-1 assume !(1 == ~T6_E~0); 660325#L994-1 assume !(1 == ~T7_E~0); 660211#L999-1 assume !(1 == ~T8_E~0); 660212#L1004-1 assume !(1 == ~E_M~0); 659954#L1009-1 assume !(1 == ~E_1~0); 659955#L1014-1 assume !(1 == ~E_2~0); 660198#L1019-1 assume !(1 == ~E_3~0); 660768#L1024-1 assume !(1 == ~E_4~0); 660136#L1029-1 assume !(1 == ~E_5~0); 660137#L1034-1 assume !(1 == ~E_6~0); 660223#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 660945#L1044-1 assume !(1 == ~E_8~0); 660425#L1049-1 assume { :end_inline_reset_delta_events } true; 660426#L1315-2 [2023-11-26 10:43:07,598 INFO L750 eck$LassoCheckResult]: Loop: 660426#L1315-2 assume !false; 666525#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 666523#L841-1 assume !false; 666521#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 666507#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 666501#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 666499#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 666497#L724 assume !(0 != eval_~tmp~0#1); 666498#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 692782#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 692780#L866-3 assume !(0 == ~M_E~0); 692777#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 692775#L871-3 assume !(0 == ~T2_E~0); 692773#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 692771#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 692769#L886-3 assume !(0 == ~T5_E~0); 692767#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 692764#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 692762#L901-3 assume !(0 == ~T8_E~0); 692760#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 692758#L911-3 assume !(0 == ~E_1~0); 692756#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 692752#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 692750#L926-3 assume !(0 == ~E_4~0); 692748#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 692746#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 692744#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 692742#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 692239#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 692236#L430-30 assume 1 == ~m_pc~0; 692234#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 692235#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 692638#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 692224#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 692220#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 692218#L449-30 assume !(1 == ~t1_pc~0); 692216#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 692214#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 692211#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 692209#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 692207#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 692204#L468-30 assume 1 == ~t2_pc~0; 692200#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 692198#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 692196#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 692194#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 692191#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 692189#L487-30 assume !(1 == ~t3_pc~0); 692187#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 692185#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 692177#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 692170#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 692163#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 692157#L506-30 assume !(1 == ~t4_pc~0); 692152#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 692149#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 692115#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 692109#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 692106#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 692103#L525-30 assume !(1 == ~t5_pc~0); 692099#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 692092#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 692078#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 684164#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 682084#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 682083#L544-30 assume !(1 == ~t6_pc~0); 682038#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 682036#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 682034#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 682032#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 682030#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 666909#L563-30 assume !(1 == ~t7_pc~0); 666907#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 666904#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 666902#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 666900#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 666898#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 666896#L582-30 assume !(1 == ~t8_pc~0); 666894#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 666892#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 666890#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 666888#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 666886#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 666884#L964-3 assume !(1 == ~M_E~0); 666882#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 666879#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 666877#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 666875#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 666873#L984-3 assume !(1 == ~T5_E~0); 666871#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 666869#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 666867#L999-3 assume !(1 == ~T8_E~0); 666865#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 666863#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 666861#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 666859#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 666857#L1024-3 assume !(1 == ~E_4~0); 666854#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 666852#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 666850#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 666848#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 666846#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 666844#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 666835#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 666833#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 666830#L1334 assume !(0 == start_simulation_~tmp~3#1); 666828#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 666820#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 666812#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 666810#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 666808#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 666807#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 666804#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 666803#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 660426#L1315-2 [2023-11-26 10:43:07,599 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:07,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1031757063, now seen corresponding path program 1 times [2023-11-26 10:43:07,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:07,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1871678442] [2023-11-26 10:43:07,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:07,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:07,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:07,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:07,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:07,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1871678442] [2023-11-26 10:43:07,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1871678442] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:07,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:07,695 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:43:07,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145287408] [2023-11-26 10:43:07,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:07,696 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:43:07,697 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:07,697 INFO L85 PathProgramCache]: Analyzing trace with hash -270187960, now seen corresponding path program 1 times [2023-11-26 10:43:07,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:07,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323102285] [2023-11-26 10:43:07,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:07,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:07,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:07,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:07,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:07,775 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323102285] [2023-11-26 10:43:07,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323102285] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:07,775 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:07,775 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:43:07,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316956110] [2023-11-26 10:43:07,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:07,776 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:43:07,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:07,777 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:43:07,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:43:07,777 INFO L87 Difference]: Start difference. First operand 43969 states and 62160 transitions. cyclomatic complexity: 18223 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:08,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:08,231 INFO L93 Difference]: Finished difference Result 68195 states and 96162 transitions. [2023-11-26 10:43:08,231 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68195 states and 96162 transitions. [2023-11-26 10:43:08,566 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 67632 [2023-11-26 10:43:08,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68195 states to 68195 states and 96162 transitions. [2023-11-26 10:43:08,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68195 [2023-11-26 10:43:08,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68195 [2023-11-26 10:43:08,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68195 states and 96162 transitions. [2023-11-26 10:43:08,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:08,809 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68195 states and 96162 transitions. [2023-11-26 10:43:08,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68195 states and 96162 transitions. [2023-11-26 10:43:09,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68195 to 49297. [2023-11-26 10:43:09,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49297 states, 49297 states have (on average 1.4115057711422603) internal successors, (69583), 49296 states have internal predecessors, (69583), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:10,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49297 states to 49297 states and 69583 transitions. [2023-11-26 10:43:10,035 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49297 states and 69583 transitions. [2023-11-26 10:43:10,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:43:10,036 INFO L428 stractBuchiCegarLoop]: Abstraction has 49297 states and 69583 transitions. [2023-11-26 10:43:10,036 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 10:43:10,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49297 states and 69583 transitions. [2023-11-26 10:43:10,164 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48880 [2023-11-26 10:43:10,164 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:10,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:10,167 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:10,167 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:10,167 INFO L748 eck$LassoCheckResult]: Stem: 772318#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 772319#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 773171#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 773172#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 772648#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 772649#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 772192#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 772193#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 772282#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 773153#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 772161#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 772162#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 772603#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 772635#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 772286#L866 assume !(0 == ~M_E~0); 772287#L866-2 assume !(0 == ~T1_E~0); 772859#L871-1 assume !(0 == ~T2_E~0); 772860#L876-1 assume !(0 == ~T3_E~0); 773236#L881-1 assume !(0 == ~T4_E~0); 772877#L886-1 assume !(0 == ~T5_E~0); 772591#L891-1 assume !(0 == ~T6_E~0); 772592#L896-1 assume !(0 == ~T7_E~0); 772867#L901-1 assume !(0 == ~T8_E~0); 772898#L906-1 assume !(0 == ~E_M~0); 772899#L911-1 assume !(0 == ~E_1~0); 772645#L916-1 assume !(0 == ~E_2~0); 772646#L921-1 assume !(0 == ~E_3~0); 773029#L926-1 assume !(0 == ~E_4~0); 773167#L931-1 assume !(0 == ~E_5~0); 773246#L936-1 assume !(0 == ~E_6~0); 773254#L941-1 assume 0 == ~E_7~0;~E_7~0 := 1; 772650#L946-1 assume !(0 == ~E_8~0); 772651#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 773257#L430 assume !(1 == ~m_pc~0); 773258#L430-2 is_master_triggered_~__retres1~0#1 := 0; 772106#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 772107#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 772786#L1073 assume !(0 != activate_threads_~tmp~1#1); 772787#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 773000#L449 assume !(1 == ~t1_pc~0); 773001#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 773223#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 773224#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 773261#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 773262#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 772717#L468 assume !(1 == ~t2_pc~0); 772718#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 772837#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 772838#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 772489#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 772490#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 773255#L487 assume !(1 == ~t3_pc~0); 773256#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 772198#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 772199#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 773087#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 773088#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 772710#L506 assume !(1 == ~t4_pc~0); 772711#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 773295#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 773296#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 773229#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 773230#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 772503#L525 assume !(1 == ~t5_pc~0); 772504#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 773144#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 773145#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 773288#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 773289#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 772697#L544 assume !(1 == ~t6_pc~0); 772698#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 773317#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 772472#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 772473#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 773211#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 773212#L563 assume !(1 == ~t7_pc~0); 773316#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 772152#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 772153#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 772593#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 772594#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 773315#L582 assume !(1 == ~t8_pc~0); 773270#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 773271#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 773012#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 772555#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 772556#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 773007#L964 assume !(1 == ~M_E~0); 773008#L964-2 assume !(1 == ~T1_E~0); 772352#L969-1 assume !(1 == ~T2_E~0); 772353#L974-1 assume !(1 == ~T3_E~0); 773056#L979-1 assume !(1 == ~T4_E~0); 773057#L984-1 assume !(1 == ~T5_E~0); 772511#L989-1 assume !(1 == ~T6_E~0); 772512#L994-1 assume !(1 == ~T7_E~0); 772387#L999-1 assume !(1 == ~T8_E~0); 772388#L1004-1 assume !(1 == ~E_M~0); 772130#L1009-1 assume !(1 == ~E_1~0); 772131#L1014-1 assume !(1 == ~E_2~0); 772989#L1019-1 assume !(1 == ~E_3~0); 772990#L1024-1 assume !(1 == ~E_4~0); 772315#L1029-1 assume !(1 == ~E_5~0); 772316#L1034-1 assume !(1 == ~E_6~0); 773308#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 773187#L1044-1 assume !(1 == ~E_8~0); 772614#L1049-1 assume { :end_inline_reset_delta_events } true; 772615#L1315-2 [2023-11-26 10:43:10,168 INFO L750 eck$LassoCheckResult]: Loop: 772615#L1315-2 assume !false; 790202#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 790201#L841-1 assume !false; 790200#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 790182#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 790176#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 790174#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 790171#L724 assume !(0 != eval_~tmp~0#1); 790172#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 794887#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 794880#L866-3 assume !(0 == ~M_E~0); 794874#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 794869#L871-3 assume !(0 == ~T2_E~0); 794863#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 794858#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 794853#L886-3 assume !(0 == ~T5_E~0); 794848#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 794844#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 794839#L901-3 assume !(0 == ~T8_E~0); 794835#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 794830#L911-3 assume !(0 == ~E_1~0); 794825#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 794819#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 794814#L926-3 assume !(0 == ~E_4~0); 794809#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 794755#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 784593#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 784591#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 784589#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 784587#L430-30 assume !(1 == ~m_pc~0); 784585#L430-32 is_master_triggered_~__retres1~0#1 := 0; 784601#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 784602#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 784565#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 784562#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 784560#L449-30 assume !(1 == ~t1_pc~0); 784558#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 784556#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 784554#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 784546#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 784538#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 784532#L468-30 assume !(1 == ~t2_pc~0); 784525#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 784488#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 784481#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 784351#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 784278#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 784274#L487-30 assume !(1 == ~t3_pc~0); 784271#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 784268#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 784265#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 784262#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 784259#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 784256#L506-30 assume !(1 == ~t4_pc~0); 784251#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 784252#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 791966#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 791964#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 784236#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 784232#L525-30 assume !(1 == ~t5_pc~0); 784233#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 784224#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 784225#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 784216#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 784217#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 784207#L544-30 assume 1 == ~t6_pc~0; 784209#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 784156#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 784157#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 784149#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 784150#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 784142#L563-30 assume !(1 == ~t7_pc~0); 784141#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 784140#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 784139#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 784138#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 784137#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 784136#L582-30 assume !(1 == ~t8_pc~0); 784135#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 784134#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 784133#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 784132#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 784131#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 784130#L964-3 assume !(1 == ~M_E~0); 784129#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 784128#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 784127#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 784126#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 784125#L984-3 assume !(1 == ~T5_E~0); 784124#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 784123#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 784122#L999-3 assume !(1 == ~T8_E~0); 784121#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 784120#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 784119#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 784118#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 784117#L1024-3 assume !(1 == ~E_4~0); 784116#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 784115#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 784113#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 784111#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 784109#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 784107#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 784090#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 784080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 782780#L1334 assume !(0 == start_simulation_~tmp~3#1); 782781#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 790230#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 790222#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 790220#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 790218#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 790216#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 790214#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 790212#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 772615#L1315-2 [2023-11-26 10:43:10,169 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:10,169 INFO L85 PathProgramCache]: Analyzing trace with hash -1185873335, now seen corresponding path program 1 times [2023-11-26 10:43:10,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:10,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526281388] [2023-11-26 10:43:10,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:10,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:10,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:10,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:10,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:10,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526281388] [2023-11-26 10:43:10,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1526281388] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:10,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:10,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:43:10,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1440323918] [2023-11-26 10:43:10,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:10,240 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:43:10,240 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:10,240 INFO L85 PathProgramCache]: Analyzing trace with hash -1881427957, now seen corresponding path program 1 times [2023-11-26 10:43:10,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:10,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267168018] [2023-11-26 10:43:10,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:10,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:10,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:10,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:10,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:10,309 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267168018] [2023-11-26 10:43:10,309 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267168018] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:10,310 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:10,310 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:43:10,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [756143321] [2023-11-26 10:43:10,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:10,310 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:43:10,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:10,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:43:10,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:43:10,311 INFO L87 Difference]: Start difference. First operand 49297 states and 69583 transitions. cyclomatic complexity: 20318 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:10,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:10,645 INFO L93 Difference]: Finished difference Result 62497 states and 87838 transitions. [2023-11-26 10:43:10,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62497 states and 87838 transitions. [2023-11-26 10:43:11,366 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 62016 [2023-11-26 10:43:11,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62497 states to 62497 states and 87838 transitions. [2023-11-26 10:43:11,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62497 [2023-11-26 10:43:11,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62497 [2023-11-26 10:43:11,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62497 states and 87838 transitions. [2023-11-26 10:43:11,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:11,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62497 states and 87838 transitions. [2023-11-26 10:43:11,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62497 states and 87838 transitions. [2023-11-26 10:43:11,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62497 to 43969. [2023-11-26 10:43:11,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43969 states, 43969 states have (on average 1.4045804998976552) internal successors, (61758), 43968 states have internal predecessors, (61758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:12,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43969 states to 43969 states and 61758 transitions. [2023-11-26 10:43:12,032 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43969 states and 61758 transitions. [2023-11-26 10:43:12,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:43:12,033 INFO L428 stractBuchiCegarLoop]: Abstraction has 43969 states and 61758 transitions. [2023-11-26 10:43:12,033 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 10:43:12,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43969 states and 61758 transitions. [2023-11-26 10:43:12,150 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43632 [2023-11-26 10:43:12,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:12,150 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:12,153 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:12,153 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:12,153 INFO L748 eck$LassoCheckResult]: Stem: 884122#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 884123#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 884953#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 884954#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 884450#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 884451#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 883998#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 883999#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 884086#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 884933#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 883967#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 883968#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 884406#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 884437#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 884090#L866 assume !(0 == ~M_E~0); 884091#L866-2 assume !(0 == ~T1_E~0); 884657#L871-1 assume !(0 == ~T2_E~0); 884658#L876-1 assume !(0 == ~T3_E~0); 885003#L881-1 assume !(0 == ~T4_E~0); 884672#L886-1 assume !(0 == ~T5_E~0); 884395#L891-1 assume !(0 == ~T6_E~0); 884396#L896-1 assume !(0 == ~T7_E~0); 884665#L901-1 assume !(0 == ~T8_E~0); 884691#L906-1 assume !(0 == ~E_M~0); 884692#L911-1 assume !(0 == ~E_1~0); 884447#L916-1 assume !(0 == ~E_2~0); 884448#L921-1 assume !(0 == ~E_3~0); 884801#L926-1 assume !(0 == ~E_4~0); 884950#L931-1 assume !(0 == ~E_5~0); 885014#L936-1 assume !(0 == ~E_6~0); 885025#L941-1 assume !(0 == ~E_7~0); 884452#L946-1 assume !(0 == ~E_8~0); 884453#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 884977#L430 assume !(1 == ~m_pc~0); 884292#L430-2 is_master_triggered_~__retres1~0#1 := 0; 883912#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 883913#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 884583#L1073 assume !(0 != activate_threads_~tmp~1#1); 884584#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 884776#L449 assume !(1 == ~t1_pc~0); 884096#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 884097#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 883939#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 883940#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 884706#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 884512#L468 assume !(1 == ~t2_pc~0); 883900#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 883899#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 884302#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 884297#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 883914#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 883915#L487 assume !(1 == ~t3_pc~0); 884029#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 884004#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 883896#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 883897#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 884374#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 884375#L506 assume !(1 == ~t4_pc~0); 884506#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 884565#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 883990#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 883991#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 884500#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 884309#L525 assume !(1 == ~t5_pc~0); 883952#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 883953#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 884865#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 884866#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 884156#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 884157#L544 assume !(1 == ~t6_pc~0); 884310#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 884311#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 884279#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 883934#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 883935#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 884920#L563 assume !(1 == ~t7_pc~0); 884719#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 883958#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 883959#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 884397#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 884098#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 884099#L582 assume !(1 == ~t8_pc~0); 884723#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 884998#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 884784#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 884362#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 884238#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 884239#L964 assume !(1 == ~M_E~0); 884781#L964-2 assume !(1 == ~T1_E~0); 884158#L969-1 assume !(1 == ~T2_E~0); 884159#L974-1 assume !(1 == ~T3_E~0); 884828#L979-1 assume !(1 == ~T4_E~0); 884829#L984-1 assume !(1 == ~T5_E~0); 884317#L989-1 assume !(1 == ~T6_E~0); 884318#L994-1 assume !(1 == ~T7_E~0); 884191#L999-1 assume !(1 == ~T8_E~0); 884192#L1004-1 assume !(1 == ~E_M~0); 883936#L1009-1 assume !(1 == ~E_1~0); 883937#L1014-1 assume !(1 == ~E_2~0); 884179#L1019-1 assume !(1 == ~E_3~0); 884767#L1024-1 assume !(1 == ~E_4~0); 884119#L1029-1 assume !(1 == ~E_5~0); 884120#L1034-1 assume !(1 == ~E_6~0); 884205#L1039-1 assume !(1 == ~E_7~0); 884966#L1044-1 assume !(1 == ~E_8~0); 884416#L1049-1 assume { :end_inline_reset_delta_events } true; 884417#L1315-2 [2023-11-26 10:43:12,154 INFO L750 eck$LassoCheckResult]: Loop: 884417#L1315-2 assume !false; 911880#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 911876#L841-1 assume !false; 911874#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 911861#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 911855#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 911853#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 911850#L724 assume !(0 != eval_~tmp~0#1); 911851#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 925887#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 925881#L866-3 assume !(0 == ~M_E~0); 925874#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 925857#L871-3 assume !(0 == ~T2_E~0); 925850#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 925841#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 925834#L886-3 assume !(0 == ~T5_E~0); 925827#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 925819#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 925811#L901-3 assume !(0 == ~T8_E~0); 925804#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 925796#L911-3 assume !(0 == ~E_1~0); 925789#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 925782#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 925773#L926-3 assume !(0 == ~E_4~0); 925764#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 925757#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 925751#L941-3 assume !(0 == ~E_7~0); 925744#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 925737#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 925668#L430-30 assume 1 == ~m_pc~0; 925666#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 925667#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 925736#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 925656#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 925654#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 925652#L449-30 assume !(1 == ~t1_pc~0); 925649#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 925647#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 925645#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 925643#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 925641#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 925639#L468-30 assume !(1 == ~t2_pc~0); 925636#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 925633#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 925631#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 925629#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 925627#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 925625#L487-30 assume !(1 == ~t3_pc~0); 925622#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 925620#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 925618#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 925616#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 925614#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 925612#L506-30 assume !(1 == ~t4_pc~0); 925608#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 925606#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 925604#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 925602#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 925600#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 925598#L525-30 assume !(1 == ~t5_pc~0); 925595#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 925593#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 925591#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 925589#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 925587#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 925585#L544-30 assume 1 == ~t6_pc~0; 925582#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 925579#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 925577#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 925575#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 925573#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 910910#L563-30 assume !(1 == ~t7_pc~0); 910908#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 910906#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 910904#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 910901#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 910899#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 910897#L582-30 assume !(1 == ~t8_pc~0); 910895#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 910893#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 910891#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 910888#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 910886#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 910884#L964-3 assume !(1 == ~M_E~0); 910882#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 910880#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 910878#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 910875#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 910873#L984-3 assume !(1 == ~T5_E~0); 910871#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 910869#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 910867#L999-3 assume !(1 == ~T8_E~0); 910864#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 910862#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 910860#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 910858#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 910856#L1024-3 assume !(1 == ~E_4~0); 910854#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 910852#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 910850#L1039-3 assume !(1 == ~E_7~0); 910847#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 910845#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 910843#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 910833#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 908262#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 896171#L1334 assume !(0 == start_simulation_~tmp~3#1); 896172#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 918799#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 918791#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 918789#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 918787#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 918785#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 918783#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 918781#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 884417#L1315-2 [2023-11-26 10:43:12,155 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:12,155 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 1 times [2023-11-26 10:43:12,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:12,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449498408] [2023-11-26 10:43:12,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:12,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:12,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:12,176 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:12,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:12,256 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:12,257 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:12,257 INFO L85 PathProgramCache]: Analyzing trace with hash -1880960632, now seen corresponding path program 1 times [2023-11-26 10:43:12,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:12,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248302523] [2023-11-26 10:43:12,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:12,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:12,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:12,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:12,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:12,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248302523] [2023-11-26 10:43:12,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248302523] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:12,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:12,330 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:43:12,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770469628] [2023-11-26 10:43:12,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:12,331 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:43:12,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:12,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:43:12,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:43:12,332 INFO L87 Difference]: Start difference. First operand 43969 states and 61758 transitions. cyclomatic complexity: 17821 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:13,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:13,193 INFO L93 Difference]: Finished difference Result 80433 states and 111582 transitions. [2023-11-26 10:43:13,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80433 states and 111582 transitions. [2023-11-26 10:43:13,536 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79872 [2023-11-26 10:43:13,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80433 states to 80433 states and 111582 transitions. [2023-11-26 10:43:13,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 80433 [2023-11-26 10:43:13,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 80433 [2023-11-26 10:43:13,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80433 states and 111582 transitions. [2023-11-26 10:43:13,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:13,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80433 states and 111582 transitions. [2023-11-26 10:43:13,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80433 states and 111582 transitions. [2023-11-26 10:43:14,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80433 to 44161. [2023-11-26 10:43:14,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44161 states, 44161 states have (on average 1.4028214940784856) internal successors, (61950), 44160 states have internal predecessors, (61950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:14,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44161 states to 44161 states and 61950 transitions. [2023-11-26 10:43:14,557 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44161 states and 61950 transitions. [2023-11-26 10:43:14,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 10:43:14,558 INFO L428 stractBuchiCegarLoop]: Abstraction has 44161 states and 61950 transitions. [2023-11-26 10:43:14,558 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-26 10:43:14,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44161 states and 61950 transitions. [2023-11-26 10:43:14,699 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43824 [2023-11-26 10:43:14,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:14,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:14,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:14,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:14,702 INFO L748 eck$LassoCheckResult]: Stem: 1008542#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1008543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1009381#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1009382#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1008868#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1008869#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1008414#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1008415#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1008504#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1009363#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1008383#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1008384#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1008823#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1008855#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1008510#L866 assume !(0 == ~M_E~0); 1008511#L866-2 assume !(0 == ~T1_E~0); 1009071#L871-1 assume !(0 == ~T2_E~0); 1009072#L876-1 assume !(0 == ~T3_E~0); 1009443#L881-1 assume !(0 == ~T4_E~0); 1009086#L886-1 assume !(0 == ~T5_E~0); 1008812#L891-1 assume !(0 == ~T6_E~0); 1008813#L896-1 assume !(0 == ~T7_E~0); 1009079#L901-1 assume !(0 == ~T8_E~0); 1009106#L906-1 assume !(0 == ~E_M~0); 1009107#L911-1 assume !(0 == ~E_1~0); 1008865#L916-1 assume !(0 == ~E_2~0); 1008866#L921-1 assume !(0 == ~E_3~0); 1009232#L926-1 assume !(0 == ~E_4~0); 1009377#L931-1 assume !(0 == ~E_5~0); 1009448#L936-1 assume !(0 == ~E_6~0); 1009469#L941-1 assume !(0 == ~E_7~0); 1008870#L946-1 assume !(0 == ~E_8~0); 1008871#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1009414#L430 assume !(1 == ~m_pc~0); 1008706#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1008330#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1008331#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1008999#L1073 assume !(0 != activate_threads_~tmp~1#1); 1009000#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1009210#L449 assume !(1 == ~t1_pc~0); 1008516#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1008517#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1008357#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1008358#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1009121#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1008931#L468 assume !(1 == ~t2_pc~0); 1008319#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1008318#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1008716#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1008711#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1008332#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1008333#L487 assume !(1 == ~t3_pc~0); 1008445#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1008420#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1008315#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1008316#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1008791#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1008792#L506 assume !(1 == ~t4_pc~0); 1008926#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1008982#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1008406#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1008407#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1008919#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1008723#L525 assume !(1 == ~t5_pc~0); 1008369#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1008370#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1009300#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1009301#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1008575#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1008576#L544 assume !(1 == ~t6_pc~0); 1008724#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1008725#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1008695#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1008352#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1008353#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1009351#L563 assume !(1 == ~t7_pc~0); 1009135#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1008375#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1008376#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1008814#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1008518#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1008519#L582 assume !(1 == ~t8_pc~0); 1009138#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1009433#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1009217#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1008777#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1008658#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1008659#L964 assume !(1 == ~M_E~0); 1009213#L964-2 assume !(1 == ~T1_E~0); 1008577#L969-1 assume !(1 == ~T2_E~0); 1008578#L974-1 assume !(1 == ~T3_E~0); 1009259#L979-1 assume !(1 == ~T4_E~0); 1009260#L984-1 assume !(1 == ~T5_E~0); 1008731#L989-1 assume !(1 == ~T6_E~0); 1008732#L994-1 assume !(1 == ~T7_E~0); 1008608#L999-1 assume !(1 == ~T8_E~0); 1008609#L1004-1 assume !(1 == ~E_M~0); 1008354#L1009-1 assume !(1 == ~E_1~0); 1008355#L1014-1 assume !(1 == ~E_2~0); 1008597#L1019-1 assume !(1 == ~E_3~0); 1009200#L1024-1 assume !(1 == ~E_4~0); 1008539#L1029-1 assume !(1 == ~E_5~0); 1008540#L1034-1 assume !(1 == ~E_6~0); 1008625#L1039-1 assume !(1 == ~E_7~0); 1009397#L1044-1 assume !(1 == ~E_8~0); 1008833#L1049-1 assume { :end_inline_reset_delta_events } true; 1008834#L1315-2 [2023-11-26 10:43:14,703 INFO L750 eck$LassoCheckResult]: Loop: 1008834#L1315-2 assume !false; 1041696#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1041694#L841-1 assume !false; 1041171#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1041163#L662 assume !(0 == ~m_st~0); 1041164#L666 assume !(0 == ~t1_st~0); 1041167#L670 assume !(0 == ~t2_st~0); 1041161#L674 assume !(0 == ~t3_st~0); 1041162#L678 assume !(0 == ~t4_st~0); 1041166#L682 assume !(0 == ~t5_st~0); 1041159#L686 assume !(0 == ~t6_st~0); 1041160#L690 assume !(0 == ~t7_st~0); 1041165#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1041168#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1021138#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1021139#L724 assume !(0 != eval_~tmp~0#1); 1041153#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1041152#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1041151#L866-3 assume !(0 == ~M_E~0); 1041150#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1041149#L871-3 assume !(0 == ~T2_E~0); 1041148#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1041147#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1041146#L886-3 assume !(0 == ~T5_E~0); 1041145#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1041144#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1041143#L901-3 assume !(0 == ~T8_E~0); 1041142#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1041141#L911-3 assume !(0 == ~E_1~0); 1041140#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1041139#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1041138#L926-3 assume !(0 == ~E_4~0); 1041137#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1041136#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1041135#L941-3 assume !(0 == ~E_7~0); 1041134#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1041133#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1041132#L430-30 assume !(1 == ~m_pc~0); 1041131#L430-32 is_master_triggered_~__retres1~0#1 := 0; 1041129#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1041127#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1041125#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 1041123#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1041122#L449-30 assume !(1 == ~t1_pc~0); 1041121#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1041120#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1041119#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1041118#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1041117#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1041116#L468-30 assume !(1 == ~t2_pc~0); 1041115#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1041113#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1041112#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1041111#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 1041110#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1041109#L487-30 assume !(1 == ~t3_pc~0); 1041108#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1041107#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1041106#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1041105#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1041104#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1041103#L506-30 assume 1 == ~t4_pc~0; 1041102#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1041100#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1041099#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1041098#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1041097#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1041096#L525-30 assume !(1 == ~t5_pc~0); 1041095#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1041094#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1041093#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1041092#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1041091#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1041090#L544-30 assume 1 == ~t6_pc~0; 1041089#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1041087#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1041086#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1041085#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1041084#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1041083#L563-30 assume !(1 == ~t7_pc~0); 1021646#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1041082#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1041081#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1041080#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1041079#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1041078#L582-30 assume !(1 == ~t8_pc~0); 1041077#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1041076#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1041075#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1041074#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1041073#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1041072#L964-3 assume !(1 == ~M_E~0); 1041071#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1041070#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1041069#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1041068#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1041067#L984-3 assume !(1 == ~T5_E~0); 1041066#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1041065#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1041064#L999-3 assume !(1 == ~T8_E~0); 1041063#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1041062#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1041061#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1041060#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1041059#L1024-3 assume !(1 == ~E_4~0); 1041058#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1041057#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1041056#L1039-3 assume !(1 == ~E_7~0); 1041055#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1041054#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1041053#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1041043#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1041041#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1041038#L1334 assume !(0 == start_simulation_~tmp~3#1); 1041039#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1042448#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1042428#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1042423#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1042420#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1042416#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1042105#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1042040#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1008834#L1315-2 [2023-11-26 10:43:14,704 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:14,704 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 2 times [2023-11-26 10:43:14,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:14,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402012763] [2023-11-26 10:43:14,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:14,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:14,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:14,741 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:14,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:14,801 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:14,802 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:14,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1224829236, now seen corresponding path program 1 times [2023-11-26 10:43:14,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:14,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [839195617] [2023-11-26 10:43:14,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:14,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:14,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:14,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:14,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:14,859 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [839195617] [2023-11-26 10:43:14,859 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [839195617] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:14,859 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:14,859 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:43:14,859 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1589904615] [2023-11-26 10:43:14,860 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:14,860 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:43:14,860 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:14,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:43:14,861 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:43:14,861 INFO L87 Difference]: Start difference. First operand 44161 states and 61950 transitions. cyclomatic complexity: 17821 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:15,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:15,624 INFO L93 Difference]: Finished difference Result 82684 states and 114986 transitions. [2023-11-26 10:43:15,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82684 states and 114986 transitions. [2023-11-26 10:43:15,920 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 82080 [2023-11-26 10:43:16,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82684 states to 82684 states and 114986 transitions. [2023-11-26 10:43:16,112 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82684 [2023-11-26 10:43:16,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82684 [2023-11-26 10:43:16,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82684 states and 114986 transitions. [2023-11-26 10:43:16,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:16,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82684 states and 114986 transitions. [2023-11-26 10:43:16,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82684 states and 114986 transitions. [2023-11-26 10:43:17,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82684 to 82652. [2023-11-26 10:43:17,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82652 states, 82652 states have (on average 1.3908193389149688) internal successors, (114954), 82651 states have internal predecessors, (114954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:17,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82652 states to 82652 states and 114954 transitions. [2023-11-26 10:43:17,558 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82652 states and 114954 transitions. [2023-11-26 10:43:17,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:43:17,559 INFO L428 stractBuchiCegarLoop]: Abstraction has 82652 states and 114954 transitions. [2023-11-26 10:43:17,559 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-26 10:43:17,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82652 states and 114954 transitions. [2023-11-26 10:43:17,756 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 82048 [2023-11-26 10:43:17,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:17,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:17,757 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:17,758 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:17,758 INFO L748 eck$LassoCheckResult]: Stem: 1135389#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1135390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1136242#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1136243#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1135722#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1135723#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1135265#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1135266#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1135353#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1136213#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1135234#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1135235#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1135677#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1135709#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1135357#L866 assume !(0 == ~M_E~0); 1135358#L866-2 assume !(0 == ~T1_E~0); 1135927#L871-1 assume !(0 == ~T2_E~0); 1135928#L876-1 assume !(0 == ~T3_E~0); 1136310#L881-1 assume !(0 == ~T4_E~0); 1135945#L886-1 assume !(0 == ~T5_E~0); 1135665#L891-1 assume !(0 == ~T6_E~0); 1135666#L896-1 assume !(0 == ~T7_E~0); 1135935#L901-1 assume !(0 == ~T8_E~0); 1135964#L906-1 assume !(0 == ~E_M~0); 1135965#L911-1 assume !(0 == ~E_1~0); 1135719#L916-1 assume !(0 == ~E_2~0); 1135720#L921-1 assume !(0 == ~E_3~0); 1136088#L926-1 assume !(0 == ~E_4~0); 1136238#L931-1 assume !(0 == ~E_5~0); 1136321#L936-1 assume !(0 == ~E_6~0); 1136328#L941-1 assume !(0 == ~E_7~0); 1135724#L946-1 assume !(0 == ~E_8~0); 1135725#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1136277#L430 assume !(1 == ~m_pc~0); 1135556#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1136181#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1136382#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1135854#L1073 assume !(0 != activate_threads_~tmp~1#1); 1135855#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1136061#L449 assume !(1 == ~t1_pc~0); 1135363#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1135364#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1135207#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1135208#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1135979#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1135787#L468 assume !(1 == ~t2_pc~0); 1135170#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1135169#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1135566#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1135561#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1135183#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1135184#L487 assume !(1 == ~t3_pc~0); 1135296#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1135271#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1135166#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1135167#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1135644#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1135645#L506 assume !(1 == ~t4_pc~0); 1135782#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1136319#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1136366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1136301#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1136302#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1135575#L525 assume !(1 == ~t5_pc~0); 1135576#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1136198#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1136199#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1136363#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1136364#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1135771#L544 assume !(1 == ~t6_pc~0); 1135772#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1136392#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1135545#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1135546#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1136286#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1136287#L563 assume !(1 == ~t7_pc~0); 1136391#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1135225#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1135226#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1135667#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1135668#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1136390#L582 assume !(1 == ~t8_pc~0); 1136338#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1136339#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1136071#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1135630#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1135631#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1136065#L964 assume !(1 == ~M_E~0); 1136066#L964-2 assume !(1 == ~T1_E~0); 1135425#L969-1 assume !(1 == ~T2_E~0); 1135426#L974-1 assume !(1 == ~T3_E~0); 1136113#L979-1 assume !(1 == ~T4_E~0); 1136114#L984-1 assume !(1 == ~T5_E~0); 1135583#L989-1 assume !(1 == ~T6_E~0); 1135584#L994-1 assume !(1 == ~T7_E~0); 1136388#L999-1 assume !(1 == ~T8_E~0); 1136387#L1004-1 assume !(1 == ~E_M~0); 1136386#L1009-1 assume !(1 == ~E_1~0); 1136385#L1014-1 assume !(1 == ~E_2~0); 1136384#L1019-1 assume !(1 == ~E_3~0); 1136383#L1024-1 assume !(1 == ~E_4~0); 1135386#L1029-1 assume !(1 == ~E_5~0); 1135387#L1034-1 assume !(1 == ~E_6~0); 1135474#L1039-1 assume !(1 == ~E_7~0); 1136263#L1044-1 assume !(1 == ~E_8~0); 1135688#L1049-1 assume { :end_inline_reset_delta_events } true; 1135689#L1315-2 [2023-11-26 10:43:17,758 INFO L750 eck$LassoCheckResult]: Loop: 1135689#L1315-2 assume !false; 1143101#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1143099#L841-1 assume !false; 1143097#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1142623#L662 assume !(0 == ~m_st~0); 1142624#L666 assume !(0 == ~t1_st~0); 1142627#L670 assume !(0 == ~t2_st~0); 1142621#L674 assume !(0 == ~t3_st~0); 1142622#L678 assume !(0 == ~t4_st~0); 1142626#L682 assume !(0 == ~t5_st~0); 1142619#L686 assume !(0 == ~t6_st~0); 1142620#L690 assume !(0 == ~t7_st~0); 1142625#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1142628#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1143467#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1143465#L724 assume !(0 != eval_~tmp~0#1); 1143463#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1143461#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1143459#L866-3 assume !(0 == ~M_E~0); 1143457#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1143455#L871-3 assume !(0 == ~T2_E~0); 1143453#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1143451#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1143449#L886-3 assume !(0 == ~T5_E~0); 1143447#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1143445#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1143443#L901-3 assume !(0 == ~T8_E~0); 1143441#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1143439#L911-3 assume !(0 == ~E_1~0); 1143437#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1143435#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1143433#L926-3 assume !(0 == ~E_4~0); 1143431#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1143429#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1143427#L941-3 assume !(0 == ~E_7~0); 1143425#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1143423#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1143419#L430-30 assume !(1 == ~m_pc~0); 1143415#L430-32 is_master_triggered_~__retres1~0#1 := 0; 1143413#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1143411#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1143408#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 1143405#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1143403#L449-30 assume !(1 == ~t1_pc~0); 1143401#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1143399#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1143397#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1143395#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1143393#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1143391#L468-30 assume 1 == ~t2_pc~0; 1143387#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1143385#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1143383#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1143381#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 1143379#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1143377#L487-30 assume !(1 == ~t3_pc~0); 1143375#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1143373#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1143371#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1143369#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1143367#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1143365#L506-30 assume !(1 == ~t4_pc~0); 1143363#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1143360#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1143358#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1143356#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1143354#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1143352#L525-30 assume !(1 == ~t5_pc~0); 1143350#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1143348#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1143346#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1143344#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1143342#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1143340#L544-30 assume !(1 == ~t6_pc~0); 1143337#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1143334#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1143332#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1143330#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1143328#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1143326#L563-30 assume !(1 == ~t7_pc~0); 1142169#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1143324#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1143322#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1143320#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143318#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1143316#L582-30 assume !(1 == ~t8_pc~0); 1143314#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1143312#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1143310#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1143308#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1143306#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1143304#L964-3 assume !(1 == ~M_E~0); 1143302#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1143300#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1143298#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1143296#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1143294#L984-3 assume !(1 == ~T5_E~0); 1143292#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1143290#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1143288#L999-3 assume !(1 == ~T8_E~0); 1143286#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1143284#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1143282#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1143280#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1143277#L1024-3 assume !(1 == ~E_4~0); 1143276#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1143275#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1143274#L1039-3 assume !(1 == ~E_7~0); 1143273#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1143272#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1143270#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1143261#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1143260#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1143258#L1334 assume !(0 == start_simulation_~tmp~3#1); 1143257#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1143251#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1143243#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1143241#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1143239#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1143236#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1143234#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1143232#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1135689#L1315-2 [2023-11-26 10:43:17,759 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:17,759 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 3 times [2023-11-26 10:43:17,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:17,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310136307] [2023-11-26 10:43:17,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:17,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:17,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:17,773 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:17,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:17,814 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:17,815 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:17,815 INFO L85 PathProgramCache]: Analyzing trace with hash 1589576693, now seen corresponding path program 1 times [2023-11-26 10:43:17,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:17,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745181518] [2023-11-26 10:43:17,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:17,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:17,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:17,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:17,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:17,861 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745181518] [2023-11-26 10:43:17,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745181518] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:17,861 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:17,862 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:43:17,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015216449] [2023-11-26 10:43:17,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:17,862 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:43:17,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:17,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:43:17,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:43:17,863 INFO L87 Difference]: Start difference. First operand 82652 states and 114954 transitions. cyclomatic complexity: 32334 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:18,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:18,319 INFO L93 Difference]: Finished difference Result 156188 states and 214778 transitions. [2023-11-26 10:43:18,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156188 states and 214778 transitions. [2023-11-26 10:43:19,754 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 155136 [2023-11-26 10:43:20,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156188 states to 156188 states and 214778 transitions. [2023-11-26 10:43:20,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 156188 [2023-11-26 10:43:20,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 156188 [2023-11-26 10:43:20,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156188 states and 214778 transitions. [2023-11-26 10:43:20,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:20,252 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156188 states and 214778 transitions. [2023-11-26 10:43:20,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156188 states and 214778 transitions. [2023-11-26 10:43:22,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156188 to 149084. [2023-11-26 10:43:22,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149084 states, 149084 states have (on average 1.3775455447935392) internal successors, (205370), 149083 states have internal predecessors, (205370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:22,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149084 states to 149084 states and 205370 transitions. [2023-11-26 10:43:22,524 INFO L240 hiAutomatonCegarLoop]: Abstraction has 149084 states and 205370 transitions. [2023-11-26 10:43:22,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:43:22,524 INFO L428 stractBuchiCegarLoop]: Abstraction has 149084 states and 205370 transitions. [2023-11-26 10:43:22,525 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-26 10:43:22,525 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149084 states and 205370 transitions. [2023-11-26 10:43:23,741 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 148032 [2023-11-26 10:43:23,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:23,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:23,743 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:23,743 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:23,743 INFO L748 eck$LassoCheckResult]: Stem: 1374241#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1374242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1375098#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1375099#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1374570#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1374571#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1374114#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1374115#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1374203#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1375077#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1374081#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1374082#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1374524#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1374557#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1374208#L866 assume !(0 == ~M_E~0); 1374209#L866-2 assume !(0 == ~T1_E~0); 1374780#L871-1 assume !(0 == ~T2_E~0); 1374781#L876-1 assume !(0 == ~T3_E~0); 1375158#L881-1 assume !(0 == ~T4_E~0); 1374798#L886-1 assume !(0 == ~T5_E~0); 1374510#L891-1 assume !(0 == ~T6_E~0); 1374511#L896-1 assume !(0 == ~T7_E~0); 1374789#L901-1 assume !(0 == ~T8_E~0); 1374818#L906-1 assume !(0 == ~E_M~0); 1374819#L911-1 assume !(0 == ~E_1~0); 1374567#L916-1 assume !(0 == ~E_2~0); 1374568#L921-1 assume !(0 == ~E_3~0); 1374945#L926-1 assume !(0 == ~E_4~0); 1375094#L931-1 assume !(0 == ~E_5~0); 1375167#L936-1 assume !(0 == ~E_6~0); 1375182#L941-1 assume !(0 == ~E_7~0); 1374572#L946-1 assume !(0 == ~E_8~0); 1374573#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1375125#L430 assume !(1 == ~m_pc~0); 1374406#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1375046#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1375242#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1374703#L1073 assume !(0 != activate_threads_~tmp~1#1); 1374704#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1374917#L449 assume !(1 == ~t1_pc~0); 1374214#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1374215#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1374059#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1374060#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1374835#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1374638#L468 assume !(1 == ~t2_pc~0); 1374016#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1374015#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1374413#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1374409#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1374031#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1374032#L487 assume !(1 == ~t3_pc~0); 1374145#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1374120#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1374012#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1374013#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1374488#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1374489#L506 assume !(1 == ~t4_pc~0); 1374628#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1375164#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1374106#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1374107#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1374623#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1374624#L525 assume !(1 == ~t5_pc~0); 1374067#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1374068#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1375004#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1375005#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1374272#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1374273#L544 assume !(1 == ~t6_pc~0); 1374422#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1374423#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1374850#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1374048#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1374049#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1375059#L563 assume !(1 == ~t7_pc~0); 1374846#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1374847#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1375210#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1375211#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1374218#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1374219#L582 assume !(1 == ~t8_pc~0); 1374851#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1375153#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1375154#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1375250#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1374352#L1137-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1374353#L964 assume !(1 == ~M_E~0); 1375149#L964-2 assume !(1 == ~T1_E~0); 1375150#L969-1 assume !(1 == ~T2_E~0); 1375103#L974-1 assume !(1 == ~T3_E~0); 1375104#L979-1 assume !(1 == ~T4_E~0); 1375249#L984-1 assume !(1 == ~T5_E~0); 1375248#L989-1 assume !(1 == ~T6_E~0); 1374793#L994-1 assume !(1 == ~T7_E~0); 1374309#L999-1 assume !(1 == ~T8_E~0); 1374310#L1004-1 assume !(1 == ~E_M~0); 1374930#L1009-1 assume !(1 == ~E_1~0); 1375245#L1014-1 assume !(1 == ~E_2~0); 1375244#L1019-1 assume !(1 == ~E_3~0); 1375243#L1024-1 assume !(1 == ~E_4~0); 1374238#L1029-1 assume !(1 == ~E_5~0); 1374239#L1034-1 assume !(1 == ~E_6~0); 1374321#L1039-1 assume !(1 == ~E_7~0); 1375116#L1044-1 assume !(1 == ~E_8~0); 1374535#L1049-1 assume { :end_inline_reset_delta_events } true; 1374536#L1315-2 [2023-11-26 10:43:23,744 INFO L750 eck$LassoCheckResult]: Loop: 1374536#L1315-2 assume !false; 1384919#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1384917#L841-1 assume !false; 1384915#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1384912#L662 assume !(0 == ~m_st~0); 1384913#L666 assume !(0 == ~t1_st~0); 1387634#L670 assume !(0 == ~t2_st~0); 1387631#L674 assume !(0 == ~t3_st~0); 1387628#L678 assume !(0 == ~t4_st~0); 1387625#L682 assume !(0 == ~t5_st~0); 1387621#L686 assume !(0 == ~t6_st~0); 1387617#L690 assume !(0 == ~t7_st~0); 1387611#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1387606#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1387602#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1387598#L724 assume !(0 != eval_~tmp~0#1); 1387594#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1387588#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1387583#L866-3 assume !(0 == ~M_E~0); 1387578#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1387574#L871-3 assume !(0 == ~T2_E~0); 1387570#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1387565#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1387561#L886-3 assume !(0 == ~T5_E~0); 1387557#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1387553#L896-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1387549#L901-3 assume !(0 == ~T8_E~0); 1387545#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1387540#L911-3 assume !(0 == ~E_1~0); 1387534#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1387528#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1387524#L926-3 assume !(0 == ~E_4~0); 1387520#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1387516#L936-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1387512#L941-3 assume !(0 == ~E_7~0); 1387508#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1387504#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1387500#L430-30 assume 1 == ~m_pc~0; 1387495#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1387489#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1387485#is_master_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1387480#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1387475#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1387470#L449-30 assume !(1 == ~t1_pc~0); 1387466#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1387462#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1387458#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1387454#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1387451#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1387448#L468-30 assume !(1 == ~t2_pc~0); 1387444#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1387439#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1387434#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1387430#L1089-30 assume !(0 != activate_threads_~tmp___1~0#1); 1387426#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1387422#L487-30 assume !(1 == ~t3_pc~0); 1387418#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1387414#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1387411#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1387406#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1387399#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1387379#L506-30 assume 1 == ~t4_pc~0; 1387378#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1385048#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1385046#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1385044#L1105-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1385041#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1385039#L525-30 assume !(1 == ~t5_pc~0); 1385037#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1385035#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1385033#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1385031#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1385029#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1385027#L544-30 assume 1 == ~t6_pc~0; 1385025#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1385022#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1385020#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1385018#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1385016#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1385014#L563-30 assume !(1 == ~t7_pc~0); 1384686#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1385011#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1385009#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1385007#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1385005#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1385003#L582-30 assume !(1 == ~t8_pc~0); 1385001#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1384999#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1384997#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1384995#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1384993#L1137-32 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1384991#L964-3 assume !(1 == ~M_E~0); 1384989#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1384987#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1384985#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1384983#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1384981#L984-3 assume !(1 == ~T5_E~0); 1384979#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1384977#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1384975#L999-3 assume !(1 == ~T8_E~0); 1384973#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1384971#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1384969#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1384968#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1384964#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1384961#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1384959#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1384956#L1039-3 assume !(1 == ~E_7~0); 1384955#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1384954#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1384952#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1384951#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1384950#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1384948#L1334 assume !(0 == start_simulation_~tmp~3#1); 1384946#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1384943#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1384941#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1384940#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1384938#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1384935#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1384933#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1384931#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1374536#L1315-2 [2023-11-26 10:43:23,745 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:23,745 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 4 times [2023-11-26 10:43:23,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:23,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526654404] [2023-11-26 10:43:23,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:23,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:23,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:23,773 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:23,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:23,830 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:23,830 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:23,831 INFO L85 PathProgramCache]: Analyzing trace with hash 1199031347, now seen corresponding path program 1 times [2023-11-26 10:43:23,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:23,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140723414] [2023-11-26 10:43:23,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:23,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:23,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:23,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:23,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:23,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140723414] [2023-11-26 10:43:23,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140723414] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:23,941 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:23,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:43:23,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899730741] [2023-11-26 10:43:23,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:23,942 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:43:23,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:23,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:43:23,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:43:23,943 INFO L87 Difference]: Start difference. First operand 149084 states and 205370 transitions. cyclomatic complexity: 56318 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)