./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:49:36,478 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:49:36,610 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:49:36,620 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:49:36,622 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:49:36,667 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:49:36,668 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:49:36,669 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:49:36,671 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:49:36,676 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:49:36,678 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:49:36,678 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:49:36,679 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:49:36,681 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:49:36,682 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:49:36,683 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:49:36,683 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:49:36,684 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:49:36,684 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:49:36,685 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:49:36,685 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:49:36,686 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:49:36,687 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:49:36,687 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:49:36,688 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:49:36,688 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:49:36,689 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:49:36,689 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:49:36,690 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:49:36,690 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:49:36,692 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:49:36,692 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:49:36,692 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:49:36,693 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:49:36,693 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:49:36,694 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:49:36,694 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:49:36,695 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:49:36,695 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2023-11-26 11:49:37,063 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:49:37,101 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:49:37,105 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:49:37,107 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:49:37,108 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:49:37,109 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/transmitter.02.cil.c [2023-11-26 11:49:40,336 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:49:40,603 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:49:40,608 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/sv-benchmarks/c/systemc/transmitter.02.cil.c [2023-11-26 11:49:40,626 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/data/37537cccd/819251cb478549469ac024e6626b2c69/FLAG3bc111c26 [2023-11-26 11:49:40,645 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/data/37537cccd/819251cb478549469ac024e6626b2c69 [2023-11-26 11:49:40,652 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:49:40,656 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:49:40,659 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:49:40,659 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:49:40,665 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:49:40,666 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:49:40" (1/1) ... [2023-11-26 11:49:40,667 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5bdf16ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:40, skipping insertion in model container [2023-11-26 11:49:40,667 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:49:40" (1/1) ... [2023-11-26 11:49:40,725 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:49:40,951 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:49:40,965 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:49:41,007 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:49:41,032 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:49:41,036 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41 WrapperNode [2023-11-26 11:49:41,037 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:49:41,038 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:49:41,039 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:49:41,039 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:49:41,048 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,057 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,098 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 45, statements flattened = 536 [2023-11-26 11:49:41,099 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:49:41,099 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:49:41,105 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:49:41,106 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:49:41,115 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,116 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,120 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,137 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 11:49:41,137 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,138 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,149 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,165 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,168 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,171 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,193 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:49:41,194 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:49:41,194 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:49:41,194 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:49:41,195 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (1/1) ... [2023-11-26 11:49:41,203 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:41,217 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:41,238 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:41,241 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:49:41,283 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:49:41,284 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:49:41,284 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:49:41,284 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:49:41,400 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:49:41,420 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:49:42,038 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:49:42,054 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:49:42,054 INFO L309 CfgBuilder]: Removed 6 assume(true) statements. [2023-11-26 11:49:42,056 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:49:42 BoogieIcfgContainer [2023-11-26 11:49:42,056 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:49:42,057 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:49:42,058 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:49:42,062 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:49:42,063 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:49:42,063 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:49:40" (1/3) ... [2023-11-26 11:49:42,064 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6830d5fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:49:42, skipping insertion in model container [2023-11-26 11:49:42,073 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:49:42,073 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:49:41" (2/3) ... [2023-11-26 11:49:42,074 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6830d5fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:49:42, skipping insertion in model container [2023-11-26 11:49:42,074 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:49:42,074 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:49:42" (3/3) ... [2023-11-26 11:49:42,076 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2023-11-26 11:49:42,138 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:49:42,139 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:49:42,139 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:49:42,139 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:49:42,139 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:49:42,140 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:49:42,140 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:49:42,140 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:49:42,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:42,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2023-11-26 11:49:42,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:42,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:42,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:42,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:42,190 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:49:42,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:42,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2023-11-26 11:49:42,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:42,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:42,219 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:42,220 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:42,229 INFO L748 eck$LassoCheckResult]: Stem: 147#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 158#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 205#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 182#L221true assume !(1 == ~m_i~0);~m_st~0 := 2; 60#L221-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 42#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 162#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33#L334true assume !(0 == ~M_E~0); 169#L334-2true assume !(0 == ~T1_E~0); 113#L339-1true assume !(0 == ~T2_E~0); 108#L344-1true assume 0 == ~E_1~0;~E_1~0 := 1; 143#L349-1true assume !(0 == ~E_2~0); 41#L354-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117#L156true assume !(1 == ~m_pc~0); 154#L156-2true is_master_triggered_~__retres1~0#1 := 0; 136#L167true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128#is_master_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 78#L405true assume !(0 != activate_threads_~tmp~1#1); 63#L405-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126#L175true assume 1 == ~t1_pc~0; 161#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64#L186true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 115#L413true assume !(0 != activate_threads_~tmp___0~0#1); 185#L413-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187#L194true assume !(1 == ~t2_pc~0); 203#L194-2true is_transmit2_triggered_~__retres1~2#1 := 0; 70#L205true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27#L421true assume !(0 != activate_threads_~tmp___1~0#1); 85#L421-2true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12#L367true assume !(1 == ~M_E~0); 186#L367-2true assume !(1 == ~T1_E~0); 130#L372-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 132#L377-1true assume !(1 == ~E_1~0); 25#L382-1true assume !(1 == ~E_2~0); 80#L387-1true assume { :end_inline_reset_delta_events } true; 107#L528-2true [2023-11-26 11:49:42,231 INFO L750 eck$LassoCheckResult]: Loop: 107#L528-2true assume !false; 88#L529true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17#L309-1true assume false; 82#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 207#L334-3true assume 0 == ~M_E~0;~M_E~0 := 1; 159#L334-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 116#L339-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 183#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 76#L349-3true assume !(0 == ~E_2~0); 32#L354-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101#L156-9true assume !(1 == ~m_pc~0); 4#L156-11true is_master_triggered_~__retres1~0#1 := 0; 57#L167-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135#is_master_triggered_returnLabel#4true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 118#L405-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21#L405-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192#L175-9true assume !(1 == ~t1_pc~0); 141#L175-11true is_transmit1_triggered_~__retres1~1#1 := 0; 14#L186-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201#is_transmit1_triggered_returnLabel#4true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 153#L413-9true assume !(0 != activate_threads_~tmp___0~0#1); 146#L413-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190#L194-9true assume !(1 == ~t2_pc~0); 28#L194-11true is_transmit2_triggered_~__retres1~2#1 := 0; 196#L205-3true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5#is_transmit2_triggered_returnLabel#4true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 110#L421-9true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 144#L421-11true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54#L367-3true assume 1 == ~M_E~0;~M_E~0 := 2; 7#L367-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 34#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 18#L377-3true assume !(1 == ~E_1~0); 30#L382-3true assume 1 == ~E_2~0;~E_2~0 := 2; 111#L387-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 145#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 180#L261-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 188#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 152#L547true assume !(0 == start_simulation_~tmp~3#1); 166#L547-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 149#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 52#L261-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 37#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 40#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49#L509true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 20#L560true assume !(0 != start_simulation_~tmp___0~1#1); 107#L528-2true [2023-11-26 11:49:42,237 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:42,238 INFO L85 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2023-11-26 11:49:42,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:42,249 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613606386] [2023-11-26 11:49:42,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:42,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:42,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:42,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:42,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:42,580 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613606386] [2023-11-26 11:49:42,581 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613606386] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:42,582 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:42,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:42,584 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1333997697] [2023-11-26 11:49:42,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:42,590 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:49:42,592 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:42,593 INFO L85 PathProgramCache]: Analyzing trace with hash -294698413, now seen corresponding path program 1 times [2023-11-26 11:49:42,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:42,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782197205] [2023-11-26 11:49:42,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:42,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:42,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:42,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:42,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:42,665 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782197205] [2023-11-26 11:49:42,665 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1782197205] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:42,666 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:42,666 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:49:42,666 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101750975] [2023-11-26 11:49:42,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:42,668 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:49:42,669 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:42,704 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:49:42,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:49:42,708 INFO L87 Difference]: Start difference. First operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:42,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:42,747 INFO L93 Difference]: Finished difference Result 207 states and 302 transitions. [2023-11-26 11:49:42,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 207 states and 302 transitions. [2023-11-26 11:49:42,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-26 11:49:42,761 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 207 states to 201 states and 296 transitions. [2023-11-26 11:49:42,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2023-11-26 11:49:42,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2023-11-26 11:49:42,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 296 transitions. [2023-11-26 11:49:42,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:49:42,767 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2023-11-26 11:49:42,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 296 transitions. [2023-11-26 11:49:42,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2023-11-26 11:49:42,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.472636815920398) internal successors, (296), 200 states have internal predecessors, (296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:42,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 296 transitions. [2023-11-26 11:49:42,815 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2023-11-26 11:49:42,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:49:42,821 INFO L428 stractBuchiCegarLoop]: Abstraction has 201 states and 296 transitions. [2023-11-26 11:49:42,821 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:49:42,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 296 transitions. [2023-11-26 11:49:42,825 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-26 11:49:42,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:42,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:42,828 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:42,828 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:42,829 INFO L748 eck$LassoCheckResult]: Stem: 608#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 617#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 616#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 530#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 505#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 506#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 489#L334 assume !(0 == ~M_E~0); 490#L334-2 assume !(0 == ~T1_E~0); 585#L339-1 assume !(0 == ~T2_E~0); 579#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 580#L349-1 assume !(0 == ~E_2~0); 503#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 504#L156 assume !(1 == ~m_pc~0); 436#L156-2 is_master_triggered_~__retres1~0#1 := 0; 435#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 597#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 552#L405 assume !(0 != activate_threads_~tmp~1#1); 534#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 535#L175 assume 1 == ~t1_pc~0; 594#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 536#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 500#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 501#L413 assume !(0 != activate_threads_~tmp___0~0#1); 587#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 624#L194 assume !(1 == ~t2_pc~0); 578#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 546#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 478#L421 assume !(0 != activate_threads_~tmp___1~0#1); 479#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 448#L367 assume !(1 == ~M_E~0); 449#L367-2 assume !(1 == ~T1_E~0); 598#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 599#L377-1 assume !(1 == ~E_1~0); 475#L382-1 assume !(1 == ~E_2~0); 476#L387-1 assume { :end_inline_reset_delta_events } true; 465#L528-2 [2023-11-26 11:49:42,829 INFO L750 eck$LassoCheckResult]: Loop: 465#L528-2 assume !false; 559#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 458#L309-1 assume !false; 459#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 439#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 440#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 447#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 425#L276 assume !(0 != eval_~tmp~0#1); 427#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 584#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 618#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 588#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 589#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 551#L349-3 assume !(0 == ~E_2~0); 487#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488#L156-9 assume 1 == ~m_pc~0; 573#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 431#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 527#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 590#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 466#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 467#L175-9 assume 1 == ~t1_pc~0; 512#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 452#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 453#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 614#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 606#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607#L194-9 assume !(1 == ~t2_pc~0); 480#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 481#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 432#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 433#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 582#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 523#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 437#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 438#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 460#L377-3 assume !(1 == ~E_1~0); 461#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 484#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 583#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 492#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 613#L547 assume !(0 == start_simulation_~tmp~3#1); 600#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 610#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 521#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 495#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 496#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 502#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 517#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 464#L560 assume !(0 != start_simulation_~tmp___0~1#1); 465#L528-2 [2023-11-26 11:49:42,830 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:42,830 INFO L85 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2023-11-26 11:49:42,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:42,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76473982] [2023-11-26 11:49:42,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:42,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:42,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:42,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:42,890 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:42,890 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [76473982] [2023-11-26 11:49:42,891 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [76473982] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:42,891 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:42,891 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:42,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505942622] [2023-11-26 11:49:42,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:42,892 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:49:42,893 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:42,893 INFO L85 PathProgramCache]: Analyzing trace with hash -724130786, now seen corresponding path program 1 times [2023-11-26 11:49:42,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:42,894 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38947531] [2023-11-26 11:49:42,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:42,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:42,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:43,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:43,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:43,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38947531] [2023-11-26 11:49:43,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [38947531] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:43,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:43,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:43,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1068190563] [2023-11-26 11:49:43,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:43,059 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:49:43,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:43,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:49:43,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:49:43,062 INFO L87 Difference]: Start difference. First operand 201 states and 296 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:43,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:43,099 INFO L93 Difference]: Finished difference Result 201 states and 295 transitions. [2023-11-26 11:49:43,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201 states and 295 transitions. [2023-11-26 11:49:43,102 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-26 11:49:43,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201 states to 201 states and 295 transitions. [2023-11-26 11:49:43,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2023-11-26 11:49:43,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2023-11-26 11:49:43,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 295 transitions. [2023-11-26 11:49:43,113 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:49:43,115 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2023-11-26 11:49:43,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 295 transitions. [2023-11-26 11:49:43,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2023-11-26 11:49:43,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.4676616915422886) internal successors, (295), 200 states have internal predecessors, (295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:43,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 295 transitions. [2023-11-26 11:49:43,127 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2023-11-26 11:49:43,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:49:43,129 INFO L428 stractBuchiCegarLoop]: Abstraction has 201 states and 295 transitions. [2023-11-26 11:49:43,129 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:49:43,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 295 transitions. [2023-11-26 11:49:43,131 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-26 11:49:43,131 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:43,131 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:43,133 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:43,134 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:43,134 INFO L748 eck$LassoCheckResult]: Stem: 1017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1025#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 939#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 914#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 915#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 898#L334 assume !(0 == ~M_E~0); 899#L334-2 assume !(0 == ~T1_E~0); 994#L339-1 assume !(0 == ~T2_E~0); 988#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 989#L349-1 assume !(0 == ~E_2~0); 912#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 913#L156 assume !(1 == ~m_pc~0); 845#L156-2 is_master_triggered_~__retres1~0#1 := 0; 844#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 961#L405 assume !(0 != activate_threads_~tmp~1#1); 943#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 944#L175 assume 1 == ~t1_pc~0; 1003#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 945#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 909#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 910#L413 assume !(0 != activate_threads_~tmp___0~0#1); 996#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1033#L194 assume !(1 == ~t2_pc~0); 987#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 955#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 887#L421 assume !(0 != activate_threads_~tmp___1~0#1); 888#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 857#L367 assume !(1 == ~M_E~0); 858#L367-2 assume !(1 == ~T1_E~0); 1007#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1008#L377-1 assume !(1 == ~E_1~0); 884#L382-1 assume !(1 == ~E_2~0); 885#L387-1 assume { :end_inline_reset_delta_events } true; 874#L528-2 [2023-11-26 11:49:43,135 INFO L750 eck$LassoCheckResult]: Loop: 874#L528-2 assume !false; 968#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 867#L309-1 assume !false; 868#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 848#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 849#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 856#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 834#L276 assume !(0 != eval_~tmp~0#1); 836#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 964#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 993#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1027#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 997#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 998#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 960#L349-3 assume !(0 == ~E_2~0); 896#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 897#L156-9 assume 1 == ~m_pc~0; 982#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 840#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 936#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 999#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 875#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 876#L175-9 assume 1 == ~t1_pc~0; 921#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 861#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 862#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1023#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 1015#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1016#L194-9 assume 1 == ~t2_pc~0; 963#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 890#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 841#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 842#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 991#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 932#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 846#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 847#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 869#L377-3 assume !(1 == ~E_1~0); 870#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 893#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 992#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 901#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1032#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1022#L547 assume !(0 == start_simulation_~tmp~3#1); 1009#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1019#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 930#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 904#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 905#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 911#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 926#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 873#L560 assume !(0 != start_simulation_~tmp___0~1#1); 874#L528-2 [2023-11-26 11:49:43,135 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:43,136 INFO L85 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2023-11-26 11:49:43,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:43,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661776891] [2023-11-26 11:49:43,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:43,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:43,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:43,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:43,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:43,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661776891] [2023-11-26 11:49:43,231 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661776891] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:43,231 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:43,231 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:43,231 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103140242] [2023-11-26 11:49:43,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:43,232 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:49:43,233 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:43,233 INFO L85 PathProgramCache]: Analyzing trace with hash 866264191, now seen corresponding path program 1 times [2023-11-26 11:49:43,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:43,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511155623] [2023-11-26 11:49:43,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:43,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:43,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:43,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:43,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:43,289 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511155623] [2023-11-26 11:49:43,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511155623] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:43,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:43,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:43,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319777988] [2023-11-26 11:49:43,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:43,291 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:49:43,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:43,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:49:43,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:49:43,292 INFO L87 Difference]: Start difference. First operand 201 states and 295 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:43,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:43,418 INFO L93 Difference]: Finished difference Result 342 states and 498 transitions. [2023-11-26 11:49:43,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 498 transitions. [2023-11-26 11:49:43,422 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2023-11-26 11:49:43,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 498 transitions. [2023-11-26 11:49:43,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 342 [2023-11-26 11:49:43,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 342 [2023-11-26 11:49:43,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 498 transitions. [2023-11-26 11:49:43,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:49:43,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 498 transitions. [2023-11-26 11:49:43,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 498 transitions. [2023-11-26 11:49:43,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 340. [2023-11-26 11:49:43,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 340 states, 340 states have (on average 1.4588235294117646) internal successors, (496), 339 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:43,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 496 transitions. [2023-11-26 11:49:43,462 INFO L240 hiAutomatonCegarLoop]: Abstraction has 340 states and 496 transitions. [2023-11-26 11:49:43,468 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:49:43,470 INFO L428 stractBuchiCegarLoop]: Abstraction has 340 states and 496 transitions. [2023-11-26 11:49:43,471 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:49:43,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 340 states and 496 transitions. [2023-11-26 11:49:43,474 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2023-11-26 11:49:43,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:43,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:43,479 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:43,479 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:43,480 INFO L748 eck$LassoCheckResult]: Stem: 1591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1602#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1599#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1600#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1501#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1472#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1473#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1454#L334 assume !(0 == ~M_E~0); 1455#L334-2 assume !(0 == ~T1_E~0); 1561#L339-1 assume !(0 == ~T2_E~0); 1554#L344-1 assume !(0 == ~E_1~0); 1555#L349-1 assume !(0 == ~E_2~0); 1470#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1471#L156 assume !(1 == ~m_pc~0); 1398#L156-2 is_master_triggered_~__retres1~0#1 := 0; 1397#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1578#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1525#L405 assume !(0 != activate_threads_~tmp~1#1); 1505#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1506#L175 assume 1 == ~t1_pc~0; 1575#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1507#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1466#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1467#L413 assume !(0 != activate_threads_~tmp___0~0#1); 1563#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1612#L194 assume !(1 == ~t2_pc~0); 1552#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1517#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1442#L421 assume !(0 != activate_threads_~tmp___1~0#1); 1443#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1411#L367 assume !(1 == ~M_E~0); 1412#L367-2 assume !(1 == ~T1_E~0); 1579#L372-1 assume !(1 == ~T2_E~0); 1580#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1439#L382-1 assume !(1 == ~E_2~0); 1440#L387-1 assume { :end_inline_reset_delta_events } true; 1429#L528-2 [2023-11-26 11:49:43,480 INFO L750 eck$LassoCheckResult]: Loop: 1429#L528-2 assume !false; 1553#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1421#L309-1 assume !false; 1422#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1401#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1402#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1409#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1410#L276 assume !(0 != eval_~tmp~0#1); 1528#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1529#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1619#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1603#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1604#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1620#L344-3 assume !(0 == ~E_1~0); 1695#L349-3 assume !(0 == ~E_2~0); 1694#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1693#L156-9 assume !(1 == ~m_pc~0); 1691#L156-11 is_master_triggered_~__retres1~0#1 := 0; 1690#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1689#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1688#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1687#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1686#L175-9 assume 1 == ~t1_pc~0; 1481#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1415#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1416#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1598#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 1589#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1590#L194-9 assume 1 == ~t2_pc~0; 1613#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1680#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1679#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1678#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1677#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1676#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1675#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1674#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L377-3 assume !(1 == ~E_1~0); 1425#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1673#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1672#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1669#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1668#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1666#L547 assume !(0 == start_simulation_~tmp~3#1); 1664#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1593#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1595#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1462#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1486#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1487#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1428#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1429#L528-2 [2023-11-26 11:49:43,481 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:43,481 INFO L85 PathProgramCache]: Analyzing trace with hash -1288865440, now seen corresponding path program 1 times [2023-11-26 11:49:43,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:43,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581672547] [2023-11-26 11:49:43,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:43,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:43,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:43,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:43,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:43,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581672547] [2023-11-26 11:49:43,572 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581672547] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:43,572 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:43,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:49:43,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317521984] [2023-11-26 11:49:43,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:43,574 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:49:43,575 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:43,575 INFO L85 PathProgramCache]: Analyzing trace with hash 1551047712, now seen corresponding path program 1 times [2023-11-26 11:49:43,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:43,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260097203] [2023-11-26 11:49:43,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:43,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:43,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:43,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:43,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:43,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1260097203] [2023-11-26 11:49:43,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1260097203] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:43,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:43,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:43,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069877145] [2023-11-26 11:49:43,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:43,646 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:49:43,647 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:43,647 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:49:43,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:49:43,647 INFO L87 Difference]: Start difference. First operand 340 states and 496 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:43,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:43,692 INFO L93 Difference]: Finished difference Result 582 states and 842 transitions. [2023-11-26 11:49:43,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 582 states and 842 transitions. [2023-11-26 11:49:43,698 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 535 [2023-11-26 11:49:43,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 582 states to 582 states and 842 transitions. [2023-11-26 11:49:43,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 582 [2023-11-26 11:49:43,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 582 [2023-11-26 11:49:43,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 582 states and 842 transitions. [2023-11-26 11:49:43,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:49:43,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 582 states and 842 transitions. [2023-11-26 11:49:43,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states and 842 transitions. [2023-11-26 11:49:43,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 578. [2023-11-26 11:49:43,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 578 states, 578 states have (on average 1.4498269896193772) internal successors, (838), 577 states have internal predecessors, (838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:43,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 578 states to 578 states and 838 transitions. [2023-11-26 11:49:43,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 578 states and 838 transitions. [2023-11-26 11:49:43,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:49:43,732 INFO L428 stractBuchiCegarLoop]: Abstraction has 578 states and 838 transitions. [2023-11-26 11:49:43,733 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:49:43,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 578 states and 838 transitions. [2023-11-26 11:49:43,737 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2023-11-26 11:49:43,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:43,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:43,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:43,743 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:43,744 INFO L748 eck$LassoCheckResult]: Stem: 2518#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2531#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2526#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2527#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2428#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2400#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2401#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2382#L334 assume !(0 == ~M_E~0); 2383#L334-2 assume !(0 == ~T1_E~0); 2490#L339-1 assume !(0 == ~T2_E~0); 2483#L344-1 assume !(0 == ~E_1~0); 2484#L349-1 assume !(0 == ~E_2~0); 2398#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2399#L156 assume !(1 == ~m_pc~0); 2329#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2328#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2501#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2453#L405 assume !(0 != activate_threads_~tmp~1#1); 2436#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2437#L175 assume !(1 == ~t1_pc~0); 2441#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2438#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2394#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2395#L413 assume !(0 != activate_threads_~tmp___0~0#1); 2492#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2545#L194 assume !(1 == ~t2_pc~0); 2482#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2448#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2449#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2370#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2371#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2339#L367 assume !(1 == ~M_E~0); 2340#L367-2 assume !(1 == ~T1_E~0); 2502#L372-1 assume !(1 == ~T2_E~0); 2503#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2506#L382-1 assume !(1 == ~E_2~0); 2825#L387-1 assume { :end_inline_reset_delta_events } true; 2823#L528-2 [2023-11-26 11:49:43,744 INFO L750 eck$LassoCheckResult]: Loop: 2823#L528-2 assume !false; 2785#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2783#L309-1 assume !false; 2782#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2780#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2778#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2777#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2316#L276 assume !(0 != eval_~tmp~0#1); 2318#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2456#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2775#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2774#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2772#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2773#L344-3 assume !(0 == ~E_1~0); 2893#L349-3 assume !(0 == ~E_2~0); 2892#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2891#L156-9 assume !(1 == ~m_pc~0); 2889#L156-11 is_master_triggered_~__retres1~0#1 := 0; 2888#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2887#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2886#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2885#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2884#L175-9 assume !(1 == ~t1_pc~0); 2883#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2882#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2881#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2880#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 2879#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2878#L194-9 assume 1 == ~t2_pc~0; 2876#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2875#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2874#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2873#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2872#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2871#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2870#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2869#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2384#L377-3 assume !(1 == ~E_1~0); 2353#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2868#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2514#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2386#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2639#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2640#L547 assume !(0 == start_simulation_~tmp~3#1); 2835#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2834#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2831#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2830#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 2829#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2828#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2827#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2826#L560 assume !(0 != start_simulation_~tmp___0~1#1); 2823#L528-2 [2023-11-26 11:49:43,745 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:43,745 INFO L85 PathProgramCache]: Analyzing trace with hash -148513729, now seen corresponding path program 1 times [2023-11-26 11:49:43,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:43,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102995840] [2023-11-26 11:49:43,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:43,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:43,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:43,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:43,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:43,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102995840] [2023-11-26 11:49:43,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102995840] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:43,838 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:43,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:43,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1486345116] [2023-11-26 11:49:43,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:43,839 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:49:43,840 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:43,840 INFO L85 PathProgramCache]: Analyzing trace with hash 1493903487, now seen corresponding path program 1 times [2023-11-26 11:49:43,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:43,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709744105] [2023-11-26 11:49:43,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:43,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:43,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:43,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:43,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:43,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709744105] [2023-11-26 11:49:43,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709744105] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:43,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:43,896 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:49:43,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1889986359] [2023-11-26 11:49:43,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:43,897 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:49:43,897 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:43,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:49:43,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:49:43,898 INFO L87 Difference]: Start difference. First operand 578 states and 838 transitions. cyclomatic complexity: 264 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:43,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:43,987 INFO L93 Difference]: Finished difference Result 592 states and 834 transitions. [2023-11-26 11:49:43,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 592 states and 834 transitions. [2023-11-26 11:49:43,993 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 544 [2023-11-26 11:49:44,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 592 states to 592 states and 834 transitions. [2023-11-26 11:49:44,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 592 [2023-11-26 11:49:44,020 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 592 [2023-11-26 11:49:44,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 592 states and 834 transitions. [2023-11-26 11:49:44,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:49:44,021 INFO L218 hiAutomatonCegarLoop]: Abstraction has 592 states and 834 transitions. [2023-11-26 11:49:44,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states and 834 transitions. [2023-11-26 11:49:44,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 575. [2023-11-26 11:49:44,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 575 states, 575 states have (on average 1.413913043478261) internal successors, (813), 574 states have internal predecessors, (813), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:44,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 575 states to 575 states and 813 transitions. [2023-11-26 11:49:44,035 INFO L240 hiAutomatonCegarLoop]: Abstraction has 575 states and 813 transitions. [2023-11-26 11:49:44,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:49:44,037 INFO L428 stractBuchiCegarLoop]: Abstraction has 575 states and 813 transitions. [2023-11-26 11:49:44,037 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:49:44,037 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 575 states and 813 transitions. [2023-11-26 11:49:44,041 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2023-11-26 11:49:44,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:44,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:44,042 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:44,042 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:44,042 INFO L748 eck$LassoCheckResult]: Stem: 3706#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3719#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3715#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3716#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 3610#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3579#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3580#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3563#L334 assume !(0 == ~M_E~0); 3564#L334-2 assume !(0 == ~T1_E~0); 3673#L339-1 assume !(0 == ~T2_E~0); 3666#L344-1 assume !(0 == ~E_1~0); 3667#L349-1 assume !(0 == ~E_2~0); 3577#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3578#L156 assume !(1 == ~m_pc~0); 3511#L156-2 is_master_triggered_~__retres1~0#1 := 0; 3510#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3687#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3633#L405 assume !(0 != activate_threads_~tmp~1#1); 3617#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3618#L175 assume !(1 == ~t1_pc~0); 3622#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3619#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3574#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3575#L413 assume !(0 != activate_threads_~tmp___0~0#1); 3677#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3735#L194 assume !(1 == ~t2_pc~0); 3665#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3627#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3628#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3551#L421 assume !(0 != activate_threads_~tmp___1~0#1); 3552#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3522#L367 assume !(1 == ~M_E~0); 3523#L367-2 assume !(1 == ~T1_E~0); 3688#L372-1 assume !(1 == ~T2_E~0); 3689#L377-1 assume !(1 == ~E_1~0); 3548#L382-1 assume !(1 == ~E_2~0); 3549#L387-1 assume { :end_inline_reset_delta_events } true; 3635#L528-2 [2023-11-26 11:49:44,043 INFO L750 eck$LassoCheckResult]: Loop: 3635#L528-2 assume !false; 3819#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3813#L309-1 assume !false; 3792#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3793#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3684#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3519#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3498#L276 assume !(0 != eval_~tmp~0#1); 3500#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3806#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3804#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3802#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3799#L339-3 assume !(0 == ~T2_E~0); 3800#L344-3 assume !(0 == ~E_1~0); 3790#L349-3 assume !(0 == ~E_2~0); 3791#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3959#L156-9 assume !(1 == ~m_pc~0); 3957#L156-11 is_master_triggered_~__retres1~0#1 := 0; 3605#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3606#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3678#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3679#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3739#L175-9 assume !(1 == ~t1_pc~0); 3740#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 3955#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3949#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3946#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 3942#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3939#L194-9 assume 1 == ~t2_pc~0; 3934#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3930#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3926#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3922#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3917#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3912#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3908#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3904#L372-3 assume !(1 == ~T2_E~0); 3899#L377-3 assume !(1 == ~E_1~0); 3895#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3891#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3887#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3881#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3877#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 3872#L547 assume !(0 == start_simulation_~tmp~3#1); 3866#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3863#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3857#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3852#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 3841#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3837#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3835#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3833#L560 assume !(0 != start_simulation_~tmp___0~1#1); 3635#L528-2 [2023-11-26 11:49:44,043 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:44,043 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2023-11-26 11:49:44,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:44,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958836451] [2023-11-26 11:49:44,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:44,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:44,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:44,052 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:44,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:44,082 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:44,082 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:44,082 INFO L85 PathProgramCache]: Analyzing trace with hash -898972165, now seen corresponding path program 1 times [2023-11-26 11:49:44,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:44,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335546673] [2023-11-26 11:49:44,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:44,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:44,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:44,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:44,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:44,143 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335546673] [2023-11-26 11:49:44,143 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335546673] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:44,143 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:44,143 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:49:44,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096108945] [2023-11-26 11:49:44,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:44,144 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:49:44,144 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:44,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:49:44,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:49:44,145 INFO L87 Difference]: Start difference. First operand 575 states and 813 transitions. cyclomatic complexity: 242 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:44,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:44,240 INFO L93 Difference]: Finished difference Result 972 states and 1348 transitions. [2023-11-26 11:49:44,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 972 states and 1348 transitions. [2023-11-26 11:49:44,249 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 924 [2023-11-26 11:49:44,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 972 states to 972 states and 1348 transitions. [2023-11-26 11:49:44,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 972 [2023-11-26 11:49:44,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 972 [2023-11-26 11:49:44,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 972 states and 1348 transitions. [2023-11-26 11:49:44,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:49:44,260 INFO L218 hiAutomatonCegarLoop]: Abstraction has 972 states and 1348 transitions. [2023-11-26 11:49:44,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 972 states and 1348 transitions. [2023-11-26 11:49:44,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 972 to 587. [2023-11-26 11:49:44,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 587 states, 587 states have (on average 1.405451448040886) internal successors, (825), 586 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:44,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 587 states and 825 transitions. [2023-11-26 11:49:44,276 INFO L240 hiAutomatonCegarLoop]: Abstraction has 587 states and 825 transitions. [2023-11-26 11:49:44,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 11:49:44,278 INFO L428 stractBuchiCegarLoop]: Abstraction has 587 states and 825 transitions. [2023-11-26 11:49:44,278 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:49:44,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 587 states and 825 transitions. [2023-11-26 11:49:44,282 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 543 [2023-11-26 11:49:44,282 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:44,282 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:44,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:44,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:44,283 INFO L748 eck$LassoCheckResult]: Stem: 5266#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 5267#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5278#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5275#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 5170#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5145#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5146#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5127#L334 assume !(0 == ~M_E~0); 5128#L334-2 assume !(0 == ~T1_E~0); 5236#L339-1 assume !(0 == ~T2_E~0); 5229#L344-1 assume !(0 == ~E_1~0); 5230#L349-1 assume !(0 == ~E_2~0); 5143#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5144#L156 assume !(1 == ~m_pc~0); 5072#L156-2 is_master_triggered_~__retres1~0#1 := 0; 5071#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5249#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5194#L405 assume !(0 != activate_threads_~tmp~1#1); 5175#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5176#L175 assume !(1 == ~t1_pc~0); 5183#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5177#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5139#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5140#L413 assume !(0 != activate_threads_~tmp___0~0#1); 5238#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5293#L194 assume !(1 == ~t2_pc~0); 5226#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5187#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5188#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5115#L421 assume !(0 != activate_threads_~tmp___1~0#1); 5116#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5085#L367 assume !(1 == ~M_E~0); 5086#L367-2 assume !(1 == ~T1_E~0); 5250#L372-1 assume !(1 == ~T2_E~0); 5251#L377-1 assume !(1 == ~E_1~0); 5112#L382-1 assume !(1 == ~E_2~0); 5113#L387-1 assume { :end_inline_reset_delta_events } true; 5196#L528-2 [2023-11-26 11:49:44,284 INFO L750 eck$LassoCheckResult]: Loop: 5196#L528-2 assume !false; 5375#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5371#L309-1 assume !false; 5363#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5361#L244 assume !(0 == ~m_st~0); 5359#L248 assume !(0 == ~t1_st~0); 5356#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 5354#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5348#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5345#L276 assume !(0 != eval_~tmp~0#1); 5342#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5340#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5338#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5336#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5333#L339-3 assume !(0 == ~T2_E~0); 5334#L344-3 assume !(0 == ~E_1~0); 5327#L349-3 assume !(0 == ~E_2~0); 5328#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5320#L156-9 assume 1 == ~m_pc~0; 5321#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5312#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5313#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5466#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5103#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5104#L175-9 assume !(1 == ~t1_pc~0); 5297#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 5529#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5528#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5527#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 5526#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5525#L194-9 assume 1 == ~t2_pc~0; 5523#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5522#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5521#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5520#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5519#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5518#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5517#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5516#L372-3 assume !(1 == ~T2_E~0); 5515#L377-3 assume !(1 == ~E_1~0); 5514#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5513#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5512#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5506#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5503#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 5499#L547 assume !(0 == start_simulation_~tmp~3#1); 5496#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5495#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5491#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5488#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 5485#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5482#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5480#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5478#L560 assume !(0 != start_simulation_~tmp___0~1#1); 5196#L528-2 [2023-11-26 11:49:44,284 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:44,284 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2023-11-26 11:49:44,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:44,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [769860835] [2023-11-26 11:49:44,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:44,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:44,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:44,293 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:44,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:44,306 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:44,306 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:44,306 INFO L85 PathProgramCache]: Analyzing trace with hash -1914923147, now seen corresponding path program 1 times [2023-11-26 11:49:44,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:44,307 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434276603] [2023-11-26 11:49:44,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:44,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:44,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:44,317 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:44,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:44,332 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:44,333 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:44,333 INFO L85 PathProgramCache]: Analyzing trace with hash 1578773301, now seen corresponding path program 1 times [2023-11-26 11:49:44,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:44,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42717981] [2023-11-26 11:49:44,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:44,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:44,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:44,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:44,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:44,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42717981] [2023-11-26 11:49:44,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [42717981] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:44,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:44,386 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:44,386 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533260741] [2023-11-26 11:49:44,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:45,134 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 11:49:45,134 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 11:49:45,134 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 11:49:45,135 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 11:49:45,135 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-26 11:49:45,135 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:45,135 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 11:49:45,135 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 11:49:45,135 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration7_Loop [2023-11-26 11:49:45,135 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 11:49:45,136 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 11:49:45,162 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,180 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,184 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,186 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,189 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,192 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,196 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,198 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,201 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,204 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,208 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,211 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,214 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,220 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,227 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,233 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,237 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,239 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,242 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,247 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,250 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,253 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,257 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,263 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,266 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,268 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,272 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,274 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,278 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,280 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,289 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,292 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,298 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,306 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,308 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,316 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,319 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,322 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,326 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:45,716 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 11:49:45,717 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-26 11:49:45,719 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:45,720 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:45,723 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:45,726 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-26 11:49:45,727 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:45,728 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:45,758 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:45,759 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:45,770 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:45,771 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:45,771 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:45,773 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:45,786 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:45,786 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:45,799 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-26 11:49:45,810 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:45,810 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_#res#1=1} Honda state: {ULTIMATE.start_is_master_triggered_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:45,819 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:45,820 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:45,820 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:45,821 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:45,826 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-26 11:49:45,847 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:45,847 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:45,876 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:45,876 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret13#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret13#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:45,880 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:45,880 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:45,881 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:45,882 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:45,888 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-26 11:49:45,891 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:45,891 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:45,924 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:45,924 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:45,933 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:45,934 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:45,934 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:45,935 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:45,948 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:45,949 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:45,961 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-26 11:49:45,975 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:45,976 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:45,984 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:45,985 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:45,985 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:45,987 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:45,992 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:45,992 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:45,993 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-26 11:49:46,015 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:46,015 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:46,020 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:46,020 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,020 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:46,021 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:46,025 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:46,025 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:46,036 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-26 11:49:46,060 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:46,060 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:46,068 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2023-11-26 11:49:46,069 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,069 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:46,070 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:46,074 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-26 11:49:46,075 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:46,075 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:46,104 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:46,104 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:46,112 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:46,113 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,113 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:46,114 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:46,128 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:46,129 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:46,142 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-26 11:49:46,151 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:46,151 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:46,163 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:46,163 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,164 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:46,165 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:46,177 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:46,177 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:46,200 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-26 11:49:46,214 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:46,215 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:46,224 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:46,224 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,224 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:46,228 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:46,234 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-26 11:49:46,235 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:46,235 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:46,257 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:46,257 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret8#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret8#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:46,266 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:46,267 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,267 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:46,268 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:46,281 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:46,281 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:46,295 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-26 11:49:46,312 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:46,312 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res#1=1} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:46,321 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:46,321 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,322 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:46,323 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:46,327 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:46,327 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:46,340 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-26 11:49:46,351 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:49:46,351 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_1~0=-1} Honda state: {~E_1~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:49:46,356 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:46,356 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,356 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:46,357 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:46,358 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-26 11:49:46,360 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:49:46,360 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:46,376 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:46,376 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,376 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:46,377 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:46,379 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-26 11:49:46,380 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-26 11:49:46,380 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:49:46,421 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-26 11:49:46,430 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:46,430 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 11:49:46,430 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 11:49:46,430 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 11:49:46,431 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 11:49:46,431 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-26 11:49:46,431 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,431 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 11:49:46,431 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 11:49:46,431 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration7_Loop [2023-11-26 11:49:46,431 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 11:49:46,431 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 11:49:46,435 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,443 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,445 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,448 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,451 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,457 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,460 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,462 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,468 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,472 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,475 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,478 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,483 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,491 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,496 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,499 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,501 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,531 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,535 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,537 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,541 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,545 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,548 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,555 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,557 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,560 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,563 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,566 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,568 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,571 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,576 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,579 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,584 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,589 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,591 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,593 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,596 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,601 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:49:46,987 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 11:49:46,991 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-26 11:49:46,993 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:46,993 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:46,994 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,003 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,016 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,016 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,017 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,017 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,017 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,019 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,019 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,021 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-26 11:49:47,030 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,039 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,040 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,040 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,041 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,053 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-26 11:49:47,053 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,066 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,066 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,067 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,067 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,067 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,067 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,067 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,076 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,080 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,081 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,081 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,082 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,093 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,105 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-26 11:49:47,106 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,106 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,106 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,106 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,106 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,107 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,107 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,127 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,136 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,136 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,136 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,138 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,156 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-26 11:49:47,156 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,168 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,168 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,169 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,169 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,169 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,170 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,170 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,179 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,188 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,188 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,188 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,189 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,198 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,210 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,210 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,211 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,211 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,211 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,212 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,212 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,213 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-26 11:49:47,227 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,236 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,237 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,237 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,238 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,242 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,255 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,255 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,255 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,255 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,255 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,256 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,256 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,257 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-26 11:49:47,283 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,292 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,292 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,293 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,294 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,297 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,310 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,310 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,310 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,310 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,310 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,311 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,311 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,312 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2023-11-26 11:49:47,323 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,331 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,332 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,332 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,334 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,338 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,351 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,351 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,351 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,351 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,352 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,356 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,356 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,357 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2023-11-26 11:49:47,383 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,391 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,392 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,392 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,393 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,397 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,416 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2023-11-26 11:49:47,416 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,416 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,416 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,416 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,416 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,420 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,420 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,429 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,437 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,438 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,438 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,439 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,443 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,456 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,456 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,456 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,456 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,456 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,457 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,457 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,458 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-26 11:49:47,471 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,478 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,479 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,479 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,480 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,483 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,496 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,496 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,496 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,496 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-26 11:49:47,497 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,497 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-26 11:49:47,498 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-26 11:49:47,498 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,515 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,523 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,524 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,524 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,525 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,528 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,541 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,541 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,541 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,542 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,542 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,542 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,543 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,543 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2023-11-26 11:49:47,559 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,568 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,569 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,569 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,570 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,574 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,586 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,586 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,586 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,586 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,586 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,587 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,587 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,588 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2023-11-26 11:49:47,599 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,607 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,608 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,608 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,609 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,613 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,625 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,625 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,625 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,625 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-26 11:49:47,625 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,626 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-26 11:49:47,627 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,627 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2023-11-26 11:49:47,651 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,656 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,656 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,656 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,660 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,664 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,677 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,677 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,677 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,677 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-26 11:49:47,677 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,679 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2023-11-26 11:49:47,680 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-26 11:49:47,680 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,695 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:49:47,703 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2023-11-26 11:49:47,704 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,704 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,705 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,709 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:49:47,721 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:49:47,722 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:49:47,722 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:49:47,722 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:49:47,722 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:49:47,723 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:49:47,723 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:49:47,724 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2023-11-26 11:49:47,737 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-26 11:49:47,741 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-26 11:49:47,741 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-26 11:49:47,743 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:49:47,743 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:49:47,776 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:49:47,777 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2023-11-26 11:49:47,778 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-26 11:49:47,778 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-26 11:49:47,778 INFO L513 LassoAnalysis]: Proved termination. [2023-11-26 11:49:47,779 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2023-11-26 11:49:47,781 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2023-11-26 11:49:47,783 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-26 11:49:47,813 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:47,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:47,844 INFO L262 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-26 11:49:47,846 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:49:47,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:47,929 INFO L262 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-26 11:49:47,932 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:49:48,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:48,110 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-26 11:49:48,111 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 587 states and 825 transitions. cyclomatic complexity: 242 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:48,160 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2023-11-26 11:49:48,270 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 587 states and 825 transitions. cyclomatic complexity: 242. Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 1479 states and 2094 transitions. Complement of second has 5 states. [2023-11-26 11:49:48,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-26 11:49:48,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:48,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 246 transitions. [2023-11-26 11:49:48,281 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 246 transitions. Stem has 38 letters. Loop has 54 letters. [2023-11-26 11:49:48,287 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:49:48,287 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 246 transitions. Stem has 92 letters. Loop has 54 letters. [2023-11-26 11:49:48,289 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:49:48,289 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 246 transitions. Stem has 38 letters. Loop has 108 letters. [2023-11-26 11:49:48,292 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:49:48,292 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1479 states and 2094 transitions. [2023-11-26 11:49:48,308 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 976 [2023-11-26 11:49:48,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1479 states to 1479 states and 2094 transitions. [2023-11-26 11:49:48,322 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1025 [2023-11-26 11:49:48,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1034 [2023-11-26 11:49:48,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1479 states and 2094 transitions. [2023-11-26 11:49:48,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:49:48,324 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1479 states and 2094 transitions. [2023-11-26 11:49:48,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1479 states and 2094 transitions. [2023-11-26 11:49:48,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1479 to 1470. [2023-11-26 11:49:48,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1470 states, 1470 states have (on average 1.4156462585034013) internal successors, (2081), 1469 states have internal predecessors, (2081), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:48,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1470 states to 1470 states and 2081 transitions. [2023-11-26 11:49:48,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1470 states and 2081 transitions. [2023-11-26 11:49:48,359 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:48,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:49:48,360 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:49:48,360 INFO L87 Difference]: Start difference. First operand 1470 states and 2081 transitions. Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:48,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:48,422 INFO L93 Difference]: Finished difference Result 2511 states and 3446 transitions. [2023-11-26 11:49:48,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2511 states and 3446 transitions. [2023-11-26 11:49:48,443 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1696 [2023-11-26 11:49:48,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2511 states to 2511 states and 3446 transitions. [2023-11-26 11:49:48,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1753 [2023-11-26 11:49:48,468 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1753 [2023-11-26 11:49:48,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2511 states and 3446 transitions. [2023-11-26 11:49:48,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:49:48,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2511 states and 3446 transitions. [2023-11-26 11:49:48,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2511 states and 3446 transitions. [2023-11-26 11:49:48,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2511 to 2406. [2023-11-26 11:49:48,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2406 states, 2406 states have (on average 1.3761429758935992) internal successors, (3311), 2405 states have internal predecessors, (3311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:48,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2406 states to 2406 states and 3311 transitions. [2023-11-26 11:49:48,522 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2406 states and 3311 transitions. [2023-11-26 11:49:48,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:49:48,525 INFO L428 stractBuchiCegarLoop]: Abstraction has 2406 states and 3311 transitions. [2023-11-26 11:49:48,526 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:49:48,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2406 states and 3311 transitions. [2023-11-26 11:49:48,547 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1626 [2023-11-26 11:49:48,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:48,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:48,548 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:48,548 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:48,549 INFO L748 eck$LassoCheckResult]: Stem: 11763#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 11764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 11785#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11781#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11782#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 11592#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11540#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11541#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11513#L334 assume !(0 == ~M_E~0); 11514#L334-2 assume !(0 == ~T1_E~0); 11704#L339-1 assume !(0 == ~T2_E~0); 11693#L344-1 assume !(0 == ~E_1~0); 11694#L349-1 assume !(0 == ~E_2~0); 11538#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11539#L156 assume !(1 == ~m_pc~0); 11423#L156-2 is_master_triggered_~__retres1~0#1 := 0; 11422#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11736#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11631#L405 assume !(0 != activate_threads_~tmp~1#1); 11601#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11602#L175 assume !(1 == ~t1_pc~0); 11612#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11603#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11534#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11535#L413 assume !(0 != activate_threads_~tmp___0~0#1); 11707#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11817#L194 assume !(1 == ~t2_pc~0); 11690#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11619#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11620#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11495#L421 assume !(0 != activate_threads_~tmp___1~0#1); 11496#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11440#L367 assume !(1 == ~M_E~0); 11441#L367-2 assume !(1 == ~T1_E~0); 11737#L372-1 assume !(1 == ~T2_E~0); 11738#L377-1 assume !(1 == ~E_1~0); 11491#L382-1 assume !(1 == ~E_2~0); 11492#L387-1 assume { :end_inline_reset_delta_events } true; 11636#L528-2 assume !false; 12354#L529 [2023-11-26 11:49:48,554 INFO L750 eck$LassoCheckResult]: Loop: 12354#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13349#L309-1 assume !false; 13344#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13340#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13125#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13329#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13322#L276 assume 0 != eval_~tmp~0#1; 13316#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 13269#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 13306#L47 assume !(0 == ~m_pc~0); 13300#L50 assume 1 == ~m_pc~0; 13291#$Ultimate##124 assume !false; 13283#L67 ~m_pc~0 := 1;~m_st~0 := 2; 13275#master_returnLabel#1 assume { :end_inline_master } true; 13268#L284-2 havoc eval_~tmp_ndt_1~0#1; 13265#L281-1 assume !(0 == ~t1_st~0); 13133#L295-1 assume !(0 == ~t2_st~0); 13129#L309-1 assume !false; 13127#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13124#L244 assume !(0 == ~m_st~0); 13094#L248 assume !(0 == ~t1_st~0); 13087#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 13081#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13065#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13054#L276 assume !(0 != eval_~tmp~0#1); 11639#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11640#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11702#L334-3 assume !(0 == ~M_E~0); 11786#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11708#L339-3 assume !(0 == ~T2_E~0); 11709#L344-3 assume !(0 == ~E_1~0); 13646#L349-3 assume !(0 == ~E_2~0); 13644#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13635#L156-9 assume !(1 == ~m_pc~0); 13633#L156-11 is_master_triggered_~__retres1~0#1 := 0; 11586#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11587#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11712#L405-9 assume !(0 != activate_threads_~tmp~1#1); 11473#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11474#L175-9 assume !(1 == ~t1_pc~0); 11749#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 11446#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11447#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11834#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 11759#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11760#L194-9 assume 1 == ~t2_pc~0; 11637#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11498#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11417#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11418#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11696#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13386#L367-3 assume !(1 == ~M_E~0); 13352#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13346#L372-3 assume !(1 == ~T2_E~0); 13342#L377-3 assume !(1 == ~E_1~0); 13336#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13331#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13325#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13326#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13385#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 13383#L547 assume !(0 == start_simulation_~tmp~3#1); 13382#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13380#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13287#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13379#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 13377#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13375#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13373#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 13372#L560 assume !(0 != start_simulation_~tmp___0~1#1); 13369#L528-2 assume !false; 12354#L529 [2023-11-26 11:49:48,555 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:48,555 INFO L85 PathProgramCache]: Analyzing trace with hash -308898552, now seen corresponding path program 1 times [2023-11-26 11:49:48,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:48,556 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365697143] [2023-11-26 11:49:48,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:48,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:48,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:48,568 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:48,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:48,593 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:48,597 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:48,600 INFO L85 PathProgramCache]: Analyzing trace with hash -1804567034, now seen corresponding path program 1 times [2023-11-26 11:49:48,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:48,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131799012] [2023-11-26 11:49:48,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:48,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:48,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:48,635 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:48,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:48,636 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2131799012] [2023-11-26 11:49:48,636 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2131799012] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:48,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:48,636 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:48,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083326074] [2023-11-26 11:49:48,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:48,637 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:49:48,637 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:48,638 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:49:48,638 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:49:48,638 INFO L87 Difference]: Start difference. First operand 2406 states and 3311 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 23.333333333333332) internal successors, (70), 3 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:48,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:48,681 INFO L93 Difference]: Finished difference Result 2618 states and 3536 transitions. [2023-11-26 11:49:48,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2618 states and 3536 transitions. [2023-11-26 11:49:48,702 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 1599 [2023-11-26 11:49:48,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2618 states to 2618 states and 3536 transitions. [2023-11-26 11:49:48,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1778 [2023-11-26 11:49:48,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1778 [2023-11-26 11:49:48,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2618 states and 3536 transitions. [2023-11-26 11:49:48,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:49:48,725 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2618 states and 3536 transitions. [2023-11-26 11:49:48,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2618 states and 3536 transitions. [2023-11-26 11:49:48,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2618 to 2532. [2023-11-26 11:49:48,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2532 states, 2532 states have (on average 1.353080568720379) internal successors, (3426), 2531 states have internal predecessors, (3426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:48,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2532 states to 2532 states and 3426 transitions. [2023-11-26 11:49:48,782 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2532 states and 3426 transitions. [2023-11-26 11:49:48,782 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:49:48,783 INFO L428 stractBuchiCegarLoop]: Abstraction has 2532 states and 3426 transitions. [2023-11-26 11:49:48,784 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 11:49:48,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2532 states and 3426 transitions. [2023-11-26 11:49:48,799 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 1599 [2023-11-26 11:49:48,800 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:48,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:48,801 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:48,801 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:48,801 INFO L748 eck$LassoCheckResult]: Stem: 16781#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 16782#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 16803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16799#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16800#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 16618#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16570#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16571#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16542#L334 assume !(0 == ~M_E~0); 16543#L334-2 assume !(0 == ~T1_E~0); 16726#L339-1 assume !(0 == ~T2_E~0); 16716#L344-1 assume !(0 == ~E_1~0); 16717#L349-1 assume !(0 == ~E_2~0); 16568#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16569#L156 assume 1 == ~m_pc~0; 16455#L157 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16456#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16757#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16758#L405 assume !(0 != activate_threads_~tmp~1#1); 16960#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16958#L175 assume !(1 == ~t1_pc~0); 16956#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16954#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16563#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16564#L413 assume !(0 != activate_threads_~tmp___0~0#1); 16730#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16838#L194 assume !(1 == ~t2_pc~0); 16715#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16645#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16646#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16524#L421 assume !(0 != activate_threads_~tmp___1~0#1); 16525#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16469#L367 assume !(1 == ~M_E~0); 16470#L367-2 assume !(1 == ~T1_E~0); 16933#L372-1 assume !(1 == ~T2_E~0); 16929#L377-1 assume !(1 == ~E_1~0); 16926#L382-1 assume !(1 == ~E_2~0); 16660#L387-1 assume { :end_inline_reset_delta_events } true; 16661#L528-2 assume !false; 17482#L529 [2023-11-26 11:49:48,802 INFO L750 eck$LassoCheckResult]: Loop: 17482#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18506#L309-1 assume !false; 18504#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18502#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18465#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18499#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18497#L276 assume 0 != eval_~tmp~0#1; 18495#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 18482#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 18491#L47 assume !(0 == ~m_pc~0); 18488#L50 assume 1 == ~m_pc~0; 16858#$Ultimate##124 assume !false; 18487#L67 ~m_pc~0 := 1;~m_st~0 := 2; 18486#master_returnLabel#1 assume { :end_inline_master } true; 18481#L284-2 havoc eval_~tmp_ndt_1~0#1; 18479#L281-1 assume !(0 == ~t1_st~0); 18474#L295-1 assume !(0 == ~t2_st~0); 18470#L309-1 assume !false; 18468#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18464#L244 assume !(0 == ~m_st~0); 18463#L248 assume !(0 == ~t1_st~0); 18460#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 18459#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18458#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18456#L276 assume !(0 != eval_~tmp~0#1); 18455#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18454#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18453#L334-3 assume !(0 == ~M_E~0); 18451#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18449#L339-3 assume !(0 == ~T2_E~0); 18447#L344-3 assume !(0 == ~E_1~0); 18446#L349-3 assume !(0 == ~E_2~0); 18443#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18442#L156-9 assume 1 == ~m_pc~0; 18441#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18439#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18434#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 18431#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18432#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18879#L175-9 assume !(1 == ~t1_pc~0); 18877#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 18875#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18873#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 18871#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 18869#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18867#L194-9 assume 1 == ~t2_pc~0; 18864#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18863#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18860#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 18858#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18856#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18854#L367-3 assume !(1 == ~M_E~0); 18852#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18850#L372-3 assume !(1 == ~T2_E~0); 18827#L377-3 assume !(1 == ~E_1~0); 18801#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18795#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18362#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18361#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18358#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 18355#L547 assume !(0 == start_simulation_~tmp~3#1); 18356#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18540#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18537#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18535#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 18533#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18530#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18528#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 18525#L560 assume !(0 != start_simulation_~tmp___0~1#1); 18523#L528-2 assume !false; 17482#L529 [2023-11-26 11:49:48,802 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:48,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1748705479, now seen corresponding path program 1 times [2023-11-26 11:49:48,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:48,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513162582] [2023-11-26 11:49:48,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:48,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:48,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:48,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:48,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:48,831 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513162582] [2023-11-26 11:49:48,831 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [513162582] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:48,831 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:48,831 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:49:48,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224148952] [2023-11-26 11:49:48,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:48,832 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:49:48,832 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:48,832 INFO L85 PathProgramCache]: Analyzing trace with hash 1437526851, now seen corresponding path program 1 times [2023-11-26 11:49:48,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:48,833 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724145585] [2023-11-26 11:49:48,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:48,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:48,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:48,865 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2023-11-26 11:49:48,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:48,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724145585] [2023-11-26 11:49:48,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [724145585] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:48,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:48,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:48,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186541996] [2023-11-26 11:49:48,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:48,866 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:49:48,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:48,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:49:48,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:49:48,868 INFO L87 Difference]: Start difference. First operand 2532 states and 3426 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 13.0) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:48,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:48,918 INFO L93 Difference]: Finished difference Result 1398 states and 1885 transitions. [2023-11-26 11:49:48,918 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1398 states and 1885 transitions. [2023-11-26 11:49:48,932 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 833 [2023-11-26 11:49:48,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1398 states to 1398 states and 1885 transitions. [2023-11-26 11:49:48,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 937 [2023-11-26 11:49:48,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 937 [2023-11-26 11:49:48,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1398 states and 1885 transitions. [2023-11-26 11:49:48,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:49:48,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1398 states and 1885 transitions. [2023-11-26 11:49:48,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1398 states and 1885 transitions. [2023-11-26 11:49:48,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1398 to 1390. [2023-11-26 11:49:48,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1390 states, 1390 states have (on average 1.3503597122302158) internal successors, (1877), 1389 states have internal predecessors, (1877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:48,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1390 states to 1390 states and 1877 transitions. [2023-11-26 11:49:48,981 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1390 states and 1877 transitions. [2023-11-26 11:49:48,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:49:48,982 INFO L428 stractBuchiCegarLoop]: Abstraction has 1390 states and 1877 transitions. [2023-11-26 11:49:48,983 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 11:49:48,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1390 states and 1877 transitions. [2023-11-26 11:49:48,991 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 833 [2023-11-26 11:49:48,992 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:48,992 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:48,996 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:48,996 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:48,997 INFO L748 eck$LassoCheckResult]: Stem: 20713#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 20714#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 20735#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20731#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20732#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 20549#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20496#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20497#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20469#L334 assume !(0 == ~M_E~0); 20470#L334-2 assume !(0 == ~T1_E~0); 20662#L339-1 assume !(0 == ~T2_E~0); 20650#L344-1 assume !(0 == ~E_1~0); 20651#L349-1 assume !(0 == ~E_2~0); 20494#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20495#L156 assume !(1 == ~m_pc~0); 20670#L156-2 is_master_triggered_~__retres1~0#1 := 0; 20696#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20690#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 20593#L405 assume !(0 != activate_threads_~tmp~1#1); 20560#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20561#L175 assume !(1 == ~t1_pc~0); 20572#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20562#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20489#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20490#L413 assume !(0 != activate_threads_~tmp___0~0#1); 20665#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20769#L194 assume !(1 == ~t2_pc~0); 20649#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20579#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20580#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20451#L421 assume !(0 != activate_threads_~tmp___1~0#1); 20452#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20402#L367 assume !(1 == ~M_E~0); 20403#L367-2 assume !(1 == ~T1_E~0); 20691#L372-1 assume !(1 == ~T2_E~0); 20692#L377-1 assume !(1 == ~E_1~0); 20447#L382-1 assume !(1 == ~E_2~0); 20448#L387-1 assume { :end_inline_reset_delta_events } true; 20598#L528-2 assume !false; 20826#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20824#L309-1 [2023-11-26 11:49:48,997 INFO L750 eck$LassoCheckResult]: Loop: 20824#L309-1 assume !false; 20823#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 20822#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 20821#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 20820#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20819#L276 assume 0 != eval_~tmp~0#1; 20818#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 20816#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 20817#L284-2 havoc eval_~tmp_ndt_1~0#1; 20833#L281-1 assume !(0 == ~t1_st~0); 20827#L295-1 assume !(0 == ~t2_st~0); 20824#L309-1 [2023-11-26 11:49:48,997 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:48,998 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 1 times [2023-11-26 11:49:48,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:48,998 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914190743] [2023-11-26 11:49:48,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:48,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,006 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:49,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,017 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:49,018 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:49,018 INFO L85 PathProgramCache]: Analyzing trace with hash 993947407, now seen corresponding path program 1 times [2023-11-26 11:49:49,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:49,018 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149496428] [2023-11-26 11:49:49,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:49,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,023 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:49,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,031 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:49,032 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:49,032 INFO L85 PathProgramCache]: Analyzing trace with hash 1252886829, now seen corresponding path program 1 times [2023-11-26 11:49:49,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:49,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657823860] [2023-11-26 11:49:49,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:49,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:49,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:49,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:49,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657823860] [2023-11-26 11:49:49,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657823860] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:49,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:49,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:49,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779942859] [2023-11-26 11:49:49,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:49,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:49,150 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:49:49,151 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:49:49,151 INFO L87 Difference]: Start difference. First operand 1390 states and 1877 transitions. cyclomatic complexity: 497 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:49,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:49,204 INFO L93 Difference]: Finished difference Result 2400 states and 3187 transitions. [2023-11-26 11:49:49,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2400 states and 3187 transitions. [2023-11-26 11:49:49,219 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1265 [2023-11-26 11:49:49,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2400 states to 2400 states and 3187 transitions. [2023-11-26 11:49:49,239 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1619 [2023-11-26 11:49:49,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1619 [2023-11-26 11:49:49,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2400 states and 3187 transitions. [2023-11-26 11:49:49,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:49:49,241 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2400 states and 3187 transitions. [2023-11-26 11:49:49,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2400 states and 3187 transitions. [2023-11-26 11:49:49,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2400 to 2312. [2023-11-26 11:49:49,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2312 states, 2312 states have (on average 1.3300173010380623) internal successors, (3075), 2311 states have internal predecessors, (3075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:49,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2312 states to 2312 states and 3075 transitions. [2023-11-26 11:49:49,294 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2312 states and 3075 transitions. [2023-11-26 11:49:49,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:49:49,295 INFO L428 stractBuchiCegarLoop]: Abstraction has 2312 states and 3075 transitions. [2023-11-26 11:49:49,295 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 11:49:49,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2312 states and 3075 transitions. [2023-11-26 11:49:49,305 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1210 [2023-11-26 11:49:49,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:49,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:49,306 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:49,306 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:49,306 INFO L748 eck$LassoCheckResult]: Stem: 24507#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 24508#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24534#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24528#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24529#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 24344#L221-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 24292#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24293#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24903#L334 assume !(0 == ~M_E~0); 24552#L334-2 assume !(0 == ~T1_E~0); 24455#L339-1 assume !(0 == ~T2_E~0); 24444#L344-1 assume !(0 == ~E_1~0); 24445#L349-1 assume !(0 == ~E_2~0); 24500#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24899#L156 assume !(1 == ~m_pc~0); 24898#L156-2 is_master_triggered_~__retres1~0#1 := 0; 24897#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24896#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 24384#L405 assume !(0 != activate_threads_~tmp~1#1); 24352#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24353#L175 assume !(1 == ~t1_pc~0); 24363#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24354#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24286#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24287#L413 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24458#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24569#L194 assume !(1 == ~t2_pc~0); 24442#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24370#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24371#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24249#L421 assume !(0 != activate_threads_~tmp___1~0#1); 24250#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24200#L367 assume !(1 == ~M_E~0); 24201#L367-2 assume !(1 == ~T1_E~0); 24870#L372-1 assume !(1 == ~T2_E~0); 24867#L377-1 assume !(1 == ~E_1~0); 24866#L382-1 assume !(1 == ~E_2~0); 24389#L387-1 assume { :end_inline_reset_delta_events } true; 24390#L528-2 assume !false; 24952#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24951#L309-1 [2023-11-26 11:49:49,307 INFO L750 eck$LassoCheckResult]: Loop: 24951#L309-1 assume !false; 24944#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24945#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 24937#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24938#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24931#L276 assume 0 != eval_~tmp~0#1; 24932#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 24925#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 24926#L284-2 havoc eval_~tmp_ndt_1~0#1; 24979#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 24964#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 24962#L298-2 havoc eval_~tmp_ndt_2~0#1; 24953#L295-1 assume !(0 == ~t2_st~0); 24951#L309-1 [2023-11-26 11:49:49,307 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:49,307 INFO L85 PathProgramCache]: Analyzing trace with hash -808857497, now seen corresponding path program 1 times [2023-11-26 11:49:49,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:49,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283977255] [2023-11-26 11:49:49,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:49,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:49,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:49,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:49,329 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283977255] [2023-11-26 11:49:49,329 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1283977255] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:49,329 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:49,329 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:49:49,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1836245095] [2023-11-26 11:49:49,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:49,330 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:49:49,330 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:49,330 INFO L85 PathProgramCache]: Analyzing trace with hash 1697436410, now seen corresponding path program 1 times [2023-11-26 11:49:49,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:49,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [231541285] [2023-11-26 11:49:49,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:49,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,335 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:49,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,339 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:49,387 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:49,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:49:49,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:49:49,388 INFO L87 Difference]: Start difference. First operand 2312 states and 3075 transitions. cyclomatic complexity: 778 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:49,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:49,402 INFO L93 Difference]: Finished difference Result 1463 states and 1934 transitions. [2023-11-26 11:49:49,402 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1463 states and 1934 transitions. [2023-11-26 11:49:49,410 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 831 [2023-11-26 11:49:49,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1463 states to 1463 states and 1934 transitions. [2023-11-26 11:49:49,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2023-11-26 11:49:49,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2023-11-26 11:49:49,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1463 states and 1934 transitions. [2023-11-26 11:49:49,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:49:49,423 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1463 states and 1934 transitions. [2023-11-26 11:49:49,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1463 states and 1934 transitions. [2023-11-26 11:49:49,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1463 to 1463. [2023-11-26 11:49:49,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1463 states, 1463 states have (on average 1.3219412166780589) internal successors, (1934), 1462 states have internal predecessors, (1934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:49,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1463 states to 1463 states and 1934 transitions. [2023-11-26 11:49:49,454 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1463 states and 1934 transitions. [2023-11-26 11:49:49,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:49:49,455 INFO L428 stractBuchiCegarLoop]: Abstraction has 1463 states and 1934 transitions. [2023-11-26 11:49:49,455 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 11:49:49,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1463 states and 1934 transitions. [2023-11-26 11:49:49,460 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 831 [2023-11-26 11:49:49,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:49,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:49,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:49,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:49,462 INFO L748 eck$LassoCheckResult]: Stem: 28288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 28289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28309#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28304#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28305#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 28123#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28074#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28075#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28049#L334 assume !(0 == ~M_E~0); 28050#L334-2 assume !(0 == ~T1_E~0); 28231#L339-1 assume !(0 == ~T2_E~0); 28220#L344-1 assume !(0 == ~E_1~0); 28221#L349-1 assume !(0 == ~E_2~0); 28072#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28073#L156 assume !(1 == ~m_pc~0); 28239#L156-2 is_master_triggered_~__retres1~0#1 := 0; 28271#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28261#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 28166#L405 assume !(0 != activate_threads_~tmp~1#1); 28138#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28139#L175 assume !(1 == ~t1_pc~0); 28143#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28140#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28067#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28068#L413 assume !(0 != activate_threads_~tmp___0~0#1); 28238#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28342#L194 assume !(1 == ~t2_pc~0); 28219#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28151#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28152#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28031#L421 assume !(0 != activate_threads_~tmp___1~0#1); 28032#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27986#L367 assume !(1 == ~M_E~0); 27987#L367-2 assume !(1 == ~T1_E~0); 28262#L372-1 assume !(1 == ~T2_E~0); 28263#L377-1 assume !(1 == ~E_1~0); 28027#L382-1 assume !(1 == ~E_2~0); 28028#L387-1 assume { :end_inline_reset_delta_events } true; 28171#L528-2 assume !false; 28647#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28876#L309-1 [2023-11-26 11:49:49,462 INFO L750 eck$LassoCheckResult]: Loop: 28876#L309-1 assume !false; 28875#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 28874#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 28872#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 28870#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28868#L276 assume 0 != eval_~tmp~0#1; 28867#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 28864#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 28865#L284-2 havoc eval_~tmp_ndt_1~0#1; 28886#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 28884#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 28882#L298-2 havoc eval_~tmp_ndt_2~0#1; 28879#L295-1 assume !(0 == ~t2_st~0); 28876#L309-1 [2023-11-26 11:49:49,462 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:49,462 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 2 times [2023-11-26 11:49:49,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:49,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452154392] [2023-11-26 11:49:49,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:49,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,470 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:49,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,479 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:49,479 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:49,480 INFO L85 PathProgramCache]: Analyzing trace with hash 1697436410, now seen corresponding path program 2 times [2023-11-26 11:49:49,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:49,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816879454] [2023-11-26 11:49:49,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:49,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,484 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:49,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,487 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:49,488 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:49,488 INFO L85 PathProgramCache]: Analyzing trace with hash 1430117784, now seen corresponding path program 1 times [2023-11-26 11:49:49,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:49,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316387133] [2023-11-26 11:49:49,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:49,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:49:49,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:49:49,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:49:49,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [316387133] [2023-11-26 11:49:49,518 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [316387133] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:49:49,518 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:49:49,519 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:49:49,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15332932] [2023-11-26 11:49:49,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:49:49,572 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:49:49,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:49:49,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:49:49,573 INFO L87 Difference]: Start difference. First operand 1463 states and 1934 transitions. cyclomatic complexity: 480 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:49,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:49:49,659 INFO L93 Difference]: Finished difference Result 2565 states and 3349 transitions. [2023-11-26 11:49:49,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2565 states and 3349 transitions. [2023-11-26 11:49:49,672 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1460 [2023-11-26 11:49:49,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2565 states to 2565 states and 3349 transitions. [2023-11-26 11:49:49,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1661 [2023-11-26 11:49:49,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1661 [2023-11-26 11:49:49,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2565 states and 3349 transitions. [2023-11-26 11:49:49,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:49:49,691 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2565 states and 3349 transitions. [2023-11-26 11:49:49,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2565 states and 3349 transitions. [2023-11-26 11:49:49,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2565 to 2565. [2023-11-26 11:49:49,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2565 states, 2565 states have (on average 1.305653021442495) internal successors, (3349), 2564 states have internal predecessors, (3349), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:49:49,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2565 states to 2565 states and 3349 transitions. [2023-11-26 11:49:49,743 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2565 states and 3349 transitions. [2023-11-26 11:49:49,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:49:49,744 INFO L428 stractBuchiCegarLoop]: Abstraction has 2565 states and 3349 transitions. [2023-11-26 11:49:49,744 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 11:49:49,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2565 states and 3349 transitions. [2023-11-26 11:49:49,753 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1460 [2023-11-26 11:49:49,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:49:49,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:49:49,754 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:49,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:49:49,755 INFO L748 eck$LassoCheckResult]: Stem: 32315#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 32316#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 32339#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32336#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32337#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 32158#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32110#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32111#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32086#L334 assume !(0 == ~M_E~0); 32087#L334-2 assume !(0 == ~T1_E~0); 32266#L339-1 assume !(0 == ~T2_E~0); 32254#L344-1 assume !(0 == ~E_1~0); 32255#L349-1 assume !(0 == ~E_2~0); 32108#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32109#L156 assume !(1 == ~m_pc~0); 32274#L156-2 is_master_triggered_~__retres1~0#1 := 0; 32299#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32293#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 32199#L405 assume !(0 != activate_threads_~tmp~1#1); 32166#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32167#L175 assume !(1 == ~t1_pc~0); 32178#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32168#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32104#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 32105#L413 assume !(0 != activate_threads_~tmp___0~0#1); 32269#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32368#L194 assume !(1 == ~t2_pc~0); 32252#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32185#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32186#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32068#L421 assume !(0 != activate_threads_~tmp___1~0#1); 32069#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32018#L367 assume !(1 == ~M_E~0); 32019#L367-2 assume !(1 == ~T1_E~0); 32294#L372-1 assume !(1 == ~T2_E~0); 32295#L377-1 assume !(1 == ~E_1~0); 32064#L382-1 assume !(1 == ~E_2~0); 32065#L387-1 assume { :end_inline_reset_delta_events } true; 32204#L528-2 assume !false; 33456#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33453#L309-1 [2023-11-26 11:49:49,755 INFO L750 eck$LassoCheckResult]: Loop: 33453#L309-1 assume !false; 33451#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 33449#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 33447#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 33445#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33443#L276 assume 0 != eval_~tmp~0#1; 33441#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 33437#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 33433#L284-2 havoc eval_~tmp_ndt_1~0#1; 33429#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 33400#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 33402#L298-2 havoc eval_~tmp_ndt_2~0#1; 33469#L295-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 33465#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 33455#L312-2 havoc eval_~tmp_ndt_3~0#1; 33453#L309-1 [2023-11-26 11:49:49,755 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:49,756 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 3 times [2023-11-26 11:49:49,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:49,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112385715] [2023-11-26 11:49:49,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:49,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,763 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:49,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,772 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:49,773 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:49,773 INFO L85 PathProgramCache]: Analyzing trace with hash -851208175, now seen corresponding path program 1 times [2023-11-26 11:49:49,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:49,773 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387725571] [2023-11-26 11:49:49,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:49,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:49,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,780 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:49,781 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:49:49,781 INFO L85 PathProgramCache]: Analyzing trace with hash -46370001, now seen corresponding path program 1 times [2023-11-26 11:49:49,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:49:49,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924645001] [2023-11-26 11:49:49,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:49:49,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:49:49,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,790 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:49,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:49,801 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:49:50,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:50,514 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:49:50,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:49:50,674 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.11 11:49:50 BoogieIcfgContainer [2023-11-26 11:49:50,674 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-26 11:49:50,675 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-26 11:49:50,675 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-26 11:49:50,675 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-26 11:49:50,676 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:49:42" (3/4) ... [2023-11-26 11:49:50,677 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-26 11:49:50,760 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/witness.graphml [2023-11-26 11:49:50,761 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-26 11:49:50,761 INFO L158 Benchmark]: Toolchain (without parser) took 10105.75ms. Allocated memory was 127.9MB in the beginning and 247.5MB in the end (delta: 119.5MB). Free memory was 83.6MB in the beginning and 196.0MB in the end (delta: -112.4MB). Peak memory consumption was 8.9MB. Max. memory is 16.1GB. [2023-11-26 11:49:50,762 INFO L158 Benchmark]: CDTParser took 0.36ms. Allocated memory is still 127.9MB. Free memory is still 101.4MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 11:49:50,762 INFO L158 Benchmark]: CACSL2BoogieTranslator took 378.28ms. Allocated memory is still 127.9MB. Free memory was 83.3MB in the beginning and 69.9MB in the end (delta: 13.4MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-26 11:49:50,762 INFO L158 Benchmark]: Boogie Procedure Inliner took 60.61ms. Allocated memory is still 127.9MB. Free memory was 69.9MB in the beginning and 66.8MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-26 11:49:50,763 INFO L158 Benchmark]: Boogie Preprocessor took 93.41ms. Allocated memory is still 127.9MB. Free memory was 66.8MB in the beginning and 63.8MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 11:49:50,763 INFO L158 Benchmark]: RCFGBuilder took 862.83ms. Allocated memory was 127.9MB in the beginning and 169.9MB in the end (delta: 41.9MB). Free memory was 63.5MB in the beginning and 120.2MB in the end (delta: -56.7MB). Peak memory consumption was 12.5MB. Max. memory is 16.1GB. [2023-11-26 11:49:50,764 INFO L158 Benchmark]: BuchiAutomizer took 8616.62ms. Allocated memory was 169.9MB in the beginning and 247.5MB in the end (delta: 77.6MB). Free memory was 120.2MB in the beginning and 201.2MB in the end (delta: -81.0MB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 11:49:50,764 INFO L158 Benchmark]: Witness Printer took 85.98ms. Allocated memory is still 247.5MB. Free memory was 201.2MB in the beginning and 196.0MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 11:49:50,766 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.36ms. Allocated memory is still 127.9MB. Free memory is still 101.4MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 378.28ms. Allocated memory is still 127.9MB. Free memory was 83.3MB in the beginning and 69.9MB in the end (delta: 13.4MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 60.61ms. Allocated memory is still 127.9MB. Free memory was 69.9MB in the beginning and 66.8MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 93.41ms. Allocated memory is still 127.9MB. Free memory was 66.8MB in the beginning and 63.8MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 862.83ms. Allocated memory was 127.9MB in the beginning and 169.9MB in the end (delta: 41.9MB). Free memory was 63.5MB in the beginning and 120.2MB in the end (delta: -56.7MB). Peak memory consumption was 12.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 8616.62ms. Allocated memory was 169.9MB in the beginning and 247.5MB in the end (delta: 77.6MB). Free memory was 120.2MB in the beginning and 201.2MB in the end (delta: -81.0MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 85.98ms. Allocated memory is still 247.5MB. Free memory was 201.2MB in the beginning and 196.0MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (12 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function ((-1 * M_E) + 1) and consists of 3 locations. 12 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2565 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.4s and 13 iterations. TraceHistogramMax:2. Analysis of lassos took 6.0s. Construction of modules took 0.3s. Büchi inclusion checks took 1.7s. Highest rank in rank-based complementation 3. Minimization of det autom 6. Minimization of nondet autom 7. Automata minimization 0.4s AutomataMinimizationTime, 13 MinimizatonAttempts, 704 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3661 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3660 mSDsluCounter, 6857 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2862 mSDsCounter, 99 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 258 IncrementalHoareTripleChecker+Invalid, 357 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 99 mSolverCounterUnsat, 3995 mSDtfsCounter, 258 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT1 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital88 mio100 ax100 hnf100 lsp11 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 36ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 13 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.5s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L281-L292] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L295-L306] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L309-L320] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L281-L292] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L295-L306] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L309-L320] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-26 11:49:50,855 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_746b81c3-c94e-40fa-8a94-75711aa8e2df/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)