./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:47:20,273 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:47:20,389 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:47:20,396 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:47:20,397 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:47:20,438 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:47:20,439 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:47:20,439 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:47:20,440 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:47:20,445 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:47:20,447 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:47:20,448 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:47:20,448 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:47:20,450 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:47:20,451 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:47:20,452 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:47:20,452 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:47:20,452 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:47:20,453 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:47:20,453 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:47:20,454 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:47:20,455 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:47:20,455 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:47:20,455 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:47:20,456 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:47:20,456 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:47:20,457 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:47:20,457 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:47:20,457 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:47:20,458 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:47:20,459 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:47:20,460 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:47:20,460 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:47:20,460 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:47:20,460 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:47:20,461 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:47:20,461 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:47:20,462 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:47:20,462 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 [2023-11-26 11:47:20,778 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:47:20,811 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:47:20,814 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:47:20,815 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:47:20,816 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:47:20,818 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2023-11-26 11:47:24,124 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:47:24,366 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:47:24,367 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/sv-benchmarks/c/systemc/transmitter.03.cil.c [2023-11-26 11:47:24,382 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/data/a90ab42be/55efa1d10bd740359382f258e91242b1/FLAG78967bd10 [2023-11-26 11:47:24,399 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/data/a90ab42be/55efa1d10bd740359382f258e91242b1 [2023-11-26 11:47:24,402 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:47:24,404 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:47:24,406 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:47:24,406 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:47:24,413 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:47:24,414 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,415 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@13f3627b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24, skipping insertion in model container [2023-11-26 11:47:24,415 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,458 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:47:24,733 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:47:24,758 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:47:24,811 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:47:24,836 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:47:24,837 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24 WrapperNode [2023-11-26 11:47:24,837 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:47:24,838 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:47:24,839 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:47:24,839 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:47:24,848 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,859 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,907 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 57, statements flattened = 741 [2023-11-26 11:47:24,907 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:47:24,908 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:47:24,908 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:47:24,908 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:47:24,919 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,919 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,925 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,943 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 11:47:24,943 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,944 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,958 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,970 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,973 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,977 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,983 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:47:24,984 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:47:24,985 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:47:24,985 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:47:24,986 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (1/1) ... [2023-11-26 11:47:24,992 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:25,008 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:25,022 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:25,053 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:47:25,080 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:47:25,081 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:47:25,081 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:47:25,081 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:47:25,184 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:47:25,187 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:47:26,010 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:47:26,034 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:47:26,035 INFO L309 CfgBuilder]: Removed 7 assume(true) statements. [2023-11-26 11:47:26,037 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:47:26 BoogieIcfgContainer [2023-11-26 11:47:26,037 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:47:26,038 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:47:26,039 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:47:26,043 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:47:26,044 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:47:26,044 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:47:24" (1/3) ... [2023-11-26 11:47:26,046 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6f5161b0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:47:26, skipping insertion in model container [2023-11-26 11:47:26,046 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:47:26,046 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:24" (2/3) ... [2023-11-26 11:47:26,047 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6f5161b0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:47:26, skipping insertion in model container [2023-11-26 11:47:26,047 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:47:26,047 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:47:26" (3/3) ... [2023-11-26 11:47:26,052 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2023-11-26 11:47:26,122 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:47:26,123 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:47:26,123 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:47:26,123 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:47:26,123 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:47:26,124 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:47:26,124 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:47:26,124 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:47:26,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:26,174 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2023-11-26 11:47:26,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:26,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:26,186 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:26,187 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:26,187 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:47:26,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:26,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2023-11-26 11:47:26,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:26,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:26,210 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:26,210 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:26,220 INFO L748 eck$LassoCheckResult]: Stem: 192#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 205#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 292#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 178#L281true assume !(1 == ~m_i~0);~m_st~0 := 2; 241#L281-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 35#L286-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 219#L291-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 236#L296-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17#L418true assume !(0 == ~M_E~0); 177#L418-2true assume !(0 == ~T1_E~0); 227#L423-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 239#L428-1true assume !(0 == ~T3_E~0); 223#L433-1true assume !(0 == ~E_1~0); 209#L438-1true assume !(0 == ~E_2~0); 135#L443-1true assume !(0 == ~E_3~0); 130#L448-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96#L197true assume !(1 == ~m_pc~0); 268#L197-2true is_master_triggered_~__retres1~0#1 := 0; 271#L208true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170#is_master_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 247#L510true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7#L510-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 269#L216true assume 1 == ~t1_pc~0; 29#L217true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 125#L227true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8#L518true assume !(0 != activate_threads_~tmp___0~0#1); 143#L518-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278#L235true assume !(1 == ~t2_pc~0); 215#L235-2true is_transmit2_triggered_~__retres1~2#1 := 0; 85#L246true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 256#L526true assume !(0 != activate_threads_~tmp___1~0#1); 267#L526-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75#L254true assume 1 == ~t3_pc~0; 22#L255true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91#L265true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116#L534true assume !(0 != activate_threads_~tmp___2~0#1); 81#L534-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2#L461true assume !(1 == ~M_E~0); 36#L461-2true assume !(1 == ~T1_E~0); 237#L466-1true assume !(1 == ~T2_E~0); 274#L471-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 50#L476-1true assume !(1 == ~E_1~0); 277#L481-1true assume !(1 == ~E_2~0); 157#L486-1true assume !(1 == ~E_3~0); 59#L491-1true assume { :end_inline_reset_delta_events } true; 11#L652-2true [2023-11-26 11:47:26,222 INFO L750 eck$LassoCheckResult]: Loop: 11#L652-2true assume !false; 67#L653true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 162#L393-1true assume false; 114#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 147#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 294#L418-3true assume 0 == ~M_E~0;~M_E~0 := 1; 142#L418-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 166#L423-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 137#L428-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 95#L433-3true assume !(0 == ~E_1~0); 186#L438-3true assume 0 == ~E_2~0;~E_2~0 := 1; 193#L443-3true assume 0 == ~E_3~0;~E_3~0 := 1; 3#L448-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 195#L197-12true assume 1 == ~m_pc~0; 201#L198-4true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 73#L208-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141#is_master_triggered_returnLabel#5true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10#L510-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 111#L510-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72#L216-12true assume 1 == ~t1_pc~0; 286#L217-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 108#L227-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 243#is_transmit1_triggered_returnLabel#5true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 78#L518-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34#L518-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282#L235-12true assume 1 == ~t2_pc~0; 207#L236-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 257#L246-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79#is_transmit2_triggered_returnLabel#5true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 289#L526-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 131#L526-14true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 250#L254-12true assume 1 == ~t3_pc~0; 25#L255-4true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 134#L265-4true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51#is_transmit3_triggered_returnLabel#5true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 113#L534-12true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 158#L534-14true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74#L461-3true assume 1 == ~M_E~0;~M_E~0 := 2; 295#L461-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 148#L466-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 246#L471-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 69#L476-3true assume 1 == ~E_1~0;~E_1~0 := 2; 139#L481-3true assume !(1 == ~E_2~0); 90#L486-3true assume 1 == ~E_3~0;~E_3~0 := 2; 264#L491-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24#L309-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37#L331-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 259#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 149#L671true assume !(0 == start_simulation_~tmp~3#1); 183#L671-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 296#L309-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 155#L331-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 48#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 234#L626true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 161#L633true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 164#stop_simulation_returnLabel#1true start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 169#L684true assume !(0 != start_simulation_~tmp___0~1#1); 11#L652-2true [2023-11-26 11:47:26,229 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:26,229 INFO L85 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2023-11-26 11:47:26,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:26,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207380461] [2023-11-26 11:47:26,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:26,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:26,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:26,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:26,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:26,634 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207380461] [2023-11-26 11:47:26,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207380461] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:26,635 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:26,636 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:26,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452537113] [2023-11-26 11:47:26,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:26,643 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:26,645 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:26,645 INFO L85 PathProgramCache]: Analyzing trace with hash -1698573144, now seen corresponding path program 1 times [2023-11-26 11:47:26,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:26,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445767176] [2023-11-26 11:47:26,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:26,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:26,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:26,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:26,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:26,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445767176] [2023-11-26 11:47:26,701 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445767176] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:26,701 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:26,701 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:26,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338951138] [2023-11-26 11:47:26,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:26,703 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:26,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:26,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:26,742 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:26,746 INFO L87 Difference]: Start difference. First operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:26,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:26,805 INFO L93 Difference]: Finished difference Result 294 states and 434 transitions. [2023-11-26 11:47:26,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 294 states and 434 transitions. [2023-11-26 11:47:26,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-26 11:47:26,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 294 states to 288 states and 428 transitions. [2023-11-26 11:47:26,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2023-11-26 11:47:26,827 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2023-11-26 11:47:26,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 428 transitions. [2023-11-26 11:47:26,830 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:26,831 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 428 transitions. [2023-11-26 11:47:26,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 428 transitions. [2023-11-26 11:47:26,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2023-11-26 11:47:26,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4861111111111112) internal successors, (428), 287 states have internal predecessors, (428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:26,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 428 transitions. [2023-11-26 11:47:26,889 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 428 transitions. [2023-11-26 11:47:26,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:26,895 INFO L428 stractBuchiCegarLoop]: Abstraction has 288 states and 428 transitions. [2023-11-26 11:47:26,895 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:47:26,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 428 transitions. [2023-11-26 11:47:26,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-26 11:47:26,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:26,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:26,906 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:26,906 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:26,907 INFO L748 eck$LassoCheckResult]: Stem: 857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 867#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 866#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 841#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 842#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 668#L286-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 669#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 874#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 628#L418 assume !(0 == ~M_E~0); 629#L418-2 assume !(0 == ~T1_E~0); 840#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 877#L428-1 assume !(0 == ~T3_E~0); 875#L433-1 assume !(0 == ~E_1~0); 869#L438-1 assume !(0 == ~E_2~0); 806#L443-1 assume !(0 == ~E_3~0); 800#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 767#L197 assume !(1 == ~m_pc~0); 764#L197-2 is_master_triggered_~__retres1~0#1 := 0; 763#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 833#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 834#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 607#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 608#L216 assume 1 == ~t1_pc~0; 656#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 657#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 609#L518 assume !(0 != activate_threads_~tmp___0~0#1); 610#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 814#L235 assume !(1 == ~t2_pc~0); 871#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 752#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 753#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 882#L526 assume !(0 != activate_threads_~tmp___1~0#1); 883#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 735#L254 assume 1 == ~t3_pc~0; 638#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 639#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 620#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 621#L534 assume !(0 != activate_threads_~tmp___2~0#1); 746#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 599#L461 assume !(1 == ~M_E~0); 600#L461-2 assume !(1 == ~T1_E~0); 670#L466-1 assume !(1 == ~T2_E~0); 880#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 696#L476-1 assume !(1 == ~E_1~0); 697#L481-1 assume !(1 == ~E_2~0); 828#L486-1 assume !(1 == ~E_3~0); 711#L491-1 assume { :end_inline_reset_delta_events } true; 618#L652-2 [2023-11-26 11:47:26,908 INFO L750 eck$LassoCheckResult]: Loop: 618#L652-2 assume !false; 619#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 688#L393-1 assume !false; 685#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 686#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 664#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 622#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 623#L346 assume !(0 != eval_~tmp~0#1); 716#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 787#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 818#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 811#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 812#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 809#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 765#L433-3 assume !(0 == ~E_1~0); 766#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 853#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 601#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 602#L197-12 assume 1 == ~m_pc~0; 859#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 731#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 732#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 614#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 615#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 728#L216-12 assume !(1 == ~t1_pc~0); 729#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 781#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 782#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 741#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 666#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 667#L235-12 assume 1 == ~t2_pc~0; 868#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 750#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 742#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 743#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 801#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 802#L254-12 assume 1 == ~t3_pc~0; 647#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 648#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 694#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 695#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 786#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 733#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 734#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 819#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 820#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 725#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 726#L481-3 assume !(1 == ~E_2~0); 757#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 758#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 641#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 642#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 671#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 821#L671 assume !(0 == start_simulation_~tmp~3#1); 625#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 846#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 723#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 691#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 692#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 829#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 830#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 831#L684 assume !(0 != start_simulation_~tmp___0~1#1); 618#L652-2 [2023-11-26 11:47:26,909 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:26,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1627783798, now seen corresponding path program 1 times [2023-11-26 11:47:26,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:26,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691924925] [2023-11-26 11:47:26,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:26,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:26,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:27,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:27,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:27,001 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [691924925] [2023-11-26 11:47:27,001 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [691924925] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:27,002 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:27,002 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:27,002 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [88997803] [2023-11-26 11:47:27,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:27,003 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:27,004 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:27,004 INFO L85 PathProgramCache]: Analyzing trace with hash 1274205792, now seen corresponding path program 1 times [2023-11-26 11:47:27,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:27,005 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832591178] [2023-11-26 11:47:27,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:27,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:27,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:27,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:27,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:27,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [832591178] [2023-11-26 11:47:27,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [832591178] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:27,138 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:27,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:27,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000500643] [2023-11-26 11:47:27,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:27,139 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:27,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:27,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:27,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:27,141 INFO L87 Difference]: Start difference. First operand 288 states and 428 transitions. cyclomatic complexity: 141 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:27,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:27,172 INFO L93 Difference]: Finished difference Result 288 states and 427 transitions. [2023-11-26 11:47:27,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 427 transitions. [2023-11-26 11:47:27,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-26 11:47:27,181 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 427 transitions. [2023-11-26 11:47:27,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2023-11-26 11:47:27,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2023-11-26 11:47:27,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 427 transitions. [2023-11-26 11:47:27,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:27,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 427 transitions. [2023-11-26 11:47:27,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 427 transitions. [2023-11-26 11:47:27,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2023-11-26 11:47:27,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4826388888888888) internal successors, (427), 287 states have internal predecessors, (427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:27,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 427 transitions. [2023-11-26 11:47:27,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 427 transitions. [2023-11-26 11:47:27,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:27,205 INFO L428 stractBuchiCegarLoop]: Abstraction has 288 states and 427 transitions. [2023-11-26 11:47:27,205 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:47:27,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 427 transitions. [2023-11-26 11:47:27,209 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-26 11:47:27,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:27,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:27,212 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:27,212 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:27,213 INFO L748 eck$LassoCheckResult]: Stem: 1440#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1450#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1449#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1424#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 1425#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1251#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1252#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1457#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1214#L418 assume !(0 == ~M_E~0); 1215#L418-2 assume !(0 == ~T1_E~0); 1423#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1460#L428-1 assume !(0 == ~T3_E~0); 1458#L433-1 assume !(0 == ~E_1~0); 1452#L438-1 assume !(0 == ~E_2~0); 1389#L443-1 assume !(0 == ~E_3~0); 1383#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1350#L197 assume !(1 == ~m_pc~0); 1347#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1346#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1416#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1417#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1190#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1191#L216 assume 1 == ~t1_pc~0; 1239#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1240#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1276#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1192#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1193#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1398#L235 assume !(1 == ~t2_pc~0); 1456#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1335#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1465#L526 assume !(0 != activate_threads_~tmp___1~0#1); 1466#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1318#L254 assume 1 == ~t3_pc~0; 1221#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1222#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1203#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1204#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1329#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1182#L461 assume !(1 == ~M_E~0); 1183#L461-2 assume !(1 == ~T1_E~0); 1253#L466-1 assume !(1 == ~T2_E~0); 1463#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1279#L476-1 assume !(1 == ~E_1~0); 1280#L481-1 assume !(1 == ~E_2~0); 1411#L486-1 assume !(1 == ~E_3~0); 1298#L491-1 assume { :end_inline_reset_delta_events } true; 1201#L652-2 [2023-11-26 11:47:27,213 INFO L750 eck$LassoCheckResult]: Loop: 1201#L652-2 assume !false; 1202#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1271#L393-1 assume !false; 1268#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1269#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1247#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1205#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1206#L346 assume !(0 != eval_~tmp~0#1); 1299#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1370#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1401#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1394#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1395#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1392#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1348#L433-3 assume !(0 == ~E_1~0); 1349#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1436#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1184#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1185#L197-12 assume 1 == ~m_pc~0; 1442#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1314#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1315#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1197#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1198#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1311#L216-12 assume !(1 == ~t1_pc~0); 1312#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1364#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1365#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1322#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1249#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1250#L235-12 assume !(1 == ~t2_pc~0); 1332#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1333#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1325#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1326#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1384#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1385#L254-12 assume !(1 == ~t3_pc~0); 1232#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 1231#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1277#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1278#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1369#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1316#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1317#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1402#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1403#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1308#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1309#L481-3 assume !(1 == ~E_2~0); 1340#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1341#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1224#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1225#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1254#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1404#L671 assume !(0 == start_simulation_~tmp~3#1); 1208#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1429#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1306#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1274#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1275#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1412#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1413#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1414#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1201#L652-2 [2023-11-26 11:47:27,214 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:27,214 INFO L85 PathProgramCache]: Analyzing trace with hash -1769790220, now seen corresponding path program 1 times [2023-11-26 11:47:27,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:27,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202315392] [2023-11-26 11:47:27,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:27,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:27,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:27,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:27,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:27,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1202315392] [2023-11-26 11:47:27,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1202315392] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:27,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:27,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:27,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876848748] [2023-11-26 11:47:27,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:27,279 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:27,280 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:27,280 INFO L85 PathProgramCache]: Analyzing trace with hash -1463002402, now seen corresponding path program 1 times [2023-11-26 11:47:27,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:27,281 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694489332] [2023-11-26 11:47:27,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:27,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:27,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:27,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:27,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:27,403 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694489332] [2023-11-26 11:47:27,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1694489332] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:27,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:27,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:27,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84061657] [2023-11-26 11:47:27,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:27,405 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:27,405 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:27,406 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:27,406 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:27,406 INFO L87 Difference]: Start difference. First operand 288 states and 427 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:27,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:27,442 INFO L93 Difference]: Finished difference Result 288 states and 426 transitions. [2023-11-26 11:47:27,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 426 transitions. [2023-11-26 11:47:27,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-26 11:47:27,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 426 transitions. [2023-11-26 11:47:27,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2023-11-26 11:47:27,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2023-11-26 11:47:27,451 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 426 transitions. [2023-11-26 11:47:27,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:27,453 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 426 transitions. [2023-11-26 11:47:27,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 426 transitions. [2023-11-26 11:47:27,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2023-11-26 11:47:27,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4791666666666667) internal successors, (426), 287 states have internal predecessors, (426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:27,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 426 transitions. [2023-11-26 11:47:27,483 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 426 transitions. [2023-11-26 11:47:27,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:27,484 INFO L428 stractBuchiCegarLoop]: Abstraction has 288 states and 426 transitions. [2023-11-26 11:47:27,485 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:47:27,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 426 transitions. [2023-11-26 11:47:27,488 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-26 11:47:27,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:27,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:27,490 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:27,491 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:27,491 INFO L748 eck$LassoCheckResult]: Stem: 2023#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2024#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2032#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2007#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2008#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1834#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1835#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2040#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1799#L418 assume !(0 == ~M_E~0); 1800#L418-2 assume !(0 == ~T1_E~0); 2006#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2043#L428-1 assume !(0 == ~T3_E~0); 2041#L433-1 assume !(0 == ~E_1~0); 2035#L438-1 assume !(0 == ~E_2~0); 1972#L443-1 assume !(0 == ~E_3~0); 1966#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1933#L197 assume !(1 == ~m_pc~0); 1930#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1929#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1999#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2000#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1773#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1774#L216 assume 1 == ~t1_pc~0; 1822#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1823#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1859#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1778#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1779#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1981#L235 assume !(1 == ~t2_pc~0); 2039#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1918#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2048#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2049#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1904#L254 assume 1 == ~t3_pc~0; 1804#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1805#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1788#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1789#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1912#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1765#L461 assume !(1 == ~M_E~0); 1766#L461-2 assume !(1 == ~T1_E~0); 1836#L466-1 assume !(1 == ~T2_E~0); 2046#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1862#L476-1 assume !(1 == ~E_1~0); 1863#L481-1 assume !(1 == ~E_2~0); 1994#L486-1 assume !(1 == ~E_3~0); 1881#L491-1 assume { :end_inline_reset_delta_events } true; 1784#L652-2 [2023-11-26 11:47:27,491 INFO L750 eck$LassoCheckResult]: Loop: 1784#L652-2 assume !false; 1785#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1852#L393-1 assume !false; 1855#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1856#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1830#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1786#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1787#L346 assume !(0 != eval_~tmp~0#1); 1882#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1953#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1984#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1977#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1978#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1973#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1931#L433-3 assume !(0 == ~E_1~0); 1932#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2017#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1767#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1768#L197-12 assume 1 == ~m_pc~0; 2025#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1897#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1898#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1780#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1781#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1894#L216-12 assume !(1 == ~t1_pc~0); 1895#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1947#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1948#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1907#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1832#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1833#L235-12 assume 1 == ~t2_pc~0; 2034#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1916#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1908#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1909#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1967#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1968#L254-12 assume 1 == ~t3_pc~0; 1813#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1814#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1860#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1861#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1952#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1899#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1900#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1985#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1986#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1891#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1892#L481-3 assume !(1 == ~E_2~0); 1923#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1924#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1810#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1811#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1837#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1987#L671 assume !(0 == start_simulation_~tmp~3#1); 1793#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2012#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1889#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1857#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1858#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1995#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1996#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1997#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1784#L652-2 [2023-11-26 11:47:27,492 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:27,517 INFO L85 PathProgramCache]: Analyzing trace with hash -2017936714, now seen corresponding path program 1 times [2023-11-26 11:47:27,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:27,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770008151] [2023-11-26 11:47:27,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:27,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:27,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:27,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:27,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:27,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770008151] [2023-11-26 11:47:27,667 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770008151] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:27,667 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:27,668 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:27,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497851579] [2023-11-26 11:47:27,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:27,669 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:27,669 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:27,669 INFO L85 PathProgramCache]: Analyzing trace with hash 1274205792, now seen corresponding path program 2 times [2023-11-26 11:47:27,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:27,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864655684] [2023-11-26 11:47:27,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:27,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:27,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:27,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:27,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:27,719 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864655684] [2023-11-26 11:47:27,720 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864655684] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:27,720 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:27,720 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:27,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404841774] [2023-11-26 11:47:27,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:27,721 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:27,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:27,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:27,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:27,722 INFO L87 Difference]: Start difference. First operand 288 states and 426 transitions. cyclomatic complexity: 139 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:27,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:27,741 INFO L93 Difference]: Finished difference Result 288 states and 421 transitions. [2023-11-26 11:47:27,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 421 transitions. [2023-11-26 11:47:27,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-26 11:47:27,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 421 transitions. [2023-11-26 11:47:27,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2023-11-26 11:47:27,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2023-11-26 11:47:27,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 421 transitions. [2023-11-26 11:47:27,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:27,749 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 421 transitions. [2023-11-26 11:47:27,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 421 transitions. [2023-11-26 11:47:27,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2023-11-26 11:47:27,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4618055555555556) internal successors, (421), 287 states have internal predecessors, (421), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:27,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 421 transitions. [2023-11-26 11:47:27,758 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 421 transitions. [2023-11-26 11:47:27,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:27,760 INFO L428 stractBuchiCegarLoop]: Abstraction has 288 states and 421 transitions. [2023-11-26 11:47:27,760 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:47:27,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 421 transitions. [2023-11-26 11:47:27,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-26 11:47:27,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:27,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:27,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:27,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:27,765 INFO L748 eck$LassoCheckResult]: Stem: 2606#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2607#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2590#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2591#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2417#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2418#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2623#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2377#L418 assume !(0 == ~M_E~0); 2378#L418-2 assume !(0 == ~T1_E~0); 2589#L423-1 assume !(0 == ~T2_E~0); 2626#L428-1 assume !(0 == ~T3_E~0); 2624#L433-1 assume !(0 == ~E_1~0); 2618#L438-1 assume !(0 == ~E_2~0); 2555#L443-1 assume !(0 == ~E_3~0); 2549#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2516#L197 assume !(1 == ~m_pc~0); 2513#L197-2 is_master_triggered_~__retres1~0#1 := 0; 2512#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2582#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2583#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2356#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2357#L216 assume 1 == ~t1_pc~0; 2405#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2406#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2442#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2358#L518 assume !(0 != activate_threads_~tmp___0~0#1); 2359#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2562#L235 assume !(1 == ~t2_pc~0); 2620#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2500#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2631#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2632#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2484#L254 assume 1 == ~t3_pc~0; 2387#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2388#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2369#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2370#L534 assume !(0 != activate_threads_~tmp___2~0#1); 2495#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2348#L461 assume !(1 == ~M_E~0); 2349#L461-2 assume !(1 == ~T1_E~0); 2419#L466-1 assume !(1 == ~T2_E~0); 2629#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2443#L476-1 assume !(1 == ~E_1~0); 2444#L481-1 assume !(1 == ~E_2~0); 2577#L486-1 assume !(1 == ~E_3~0); 2460#L491-1 assume { :end_inline_reset_delta_events } true; 2365#L652-2 [2023-11-26 11:47:27,766 INFO L750 eck$LassoCheckResult]: Loop: 2365#L652-2 assume !false; 2366#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2437#L393-1 assume !false; 2434#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2435#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2413#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2371#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2372#L346 assume !(0 != eval_~tmp~0#1); 2465#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2536#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2567#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2560#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2561#L423-3 assume !(0 == ~T2_E~0); 2556#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2514#L433-3 assume !(0 == ~E_1~0); 2515#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2600#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2350#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2351#L197-12 assume 1 == ~m_pc~0; 2608#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2480#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2481#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2363#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2364#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2477#L216-12 assume !(1 == ~t1_pc~0); 2478#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 2530#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2531#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2490#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2415#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2416#L235-12 assume !(1 == ~t2_pc~0); 2498#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 2499#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2491#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2492#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2550#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2551#L254-12 assume 1 == ~t3_pc~0; 2396#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2397#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2445#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2446#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2535#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2482#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2483#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2568#L466-3 assume !(1 == ~T2_E~0); 2569#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2474#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2475#L481-3 assume !(1 == ~E_2~0); 2506#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2507#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2393#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2394#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2570#L671 assume !(0 == start_simulation_~tmp~3#1); 2376#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2595#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2472#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2440#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 2441#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2578#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2579#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2580#L684 assume !(0 != start_simulation_~tmp___0~1#1); 2365#L652-2 [2023-11-26 11:47:27,766 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:27,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1247671284, now seen corresponding path program 1 times [2023-11-26 11:47:27,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:27,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993632324] [2023-11-26 11:47:27,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:27,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:27,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:27,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:27,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:27,871 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [993632324] [2023-11-26 11:47:27,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [993632324] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:27,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:27,872 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:47:27,873 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2008697235] [2023-11-26 11:47:27,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:27,873 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:27,874 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:27,874 INFO L85 PathProgramCache]: Analyzing trace with hash -282044549, now seen corresponding path program 1 times [2023-11-26 11:47:27,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:27,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [945831445] [2023-11-26 11:47:27,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:27,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:27,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:27,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:27,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:27,922 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [945831445] [2023-11-26 11:47:27,922 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [945831445] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:27,922 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:27,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:27,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075014932] [2023-11-26 11:47:27,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:27,924 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:27,924 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:27,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:47:27,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:47:27,925 INFO L87 Difference]: Start difference. First operand 288 states and 421 transitions. cyclomatic complexity: 134 Second operand has 5 states, 5 states have (on average 9.8) internal successors, (49), 5 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:28,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:28,125 INFO L93 Difference]: Finished difference Result 673 states and 968 transitions. [2023-11-26 11:47:28,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 673 states and 968 transitions. [2023-11-26 11:47:28,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 565 [2023-11-26 11:47:28,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 673 states to 673 states and 968 transitions. [2023-11-26 11:47:28,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 673 [2023-11-26 11:47:28,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 673 [2023-11-26 11:47:28,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 673 states and 968 transitions. [2023-11-26 11:47:28,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:28,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 673 states and 968 transitions. [2023-11-26 11:47:28,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 673 states and 968 transitions. [2023-11-26 11:47:28,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 673 to 306. [2023-11-26 11:47:28,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 306 states, 306 states have (on average 1.434640522875817) internal successors, (439), 305 states have internal predecessors, (439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:28,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 306 states to 306 states and 439 transitions. [2023-11-26 11:47:28,154 INFO L240 hiAutomatonCegarLoop]: Abstraction has 306 states and 439 transitions. [2023-11-26 11:47:28,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:47:28,157 INFO L428 stractBuchiCegarLoop]: Abstraction has 306 states and 439 transitions. [2023-11-26 11:47:28,157 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:47:28,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 306 states and 439 transitions. [2023-11-26 11:47:28,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 250 [2023-11-26 11:47:28,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:28,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:28,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:28,161 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:28,162 INFO L748 eck$LassoCheckResult]: Stem: 3588#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 3589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3599#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3597#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3571#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 3572#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3391#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3392#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3607#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3354#L418 assume !(0 == ~M_E~0); 3355#L418-2 assume !(0 == ~T1_E~0); 3570#L423-1 assume !(0 == ~T2_E~0); 3610#L428-1 assume !(0 == ~T3_E~0); 3608#L433-1 assume !(0 == ~E_1~0); 3601#L438-1 assume !(0 == ~E_2~0); 3533#L443-1 assume !(0 == ~E_3~0); 3527#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3490#L197 assume !(1 == ~m_pc~0); 3487#L197-2 is_master_triggered_~__retres1~0#1 := 0; 3624#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3625#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3616#L510 assume !(0 != activate_threads_~tmp~1#1); 3330#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3331#L216 assume 1 == ~t1_pc~0; 3379#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3380#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3332#L518 assume !(0 != activate_threads_~tmp___0~0#1); 3333#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3543#L235 assume !(1 == ~t2_pc~0); 3603#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3475#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3476#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3618#L526 assume !(0 != activate_threads_~tmp___1~0#1); 3619#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3458#L254 assume 1 == ~t3_pc~0; 3361#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3362#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3343#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3344#L534 assume !(0 != activate_threads_~tmp___2~0#1); 3469#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3322#L461 assume !(1 == ~M_E~0); 3323#L461-2 assume !(1 == ~T1_E~0); 3393#L466-1 assume !(1 == ~T2_E~0); 3614#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3419#L476-1 assume !(1 == ~E_1~0); 3420#L481-1 assume !(1 == ~E_2~0); 3558#L486-1 assume !(1 == ~E_3~0); 3436#L491-1 assume { :end_inline_reset_delta_events } true; 3341#L652-2 [2023-11-26 11:47:28,162 INFO L750 eck$LassoCheckResult]: Loop: 3341#L652-2 assume !false; 3342#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3411#L393-1 assume !false; 3408#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3409#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3387#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3345#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3346#L346 assume !(0 != eval_~tmp~0#1); 3439#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3512#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3547#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3540#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3541#L423-3 assume !(0 == ~T2_E~0); 3536#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3488#L433-3 assume !(0 == ~E_1~0); 3489#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3583#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3324#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3325#L197-12 assume 1 == ~m_pc~0; 3590#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3598#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3538#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3539#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3338#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3451#L216-12 assume !(1 == ~t1_pc~0); 3452#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 3506#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3507#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3464#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3389#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3390#L235-12 assume 1 == ~t2_pc~0; 3600#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3473#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3465#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3466#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3528#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3529#L254-12 assume 1 == ~t3_pc~0; 3370#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3371#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3417#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3418#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3511#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3456#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3457#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3548#L466-3 assume !(1 == ~T2_E~0); 3549#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3448#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3449#L481-3 assume !(1 == ~E_2~0); 3480#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3481#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3364#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3365#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3394#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3550#L671 assume !(0 == start_simulation_~tmp~3#1); 3348#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3576#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3446#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 3415#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3559#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3560#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3561#L684 assume !(0 != start_simulation_~tmp___0~1#1); 3341#L652-2 [2023-11-26 11:47:28,163 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:28,163 INFO L85 PathProgramCache]: Analyzing trace with hash 738198194, now seen corresponding path program 1 times [2023-11-26 11:47:28,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:28,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087425369] [2023-11-26 11:47:28,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:28,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:28,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:28,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:28,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:28,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087425369] [2023-11-26 11:47:28,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1087425369] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:28,246 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:28,246 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:28,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278679915] [2023-11-26 11:47:28,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:28,247 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:28,248 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:28,248 INFO L85 PathProgramCache]: Analyzing trace with hash -1201019172, now seen corresponding path program 1 times [2023-11-26 11:47:28,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:28,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455437931] [2023-11-26 11:47:28,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:28,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:28,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:28,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:28,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:28,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455437931] [2023-11-26 11:47:28,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455437931] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:28,352 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:28,352 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:28,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238233453] [2023-11-26 11:47:28,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:28,355 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:28,355 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:28,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:28,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:28,356 INFO L87 Difference]: Start difference. First operand 306 states and 439 transitions. cyclomatic complexity: 134 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:28,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:28,411 INFO L93 Difference]: Finished difference Result 517 states and 735 transitions. [2023-11-26 11:47:28,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 517 states and 735 transitions. [2023-11-26 11:47:28,417 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 460 [2023-11-26 11:47:28,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 517 states to 517 states and 735 transitions. [2023-11-26 11:47:28,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 517 [2023-11-26 11:47:28,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 517 [2023-11-26 11:47:28,425 INFO L73 IsDeterministic]: Start isDeterministic. Operand 517 states and 735 transitions. [2023-11-26 11:47:28,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:28,426 INFO L218 hiAutomatonCegarLoop]: Abstraction has 517 states and 735 transitions. [2023-11-26 11:47:28,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states and 735 transitions. [2023-11-26 11:47:28,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 515. [2023-11-26 11:47:28,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 515 states, 515 states have (on average 1.4233009708737865) internal successors, (733), 514 states have internal predecessors, (733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:28,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 515 states to 515 states and 733 transitions. [2023-11-26 11:47:28,442 INFO L240 hiAutomatonCegarLoop]: Abstraction has 515 states and 733 transitions. [2023-11-26 11:47:28,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:28,445 INFO L428 stractBuchiCegarLoop]: Abstraction has 515 states and 733 transitions. [2023-11-26 11:47:28,445 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:47:28,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 515 states and 733 transitions. [2023-11-26 11:47:28,453 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 458 [2023-11-26 11:47:28,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:28,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:28,458 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:28,458 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:28,460 INFO L748 eck$LassoCheckResult]: Stem: 4415#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 4416#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4426#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4424#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4398#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 4399#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4219#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4220#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4434#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4181#L418 assume !(0 == ~M_E~0); 4182#L418-2 assume !(0 == ~T1_E~0); 4397#L423-1 assume !(0 == ~T2_E~0); 4437#L428-1 assume !(0 == ~T3_E~0); 4435#L433-1 assume !(0 == ~E_1~0); 4428#L438-1 assume !(0 == ~E_2~0); 4359#L443-1 assume !(0 == ~E_3~0); 4352#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4317#L197 assume !(1 == ~m_pc~0); 4314#L197-2 is_master_triggered_~__retres1~0#1 := 0; 4454#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4390#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4391#L510 assume !(0 != activate_threads_~tmp~1#1); 4160#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4161#L216 assume !(1 == ~t1_pc~0); 4215#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4216#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4244#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4162#L518 assume !(0 != activate_threads_~tmp___0~0#1); 4163#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4367#L235 assume !(1 == ~t2_pc~0); 4430#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4302#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4303#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4449#L526 assume !(0 != activate_threads_~tmp___1~0#1); 4450#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4285#L254 assume 1 == ~t3_pc~0; 4191#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4192#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4173#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4174#L534 assume !(0 != activate_threads_~tmp___2~0#1); 4296#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4152#L461 assume !(1 == ~M_E~0); 4153#L461-2 assume !(1 == ~T1_E~0); 4221#L466-1 assume !(1 == ~T2_E~0); 4440#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4245#L476-1 assume !(1 == ~E_1~0); 4246#L481-1 assume !(1 == ~E_2~0); 4382#L486-1 assume !(1 == ~E_3~0); 4262#L491-1 assume { :end_inline_reset_delta_events } true; 4169#L652-2 [2023-11-26 11:47:28,460 INFO L750 eck$LassoCheckResult]: Loop: 4169#L652-2 assume !false; 4170#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4239#L393-1 assume !false; 4236#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4237#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4213#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4175#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4176#L346 assume !(0 != eval_~tmp~0#1); 4267#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4337#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4371#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4499#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4497#L423-3 assume !(0 == ~T2_E~0); 4360#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4315#L433-3 assume !(0 == ~E_1~0); 4316#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4408#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4154#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4155#L197-12 assume 1 == ~m_pc~0; 4417#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4425#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4613#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4612#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4168#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4279#L216-12 assume !(1 == ~t1_pc~0); 4280#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 4645#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4642#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4640#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4638#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4636#L235-12 assume 1 == ~t2_pc~0; 4633#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4631#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4628#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4626#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4624#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4623#L254-12 assume !(1 == ~t3_pc~0); 4621#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 4620#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4619#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4618#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4617#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4616#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4615#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4372#L466-3 assume !(1 == ~T2_E~0); 4373#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4276#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4277#L481-3 assume !(1 == ~E_2~0); 4307#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4308#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4196#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4197#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4222#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4374#L671 assume !(0 == start_simulation_~tmp~3#1); 4178#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4403#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4274#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4242#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 4243#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4384#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4385#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4387#L684 assume !(0 != start_simulation_~tmp___0~1#1); 4169#L652-2 [2023-11-26 11:47:28,461 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:28,463 INFO L85 PathProgramCache]: Analyzing trace with hash 1376982673, now seen corresponding path program 1 times [2023-11-26 11:47:28,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:28,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404311202] [2023-11-26 11:47:28,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:28,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:28,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:28,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:28,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:28,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404311202] [2023-11-26 11:47:28,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [404311202] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:28,575 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:28,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:28,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577607569] [2023-11-26 11:47:28,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:28,577 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:28,577 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:28,577 INFO L85 PathProgramCache]: Analyzing trace with hash -562234693, now seen corresponding path program 1 times [2023-11-26 11:47:28,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:28,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376300230] [2023-11-26 11:47:28,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:28,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:28,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:28,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:28,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:28,629 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376300230] [2023-11-26 11:47:28,630 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376300230] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:28,630 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:28,630 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:28,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039021606] [2023-11-26 11:47:28,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:28,632 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:28,632 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:28,632 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:28,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:28,633 INFO L87 Difference]: Start difference. First operand 515 states and 733 transitions. cyclomatic complexity: 220 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:28,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:28,682 INFO L93 Difference]: Finished difference Result 961 states and 1352 transitions. [2023-11-26 11:47:28,682 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 961 states and 1352 transitions. [2023-11-26 11:47:28,692 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 901 [2023-11-26 11:47:28,704 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 961 states to 961 states and 1352 transitions. [2023-11-26 11:47:28,704 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 961 [2023-11-26 11:47:28,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 961 [2023-11-26 11:47:28,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 961 states and 1352 transitions. [2023-11-26 11:47:28,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:28,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 961 states and 1352 transitions. [2023-11-26 11:47:28,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 961 states and 1352 transitions. [2023-11-26 11:47:28,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 961 to 957. [2023-11-26 11:47:28,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 957 states have (on average 1.4085684430512018) internal successors, (1348), 956 states have internal predecessors, (1348), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:28,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1348 transitions. [2023-11-26 11:47:28,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 957 states and 1348 transitions. [2023-11-26 11:47:28,735 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:28,738 INFO L428 stractBuchiCegarLoop]: Abstraction has 957 states and 1348 transitions. [2023-11-26 11:47:28,738 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:47:28,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 957 states and 1348 transitions. [2023-11-26 11:47:28,745 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2023-11-26 11:47:28,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:28,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:28,746 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:28,746 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:28,747 INFO L748 eck$LassoCheckResult]: Stem: 5903#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 5904#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 5916#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5914#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5885#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 5886#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5699#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5700#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5927#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5664#L418 assume !(0 == ~M_E~0); 5665#L418-2 assume !(0 == ~T1_E~0); 5884#L423-1 assume !(0 == ~T2_E~0); 5931#L428-1 assume !(0 == ~T3_E~0); 5929#L433-1 assume !(0 == ~E_1~0); 5918#L438-1 assume !(0 == ~E_2~0); 5844#L443-1 assume !(0 == ~E_3~0); 5837#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5800#L197 assume !(1 == ~m_pc~0); 5797#L197-2 is_master_triggered_~__retres1~0#1 := 0; 5947#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5877#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5878#L510 assume !(0 != activate_threads_~tmp~1#1); 5643#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5644#L216 assume !(1 == ~t1_pc~0); 5695#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5696#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5726#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5645#L518 assume !(0 != activate_threads_~tmp___0~0#1); 5646#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5852#L235 assume !(1 == ~t2_pc~0); 5924#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5784#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5785#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5941#L526 assume !(0 != activate_threads_~tmp___1~0#1); 5942#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5768#L254 assume !(1 == ~t3_pc~0); 5703#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5704#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5656#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5657#L534 assume !(0 != activate_threads_~tmp___2~0#1); 5779#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5635#L461 assume !(1 == ~M_E~0); 5636#L461-2 assume !(1 == ~T1_E~0); 5701#L466-1 assume !(1 == ~T2_E~0); 5934#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5727#L476-1 assume !(1 == ~E_1~0); 5728#L481-1 assume !(1 == ~E_2~0); 5868#L486-1 assume !(1 == ~E_3~0); 5744#L491-1 assume { :end_inline_reset_delta_events } true; 5652#L652-2 [2023-11-26 11:47:28,747 INFO L750 eck$LassoCheckResult]: Loop: 5652#L652-2 assume !false; 5653#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5721#L393-1 assume !false; 5718#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5719#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5693#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5658#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5659#L346 assume !(0 != eval_~tmp~0#1); 5749#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6577#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6575#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6573#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6571#L423-3 assume !(0 == ~T2_E~0); 6568#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6566#L433-3 assume !(0 == ~E_1~0); 6565#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6564#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6563#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6562#L197-12 assume 1 == ~m_pc~0; 6560#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6558#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6555#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6552#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6551#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5762#L216-12 assume !(1 == ~t1_pc~0); 5763#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 5814#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5815#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5772#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5697#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5698#L235-12 assume !(1 == ~t2_pc~0); 5782#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 5783#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5775#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5776#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5838#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5839#L254-12 assume !(1 == ~t3_pc~0); 5936#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 5843#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5729#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5730#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5820#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5766#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5767#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5857#L466-3 assume !(1 == ~T2_E~0); 5858#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5759#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5760#L481-3 assume !(1 == ~E_2~0); 5790#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5791#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5676#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5677#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5702#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5859#L671 assume !(0 == start_simulation_~tmp~3#1); 5663#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5891#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5757#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5724#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 5725#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5873#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5874#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 5875#L684 assume !(0 != start_simulation_~tmp___0~1#1); 5652#L652-2 [2023-11-26 11:47:28,748 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:28,748 INFO L85 PathProgramCache]: Analyzing trace with hash 372621552, now seen corresponding path program 1 times [2023-11-26 11:47:28,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:28,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342645121] [2023-11-26 11:47:28,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:28,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:28,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:28,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:28,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:28,818 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342645121] [2023-11-26 11:47:28,818 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1342645121] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:28,818 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:28,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:28,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173295186] [2023-11-26 11:47:28,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:28,819 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:28,820 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:28,820 INFO L85 PathProgramCache]: Analyzing trace with hash 356739930, now seen corresponding path program 1 times [2023-11-26 11:47:28,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:28,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954327432] [2023-11-26 11:47:28,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:28,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:28,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:28,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:28,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:28,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954327432] [2023-11-26 11:47:28,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [954327432] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:28,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:28,872 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:28,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261618364] [2023-11-26 11:47:28,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:28,873 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:28,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:28,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:47:28,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:47:28,874 INFO L87 Difference]: Start difference. First operand 957 states and 1348 transitions. cyclomatic complexity: 395 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:28,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:28,972 INFO L93 Difference]: Finished difference Result 2053 states and 2878 transitions. [2023-11-26 11:47:28,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2053 states and 2878 transitions. [2023-11-26 11:47:28,991 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1946 [2023-11-26 11:47:29,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2053 states to 2053 states and 2878 transitions. [2023-11-26 11:47:29,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2053 [2023-11-26 11:47:29,015 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2053 [2023-11-26 11:47:29,015 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2053 states and 2878 transitions. [2023-11-26 11:47:29,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:29,018 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2053 states and 2878 transitions. [2023-11-26 11:47:29,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2053 states and 2878 transitions. [2023-11-26 11:47:29,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2053 to 1146. [2023-11-26 11:47:29,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1146 states, 1146 states have (on average 1.4013961605584642) internal successors, (1606), 1145 states have internal predecessors, (1606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:29,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1146 states to 1146 states and 1606 transitions. [2023-11-26 11:47:29,052 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1146 states and 1606 transitions. [2023-11-26 11:47:29,052 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:47:29,055 INFO L428 stractBuchiCegarLoop]: Abstraction has 1146 states and 1606 transitions. [2023-11-26 11:47:29,055 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 11:47:29,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1146 states and 1606 transitions. [2023-11-26 11:47:29,062 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1049 [2023-11-26 11:47:29,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:29,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:29,089 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:29,089 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:29,090 INFO L748 eck$LassoCheckResult]: Stem: 8935#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 8936#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8950#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8947#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8917#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 8918#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8718#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8719#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8962#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8684#L418 assume !(0 == ~M_E~0); 8685#L418-2 assume !(0 == ~T1_E~0); 8916#L423-1 assume !(0 == ~T2_E~0); 8969#L428-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8974#L433-1 assume !(0 == ~E_1~0); 8952#L438-1 assume !(0 == ~E_2~0); 8953#L443-1 assume !(0 == ~E_3~0); 8868#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8869#L197 assume !(1 == ~m_pc~0); 8823#L197-2 is_master_triggered_~__retres1~0#1 := 0; 8995#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8909#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8910#L510 assume !(0 != activate_threads_~tmp~1#1); 8663#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8664#L216 assume !(1 == ~t1_pc~0); 8714#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8715#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9029#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9028#L518 assume !(0 != activate_threads_~tmp___0~0#1); 9027#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9026#L235 assume !(1 == ~t2_pc~0); 9025#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9023#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9007#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8984#L526 assume !(0 != activate_threads_~tmp___1~0#1); 8985#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8790#L254 assume !(1 == ~t3_pc~0); 8791#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8816#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8817#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8852#L534 assume !(0 != activate_threads_~tmp___2~0#1); 8853#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9020#L461 assume !(1 == ~M_E~0); 8720#L461-2 assume !(1 == ~T1_E~0); 8721#L466-1 assume !(1 == ~T2_E~0); 8973#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8749#L476-1 assume !(1 == ~E_1~0); 8750#L481-1 assume !(1 == ~E_2~0); 8902#L486-1 assume !(1 == ~E_3~0); 8765#L491-1 assume { :end_inline_reset_delta_events } true; 8766#L652-2 [2023-11-26 11:47:29,090 INFO L750 eck$LassoCheckResult]: Loop: 8766#L652-2 assume !false; 9327#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8741#L393-1 assume !false; 9325#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9323#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9318#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9316#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9312#L346 assume !(0 != eval_~tmp~0#1); 9313#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9413#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9410#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9407#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9404#L423-3 assume !(0 == ~T2_E~0); 9400#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9399#L433-3 assume !(0 == ~E_1~0); 9398#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9397#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9396#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9395#L197-12 assume 1 == ~m_pc~0; 9393#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9391#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9389#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9387#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9386#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9385#L216-12 assume !(1 == ~t1_pc~0); 9384#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 9383#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9382#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9381#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9380#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9379#L235-12 assume 1 == ~t2_pc~0; 9377#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9376#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9375#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9374#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9373#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9372#L254-12 assume !(1 == ~t3_pc~0); 9371#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 9370#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9369#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9368#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9367#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9366#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9365#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9364#L466-3 assume !(1 == ~T2_E~0); 9362#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9360#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9358#L481-3 assume !(1 == ~E_2~0); 9356#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9354#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9352#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9347#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9345#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 9342#L671 assume !(0 == start_simulation_~tmp~3#1); 9341#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9339#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9336#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9335#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 9334#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9333#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9330#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 9328#L684 assume !(0 != start_simulation_~tmp___0~1#1); 8766#L652-2 [2023-11-26 11:47:29,090 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:29,091 INFO L85 PathProgramCache]: Analyzing trace with hash -286909970, now seen corresponding path program 1 times [2023-11-26 11:47:29,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:29,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541688971] [2023-11-26 11:47:29,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:29,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:29,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:29,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:29,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:29,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541688971] [2023-11-26 11:47:29,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541688971] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:29,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:29,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:29,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812995050] [2023-11-26 11:47:29,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:29,143 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:29,143 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:29,143 INFO L85 PathProgramCache]: Analyzing trace with hash -562234693, now seen corresponding path program 2 times [2023-11-26 11:47:29,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:29,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513414910] [2023-11-26 11:47:29,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:29,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:29,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:29,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:29,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:29,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513414910] [2023-11-26 11:47:29,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [513414910] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:29,178 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:29,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:29,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [576239354] [2023-11-26 11:47:29,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:29,178 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:29,179 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:29,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:47:29,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:47:29,179 INFO L87 Difference]: Start difference. First operand 1146 states and 1606 transitions. cyclomatic complexity: 464 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:29,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:29,220 INFO L93 Difference]: Finished difference Result 957 states and 1334 transitions. [2023-11-26 11:47:29,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 957 states and 1334 transitions. [2023-11-26 11:47:29,227 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2023-11-26 11:47:29,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 957 states to 957 states and 1334 transitions. [2023-11-26 11:47:29,235 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 957 [2023-11-26 11:47:29,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 957 [2023-11-26 11:47:29,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 957 states and 1334 transitions. [2023-11-26 11:47:29,238 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:29,238 INFO L218 hiAutomatonCegarLoop]: Abstraction has 957 states and 1334 transitions. [2023-11-26 11:47:29,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states and 1334 transitions. [2023-11-26 11:47:29,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 957. [2023-11-26 11:47:29,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 957 states have (on average 1.393939393939394) internal successors, (1334), 956 states have internal predecessors, (1334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:29,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1334 transitions. [2023-11-26 11:47:29,260 INFO L240 hiAutomatonCegarLoop]: Abstraction has 957 states and 1334 transitions. [2023-11-26 11:47:29,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:29,261 INFO L428 stractBuchiCegarLoop]: Abstraction has 957 states and 1334 transitions. [2023-11-26 11:47:29,261 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 11:47:29,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 957 states and 1334 transitions. [2023-11-26 11:47:29,266 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2023-11-26 11:47:29,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:29,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:29,268 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:29,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:29,268 INFO L748 eck$LassoCheckResult]: Stem: 11037#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 11038#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 11054#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11051#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11021#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 11022#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10831#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10832#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11063#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10801#L418 assume !(0 == ~M_E~0); 10802#L418-2 assume !(0 == ~T1_E~0); 11020#L423-1 assume !(0 == ~T2_E~0); 11066#L428-1 assume !(0 == ~T3_E~0); 11064#L433-1 assume !(0 == ~E_1~0); 11056#L438-1 assume !(0 == ~E_2~0); 10976#L443-1 assume !(0 == ~E_3~0); 10970#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10934#L197 assume !(1 == ~m_pc~0); 10931#L197-2 is_master_triggered_~__retres1~0#1 := 0; 11091#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11012#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11013#L510 assume !(0 != activate_threads_~tmp~1#1); 10776#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10777#L216 assume !(1 == ~t1_pc~0); 10829#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10830#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10858#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10778#L518 assume !(0 != activate_threads_~tmp___0~0#1); 10779#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10988#L235 assume !(1 == ~t2_pc~0); 11062#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10917#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10918#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11081#L526 assume !(0 != activate_threads_~tmp___1~0#1); 11082#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10900#L254 assume !(1 == ~t3_pc~0); 10835#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10836#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10789#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10790#L534 assume !(0 != activate_threads_~tmp___2~0#1); 10911#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10768#L461 assume !(1 == ~M_E~0); 10769#L461-2 assume !(1 == ~T1_E~0); 10833#L466-1 assume !(1 == ~T2_E~0); 11071#L471-1 assume !(1 == ~T3_E~0); 10861#L476-1 assume !(1 == ~E_1~0); 10862#L481-1 assume !(1 == ~E_2~0); 11004#L486-1 assume !(1 == ~E_3~0); 10879#L491-1 assume { :end_inline_reset_delta_events } true; 10880#L652-2 [2023-11-26 11:47:29,268 INFO L750 eck$LassoCheckResult]: Loop: 10880#L652-2 assume !false; 11508#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10855#L393-1 assume !false; 11504#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11503#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11494#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 10791#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10792#L346 assume !(0 != eval_~tmp~0#1); 10881#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10955#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10991#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10984#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10985#L423-3 assume !(0 == ~T2_E~0); 10979#L428-3 assume !(0 == ~T3_E~0); 10932#L433-3 assume !(0 == ~E_1~0); 10933#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11034#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10770#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10771#L197-12 assume 1 == ~m_pc~0; 11040#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11052#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11688#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11122#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11123#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11638#L216-12 assume !(1 == ~t1_pc~0); 11636#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 11634#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11632#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11630#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11628#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11626#L235-12 assume 1 == ~t2_pc~0; 11623#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11621#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11619#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11617#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11615#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11074#L254-12 assume !(1 == ~t3_pc~0); 11075#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 11080#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11613#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11611#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11609#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11607#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11605#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11603#L466-3 assume !(1 == ~T2_E~0); 11601#L471-3 assume !(1 == ~T3_E~0); 11599#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11597#L481-3 assume !(1 == ~E_2~0); 11595#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11593#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11591#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11586#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11584#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 11532#L671 assume !(0 == start_simulation_~tmp~3#1); 11530#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11526#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11523#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11522#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 11520#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11518#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11516#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 11515#L684 assume !(0 != start_simulation_~tmp___0~1#1); 10880#L652-2 [2023-11-26 11:47:29,269 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:29,269 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2023-11-26 11:47:29,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:29,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655512090] [2023-11-26 11:47:29,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:29,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:29,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:29,278 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:29,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:29,310 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:29,311 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:29,311 INFO L85 PathProgramCache]: Analyzing trace with hash 2128865983, now seen corresponding path program 1 times [2023-11-26 11:47:29,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:29,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1250568376] [2023-11-26 11:47:29,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:29,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:29,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:29,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:29,344 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:29,344 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1250568376] [2023-11-26 11:47:29,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1250568376] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:29,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:29,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:29,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [637230459] [2023-11-26 11:47:29,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:29,345 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:29,346 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:29,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:29,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:29,346 INFO L87 Difference]: Start difference. First operand 957 states and 1334 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:29,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:29,447 INFO L93 Difference]: Finished difference Result 1656 states and 2278 transitions. [2023-11-26 11:47:29,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1656 states and 2278 transitions. [2023-11-26 11:47:29,464 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1553 [2023-11-26 11:47:29,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1656 states to 1656 states and 2278 transitions. [2023-11-26 11:47:29,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1656 [2023-11-26 11:47:29,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1656 [2023-11-26 11:47:29,483 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1656 states and 2278 transitions. [2023-11-26 11:47:29,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:29,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1656 states and 2278 transitions. [2023-11-26 11:47:29,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1656 states and 2278 transitions. [2023-11-26 11:47:29,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1656 to 1654. [2023-11-26 11:47:29,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1654 states, 1654 states have (on average 1.3760580411124546) internal successors, (2276), 1653 states have internal predecessors, (2276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:29,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1654 states to 1654 states and 2276 transitions. [2023-11-26 11:47:29,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1654 states and 2276 transitions. [2023-11-26 11:47:29,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:29,542 INFO L428 stractBuchiCegarLoop]: Abstraction has 1654 states and 2276 transitions. [2023-11-26 11:47:29,542 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 11:47:29,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1654 states and 2276 transitions. [2023-11-26 11:47:29,555 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1551 [2023-11-26 11:47:29,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:29,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:29,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:29,557 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:29,558 INFO L748 eck$LassoCheckResult]: Stem: 13677#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 13678#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 13690#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13687#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13660#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 13661#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13451#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13452#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13703#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13421#L418 assume !(0 == ~M_E~0); 13422#L418-2 assume !(0 == ~T1_E~0); 13659#L423-1 assume !(0 == ~T2_E~0); 13706#L428-1 assume !(0 == ~T3_E~0); 13704#L433-1 assume !(0 == ~E_1~0); 13693#L438-1 assume 0 == ~E_2~0;~E_2~0 := 1; 13611#L443-1 assume !(0 == ~E_3~0); 13603#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13604#L197 assume !(1 == ~m_pc~0); 13553#L197-2 is_master_triggered_~__retres1~0#1 := 0; 13736#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13804#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13718#L510 assume !(0 != activate_threads_~tmp~1#1); 13719#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13737#L216 assume !(1 == ~t1_pc~0); 13449#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13450#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13480#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13400#L518 assume !(0 != activate_threads_~tmp___0~0#1); 13401#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13621#L235 assume !(1 == ~t2_pc~0); 13702#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13539#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13540#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13725#L526 assume !(0 != activate_threads_~tmp___1~0#1); 13726#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13781#L254 assume !(1 == ~t3_pc~0); 13779#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13777#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13774#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13771#L534 assume !(0 != activate_threads_~tmp___2~0#1); 13768#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13765#L461 assume !(1 == ~M_E~0); 13453#L461-2 assume !(1 == ~T1_E~0); 13454#L466-1 assume !(1 == ~T2_E~0); 13711#L471-1 assume !(1 == ~T3_E~0); 13483#L476-1 assume !(1 == ~E_1~0); 13484#L481-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13636#L486-1 assume !(1 == ~E_3~0); 13501#L491-1 assume { :end_inline_reset_delta_events } true; 13502#L652-2 [2023-11-26 11:47:29,558 INFO L750 eck$LassoCheckResult]: Loop: 13502#L652-2 assume !false; 14108#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14106#L393-1 assume !false; 14104#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 14043#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 14034#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 14030#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14025#L346 assume !(0 != eval_~tmp~0#1); 14026#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14313#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14311#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14309#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14307#L423-3 assume !(0 == ~T2_E~0); 14305#L428-3 assume !(0 == ~T3_E~0); 14303#L433-3 assume !(0 == ~E_1~0); 14301#L438-3 assume !(0 == ~E_2~0); 14299#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14297#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14295#L197-12 assume 1 == ~m_pc~0; 14291#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14288#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14285#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14280#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14278#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14276#L216-12 assume !(1 == ~t1_pc~0); 14274#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 14272#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14270#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14268#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14265#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14262#L235-12 assume !(1 == ~t2_pc~0); 14257#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 14254#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14251#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14247#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14241#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14235#L254-12 assume !(1 == ~t3_pc~0); 14229#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 14223#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14218#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14213#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14208#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14203#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14198#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14193#L466-3 assume !(1 == ~T2_E~0); 14188#L471-3 assume !(1 == ~T3_E~0); 14181#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14176#L481-3 assume !(1 == ~E_2~0); 14172#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14168#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 14164#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 14157#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13893#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 13894#L671 assume !(0 == start_simulation_~tmp~3#1); 14147#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 14142#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 14136#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 14132#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 14127#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 14124#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14120#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 14116#L684 assume !(0 != start_simulation_~tmp___0~1#1); 13502#L652-2 [2023-11-26 11:47:29,559 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:29,559 INFO L85 PathProgramCache]: Analyzing trace with hash 1218472174, now seen corresponding path program 1 times [2023-11-26 11:47:29,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:29,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787882976] [2023-11-26 11:47:29,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:29,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:29,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:29,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:29,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:29,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [787882976] [2023-11-26 11:47:29,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [787882976] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:29,605 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:29,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:29,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26358569] [2023-11-26 11:47:29,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:29,606 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:29,607 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:29,607 INFO L85 PathProgramCache]: Analyzing trace with hash -1600215072, now seen corresponding path program 1 times [2023-11-26 11:47:29,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:29,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1730674015] [2023-11-26 11:47:29,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:29,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:29,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:29,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:29,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:29,672 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1730674015] [2023-11-26 11:47:29,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1730674015] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:29,673 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:29,673 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:47:29,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [911572038] [2023-11-26 11:47:29,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:29,674 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:29,674 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:29,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:29,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:29,675 INFO L87 Difference]: Start difference. First operand 1654 states and 2276 transitions. cyclomatic complexity: 626 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:29,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:29,718 INFO L93 Difference]: Finished difference Result 957 states and 1301 transitions. [2023-11-26 11:47:29,718 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 957 states and 1301 transitions. [2023-11-26 11:47:29,727 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2023-11-26 11:47:29,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 957 states to 957 states and 1301 transitions. [2023-11-26 11:47:29,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 957 [2023-11-26 11:47:29,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 957 [2023-11-26 11:47:29,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 957 states and 1301 transitions. [2023-11-26 11:47:29,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:29,740 INFO L218 hiAutomatonCegarLoop]: Abstraction has 957 states and 1301 transitions. [2023-11-26 11:47:29,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states and 1301 transitions. [2023-11-26 11:47:29,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 957. [2023-11-26 11:47:29,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 957 states have (on average 1.3594566353187043) internal successors, (1301), 956 states have internal predecessors, (1301), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:29,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1301 transitions. [2023-11-26 11:47:29,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 957 states and 1301 transitions. [2023-11-26 11:47:29,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:29,766 INFO L428 stractBuchiCegarLoop]: Abstraction has 957 states and 1301 transitions. [2023-11-26 11:47:29,767 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 11:47:29,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 957 states and 1301 transitions. [2023-11-26 11:47:29,773 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2023-11-26 11:47:29,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:29,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:29,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:29,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:29,775 INFO L748 eck$LassoCheckResult]: Stem: 16282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 16283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16295#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16293#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16264#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 16265#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16071#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16072#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16307#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16036#L418 assume !(0 == ~M_E~0); 16037#L418-2 assume !(0 == ~T1_E~0); 16263#L423-1 assume !(0 == ~T2_E~0); 16311#L428-1 assume !(0 == ~T3_E~0); 16309#L433-1 assume !(0 == ~E_1~0); 16297#L438-1 assume !(0 == ~E_2~0); 16219#L443-1 assume !(0 == ~E_3~0); 16212#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16173#L197 assume !(1 == ~m_pc~0); 16170#L197-2 is_master_triggered_~__retres1~0#1 := 0; 16332#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16255#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16256#L510 assume !(0 != activate_threads_~tmp~1#1); 16015#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16016#L216 assume !(1 == ~t1_pc~0); 16067#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16068#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16098#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16017#L518 assume !(0 != activate_threads_~tmp___0~0#1); 16018#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16228#L235 assume !(1 == ~t2_pc~0); 16304#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16155#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16156#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16323#L526 assume !(0 != activate_threads_~tmp___1~0#1); 16324#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16139#L254 assume !(1 == ~t3_pc~0); 16075#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16076#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16028#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16029#L534 assume !(0 != activate_threads_~tmp___2~0#1); 16150#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16007#L461 assume !(1 == ~M_E~0); 16008#L461-2 assume !(1 == ~T1_E~0); 16073#L466-1 assume !(1 == ~T2_E~0); 16315#L471-1 assume !(1 == ~T3_E~0); 16099#L476-1 assume !(1 == ~E_1~0); 16100#L481-1 assume !(1 == ~E_2~0); 16245#L486-1 assume !(1 == ~E_3~0); 16115#L491-1 assume { :end_inline_reset_delta_events } true; 16024#L652-2 [2023-11-26 11:47:29,775 INFO L750 eck$LassoCheckResult]: Loop: 16024#L652-2 assume !false; 16025#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16250#L393-1 assume !false; 16090#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16091#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16470#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16467#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16465#L346 assume !(0 != eval_~tmp~0#1); 16195#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16196#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16232#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16226#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16227#L423-3 assume !(0 == ~T2_E~0); 16221#L428-3 assume !(0 == ~T3_E~0); 16171#L433-3 assume !(0 == ~E_1~0); 16172#L438-3 assume !(0 == ~E_2~0); 16275#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16009#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16010#L197-12 assume 1 == ~m_pc~0; 16284#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16294#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16760#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16759#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16023#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16133#L216-12 assume !(1 == ~t1_pc~0); 16134#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 16615#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16613#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16612#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16611#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16607#L235-12 assume !(1 == ~t2_pc~0); 16604#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 16602#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16601#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16598#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16597#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16594#L254-12 assume !(1 == ~t3_pc~0); 16595#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 16720#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16719#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16718#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16717#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16716#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16715#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16714#L466-3 assume !(1 == ~T2_E~0); 16713#L471-3 assume !(1 == ~T3_E~0); 16712#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16711#L481-3 assume !(1 == ~E_2~0); 16710#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16709#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16510#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16506#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16505#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 16503#L671 assume !(0 == start_simulation_~tmp~3#1); 16035#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16271#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16244#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16096#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 16097#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 16314#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16875#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 16874#L684 assume !(0 != start_simulation_~tmp___0~1#1); 16024#L652-2 [2023-11-26 11:47:29,776 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:29,776 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2023-11-26 11:47:29,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:29,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088024927] [2023-11-26 11:47:29,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:29,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:29,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:29,787 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:29,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:29,806 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:29,806 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:29,807 INFO L85 PathProgramCache]: Analyzing trace with hash -1600215072, now seen corresponding path program 2 times [2023-11-26 11:47:29,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:29,807 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486319659] [2023-11-26 11:47:29,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:29,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:29,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:29,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:29,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:29,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486319659] [2023-11-26 11:47:29,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486319659] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:29,869 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:29,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:47:29,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128591130] [2023-11-26 11:47:29,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:29,870 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:29,870 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:29,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:47:29,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:47:29,871 INFO L87 Difference]: Start difference. First operand 957 states and 1301 transitions. cyclomatic complexity: 348 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:30,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:30,014 INFO L93 Difference]: Finished difference Result 1660 states and 2228 transitions. [2023-11-26 11:47:30,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1660 states and 2228 transitions. [2023-11-26 11:47:30,031 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1594 [2023-11-26 11:47:30,045 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1660 states to 1660 states and 2228 transitions. [2023-11-26 11:47:30,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1660 [2023-11-26 11:47:30,048 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1660 [2023-11-26 11:47:30,048 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1660 states and 2228 transitions. [2023-11-26 11:47:30,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:30,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1660 states and 2228 transitions. [2023-11-26 11:47:30,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1660 states and 2228 transitions. [2023-11-26 11:47:30,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1660 to 969. [2023-11-26 11:47:30,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 969 states, 969 states have (on average 1.3550051599587203) internal successors, (1313), 968 states have internal predecessors, (1313), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:30,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 969 states to 969 states and 1313 transitions. [2023-11-26 11:47:30,105 INFO L240 hiAutomatonCegarLoop]: Abstraction has 969 states and 1313 transitions. [2023-11-26 11:47:30,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 11:47:30,107 INFO L428 stractBuchiCegarLoop]: Abstraction has 969 states and 1313 transitions. [2023-11-26 11:47:30,107 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 11:47:30,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 969 states and 1313 transitions. [2023-11-26 11:47:30,115 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 909 [2023-11-26 11:47:30,115 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:30,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:30,116 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:30,116 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:30,117 INFO L748 eck$LassoCheckResult]: Stem: 18932#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 18933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 18951#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18947#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18915#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 18916#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18706#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18707#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18962#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18670#L418 assume !(0 == ~M_E~0); 18671#L418-2 assume !(0 == ~T1_E~0); 18914#L423-1 assume !(0 == ~T2_E~0); 18968#L428-1 assume !(0 == ~T3_E~0); 18965#L433-1 assume !(0 == ~E_1~0); 18954#L438-1 assume !(0 == ~E_2~0); 18858#L443-1 assume !(0 == ~E_3~0); 18850#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18810#L197 assume !(1 == ~m_pc~0); 18807#L197-2 is_master_triggered_~__retres1~0#1 := 0; 18990#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18904#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 18905#L510 assume !(0 != activate_threads_~tmp~1#1); 18649#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18650#L216 assume !(1 == ~t1_pc~0); 18702#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18703#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18733#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 18651#L518 assume !(0 != activate_threads_~tmp___0~0#1); 18652#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18870#L235 assume !(1 == ~t2_pc~0); 18958#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18792#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18793#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18981#L526 assume !(0 != activate_threads_~tmp___1~0#1); 18982#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18776#L254 assume !(1 == ~t3_pc~0); 18710#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18711#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18662#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18663#L534 assume !(0 != activate_threads_~tmp___2~0#1); 18787#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18641#L461 assume !(1 == ~M_E~0); 18642#L461-2 assume !(1 == ~T1_E~0); 18708#L466-1 assume !(1 == ~T2_E~0); 18971#L471-1 assume !(1 == ~T3_E~0); 18734#L476-1 assume !(1 == ~E_1~0); 18735#L481-1 assume !(1 == ~E_2~0); 18889#L486-1 assume !(1 == ~E_3~0); 18751#L491-1 assume { :end_inline_reset_delta_events } true; 18752#L652-2 [2023-11-26 11:47:30,117 INFO L750 eck$LassoCheckResult]: Loop: 18752#L652-2 assume !false; 19205#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19130#L393-1 assume !false; 19128#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 19126#L309 assume !(0 == ~m_st~0); 19124#L313 assume !(0 == ~t1_st~0); 19122#L317 assume !(0 == ~t2_st~0); 19119#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 19116#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 19114#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19113#L346 assume !(0 != eval_~tmp~0#1); 19112#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18876#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18877#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18868#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18869#L423-3 assume !(0 == ~T2_E~0); 18859#L428-3 assume !(0 == ~T3_E~0); 18860#L433-3 assume !(0 == ~E_1~0); 18926#L438-3 assume !(0 == ~E_2~0); 18927#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18643#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18644#L197-12 assume 1 == ~m_pc~0; 19110#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19108#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19106#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 19104#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19103#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18770#L216-12 assume !(1 == ~t1_pc~0); 18771#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 19268#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19267#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19266#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19265#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19264#L235-12 assume !(1 == ~t2_pc~0); 18790#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 18791#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18983#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18996#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18851#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18852#L254-12 assume !(1 == ~t3_pc~0); 19260#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 19259#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19258#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19257#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19256#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19255#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19254#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19253#L466-3 assume !(1 == ~T2_E~0); 19252#L471-3 assume !(1 == ~T3_E~0); 19251#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19250#L481-3 assume !(1 == ~E_2~0); 19249#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19248#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 19247#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 19242#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 19240#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 19236#L671 assume !(0 == start_simulation_~tmp~3#1); 19235#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 19233#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 19229#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 19227#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 19225#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 19224#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19223#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 19219#L684 assume !(0 != start_simulation_~tmp___0~1#1); 18752#L652-2 [2023-11-26 11:47:30,117 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:30,118 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2023-11-26 11:47:30,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:30,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735593717] [2023-11-26 11:47:30,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:30,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:30,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:30,133 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:30,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:30,163 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:30,164 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:30,164 INFO L85 PathProgramCache]: Analyzing trace with hash -1830534438, now seen corresponding path program 1 times [2023-11-26 11:47:30,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:30,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464582868] [2023-11-26 11:47:30,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:30,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:30,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:30,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:30,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:30,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464582868] [2023-11-26 11:47:30,238 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464582868] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:30,238 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:30,238 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:47:30,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [796825302] [2023-11-26 11:47:30,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:30,239 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:30,239 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:30,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:47:30,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:47:30,241 INFO L87 Difference]: Start difference. First operand 969 states and 1313 transitions. cyclomatic complexity: 348 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:30,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:30,341 INFO L93 Difference]: Finished difference Result 1620 states and 2168 transitions. [2023-11-26 11:47:30,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1620 states and 2168 transitions. [2023-11-26 11:47:30,353 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1554 [2023-11-26 11:47:30,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1620 states to 1620 states and 2168 transitions. [2023-11-26 11:47:30,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1620 [2023-11-26 11:47:30,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1620 [2023-11-26 11:47:30,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1620 states and 2168 transitions. [2023-11-26 11:47:30,374 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:30,374 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1620 states and 2168 transitions. [2023-11-26 11:47:30,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1620 states and 2168 transitions. [2023-11-26 11:47:30,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1620 to 981. [2023-11-26 11:47:30,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981 states, 981 states have (on average 1.3506625891946993) internal successors, (1325), 980 states have internal predecessors, (1325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:30,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981 states to 981 states and 1325 transitions. [2023-11-26 11:47:30,402 INFO L240 hiAutomatonCegarLoop]: Abstraction has 981 states and 1325 transitions. [2023-11-26 11:47:30,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-26 11:47:30,404 INFO L428 stractBuchiCegarLoop]: Abstraction has 981 states and 1325 transitions. [2023-11-26 11:47:30,404 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 11:47:30,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 981 states and 1325 transitions. [2023-11-26 11:47:30,408 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 921 [2023-11-26 11:47:30,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:30,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:30,410 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:30,410 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:30,410 INFO L748 eck$LassoCheckResult]: Stem: 21517#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 21518#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21531#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21528#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21501#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 21502#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21306#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21307#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21542#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21274#L418 assume !(0 == ~M_E~0); 21275#L418-2 assume !(0 == ~T1_E~0); 21500#L423-1 assume !(0 == ~T2_E~0); 21546#L428-1 assume !(0 == ~T3_E~0); 21544#L433-1 assume !(0 == ~E_1~0); 21535#L438-1 assume !(0 == ~E_2~0); 21453#L443-1 assume !(0 == ~E_3~0); 21445#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21408#L197 assume !(1 == ~m_pc~0); 21405#L197-2 is_master_triggered_~__retres1~0#1 := 0; 21577#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21491#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21492#L510 assume !(0 != activate_threads_~tmp~1#1); 21251#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21252#L216 assume !(1 == ~t1_pc~0); 21304#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21305#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21333#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21253#L518 assume !(0 != activate_threads_~tmp___0~0#1); 21254#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21464#L235 assume !(1 == ~t2_pc~0); 21541#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21393#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21394#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21564#L526 assume !(0 != activate_threads_~tmp___1~0#1); 21565#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21375#L254 assume !(1 == ~t3_pc~0); 21310#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21311#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21264#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21265#L534 assume !(0 != activate_threads_~tmp___2~0#1); 21387#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21243#L461 assume !(1 == ~M_E~0); 21244#L461-2 assume !(1 == ~T1_E~0); 21308#L466-1 assume !(1 == ~T2_E~0); 21552#L471-1 assume !(1 == ~T3_E~0); 21336#L476-1 assume !(1 == ~E_1~0); 21337#L481-1 assume !(1 == ~E_2~0); 21479#L486-1 assume !(1 == ~E_3~0); 21354#L491-1 assume { :end_inline_reset_delta_events } true; 21260#L652-2 [2023-11-26 11:47:30,411 INFO L750 eck$LassoCheckResult]: Loop: 21260#L652-2 assume !false; 21261#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21328#L393-1 assume !false; 21325#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21326#L309 assume !(0 == ~m_st~0); 21299#L313 assume !(0 == ~t1_st~0); 21301#L317 assume !(0 == ~t2_st~0); 21490#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 21548#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21988#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21987#L346 assume !(0 != eval_~tmp~0#1); 21430#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21431#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21467#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21460#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21461#L423-3 assume !(0 == ~T2_E~0); 21456#L428-3 assume !(0 == ~T3_E~0); 21406#L433-3 assume !(0 == ~E_1~0); 21407#L438-3 assume !(0 == ~E_2~0); 21514#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21245#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21246#L197-12 assume !(1 == ~m_pc~0); 21520#L197-14 is_master_triggered_~__retres1~0#1 := 0; 21668#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21664#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21660#L510-12 assume !(0 != activate_threads_~tmp~1#1); 21656#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21653#L216-12 assume !(1 == ~t1_pc~0); 21649#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 21650#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21554#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21379#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21380#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22026#L235-12 assume !(1 == ~t2_pc~0); 21390#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 21391#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22024#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22023#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22022#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21557#L254-12 assume !(1 == ~t3_pc~0); 21558#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 21449#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21334#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21335#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21881#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21373#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21374#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21468#L466-3 assume !(1 == ~T2_E~0); 21469#L471-3 assume !(1 == ~T3_E~0); 21366#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21367#L481-3 assume !(1 == ~E_2~0); 21398#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21399#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21281#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21282#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21309#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21470#L671 assume !(0 == start_simulation_~tmp~3#1); 21269#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21508#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22115#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22113#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 22112#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22110#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22109#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 21489#L684 assume !(0 != start_simulation_~tmp___0~1#1); 21260#L652-2 [2023-11-26 11:47:30,411 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:30,411 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 4 times [2023-11-26 11:47:30,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:30,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174501945] [2023-11-26 11:47:30,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:30,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:30,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:30,422 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:30,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:30,443 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:30,446 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:30,446 INFO L85 PathProgramCache]: Analyzing trace with hash -182536711, now seen corresponding path program 1 times [2023-11-26 11:47:30,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:30,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1044314669] [2023-11-26 11:47:30,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:30,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:30,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:30,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:30,494 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:30,494 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1044314669] [2023-11-26 11:47:30,494 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1044314669] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:30,494 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:30,495 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:30,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925088198] [2023-11-26 11:47:30,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:30,496 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:30,496 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:30,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:30,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:30,497 INFO L87 Difference]: Start difference. First operand 981 states and 1325 transitions. cyclomatic complexity: 348 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:30,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:30,556 INFO L93 Difference]: Finished difference Result 1712 states and 2272 transitions. [2023-11-26 11:47:30,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1712 states and 2272 transitions. [2023-11-26 11:47:30,568 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1646 [2023-11-26 11:47:30,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1712 states to 1712 states and 2272 transitions. [2023-11-26 11:47:30,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1712 [2023-11-26 11:47:30,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1712 [2023-11-26 11:47:30,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1712 states and 2272 transitions. [2023-11-26 11:47:30,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:30,589 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1712 states and 2272 transitions. [2023-11-26 11:47:30,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1712 states and 2272 transitions. [2023-11-26 11:47:30,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1712 to 1616. [2023-11-26 11:47:30,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1616 states, 1616 states have (on average 1.3316831683168318) internal successors, (2152), 1615 states have internal predecessors, (2152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:30,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1616 states to 1616 states and 2152 transitions. [2023-11-26 11:47:30,632 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1616 states and 2152 transitions. [2023-11-26 11:47:30,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:30,633 INFO L428 stractBuchiCegarLoop]: Abstraction has 1616 states and 2152 transitions. [2023-11-26 11:47:30,633 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 11:47:30,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1616 states and 2152 transitions. [2023-11-26 11:47:30,642 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1550 [2023-11-26 11:47:30,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:30,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:30,646 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:30,646 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:30,646 INFO L748 eck$LassoCheckResult]: Stem: 24220#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 24221#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 24236#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24233#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24203#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 24204#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24005#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24006#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24246#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23971#L418 assume !(0 == ~M_E~0); 23972#L418-2 assume !(0 == ~T1_E~0); 24202#L423-1 assume !(0 == ~T2_E~0); 24252#L428-1 assume !(0 == ~T3_E~0); 24250#L433-1 assume !(0 == ~E_1~0); 24238#L438-1 assume !(0 == ~E_2~0); 24157#L443-1 assume !(0 == ~E_3~0); 24151#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24110#L197 assume !(1 == ~m_pc~0); 24107#L197-2 is_master_triggered_~__retres1~0#1 := 0; 24277#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24193#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24194#L510 assume !(0 != activate_threads_~tmp~1#1); 23950#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23951#L216 assume !(1 == ~t1_pc~0); 24001#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24002#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24033#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23952#L518 assume !(0 != activate_threads_~tmp___0~0#1); 23953#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24165#L235 assume !(1 == ~t2_pc~0); 24243#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24091#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24092#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24267#L526 assume !(0 != activate_threads_~tmp___1~0#1); 24268#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24075#L254 assume !(1 == ~t3_pc~0); 24010#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 24011#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23963#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23964#L534 assume !(0 != activate_threads_~tmp___2~0#1); 24086#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23942#L461 assume !(1 == ~M_E~0); 23943#L461-2 assume !(1 == ~T1_E~0); 24007#L466-1 assume !(1 == ~T2_E~0); 24260#L471-1 assume !(1 == ~T3_E~0); 24034#L476-1 assume !(1 == ~E_1~0); 24035#L481-1 assume !(1 == ~E_2~0); 24184#L486-1 assume !(1 == ~E_3~0); 24050#L491-1 assume { :end_inline_reset_delta_events } true; 24051#L652-2 [2023-11-26 11:47:30,647 INFO L750 eck$LassoCheckResult]: Loop: 24051#L652-2 assume !false; 24772#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24554#L393-1 assume !false; 24769#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24767#L309 assume !(0 == ~m_st~0); 23998#L313 assume !(0 == ~t1_st~0); 24000#L317 assume !(0 == ~t2_st~0); 24254#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 24255#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 23965#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23966#L346 assume !(0 != eval_~tmp~0#1); 24133#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24134#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25068#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25066#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25064#L423-3 assume !(0 == ~T2_E~0); 25062#L428-3 assume !(0 == ~T3_E~0); 25060#L433-3 assume !(0 == ~E_1~0); 25058#L438-3 assume !(0 == ~E_2~0); 25056#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25054#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25049#L197-12 assume 1 == ~m_pc~0; 25041#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 25036#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25032#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 25030#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25029#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25028#L216-12 assume !(1 == ~t1_pc~0); 25027#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 25024#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25022#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25020#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25018#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25016#L235-12 assume !(1 == ~t2_pc~0); 25013#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 24848#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24844#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24841#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24838#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24835#L254-12 assume !(1 == ~t3_pc~0); 24833#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 24831#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24829#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24827#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24825#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24823#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24821#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24819#L466-3 assume !(1 == ~T2_E~0); 24817#L471-3 assume !(1 == ~T3_E~0); 24815#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24813#L481-3 assume !(1 == ~E_2~0); 24811#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24809#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24806#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24804#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24802#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 24795#L671 assume !(0 == start_simulation_~tmp~3#1); 24793#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24791#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24789#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24787#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 24785#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24783#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24781#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 24777#L684 assume !(0 != start_simulation_~tmp___0~1#1); 24051#L652-2 [2023-11-26 11:47:30,647 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:30,648 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 5 times [2023-11-26 11:47:30,648 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:30,648 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726879364] [2023-11-26 11:47:30,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:30,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:30,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:30,663 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:30,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:30,679 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:30,680 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:30,681 INFO L85 PathProgramCache]: Analyzing trace with hash -1830594020, now seen corresponding path program 1 times [2023-11-26 11:47:30,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:30,681 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1754767037] [2023-11-26 11:47:30,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:30,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:30,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:30,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:30,799 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:30,799 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1754767037] [2023-11-26 11:47:30,799 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1754767037] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:30,800 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:30,800 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:47:30,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114370799] [2023-11-26 11:47:30,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:30,800 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:30,801 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:30,802 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:47:30,802 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:47:30,802 INFO L87 Difference]: Start difference. First operand 1616 states and 2152 transitions. cyclomatic complexity: 540 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:30,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:30,971 INFO L93 Difference]: Finished difference Result 2682 states and 3517 transitions. [2023-11-26 11:47:30,971 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2682 states and 3517 transitions. [2023-11-26 11:47:30,989 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2614 [2023-11-26 11:47:31,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2682 states to 2682 states and 3517 transitions. [2023-11-26 11:47:31,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2682 [2023-11-26 11:47:31,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2682 [2023-11-26 11:47:31,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2682 states and 3517 transitions. [2023-11-26 11:47:31,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:31,028 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2682 states and 3517 transitions. [2023-11-26 11:47:31,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2682 states and 3517 transitions. [2023-11-26 11:47:31,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2682 to 1670. [2023-11-26 11:47:31,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1670 states, 1670 states have (on average 1.3119760479041915) internal successors, (2191), 1669 states have internal predecessors, (2191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:31,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1670 states to 1670 states and 2191 transitions. [2023-11-26 11:47:31,079 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1670 states and 2191 transitions. [2023-11-26 11:47:31,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:47:31,081 INFO L428 stractBuchiCegarLoop]: Abstraction has 1670 states and 2191 transitions. [2023-11-26 11:47:31,082 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 11:47:31,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1670 states and 2191 transitions. [2023-11-26 11:47:31,090 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1604 [2023-11-26 11:47:31,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:31,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:31,092 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:31,092 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:31,092 INFO L748 eck$LassoCheckResult]: Stem: 28534#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 28535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 28553#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28549#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28514#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 28515#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28313#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28314#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28566#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28281#L418 assume !(0 == ~M_E~0); 28282#L418-2 assume !(0 == ~T1_E~0); 28513#L423-1 assume !(0 == ~T2_E~0); 28573#L428-1 assume !(0 == ~T3_E~0); 28571#L433-1 assume !(0 == ~E_1~0); 28555#L438-1 assume !(0 == ~E_2~0); 28468#L443-1 assume !(0 == ~E_3~0); 28462#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28418#L197 assume !(1 == ~m_pc~0); 28415#L197-2 is_master_triggered_~__retres1~0#1 := 0; 28598#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28505#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28506#L510 assume !(0 != activate_threads_~tmp~1#1); 28260#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28261#L216 assume !(1 == ~t1_pc~0); 28309#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28310#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28343#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28262#L518 assume !(0 != activate_threads_~tmp___0~0#1); 28263#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28476#L235 assume !(1 == ~t2_pc~0); 28562#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28401#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28402#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28589#L526 assume !(0 != activate_threads_~tmp___1~0#1); 28590#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28385#L254 assume !(1 == ~t3_pc~0); 28318#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28319#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28273#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28274#L534 assume !(0 != activate_threads_~tmp___2~0#1); 28396#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28252#L461 assume !(1 == ~M_E~0); 28253#L461-2 assume !(1 == ~T1_E~0); 28315#L466-1 assume !(1 == ~T2_E~0); 28580#L471-1 assume !(1 == ~T3_E~0); 28344#L476-1 assume !(1 == ~E_1~0); 28345#L481-1 assume !(1 == ~E_2~0); 28496#L486-1 assume !(1 == ~E_3~0); 28360#L491-1 assume { :end_inline_reset_delta_events } true; 28361#L652-2 [2023-11-26 11:47:31,093 INFO L750 eck$LassoCheckResult]: Loop: 28361#L652-2 assume !false; 28676#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28677#L393-1 assume !false; 28672#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28673#L309 assume !(0 == ~m_st~0); 28730#L313 assume !(0 == ~t1_st~0); 29025#L317 assume !(0 == ~t2_st~0); 29023#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 29021#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 29018#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 29016#L346 assume !(0 != eval_~tmp~0#1); 29014#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29005#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28999#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28972#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28965#L423-3 assume !(0 == ~T2_E~0); 28960#L428-3 assume !(0 == ~T3_E~0); 28955#L433-3 assume !(0 == ~E_1~0); 28951#L438-3 assume !(0 == ~E_2~0); 28947#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28943#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28939#L197-12 assume 1 == ~m_pc~0; 28935#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28931#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28927#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28921#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28916#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28911#L216-12 assume !(1 == ~t1_pc~0); 28906#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 28902#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28859#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28856#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 28854#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28852#L235-12 assume !(1 == ~t2_pc~0); 28849#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 28847#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28845#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28843#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28841#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28839#L254-12 assume !(1 == ~t3_pc~0); 28837#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 28835#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28833#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28831#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28829#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28827#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28826#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28825#L466-3 assume !(1 == ~T2_E~0); 28823#L471-3 assume !(1 == ~T3_E~0); 28820#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28818#L481-3 assume !(1 == ~E_2~0); 28816#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28805#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28797#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28791#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28785#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 28777#L671 assume !(0 == start_simulation_~tmp~3#1); 28773#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28767#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28763#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28757#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 28753#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28749#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28745#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 28695#L684 assume !(0 != start_simulation_~tmp___0~1#1); 28361#L652-2 [2023-11-26 11:47:31,093 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:31,094 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 6 times [2023-11-26 11:47:31,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:31,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844528923] [2023-11-26 11:47:31,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:31,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:31,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:31,109 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:31,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:31,133 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:31,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:31,134 INFO L85 PathProgramCache]: Analyzing trace with hash 220389978, now seen corresponding path program 1 times [2023-11-26 11:47:31,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:31,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166729449] [2023-11-26 11:47:31,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:31,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:31,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:31,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:31,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:31,231 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166729449] [2023-11-26 11:47:31,231 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [166729449] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:31,231 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:31,232 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:47:31,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1003884321] [2023-11-26 11:47:31,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:31,232 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:31,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:31,233 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:47:31,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:47:31,234 INFO L87 Difference]: Start difference. First operand 1670 states and 2191 transitions. cyclomatic complexity: 525 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:31,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:31,360 INFO L93 Difference]: Finished difference Result 2184 states and 2838 transitions. [2023-11-26 11:47:31,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2184 states and 2838 transitions. [2023-11-26 11:47:31,373 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2116 [2023-11-26 11:47:31,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2184 states to 2184 states and 2838 transitions. [2023-11-26 11:47:31,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2184 [2023-11-26 11:47:31,404 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2184 [2023-11-26 11:47:31,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2184 states and 2838 transitions. [2023-11-26 11:47:31,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:31,408 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2184 states and 2838 transitions. [2023-11-26 11:47:31,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2184 states and 2838 transitions. [2023-11-26 11:47:31,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2184 to 1682. [2023-11-26 11:47:31,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1682 states, 1682 states have (on average 1.2925089179548157) internal successors, (2174), 1681 states have internal predecessors, (2174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:31,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1682 states to 1682 states and 2174 transitions. [2023-11-26 11:47:31,450 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1682 states and 2174 transitions. [2023-11-26 11:47:31,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:47:31,452 INFO L428 stractBuchiCegarLoop]: Abstraction has 1682 states and 2174 transitions. [2023-11-26 11:47:31,452 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 11:47:31,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1682 states and 2174 transitions. [2023-11-26 11:47:31,459 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1616 [2023-11-26 11:47:31,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:31,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:31,460 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:31,460 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:31,461 INFO L748 eck$LassoCheckResult]: Stem: 32406#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 32407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 32425#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32420#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32386#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 32387#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32181#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32182#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32440#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32147#L418 assume !(0 == ~M_E~0); 32148#L418-2 assume !(0 == ~T1_E~0); 32385#L423-1 assume !(0 == ~T2_E~0); 32447#L428-1 assume !(0 == ~T3_E~0); 32445#L433-1 assume !(0 == ~E_1~0); 32430#L438-1 assume !(0 == ~E_2~0); 32340#L443-1 assume !(0 == ~E_3~0); 32334#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32292#L197 assume !(1 == ~m_pc~0); 32289#L197-2 is_master_triggered_~__retres1~0#1 := 0; 32474#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32375#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 32376#L510 assume !(0 != activate_threads_~tmp~1#1); 32126#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32127#L216 assume !(1 == ~t1_pc~0); 32177#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32178#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32209#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32128#L518 assume !(0 != activate_threads_~tmp___0~0#1); 32129#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32350#L235 assume !(1 == ~t2_pc~0); 32436#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32272#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32273#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 32463#L526 assume !(0 != activate_threads_~tmp___1~0#1); 32464#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32254#L254 assume !(1 == ~t3_pc~0); 32186#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32187#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32139#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32140#L534 assume !(0 != activate_threads_~tmp___2~0#1); 32265#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32118#L461 assume !(1 == ~M_E~0); 32119#L461-2 assume !(1 == ~T1_E~0); 32183#L466-1 assume !(1 == ~T2_E~0); 32454#L471-1 assume !(1 == ~T3_E~0); 32210#L476-1 assume !(1 == ~E_1~0); 32211#L481-1 assume !(1 == ~E_2~0); 32369#L486-1 assume !(1 == ~E_3~0); 32227#L491-1 assume { :end_inline_reset_delta_events } true; 32228#L652-2 [2023-11-26 11:47:31,461 INFO L750 eck$LassoCheckResult]: Loop: 32228#L652-2 assume !false; 33561#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33153#L393-1 assume !false; 33558#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 33554#L309 assume !(0 == ~m_st~0); 33460#L313 assume !(0 == ~t1_st~0); 33455#L317 assume !(0 == ~t2_st~0); 33448#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 33443#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 33438#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33433#L346 assume !(0 != eval_~tmp~0#1); 33428#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33423#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33419#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33343#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33341#L423-3 assume !(0 == ~T2_E~0); 33339#L428-3 assume !(0 == ~T3_E~0); 32290#L433-3 assume !(0 == ~E_1~0); 32291#L438-3 assume !(0 == ~E_2~0); 32408#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32409#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33332#L197-12 assume 1 == ~m_pc~0; 32421#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 32422#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33621#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 33620#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32312#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32248#L216-12 assume !(1 == ~t1_pc~0); 32249#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 32309#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32310#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32258#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 32179#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32180#L235-12 assume !(1 == ~t2_pc~0); 32270#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 32271#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33485#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33481#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 33062#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32457#L254-12 assume !(1 == ~t3_pc~0); 32458#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 33510#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33507#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33504#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33501#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33498#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33494#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33490#L466-3 assume !(1 == ~T2_E~0); 33487#L471-3 assume !(1 == ~T3_E~0); 33483#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33479#L481-3 assume !(1 == ~E_2~0); 33476#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33390#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 33385#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 33386#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 33609#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 33604#L671 assume !(0 == start_simulation_~tmp~3#1); 33603#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 33601#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 33599#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 33597#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 33595#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33593#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33591#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 33589#L684 assume !(0 != start_simulation_~tmp___0~1#1); 32228#L652-2 [2023-11-26 11:47:31,462 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:31,462 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 7 times [2023-11-26 11:47:31,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:31,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999474554] [2023-11-26 11:47:31,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:31,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:31,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:31,475 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:31,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:31,487 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:31,488 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:31,488 INFO L85 PathProgramCache]: Analyzing trace with hash -289083112, now seen corresponding path program 1 times [2023-11-26 11:47:31,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:31,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831726372] [2023-11-26 11:47:31,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:31,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:31,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:31,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:31,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:31,584 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831726372] [2023-11-26 11:47:31,584 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [831726372] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:31,584 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:31,584 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:47:31,584 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30474102] [2023-11-26 11:47:31,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:31,585 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:31,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:31,586 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:47:31,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:47:31,586 INFO L87 Difference]: Start difference. First operand 1682 states and 2174 transitions. cyclomatic complexity: 496 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:31,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:31,762 INFO L93 Difference]: Finished difference Result 2480 states and 3164 transitions. [2023-11-26 11:47:31,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2480 states and 3164 transitions. [2023-11-26 11:47:31,776 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2410 [2023-11-26 11:47:31,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2480 states to 2480 states and 3164 transitions. [2023-11-26 11:47:31,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2480 [2023-11-26 11:47:31,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2480 [2023-11-26 11:47:31,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2480 states and 3164 transitions. [2023-11-26 11:47:31,800 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:31,800 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2480 states and 3164 transitions. [2023-11-26 11:47:31,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2480 states and 3164 transitions. [2023-11-26 11:47:31,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2480 to 1730. [2023-11-26 11:47:31,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1730 states, 1730 states have (on average 1.2745664739884393) internal successors, (2205), 1729 states have internal predecessors, (2205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:31,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1730 states to 1730 states and 2205 transitions. [2023-11-26 11:47:31,849 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1730 states and 2205 transitions. [2023-11-26 11:47:31,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:47:31,851 INFO L428 stractBuchiCegarLoop]: Abstraction has 1730 states and 2205 transitions. [2023-11-26 11:47:31,851 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 11:47:31,851 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1730 states and 2205 transitions. [2023-11-26 11:47:31,859 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1664 [2023-11-26 11:47:31,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:31,860 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:31,861 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:31,861 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:31,861 INFO L748 eck$LassoCheckResult]: Stem: 36567#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 36568#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 36582#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36579#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36549#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 36550#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36354#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36355#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36598#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36321#L418 assume !(0 == ~M_E~0); 36322#L418-2 assume !(0 == ~T1_E~0); 36548#L423-1 assume !(0 == ~T2_E~0); 36604#L428-1 assume !(0 == ~T3_E~0); 36602#L433-1 assume !(0 == ~E_1~0); 36588#L438-1 assume !(0 == ~E_2~0); 36503#L443-1 assume !(0 == ~E_3~0); 36497#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36457#L197 assume !(1 == ~m_pc~0); 36454#L197-2 is_master_triggered_~__retres1~0#1 := 0; 36630#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36538#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 36539#L510 assume !(0 != activate_threads_~tmp~1#1); 36300#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36301#L216 assume !(1 == ~t1_pc~0); 36350#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36351#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36382#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 36302#L518 assume !(0 != activate_threads_~tmp___0~0#1); 36303#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36511#L235 assume !(1 == ~t2_pc~0); 36594#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36439#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36440#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36624#L526 assume !(0 != activate_threads_~tmp___1~0#1); 36625#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36422#L254 assume !(1 == ~t3_pc~0); 36359#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36360#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36313#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36314#L534 assume !(0 != activate_threads_~tmp___2~0#1); 36433#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36292#L461 assume !(1 == ~M_E~0); 36293#L461-2 assume !(1 == ~T1_E~0); 36356#L466-1 assume !(1 == ~T2_E~0); 36610#L471-1 assume !(1 == ~T3_E~0); 36383#L476-1 assume !(1 == ~E_1~0); 36384#L481-1 assume !(1 == ~E_2~0); 36528#L486-1 assume !(1 == ~E_3~0); 36399#L491-1 assume { :end_inline_reset_delta_events } true; 36400#L652-2 [2023-11-26 11:47:31,862 INFO L750 eck$LassoCheckResult]: Loop: 36400#L652-2 assume !false; 36974#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36971#L393-1 assume !false; 36968#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 36964#L309 assume !(0 == ~m_st~0); 36965#L313 assume !(0 == ~t1_st~0); 37291#L317 assume !(0 == ~t2_st~0); 37290#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 37285#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37215#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37216#L346 assume !(0 != eval_~tmp~0#1); 37274#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37269#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37264#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37258#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37254#L423-3 assume !(0 == ~T2_E~0); 37249#L428-3 assume !(0 == ~T3_E~0); 37244#L433-3 assume !(0 == ~E_1~0); 37240#L438-3 assume !(0 == ~E_2~0); 37235#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37228#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37222#L197-12 assume 1 == ~m_pc~0; 37213#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37207#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37203#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 37197#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37192#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37186#L216-12 assume !(1 == ~t1_pc~0); 37179#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 37175#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37169#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 37165#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 37148#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37144#L235-12 assume !(1 == ~t2_pc~0); 37141#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 37139#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37137#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37136#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 37134#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37131#L254-12 assume !(1 == ~t3_pc~0); 37123#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 37115#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37110#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 37105#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 37101#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37096#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37090#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37084#L466-3 assume !(1 == ~T2_E~0); 37078#L471-3 assume !(1 == ~T3_E~0); 37071#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37066#L481-3 assume !(1 == ~E_2~0); 37060#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37054#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37048#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37043#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37037#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 37031#L671 assume !(0 == start_simulation_~tmp~3#1); 37027#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37021#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37016#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37011#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 37004#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37000#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36994#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 36986#L684 assume !(0 != start_simulation_~tmp___0~1#1); 36400#L652-2 [2023-11-26 11:47:31,862 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:31,863 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 8 times [2023-11-26 11:47:31,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:31,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591997180] [2023-11-26 11:47:31,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:31,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:31,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:31,875 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:31,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:31,889 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:31,890 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:31,890 INFO L85 PathProgramCache]: Analyzing trace with hash -70228394, now seen corresponding path program 1 times [2023-11-26 11:47:31,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:31,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372247243] [2023-11-26 11:47:31,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:31,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:31,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:31,903 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:31,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:31,919 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:31,919 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:31,920 INFO L85 PathProgramCache]: Analyzing trace with hash 242449541, now seen corresponding path program 1 times [2023-11-26 11:47:31,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:31,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947460172] [2023-11-26 11:47:31,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:31,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:31,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:31,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:31,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:31,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1947460172] [2023-11-26 11:47:31,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1947460172] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:31,980 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:31,980 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:31,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388309859] [2023-11-26 11:47:31,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:33,037 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 11:47:33,038 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 11:47:33,038 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 11:47:33,039 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 11:47:33,039 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-26 11:47:33,039 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:33,039 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 11:47:33,039 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 11:47:33,039 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration18_Loop [2023-11-26 11:47:33,040 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 11:47:33,040 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 11:47:33,064 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,075 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,079 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,082 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,085 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,087 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,090 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,093 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,096 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,098 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,101 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,104 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,117 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,125 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,129 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,135 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,142 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,145 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,152 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,156 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,164 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,168 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,171 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,178 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,182 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,186 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,189 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,194 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,202 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,205 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,208 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,211 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,216 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,218 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,221 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,224 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,228 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,232 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,235 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,238 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,241 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,248 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,258 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,263 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,267 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,270 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,274 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,280 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,283 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:33,769 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 11:47:33,770 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-26 11:47:33,773 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:33,773 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:33,780 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:33,797 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-26 11:47:33,798 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:33,800 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:33,841 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:33,841 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:33,864 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2023-11-26 11:47:33,864 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:33,865 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:33,873 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:33,884 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:33,884 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:33,900 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-26 11:47:33,913 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:33,913 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=4} Honda state: {~t2_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:33,923 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:33,924 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:33,924 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:33,926 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:33,936 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:33,936 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:33,951 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-26 11:47:33,980 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:33,981 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:33,990 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:33,991 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:33,991 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:33,993 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,003 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:34,003 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,016 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-26 11:47:34,028 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:34,029 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret10#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:34,065 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,065 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,066 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:34,067 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,075 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-26 11:47:34,079 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:34,079 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,105 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:34,105 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:34,110 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,110 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,110 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:34,112 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,116 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-26 11:47:34,117 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:34,117 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,152 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:34,152 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:34,160 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,160 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,161 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:34,168 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,177 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-26 11:47:34,177 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:34,177 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,201 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:34,201 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret9#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret9#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:34,211 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,211 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,211 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:34,213 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,224 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:34,224 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,240 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-26 11:47:34,256 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:34,256 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:34,266 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,267 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,267 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:34,268 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,274 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:34,274 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,288 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-26 11:47:34,297 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:34,297 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret12#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret12#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:34,307 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,307 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,308 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:34,309 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,319 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:34,319 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,333 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-26 11:47:34,345 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:34,345 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:34,354 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,355 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,355 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:34,356 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,366 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:34,366 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,380 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-26 11:47:34,404 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:34,404 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:34,410 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,410 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,410 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:34,411 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,416 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-26 11:47:34,417 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:34,417 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,444 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:34,444 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:34,454 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,454 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,454 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:34,456 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,491 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-26 11:47:34,493 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:34,493 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,528 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,528 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,528 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:34,530 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:34,539 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-26 11:47:34,540 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:34,555 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-26 11:47:34,566 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-26 11:47:34,572 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:34,572 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 11:47:34,572 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 11:47:34,572 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 11:47:34,572 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 11:47:34,573 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-26 11:47:34,573 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:34,573 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 11:47:34,573 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 11:47:34,573 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration18_Loop [2023-11-26 11:47:34,573 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 11:47:34,573 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 11:47:34,578 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,583 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,586 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,589 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,592 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,594 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,597 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,599 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,601 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,604 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,607 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,611 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,619 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,625 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,628 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,636 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,648 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,654 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,657 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,660 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,666 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,675 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,688 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,693 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,695 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,700 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,711 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,714 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,722 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,725 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,731 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,741 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:34,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:35,154 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 11:47:35,166 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-26 11:47:35,167 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,168 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,172 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,176 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,189 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,189 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,190 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,190 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:35,190 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,192 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:35,192 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,193 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-26 11:47:35,198 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,206 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,207 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,207 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,208 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,217 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,229 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-26 11:47:35,230 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,230 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,230 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,230 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:35,230 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,231 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:35,231 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,248 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,256 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,257 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,257 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,258 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,269 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,281 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,281 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,281 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,281 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-26 11:47:35,281 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,282 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-26 11:47:35,283 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,285 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-26 11:47:35,300 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,308 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,309 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,309 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,310 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,319 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,332 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,332 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,332 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,332 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:35,332 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,335 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:35,335 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,337 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-26 11:47:35,356 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,364 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,364 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,365 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,366 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,374 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,387 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,387 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,387 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,387 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:35,387 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,388 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:35,388 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,388 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-26 11:47:35,404 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,409 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,409 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,410 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,411 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,420 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-26 11:47:35,420 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,433 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,433 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,433 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,433 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:35,433 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,434 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:35,434 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,443 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,451 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,452 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,452 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,453 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,460 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,473 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,473 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,473 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,473 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:35,473 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,474 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:35,474 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,475 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-26 11:47:35,488 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,491 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,492 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,493 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,497 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,509 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,509 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,510 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,510 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:35,510 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,510 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:35,510 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,511 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2023-11-26 11:47:35,519 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,521 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2023-11-26 11:47:35,521 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,522 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,522 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,523 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2023-11-26 11:47:35,525 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,535 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,535 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,535 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,536 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:35,536 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,536 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:35,536 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,544 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,547 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,547 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,547 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,548 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,550 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2023-11-26 11:47:35,551 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,561 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,562 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,562 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,562 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-26 11:47:35,562 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,563 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-26 11:47:35,563 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,588 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,596 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,597 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,597 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,598 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,604 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,617 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,617 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,617 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,617 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:35,617 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,618 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:35,618 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,620 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-26 11:47:35,632 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,640 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,640 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,640 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,641 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,644 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-26 11:47:35,645 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,657 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,657 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,657 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,657 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-26 11:47:35,657 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,659 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-26 11:47:35,659 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,673 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:35,681 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,681 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,681 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,682 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,687 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:35,699 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:35,699 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:35,699 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:35,700 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:35,700 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:35,701 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:35,701 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:35,703 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2023-11-26 11:47:35,716 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-26 11:47:35,745 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-26 11:47:35,746 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-26 11:47:35,747 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:35,747 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:35,775 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:35,776 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-26 11:47:35,777 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-26 11:47:35,777 INFO L513 LassoAnalysis]: Proved termination. [2023-11-26 11:47:35,777 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2023-11-26 11:47:35,780 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2023-11-26 11:47:35,783 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:35,786 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-26 11:47:35,810 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:35,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:35,852 INFO L262 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-26 11:47:35,855 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:47:35,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:35,960 INFO L262 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-26 11:47:35,962 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:47:36,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:36,155 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-26 11:47:36,156 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1730 states and 2205 transitions. cyclomatic complexity: 479 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:36,281 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1730 states and 2205 transitions. cyclomatic complexity: 479. Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 4580 states and 5868 transitions. Complement of second has 5 states. [2023-11-26 11:47:36,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-26 11:47:36,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:36,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 356 transitions. [2023-11-26 11:47:36,286 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 356 transitions. Stem has 49 letters. Loop has 65 letters. [2023-11-26 11:47:36,293 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:47:36,293 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 356 transitions. Stem has 114 letters. Loop has 65 letters. [2023-11-26 11:47:36,294 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:47:36,295 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 356 transitions. Stem has 49 letters. Loop has 130 letters. [2023-11-26 11:47:36,296 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:47:36,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4580 states and 5868 transitions. [2023-11-26 11:47:36,319 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3048 [2023-11-26 11:47:36,371 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:36,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4580 states to 4572 states and 5860 transitions. [2023-11-26 11:47:36,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3135 [2023-11-26 11:47:36,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3156 [2023-11-26 11:47:36,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4572 states and 5860 transitions. [2023-11-26 11:47:36,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:47:36,376 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4572 states and 5860 transitions. [2023-11-26 11:47:36,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4572 states and 5860 transitions. [2023-11-26 11:47:36,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4572 to 4543. [2023-11-26 11:47:36,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4543 states, 4543 states have (on average 1.2817521461589259) internal successors, (5823), 4542 states have internal predecessors, (5823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:36,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4543 states to 4543 states and 5823 transitions. [2023-11-26 11:47:36,478 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4543 states and 5823 transitions. [2023-11-26 11:47:36,479 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:36,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:36,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:36,480 INFO L87 Difference]: Start difference. First operand 4543 states and 5823 transitions. Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:36,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:36,531 INFO L93 Difference]: Finished difference Result 4867 states and 6147 transitions. [2023-11-26 11:47:36,531 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4867 states and 6147 transitions. [2023-11-26 11:47:36,553 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3264 [2023-11-26 11:47:36,573 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4867 states to 4867 states and 6147 transitions. [2023-11-26 11:47:36,573 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3343 [2023-11-26 11:47:36,577 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3343 [2023-11-26 11:47:36,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4867 states and 6147 transitions. [2023-11-26 11:47:36,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:47:36,578 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4867 states and 6147 transitions. [2023-11-26 11:47:36,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4867 states and 6147 transitions. [2023-11-26 11:47:36,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4867 to 4543. [2023-11-26 11:47:36,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4543 states, 4543 states have (on average 1.271186440677966) internal successors, (5775), 4542 states have internal predecessors, (5775), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:36,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4543 states to 4543 states and 5775 transitions. [2023-11-26 11:47:36,671 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4543 states and 5775 transitions. [2023-11-26 11:47:36,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:36,672 INFO L428 stractBuchiCegarLoop]: Abstraction has 4543 states and 5775 transitions. [2023-11-26 11:47:36,672 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 11:47:36,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4543 states and 5775 transitions. [2023-11-26 11:47:36,686 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3048 [2023-11-26 11:47:36,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:36,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:36,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:36,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:36,688 INFO L748 eck$LassoCheckResult]: Stem: 52880#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 52881#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 52904#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52899#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52853#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 52854#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52482#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52483#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52921#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52427#L418 assume !(0 == ~M_E~0); 52428#L418-2 assume !(0 == ~T1_E~0); 52852#L423-1 assume !(0 == ~T2_E~0); 52934#L428-1 assume !(0 == ~T3_E~0); 52932#L433-1 assume !(0 == ~E_1~0); 52908#L438-1 assume !(0 == ~E_2~0); 52767#L443-1 assume !(0 == ~E_3~0); 52752#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52675#L197 assume !(1 == ~m_pc~0); 52670#L197-2 is_master_triggered_~__retres1~0#1 := 0; 52979#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52995#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 52953#L510 assume !(0 != activate_threads_~tmp~1#1); 52388#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52389#L216 assume !(1 == ~t1_pc~0); 52480#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52481#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52531#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 52396#L518 assume !(0 != activate_threads_~tmp___0~0#1); 52397#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52788#L235 assume !(1 == ~t2_pc~0); 52920#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 52645#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52646#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 52967#L526 assume !(0 != activate_threads_~tmp___1~0#1); 52968#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52616#L254 assume !(1 == ~t3_pc~0); 52487#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52488#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52414#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52415#L534 assume !(0 != activate_threads_~tmp___2~0#1); 52632#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52376#L461 assume !(1 == ~M_E~0); 52377#L461-2 assume !(1 == ~T1_E~0); 52484#L466-1 assume !(1 == ~T2_E~0); 52946#L471-1 assume !(1 == ~T3_E~0); 52536#L476-1 assume !(1 == ~E_1~0); 52537#L481-1 assume !(1 == ~E_2~0); 52821#L486-1 assume !(1 == ~E_3~0); 52570#L491-1 assume { :end_inline_reset_delta_events } true; 52571#L652-2 assume !false; 53171#L653 [2023-11-26 11:47:36,688 INFO L750 eck$LassoCheckResult]: Loop: 53171#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55126#L393-1 assume !false; 55118#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 55111#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 55107#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 55104#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55100#L346 assume 0 != eval_~tmp~0#1; 55096#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 55092#L354 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 52509#L53 assume !(0 == ~m_pc~0); 52511#L56 assume 1 == ~m_pc~0; 56820#$Ultimate##157 assume !false; 55676#L73 ~m_pc~0 := 1;~m_st~0 := 2; 55669#master_returnLabel#1 assume { :end_inline_master } true; 55664#L354-2 havoc eval_~tmp_ndt_1~0#1; 55658#L351-1 assume !(0 == ~t1_st~0); 55650#L365-1 assume !(0 == ~t2_st~0); 55644#L379-1 assume !(0 == ~t3_st~0); 55638#L393-1 assume !false; 55635#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 55630#L309 assume !(0 == ~m_st~0); 55615#L313 assume !(0 == ~t1_st~0); 55593#L317 assume !(0 == ~t2_st~0); 55588#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 55584#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 55579#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55573#L346 assume !(0 != eval_~tmp~0#1); 55568#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55563#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55559#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 55553#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55548#L423-3 assume !(0 == ~T2_E~0); 55546#L428-3 assume !(0 == ~T3_E~0); 55544#L433-3 assume !(0 == ~E_1~0); 55538#L438-3 assume !(0 == ~E_2~0); 55532#L443-3 assume !(0 == ~E_3~0); 55314#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55312#L197-12 assume 1 == ~m_pc~0; 55309#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 55307#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55305#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 55302#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55300#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55298#L216-12 assume !(1 == ~t1_pc~0); 55296#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 55294#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55292#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 55290#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 55288#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55286#L235-12 assume !(1 == ~t2_pc~0); 55283#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 55275#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55268#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 55262#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 55261#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55260#L254-12 assume !(1 == ~t3_pc~0); 55259#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 55258#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55257#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55255#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 55254#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55253#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 55249#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55247#L466-3 assume !(1 == ~T2_E~0); 55245#L471-3 assume !(1 == ~T3_E~0); 55243#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55240#L481-3 assume !(1 == ~E_2~0); 55238#L486-3 assume !(1 == ~E_3~0); 55235#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 55233#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 55231#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 55229#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 55215#L671 assume !(0 == start_simulation_~tmp~3#1); 55213#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 55211#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 55209#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 55207#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 55205#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55203#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55201#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 55192#L684 assume !(0 != start_simulation_~tmp___0~1#1); 55185#L652-2 assume !false; 53171#L653 [2023-11-26 11:47:36,689 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:36,689 INFO L85 PathProgramCache]: Analyzing trace with hash -1276375252, now seen corresponding path program 1 times [2023-11-26 11:47:36,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:36,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665109880] [2023-11-26 11:47:36,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:36,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:36,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:36,698 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:36,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:36,710 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:36,710 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:36,711 INFO L85 PathProgramCache]: Analyzing trace with hash -211325414, now seen corresponding path program 1 times [2023-11-26 11:47:36,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:36,711 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47980032] [2023-11-26 11:47:36,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:36,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:36,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:36,722 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:36,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:36,737 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:36,738 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:36,738 INFO L85 PathProgramCache]: Analyzing trace with hash 132337797, now seen corresponding path program 1 times [2023-11-26 11:47:36,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:36,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404724668] [2023-11-26 11:47:36,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:36,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:36,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:36,799 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:36,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:36,800 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404724668] [2023-11-26 11:47:36,800 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [404724668] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:36,800 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:36,800 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:36,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145609404] [2023-11-26 11:47:36,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:37,781 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 11:47:37,781 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 11:47:37,781 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 11:47:37,781 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 11:47:37,781 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-26 11:47:37,781 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:37,782 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 11:47:37,782 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 11:47:37,782 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration19_Loop [2023-11-26 11:47:37,782 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 11:47:37,782 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 11:47:37,785 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,789 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,796 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,817 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,823 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,826 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,830 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,836 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,849 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,866 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,870 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,896 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,906 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,916 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,922 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,926 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,929 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,932 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,941 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,945 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,954 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,959 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,962 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,979 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,982 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,985 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,995 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:37,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:38,000 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:38,003 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:38,497 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 11:47:38,503 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-26 11:47:38,503 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,503 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,505 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,517 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,517 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,536 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2023-11-26 11:47:38,543 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,543 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,548 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:38,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,548 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,550 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,555 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,555 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,570 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2023-11-26 11:47:38,584 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,584 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,592 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:38,592 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,593 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,594 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,601 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,601 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,617 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2023-11-26 11:47:38,636 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,636 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,641 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:38,642 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,642 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,643 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,648 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,649 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,668 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2023-11-26 11:47:38,674 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,674 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet8#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet8#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,679 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:38,679 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,679 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,681 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,689 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,689 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,704 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2023-11-26 11:47:38,720 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,720 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_~__retres1~4#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_~__retres1~4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,725 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:38,726 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,726 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,727 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,734 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,734 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,744 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2023-11-26 11:47:38,758 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,758 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=-1} Honda state: {~E_3~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,762 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:38,762 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,763 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,764 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,765 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2023-11-26 11:47:38,767 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,767 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,782 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,783 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,786 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Ended with exit code 0 [2023-11-26 11:47:38,787 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,787 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,788 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,789 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2023-11-26 11:47:38,791 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,791 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,814 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,814 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=4} Honda state: {~t2_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,818 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2023-11-26 11:47:38,819 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,819 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,820 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,823 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2023-11-26 11:47:38,824 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,824 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,844 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,845 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,848 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2023-11-26 11:47:38,848 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,849 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,850 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,852 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2023-11-26 11:47:38,853 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,853 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,868 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,868 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet5#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet5#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,872 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Ended with exit code 0 [2023-11-26 11:47:38,872 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,872 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,873 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,884 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2023-11-26 11:47:38,885 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,885 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,900 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,901 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,904 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:38,904 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,905 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,906 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,923 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,923 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,940 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2023-11-26 11:47:38,953 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,953 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,966 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:38,966 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,966 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:38,968 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:38,973 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:38,973 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:38,988 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2023-11-26 11:47:38,995 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:38,995 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~ret4#1=0} Honda state: {ULTIMATE.start_eval_#t~ret4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:38,998 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Ended with exit code 0 [2023-11-26 11:47:38,998 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:38,998 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:39,000 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:39,002 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2023-11-26 11:47:39,003 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:39,003 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:39,018 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:47:39,018 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:47:39,021 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Ended with exit code 0 [2023-11-26 11:47:39,022 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:39,022 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:39,023 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:39,024 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2023-11-26 11:47:39,026 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:47:39,027 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:39,045 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2023-11-26 11:47:39,045 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:39,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:39,046 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:39,048 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2023-11-26 11:47:39,049 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-26 11:47:39,049 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:47:39,069 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-26 11:47:39,072 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Ended with exit code 0 [2023-11-26 11:47:39,072 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 11:47:39,073 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 11:47:39,073 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 11:47:39,073 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 11:47:39,073 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-26 11:47:39,073 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:39,073 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 11:47:39,073 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 11:47:39,073 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration19_Loop [2023-11-26 11:47:39,073 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 11:47:39,074 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 11:47:39,078 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,084 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,087 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,090 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,093 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,096 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,099 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,104 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,107 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,110 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,113 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,115 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,118 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,121 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,125 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,132 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,134 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,137 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,139 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,142 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,147 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,150 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,153 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,155 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,158 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,160 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,163 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,169 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,174 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,177 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,181 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,183 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,185 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,188 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,194 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,198 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,222 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,224 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,227 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,229 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,231 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,234 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,237 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,243 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,247 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,249 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,252 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,255 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,257 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,260 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,262 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,268 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:47:39,718 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 11:47:39,723 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-26 11:47:39,723 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:39,723 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:39,724 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:39,732 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:39,748 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:39,748 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:39,748 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:39,748 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:39,748 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:39,749 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:39,749 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:39,748 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2023-11-26 11:47:39,758 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:39,763 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:39,763 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:39,763 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:39,765 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:39,770 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:39,784 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2023-11-26 11:47:39,787 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:39,787 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:39,787 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:39,787 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:39,787 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:39,788 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:39,788 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:39,804 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:39,808 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:39,808 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:39,809 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:39,810 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:39,815 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:39,828 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2023-11-26 11:47:39,831 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:39,831 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:39,831 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:39,831 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:39,831 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:39,833 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:39,833 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:39,843 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:39,847 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:39,848 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:39,848 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:39,849 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:39,854 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:39,870 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2023-11-26 11:47:39,870 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:39,870 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:39,871 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:39,871 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:39,871 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:39,871 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:39,872 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:39,888 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:39,892 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Ended with exit code 0 [2023-11-26 11:47:39,892 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:39,893 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:39,894 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:39,903 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2023-11-26 11:47:39,905 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:39,922 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:39,922 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:39,922 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:39,922 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:39,923 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:39,924 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:39,924 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:39,941 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:39,944 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Ended with exit code 0 [2023-11-26 11:47:39,944 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:39,945 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:39,945 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:39,949 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2023-11-26 11:47:39,950 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:39,963 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:39,963 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:39,963 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:39,963 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:39,963 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:39,964 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:39,964 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:39,973 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:39,977 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Ended with exit code 0 [2023-11-26 11:47:39,978 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:39,978 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:39,979 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:39,983 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2023-11-26 11:47:39,985 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:39,998 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:39,998 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:39,998 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:39,998 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-26 11:47:39,998 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:40,005 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-26 11:47:40,005 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:40,007 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:40,011 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Ended with exit code 0 [2023-11-26 11:47:40,011 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:40,011 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:40,012 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:40,014 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2023-11-26 11:47:40,015 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:40,031 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:40,031 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:40,031 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:40,031 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:40,031 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:40,032 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:40,032 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:40,048 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:40,052 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:40,052 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:40,052 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:40,054 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:40,060 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:40,072 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2023-11-26 11:47:40,075 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:40,075 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:40,075 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:40,075 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-26 11:47:40,075 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:40,076 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-26 11:47:40,076 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:40,079 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:40,082 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:40,083 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:40,083 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:40,085 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:40,094 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:40,108 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2023-11-26 11:47:40,111 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:40,111 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:40,111 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:40,111 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:40,112 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:40,112 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:40,112 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:40,128 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:40,132 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:40,132 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:40,133 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:40,134 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:40,142 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:40,157 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Waiting until timeout for monitored process [2023-11-26 11:47:40,158 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:40,158 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:40,158 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:40,158 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:40,159 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:40,160 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:40,160 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:40,176 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:40,180 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:40,180 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:40,181 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:40,182 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:40,189 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:40,204 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Waiting until timeout for monitored process [2023-11-26 11:47:40,204 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:40,204 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:40,205 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:40,205 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:40,205 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:40,205 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:40,206 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:40,224 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:40,228 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:40,228 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:40,229 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:40,230 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:40,235 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:40,248 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Waiting until timeout for monitored process [2023-11-26 11:47:40,251 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:40,251 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:40,251 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:40,251 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-26 11:47:40,252 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:40,255 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-26 11:47:40,255 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:40,265 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:40,269 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:40,270 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:40,270 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:40,272 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:40,276 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:40,292 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Waiting until timeout for monitored process [2023-11-26 11:47:40,292 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:40,293 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:40,293 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:40,293 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:40,293 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:40,294 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:40,294 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:40,308 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:47:40,312 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:40,312 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:40,313 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:40,314 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:40,318 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:47:40,332 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Waiting until timeout for monitored process [2023-11-26 11:47:40,334 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:47:40,334 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:47:40,334 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:47:40,334 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:47:40,334 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:47:40,336 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:47:40,336 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:47:40,352 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-26 11:47:40,355 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-26 11:47:40,355 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-26 11:47:40,356 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:40,356 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:40,357 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:40,361 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-26 11:47:40,361 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-26 11:47:40,361 INFO L513 LassoAnalysis]: Proved termination. [2023-11-26 11:47:40,362 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T1_E~0) = -1*~T1_E~0 + 1 Supporting invariants [] [2023-11-26 11:47:40,364 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Waiting until timeout for monitored process [2023-11-26 11:47:40,366 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:40,367 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-26 11:47:40,384 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:40,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:40,421 INFO L262 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-26 11:47:40,423 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:47:40,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:40,562 INFO L262 TraceCheckSpWp]: Trace formula consists of 154 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-26 11:47:40,566 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:47:40,731 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Forceful destruction successful, exit code 0 [2023-11-26 11:47:40,835 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2023-11-26 11:47:40,837 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-26 11:47:40,837 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 4543 states and 5775 transitions. cyclomatic complexity: 1244 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:40,938 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 4543 states and 5775 transitions. cyclomatic complexity: 1244. Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 9154 states and 11610 transitions. Complement of second has 4 states. [2023-11-26 11:47:40,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-26 11:47:40,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:40,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 397 transitions. [2023-11-26 11:47:40,941 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 397 transitions. Stem has 50 letters. Loop has 82 letters. [2023-11-26 11:47:40,943 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:47:40,943 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 397 transitions. Stem has 132 letters. Loop has 82 letters. [2023-11-26 11:47:40,944 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:47:40,944 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 397 transitions. Stem has 50 letters. Loop has 164 letters. [2023-11-26 11:47:40,947 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:47:40,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9154 states and 11610 transitions. [2023-11-26 11:47:40,999 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3048 [2023-11-26 11:47:41,039 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9154 states to 9154 states and 11610 transitions. [2023-11-26 11:47:41,039 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3148 [2023-11-26 11:47:41,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3189 [2023-11-26 11:47:41,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9154 states and 11610 transitions. [2023-11-26 11:47:41,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:47:41,044 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9154 states and 11610 transitions. [2023-11-26 11:47:41,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9154 states and 11610 transitions. [2023-11-26 11:47:41,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9154 to 9113. [2023-11-26 11:47:41,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9113 states, 9113 states have (on average 1.2695051026006803) internal successors, (11569), 9112 states have internal predecessors, (11569), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:41,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9113 states to 9113 states and 11569 transitions. [2023-11-26 11:47:41,216 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9113 states and 11569 transitions. [2023-11-26 11:47:41,216 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:41,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:41,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:41,217 INFO L87 Difference]: Start difference. First operand 9113 states and 11569 transitions. Second operand has 3 states, 3 states have (on average 44.0) internal successors, (132), 2 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:41,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:41,294 INFO L93 Difference]: Finished difference Result 11337 states and 14252 transitions. [2023-11-26 11:47:41,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11337 states and 14252 transitions. [2023-11-26 11:47:41,342 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3812 [2023-11-26 11:47:41,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11337 states to 11337 states and 14252 transitions. [2023-11-26 11:47:41,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3928 [2023-11-26 11:47:41,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3928 [2023-11-26 11:47:41,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11337 states and 14252 transitions. [2023-11-26 11:47:41,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:47:41,386 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11337 states and 14252 transitions. [2023-11-26 11:47:41,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11337 states and 14252 transitions. [2023-11-26 11:47:41,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11337 to 10593. [2023-11-26 11:47:41,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10593 states, 10593 states have (on average 1.2661191352780137) internal successors, (13412), 10592 states have internal predecessors, (13412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:41,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10593 states to 10593 states and 13412 transitions. [2023-11-26 11:47:41,649 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10593 states and 13412 transitions. [2023-11-26 11:47:41,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:41,650 INFO L428 stractBuchiCegarLoop]: Abstraction has 10593 states and 13412 transitions. [2023-11-26 11:47:41,650 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 11:47:41,650 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10593 states and 13412 transitions. [2023-11-26 11:47:41,684 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3564 [2023-11-26 11:47:41,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:41,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:41,685 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:41,685 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:41,686 INFO L748 eck$LassoCheckResult]: Stem: 87474#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 87475#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 87502#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87495#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87441#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 87442#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87053#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87054#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87522#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86995#L418 assume !(0 == ~M_E~0); 86996#L418-2 assume !(0 == ~T1_E~0); 87440#L423-1 assume !(0 == ~T2_E~0); 87534#L428-1 assume !(0 == ~T3_E~0); 87530#L433-1 assume !(0 == ~E_1~0); 87506#L438-1 assume !(0 == ~E_2~0); 87347#L443-1 assume !(0 == ~E_3~0); 87332#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87243#L197 assume !(1 == ~m_pc~0); 87244#L197-2 is_master_triggered_~__retres1~0#1 := 0; 87581#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87425#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 87426#L510 assume !(0 != activate_threads_~tmp~1#1); 86954#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86955#L216 assume !(1 == ~t1_pc~0); 87051#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 87052#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87103#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 86962#L518 assume !(0 != activate_threads_~tmp___0~0#1); 86963#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87369#L235 assume !(1 == ~t2_pc~0); 87514#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 87215#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87216#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 87563#L526 assume !(0 != activate_threads_~tmp___1~0#1); 87564#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87187#L254 assume !(1 == ~t3_pc~0); 87060#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 87061#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86980#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 86981#L534 assume !(0 != activate_threads_~tmp___2~0#1); 87202#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86940#L461 assume !(1 == ~M_E~0); 86941#L461-2 assume !(1 == ~T1_E~0); 87055#L466-1 assume !(1 == ~T2_E~0); 87543#L471-1 assume !(1 == ~T3_E~0); 87108#L476-1 assume !(1 == ~E_1~0); 87109#L481-1 assume !(1 == ~E_2~0); 87405#L486-1 assume !(1 == ~E_3~0); 87144#L491-1 assume { :end_inline_reset_delta_events } true; 87145#L652-2 assume !false; 87860#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 87854#L393-1 [2023-11-26 11:47:41,686 INFO L750 eck$LassoCheckResult]: Loop: 87854#L393-1 assume !false; 87849#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 87844#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 87840#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 87834#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 87831#L346 assume 0 != eval_~tmp~0#1; 87826#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 87819#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 87814#L354-2 havoc eval_~tmp_ndt_1~0#1; 87810#L351-1 assume !(0 == ~t1_st~0); 87811#L365-1 assume !(0 == ~t2_st~0); 87863#L379-1 assume !(0 == ~t3_st~0); 87854#L393-1 [2023-11-26 11:47:41,686 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:41,687 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 1 times [2023-11-26 11:47:41,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:41,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975172499] [2023-11-26 11:47:41,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:41,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:41,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:41,697 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:41,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:41,718 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:41,719 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:41,719 INFO L85 PathProgramCache]: Analyzing trace with hash -1356345121, now seen corresponding path program 1 times [2023-11-26 11:47:41,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:41,720 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [496219016] [2023-11-26 11:47:41,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:41,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:41,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:41,724 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:41,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:41,728 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:41,728 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:41,729 INFO L85 PathProgramCache]: Analyzing trace with hash 1338864530, now seen corresponding path program 1 times [2023-11-26 11:47:41,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:41,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867747568] [2023-11-26 11:47:41,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:41,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:41,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:41,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:41,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:41,800 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1867747568] [2023-11-26 11:47:41,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1867747568] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:41,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:41,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:41,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [430214308] [2023-11-26 11:47:41,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:41,861 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:41,862 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:41,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:41,862 INFO L87 Difference]: Start difference. First operand 10593 states and 13412 transitions. cyclomatic complexity: 2867 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:42,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:42,125 INFO L93 Difference]: Finished difference Result 18276 states and 22769 transitions. [2023-11-26 11:47:42,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18276 states and 22769 transitions. [2023-11-26 11:47:42,200 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 5738 [2023-11-26 11:47:42,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18276 states to 18276 states and 22769 transitions. [2023-11-26 11:47:42,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6394 [2023-11-26 11:47:42,274 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6394 [2023-11-26 11:47:42,274 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18276 states and 22769 transitions. [2023-11-26 11:47:42,278 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:47:42,279 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18276 states and 22769 transitions. [2023-11-26 11:47:42,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18276 states and 22769 transitions. [2023-11-26 11:47:42,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18276 to 17484. [2023-11-26 11:47:42,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17484 states, 17484 states have (on average 1.2497712194005948) internal successors, (21851), 17483 states have internal predecessors, (21851), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:42,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17484 states to 17484 states and 21851 transitions. [2023-11-26 11:47:42,650 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17484 states and 21851 transitions. [2023-11-26 11:47:42,651 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:42,651 INFO L428 stractBuchiCegarLoop]: Abstraction has 17484 states and 21851 transitions. [2023-11-26 11:47:42,651 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 11:47:42,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17484 states and 21851 transitions. [2023-11-26 11:47:42,858 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 5474 [2023-11-26 11:47:42,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:42,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:42,860 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:42,860 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:42,860 INFO L748 eck$LassoCheckResult]: Stem: 116367#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 116368#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 116395#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 116388#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 116332#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 116333#L281-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 116449#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126091#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126090#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126089#L418 assume !(0 == ~M_E~0); 126088#L418-2 assume !(0 == ~T1_E~0); 126087#L423-1 assume !(0 == ~T2_E~0); 126086#L428-1 assume !(0 == ~T3_E~0); 126085#L433-1 assume !(0 == ~E_1~0); 126084#L438-1 assume !(0 == ~E_2~0); 126083#L443-1 assume !(0 == ~E_3~0); 126082#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126081#L197 assume !(1 == ~m_pc~0); 126080#L197-2 is_master_triggered_~__retres1~0#1 := 0; 126079#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126078#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 126077#L510 assume !(0 != activate_threads_~tmp~1#1); 126076#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126075#L216 assume !(1 == ~t1_pc~0); 126074#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 126073#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126072#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 126071#L518 assume !(0 != activate_threads_~tmp___0~0#1); 126070#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126069#L235 assume !(1 == ~t2_pc~0); 126067#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 126066#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126065#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 126064#L526 assume !(0 != activate_threads_~tmp___1~0#1); 126063#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126062#L254 assume !(1 == ~t3_pc~0); 126061#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 126060#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126059#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 126058#L534 assume !(0 != activate_threads_~tmp___2~0#1); 126057#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126056#L461 assume !(1 == ~M_E~0); 126055#L461-2 assume !(1 == ~T1_E~0); 126054#L466-1 assume !(1 == ~T2_E~0); 126053#L471-1 assume !(1 == ~T3_E~0); 126052#L476-1 assume !(1 == ~E_1~0); 126051#L481-1 assume !(1 == ~E_2~0); 126050#L486-1 assume !(1 == ~E_3~0); 126049#L491-1 assume { :end_inline_reset_delta_events } true; 126046#L652-2 assume !false; 126047#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 126048#L393-1 [2023-11-26 11:47:42,861 INFO L750 eck$LassoCheckResult]: Loop: 126048#L393-1 assume !false; 127180#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 127172#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 127164#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 127158#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 127157#L346 assume 0 != eval_~tmp~0#1; 127156#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 127143#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 127135#L354-2 havoc eval_~tmp_ndt_1~0#1; 127127#L351-1 assume !(0 == ~t1_st~0); 127118#L365-1 assume !(0 == ~t2_st~0); 127107#L379-1 assume !(0 == ~t3_st~0); 126048#L393-1 [2023-11-26 11:47:42,861 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:42,861 INFO L85 PathProgramCache]: Analyzing trace with hash 1015345778, now seen corresponding path program 1 times [2023-11-26 11:47:42,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:42,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588674694] [2023-11-26 11:47:42,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:42,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:42,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:42,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:42,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:42,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588674694] [2023-11-26 11:47:42,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1588674694] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:42,900 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:42,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:42,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352771004] [2023-11-26 11:47:42,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:42,901 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:42,901 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:42,902 INFO L85 PathProgramCache]: Analyzing trace with hash -1356345121, now seen corresponding path program 2 times [2023-11-26 11:47:42,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:42,902 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869193892] [2023-11-26 11:47:42,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:42,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:42,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:42,907 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:42,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:42,912 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:42,986 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:42,986 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:42,987 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:42,987 INFO L87 Difference]: Start difference. First operand 17484 states and 21851 transitions. cyclomatic complexity: 4447 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:43,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:43,055 INFO L93 Difference]: Finished difference Result 11757 states and 14743 transitions. [2023-11-26 11:47:43,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11757 states and 14743 transitions. [2023-11-26 11:47:43,125 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3979 [2023-11-26 11:47:43,181 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11757 states to 11757 states and 14743 transitions. [2023-11-26 11:47:43,181 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4166 [2023-11-26 11:47:43,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4166 [2023-11-26 11:47:43,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11757 states and 14743 transitions. [2023-11-26 11:47:43,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:47:43,189 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11757 states and 14743 transitions. [2023-11-26 11:47:43,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11757 states and 14743 transitions. [2023-11-26 11:47:43,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11757 to 11757. [2023-11-26 11:47:43,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11757 states, 11757 states have (on average 1.2539763545122056) internal successors, (14743), 11756 states have internal predecessors, (14743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:43,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11757 states to 11757 states and 14743 transitions. [2023-11-26 11:47:43,503 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11757 states and 14743 transitions. [2023-11-26 11:47:43,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:43,507 INFO L428 stractBuchiCegarLoop]: Abstraction has 11757 states and 14743 transitions. [2023-11-26 11:47:43,507 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 11:47:43,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11757 states and 14743 transitions. [2023-11-26 11:47:43,543 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3979 [2023-11-26 11:47:43,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:43,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:43,545 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:43,545 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:43,545 INFO L748 eck$LassoCheckResult]: Stem: 145605#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 145606#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 145632#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 145626#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 145574#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 145575#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 145175#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 145176#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 145651#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 145114#L418 assume !(0 == ~M_E~0); 145115#L418-2 assume !(0 == ~T1_E~0); 145573#L423-1 assume !(0 == ~T2_E~0); 145660#L428-1 assume !(0 == ~T3_E~0); 145658#L433-1 assume !(0 == ~E_1~0); 145635#L438-1 assume !(0 == ~E_2~0); 145473#L443-1 assume !(0 == ~E_3~0); 145458#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 145373#L197 assume !(1 == ~m_pc~0); 145374#L197-2 is_master_triggered_~__retres1~0#1 := 0; 145710#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 145555#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 145556#L510 assume !(0 != activate_threads_~tmp~1#1); 145078#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145079#L216 assume !(1 == ~t1_pc~0); 145169#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 145170#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 145224#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 145080#L518 assume !(0 != activate_threads_~tmp___0~0#1); 145081#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 145492#L235 assume !(1 == ~t2_pc~0); 145644#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 145343#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145344#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 145692#L526 assume !(0 != activate_threads_~tmp___1~0#1); 145693#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 145312#L254 assume !(1 == ~t3_pc~0); 145181#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 145182#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145100#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 145101#L534 assume !(0 != activate_threads_~tmp___2~0#1); 145332#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145064#L461 assume !(1 == ~M_E~0); 145065#L461-2 assume !(1 == ~T1_E~0); 145177#L466-1 assume !(1 == ~T2_E~0); 145670#L471-1 assume !(1 == ~T3_E~0); 145225#L476-1 assume !(1 == ~E_1~0); 145226#L481-1 assume !(1 == ~E_2~0); 145528#L486-1 assume !(1 == ~E_3~0); 145260#L491-1 assume { :end_inline_reset_delta_events } true; 145261#L652-2 assume !false; 147602#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 147600#L393-1 [2023-11-26 11:47:43,546 INFO L750 eck$LassoCheckResult]: Loop: 147600#L393-1 assume !false; 147598#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 147596#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 147594#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 147592#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 147589#L346 assume 0 != eval_~tmp~0#1; 147588#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 147584#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 147582#L354-2 havoc eval_~tmp_ndt_1~0#1; 147580#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 147576#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 147574#L368-2 havoc eval_~tmp_ndt_2~0#1; 147571#L365-1 assume !(0 == ~t2_st~0); 147572#L379-1 assume !(0 == ~t3_st~0); 147600#L393-1 [2023-11-26 11:47:43,547 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:43,547 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 2 times [2023-11-26 11:47:43,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:43,548 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809201178] [2023-11-26 11:47:43,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:43,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:43,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:43,557 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:43,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:43,578 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:43,579 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:43,579 INFO L85 PathProgramCache]: Analyzing trace with hash 2096165373, now seen corresponding path program 1 times [2023-11-26 11:47:43,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:43,580 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1676377819] [2023-11-26 11:47:43,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:43,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:43,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:43,586 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:43,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:43,590 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:43,591 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:43,591 INFO L85 PathProgramCache]: Analyzing trace with hash -1967606800, now seen corresponding path program 1 times [2023-11-26 11:47:43,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:43,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [75689031] [2023-11-26 11:47:43,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:43,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:43,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:43,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:43,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:43,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [75689031] [2023-11-26 11:47:43,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [75689031] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:43,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:43,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:43,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129385247] [2023-11-26 11:47:43,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:43,703 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:43,704 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:43,704 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:43,704 INFO L87 Difference]: Start difference. First operand 11757 states and 14743 transitions. cyclomatic complexity: 3034 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:43,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:43,945 INFO L93 Difference]: Finished difference Result 19045 states and 23609 transitions. [2023-11-26 11:47:43,945 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19045 states and 23609 transitions. [2023-11-26 11:47:44,039 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6296 [2023-11-26 11:47:44,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19045 states to 19045 states and 23609 transitions. [2023-11-26 11:47:44,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6608 [2023-11-26 11:47:44,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6608 [2023-11-26 11:47:44,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19045 states and 23609 transitions. [2023-11-26 11:47:44,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:47:44,125 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19045 states and 23609 transitions. [2023-11-26 11:47:44,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19045 states and 23609 transitions. [2023-11-26 11:47:44,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19045 to 19045. [2023-11-26 11:47:44,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19045 states, 19045 states have (on average 1.2396429509057496) internal successors, (23609), 19044 states have internal predecessors, (23609), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:44,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19045 states to 19045 states and 23609 transitions. [2023-11-26 11:47:44,545 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19045 states and 23609 transitions. [2023-11-26 11:47:44,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:44,546 INFO L428 stractBuchiCegarLoop]: Abstraction has 19045 states and 23609 transitions. [2023-11-26 11:47:44,546 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-26 11:47:44,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19045 states and 23609 transitions. [2023-11-26 11:47:44,608 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6296 [2023-11-26 11:47:44,608 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:44,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:44,609 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:44,610 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:44,610 INFO L748 eck$LassoCheckResult]: Stem: 176416#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 176417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 176442#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 176437#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 176383#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 176384#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 175982#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 175983#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 176463#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 175932#L418 assume !(0 == ~M_E~0); 175933#L418-2 assume !(0 == ~T1_E~0); 176382#L423-1 assume !(0 == ~T2_E~0); 176472#L428-1 assume !(0 == ~T3_E~0); 176470#L433-1 assume !(0 == ~E_1~0); 176446#L438-1 assume !(0 == ~E_2~0); 176284#L443-1 assume !(0 == ~E_3~0); 176267#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176177#L197 assume !(1 == ~m_pc~0); 176178#L197-2 is_master_triggered_~__retres1~0#1 := 0; 176530#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176365#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 176366#L510 assume !(0 != activate_threads_~tmp~1#1); 175888#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 175889#L216 assume !(1 == ~t1_pc~0); 175980#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 175981#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176032#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 175894#L518 assume !(0 != activate_threads_~tmp___0~0#1); 175895#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176304#L235 assume !(1 == ~t2_pc~0); 176462#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 176150#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176151#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 176509#L526 assume !(0 != activate_threads_~tmp___1~0#1); 176510#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176118#L254 assume !(1 == ~t3_pc~0); 175989#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 175990#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 175912#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 175913#L534 assume !(0 != activate_threads_~tmp___2~0#1); 176135#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175874#L461 assume !(1 == ~M_E~0); 175875#L461-2 assume !(1 == ~T1_E~0); 175984#L466-1 assume !(1 == ~T2_E~0); 176486#L471-1 assume !(1 == ~T3_E~0); 176037#L476-1 assume !(1 == ~E_1~0); 176038#L481-1 assume !(1 == ~E_2~0); 176341#L486-1 assume !(1 == ~E_3~0); 176074#L491-1 assume { :end_inline_reset_delta_events } true; 176075#L652-2 assume !false; 178830#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 178828#L393-1 [2023-11-26 11:47:44,610 INFO L750 eck$LassoCheckResult]: Loop: 178828#L393-1 assume !false; 178826#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 178825#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 178821#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 178819#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 178817#L346 assume 0 != eval_~tmp~0#1; 178815#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 178811#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 178812#L354-2 havoc eval_~tmp_ndt_1~0#1; 179844#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 179769#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 179770#L368-2 havoc eval_~tmp_ndt_2~0#1; 178839#L365-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 178837#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 178836#L382-2 havoc eval_~tmp_ndt_3~0#1; 178833#L379-1 assume !(0 == ~t3_st~0); 178828#L393-1 [2023-11-26 11:47:44,611 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:44,611 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 3 times [2023-11-26 11:47:44,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:44,613 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31936553] [2023-11-26 11:47:44,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:44,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:44,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:44,623 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:44,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:44,637 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:44,638 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:44,638 INFO L85 PathProgramCache]: Analyzing trace with hash 71302111, now seen corresponding path program 1 times [2023-11-26 11:47:44,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:44,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088442533] [2023-11-26 11:47:44,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:44,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:44,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:44,643 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:44,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:44,648 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:44,649 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:44,649 INFO L85 PathProgramCache]: Analyzing trace with hash -1088484078, now seen corresponding path program 1 times [2023-11-26 11:47:44,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:44,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568303532] [2023-11-26 11:47:44,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:44,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:44,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:44,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:44,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:44,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568303532] [2023-11-26 11:47:44,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568303532] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:44,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:44,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:44,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41379014] [2023-11-26 11:47:44,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:44,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:44,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:44,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:44,777 INFO L87 Difference]: Start difference. First operand 19045 states and 23609 transitions. cyclomatic complexity: 4612 Second operand has 3 states, 2 states have (on average 33.5) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:45,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:45,141 INFO L93 Difference]: Finished difference Result 24493 states and 30294 transitions. [2023-11-26 11:47:45,142 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24493 states and 30294 transitions. [2023-11-26 11:47:45,284 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8139 [2023-11-26 11:47:45,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24493 states to 24493 states and 30294 transitions. [2023-11-26 11:47:45,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8554 [2023-11-26 11:47:45,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8554 [2023-11-26 11:47:45,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24493 states and 30294 transitions. [2023-11-26 11:47:45,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:47:45,534 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24493 states and 30294 transitions. [2023-11-26 11:47:45,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24493 states and 30294 transitions. [2023-11-26 11:47:45,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24493 to 24493. [2023-11-26 11:47:46,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24493 states, 24493 states have (on average 1.2368431796839914) internal successors, (30294), 24492 states have internal predecessors, (30294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:46,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24493 states to 24493 states and 30294 transitions. [2023-11-26 11:47:46,120 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24493 states and 30294 transitions. [2023-11-26 11:47:46,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:46,121 INFO L428 stractBuchiCegarLoop]: Abstraction has 24493 states and 30294 transitions. [2023-11-26 11:47:46,121 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-26 11:47:46,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24493 states and 30294 transitions. [2023-11-26 11:47:46,193 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8139 [2023-11-26 11:47:46,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:46,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:46,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:46,195 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:46,195 INFO L748 eck$LassoCheckResult]: Stem: 219978#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 219979#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 220008#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 219999#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 219945#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 219946#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 219533#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 219534#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 220030#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 219482#L418 assume !(0 == ~M_E~0); 219483#L418-2 assume !(0 == ~T1_E~0); 219944#L423-1 assume !(0 == ~T2_E~0); 220041#L428-1 assume !(0 == ~T3_E~0); 220039#L433-1 assume !(0 == ~E_1~0); 220014#L438-1 assume !(0 == ~E_2~0); 219838#L443-1 assume !(0 == ~E_3~0); 219818#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 219727#L197 assume !(1 == ~m_pc~0); 219728#L197-2 is_master_triggered_~__retres1~0#1 := 0; 220092#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 219928#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 219929#L510 assume !(0 != activate_threads_~tmp~1#1); 219434#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 219435#L216 assume !(1 == ~t1_pc~0); 219531#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 219532#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 219581#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 219440#L518 assume !(0 != activate_threads_~tmp___0~0#1); 219441#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 219860#L235 assume !(1 == ~t2_pc~0); 220028#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 219697#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 219698#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 220075#L526 assume !(0 != activate_threads_~tmp___1~0#1); 220076#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 219665#L254 assume !(1 == ~t3_pc~0); 219540#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 219541#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 219458#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 219459#L534 assume !(0 != activate_threads_~tmp___2~0#1); 219682#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219420#L461 assume !(1 == ~M_E~0); 219421#L461-2 assume !(1 == ~T1_E~0); 219535#L466-1 assume !(1 == ~T2_E~0); 220052#L471-1 assume !(1 == ~T3_E~0); 219586#L476-1 assume !(1 == ~E_1~0); 219587#L481-1 assume !(1 == ~E_2~0); 219900#L486-1 assume !(1 == ~E_3~0); 219622#L491-1 assume { :end_inline_reset_delta_events } true; 219623#L652-2 assume !false; 229388#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 229796#L393-1 [2023-11-26 11:47:46,195 INFO L750 eck$LassoCheckResult]: Loop: 229796#L393-1 assume !false; 237994#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 237992#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 237990#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 237989#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 237988#L346 assume 0 != eval_~tmp~0#1; 237987#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 237984#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 237982#L354-2 havoc eval_~tmp_ndt_1~0#1; 237980#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 237977#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 237975#L368-2 havoc eval_~tmp_ndt_2~0#1; 237973#L365-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 237930#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 237971#L382-2 havoc eval_~tmp_ndt_3~0#1; 237999#L379-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 237998#L396 assume !(0 != eval_~tmp_ndt_4~0#1); 237997#L396-2 havoc eval_~tmp_ndt_4~0#1; 229796#L393-1 [2023-11-26 11:47:46,196 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:46,196 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 4 times [2023-11-26 11:47:46,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:46,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304620148] [2023-11-26 11:47:46,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:46,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:46,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:46,205 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:46,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:46,219 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:46,219 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:46,219 INFO L85 PathProgramCache]: Analyzing trace with hash -198166090, now seen corresponding path program 1 times [2023-11-26 11:47:46,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:46,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532064481] [2023-11-26 11:47:46,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:46,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:46,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:46,224 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:46,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:46,228 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:46,229 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:46,229 INFO L85 PathProgramCache]: Analyzing trace with hash 1938803241, now seen corresponding path program 1 times [2023-11-26 11:47:46,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:46,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621248820] [2023-11-26 11:47:46,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:46,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:46,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:46,240 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:46,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:46,256 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:47:47,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:47,271 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:47:47,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:47:47,462 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.11 11:47:47 BoogieIcfgContainer [2023-11-26 11:47:47,465 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-26 11:47:47,466 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-26 11:47:47,466 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-26 11:47:47,466 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-26 11:47:47,467 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:47:26" (3/4) ... [2023-11-26 11:47:47,468 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-26 11:47:47,562 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/witness.graphml [2023-11-26 11:47:47,563 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-26 11:47:47,563 INFO L158 Benchmark]: Toolchain (without parser) took 23159.39ms. Allocated memory was 125.8MB in the beginning and 935.3MB in the end (delta: 809.5MB). Free memory was 79.9MB in the beginning and 490.0MB in the end (delta: -410.1MB). Peak memory consumption was 400.4MB. Max. memory is 16.1GB. [2023-11-26 11:47:47,564 INFO L158 Benchmark]: CDTParser took 0.29ms. Allocated memory is still 100.7MB. Free memory is still 51.5MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 11:47:47,564 INFO L158 Benchmark]: CACSL2BoogieTranslator took 431.68ms. Allocated memory is still 125.8MB. Free memory was 79.6MB in the beginning and 65.3MB in the end (delta: 14.3MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-26 11:47:47,564 INFO L158 Benchmark]: Boogie Procedure Inliner took 68.85ms. Allocated memory is still 125.8MB. Free memory was 65.3MB in the beginning and 62.0MB in the end (delta: 3.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-26 11:47:47,565 INFO L158 Benchmark]: Boogie Preprocessor took 75.78ms. Allocated memory is still 125.8MB. Free memory was 61.7MB in the beginning and 57.8MB in the end (delta: 3.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-26 11:47:47,565 INFO L158 Benchmark]: RCFGBuilder took 1052.90ms. Allocated memory is still 125.8MB. Free memory was 57.8MB in the beginning and 66.8MB in the end (delta: -9.0MB). Peak memory consumption was 12.2MB. Max. memory is 16.1GB. [2023-11-26 11:47:47,565 INFO L158 Benchmark]: BuchiAutomizer took 21426.73ms. Allocated memory was 125.8MB in the beginning and 935.3MB in the end (delta: 809.5MB). Free memory was 66.8MB in the beginning and 496.3MB in the end (delta: -429.5MB). Peak memory consumption was 379.8MB. Max. memory is 16.1GB. [2023-11-26 11:47:47,566 INFO L158 Benchmark]: Witness Printer took 97.11ms. Allocated memory is still 935.3MB. Free memory was 496.3MB in the beginning and 490.0MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-26 11:47:47,568 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29ms. Allocated memory is still 100.7MB. Free memory is still 51.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 431.68ms. Allocated memory is still 125.8MB. Free memory was 79.6MB in the beginning and 65.3MB in the end (delta: 14.3MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 68.85ms. Allocated memory is still 125.8MB. Free memory was 65.3MB in the beginning and 62.0MB in the end (delta: 3.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 75.78ms. Allocated memory is still 125.8MB. Free memory was 61.7MB in the beginning and 57.8MB in the end (delta: 3.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1052.90ms. Allocated memory is still 125.8MB. Free memory was 57.8MB in the beginning and 66.8MB in the end (delta: -9.0MB). Peak memory consumption was 12.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 21426.73ms. Allocated memory was 125.8MB in the beginning and 935.3MB in the end (delta: 809.5MB). Free memory was 66.8MB in the beginning and 496.3MB in the end (delta: -429.5MB). Peak memory consumption was 379.8MB. Max. memory is 16.1GB. * Witness Printer took 97.11ms. Allocated memory is still 935.3MB. Free memory was 496.3MB in the beginning and 490.0MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 25 terminating modules (23 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function ((-1 * E_3) + 1) and consists of 3 locations. One deterministic module has affine ranking function ((-1 * T1_E) + 1) and consists of 3 locations. 23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 24493 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 21.2s and 24 iterations. TraceHistogramMax:2. Analysis of lassos took 12.1s. Construction of modules took 1.0s. Büchi inclusion checks took 6.8s. Highest rank in rank-based complementation 3. Minimization of det autom 17. Minimization of nondet autom 8. Automata minimization 2.9s AutomataMinimizationTime, 25 MinimizatonAttempts, 6902 StatesRemovedByMinimization, 16 NontrivialMinimizations. Non-live state removal took 1.4s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 6/6 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 9637 SdHoareTripleChecker+Valid, 1.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 9635 mSDsluCounter, 23064 SdHoareTripleChecker+Invalid, 1.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 11799 mSDsCounter, 243 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 711 IncrementalHoareTripleChecker+Invalid, 954 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 243 mSolverCounterUnsat, 11265 mSDtfsCounter, 711 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc3 concLT2 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital113 mio100 ax100 hnf100 lsp8 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp60 tf111 neg100 sie108 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 43ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 26 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 1.1s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 341]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L351-L362] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L365-L376] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L379-L390] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L393-L404] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 341]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L351-L362] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L365-L376] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L379-L390] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L393-L404] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-26 11:47:47,723 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4efb4696-9770-4e60-8ca9-ccc33d20c619/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)