./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.10.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.10.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 12:01:05,305 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 12:01:05,418 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 12:01:05,425 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 12:01:05,425 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 12:01:05,456 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 12:01:05,457 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 12:01:05,458 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 12:01:05,458 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 12:01:05,459 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 12:01:05,460 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 12:01:05,461 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 12:01:05,462 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 12:01:05,462 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 12:01:05,463 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 12:01:05,464 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 12:01:05,464 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 12:01:05,465 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 12:01:05,466 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 12:01:05,466 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 12:01:05,467 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 12:01:05,468 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 12:01:05,469 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 12:01:05,470 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 12:01:05,470 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 12:01:05,471 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 12:01:05,472 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 12:01:05,472 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 12:01:05,473 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 12:01:05,473 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 12:01:05,474 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 12:01:05,475 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 12:01:05,475 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 12:01:05,476 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 12:01:05,476 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 12:01:05,477 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 12:01:05,477 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 12:01:05,479 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 12:01:05,480 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 [2023-11-26 12:01:05,769 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 12:01:05,800 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 12:01:05,803 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 12:01:05,804 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 12:01:05,805 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 12:01:05,807 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/transmitter.10.cil.c [2023-11-26 12:01:09,158 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 12:01:09,550 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 12:01:09,551 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/sv-benchmarks/c/systemc/transmitter.10.cil.c [2023-11-26 12:01:09,572 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/data/594c0a85e/08c52733ec634475a0382e961477c6d4/FLAG9a946f831 [2023-11-26 12:01:09,589 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/data/594c0a85e/08c52733ec634475a0382e961477c6d4 [2023-11-26 12:01:09,592 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 12:01:09,594 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 12:01:09,596 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 12:01:09,596 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 12:01:09,603 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 12:01:09,605 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:01:09" (1/1) ... [2023-11-26 12:01:09,606 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2a51fbe7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:09, skipping insertion in model container [2023-11-26 12:01:09,607 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:01:09" (1/1) ... [2023-11-26 12:01:09,699 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 12:01:10,149 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:01:10,169 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 12:01:10,267 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:01:10,290 INFO L206 MainTranslator]: Completed translation [2023-11-26 12:01:10,291 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10 WrapperNode [2023-11-26 12:01:10,291 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 12:01:10,293 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 12:01:10,293 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 12:01:10,293 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 12:01:10,305 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,329 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,461 INFO L138 Inliner]: procedures = 48, calls = 61, calls flagged for inlining = 56, calls inlined = 197, statements flattened = 3016 [2023-11-26 12:01:10,462 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 12:01:10,463 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 12:01:10,463 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 12:01:10,463 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 12:01:10,478 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,478 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,491 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,550 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 12:01:10,550 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,551 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,620 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,692 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,703 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,718 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,737 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 12:01:10,739 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 12:01:10,739 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 12:01:10,740 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 12:01:10,741 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (1/1) ... [2023-11-26 12:01:10,749 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:01:10,766 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:01:10,785 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:01:10,809 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d26280c6-d7b5-45c0-b30d-c7adbb91db19/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 12:01:10,842 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 12:01:10,843 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 12:01:10,843 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 12:01:10,843 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 12:01:11,009 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 12:01:11,012 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 12:01:13,632 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 12:01:13,687 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 12:01:13,688 INFO L309 CfgBuilder]: Removed 14 assume(true) statements. [2023-11-26 12:01:13,691 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:01:13 BoogieIcfgContainer [2023-11-26 12:01:13,691 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 12:01:13,693 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 12:01:13,693 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 12:01:13,698 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 12:01:13,699 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:01:13,699 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 12:01:09" (1/3) ... [2023-11-26 12:01:13,701 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@276421ca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:01:13, skipping insertion in model container [2023-11-26 12:01:13,701 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:01:13,703 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:01:10" (2/3) ... [2023-11-26 12:01:13,706 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@276421ca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:01:13, skipping insertion in model container [2023-11-26 12:01:13,706 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:01:13,707 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:01:13" (3/3) ... [2023-11-26 12:01:13,708 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.10.cil.c [2023-11-26 12:01:13,819 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 12:01:13,819 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 12:01:13,819 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 12:01:13,819 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 12:01:13,820 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 12:01:13,820 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 12:01:13,820 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 12:01:13,820 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 12:01:13,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1297 states, 1296 states have (on average 1.5046296296296295) internal successors, (1950), 1296 states have internal predecessors, (1950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:13,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1156 [2023-11-26 12:01:13,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:13,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:13,934 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:13,934 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:13,935 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 12:01:13,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1297 states, 1296 states have (on average 1.5046296296296295) internal successors, (1950), 1296 states have internal predecessors, (1950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:13,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1156 [2023-11-26 12:01:13,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:13,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:13,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:13,979 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:14,001 INFO L748 eck$LassoCheckResult]: Stem: 182#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1179#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 951#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1175#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1282#L701true assume !(1 == ~m_i~0);~m_st~0 := 2; 1156#L701-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1178#L706-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 269#L711-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 136#L716-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1200#L721-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 891#L726-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1085#L731-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 861#L736-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 936#L741-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1236#L746-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 161#L751-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 798#L1006true assume !(0 == ~M_E~0); 84#L1006-2true assume !(0 == ~T1_E~0); 994#L1011-1true assume !(0 == ~T2_E~0); 1036#L1016-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1182#L1021-1true assume !(0 == ~T4_E~0); 24#L1026-1true assume !(0 == ~T5_E~0); 1250#L1031-1true assume !(0 == ~T6_E~0); 566#L1036-1true assume !(0 == ~T7_E~0); 564#L1041-1true assume !(0 == ~T8_E~0); 908#L1046-1true assume !(0 == ~T9_E~0); 177#L1051-1true assume !(0 == ~T10_E~0); 706#L1056-1true assume 0 == ~E_1~0;~E_1~0 := 1; 754#L1061-1true assume !(0 == ~E_2~0); 138#L1066-1true assume !(0 == ~E_3~0); 1077#L1071-1true assume !(0 == ~E_4~0); 682#L1076-1true assume !(0 == ~E_5~0); 88#L1081-1true assume !(0 == ~E_6~0); 257#L1086-1true assume !(0 == ~E_7~0); 1091#L1091-1true assume !(0 == ~E_8~0); 967#L1096-1true assume 0 == ~E_9~0;~E_9~0 := 1; 1183#L1101-1true assume !(0 == ~E_10~0); 298#L1106-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1108#L484true assume !(1 == ~m_pc~0); 365#L484-2true is_master_triggered_~__retres1~0#1 := 0; 495#L495true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 807#is_master_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 801#L1245true assume !(0 != activate_threads_~tmp~1#1); 1221#L1245-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558#L503true assume 1 == ~t1_pc~0; 571#L504true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 738#L514true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 381#L1253true assume !(0 != activate_threads_~tmp___0~0#1); 42#L1253-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912#L522true assume !(1 == ~t2_pc~0); 526#L522-2true is_transmit2_triggered_~__retres1~2#1 := 0; 144#L533true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 294#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 892#L1261true assume !(0 != activate_threads_~tmp___1~0#1); 1213#L1261-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1059#L541true assume 1 == ~t3_pc~0; 483#L542true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 836#L552true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 593#L1269true assume !(0 != activate_threads_~tmp___2~0#1); 531#L1269-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 982#L560true assume !(1 == ~t4_pc~0); 1083#L560-2true is_transmit4_triggered_~__retres1~4#1 := 0; 459#L571true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23#L1277true assume !(0 != activate_threads_~tmp___3~0#1); 898#L1277-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 166#L579true assume 1 == ~t5_pc~0; 2#L580true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55#L590true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 811#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1034#L1285true assume !(0 != activate_threads_~tmp___4~0#1); 1111#L1285-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1276#L598true assume 1 == ~t6_pc~0; 212#L599true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 402#L609true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 281#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 844#L1293true assume !(0 != activate_threads_~tmp___5~0#1); 600#L1293-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 552#L617true assume !(1 == ~t7_pc~0); 455#L617-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1193#L628true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1203#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 914#L1301true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 314#L1301-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 597#L636true assume 1 == ~t8_pc~0; 440#L637true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 789#L647true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 739#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 609#L1309true assume !(0 != activate_threads_~tmp___7~0#1); 408#L1309-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 687#L655true assume !(1 == ~t9_pc~0); 770#L655-2true is_transmit9_triggered_~__retres1~9#1 := 0; 1138#L666true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 340#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1041#L1317true assume !(0 != activate_threads_~tmp___8~0#1); 621#L1317-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 979#L674true assume 1 == ~t10_pc~0; 78#L675true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1065#L685true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 432#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1296#L1325true assume !(0 != activate_threads_~tmp___9~0#1); 400#L1325-2true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 901#L1119true assume !(1 == ~M_E~0); 127#L1119-2true assume !(1 == ~T1_E~0); 349#L1124-1true assume !(1 == ~T2_E~0); 37#L1129-1true assume !(1 == ~T3_E~0); 538#L1134-1true assume !(1 == ~T4_E~0); 192#L1139-1true assume !(1 == ~T5_E~0); 312#L1144-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1256#L1149-1true assume !(1 == ~T7_E~0); 124#L1154-1true assume !(1 == ~T8_E~0); 168#L1159-1true assume !(1 == ~T9_E~0); 1227#L1164-1true assume !(1 == ~T10_E~0); 419#L1169-1true assume !(1 == ~E_1~0); 343#L1174-1true assume !(1 == ~E_2~0); 219#L1179-1true assume !(1 == ~E_3~0); 163#L1184-1true assume 1 == ~E_4~0;~E_4~0 := 2; 190#L1189-1true assume !(1 == ~E_5~0); 247#L1194-1true assume !(1 == ~E_6~0); 1271#L1199-1true assume !(1 == ~E_7~0); 226#L1204-1true assume !(1 == ~E_8~0); 1134#L1209-1true assume !(1 == ~E_9~0); 619#L1214-1true assume !(1 == ~E_10~0); 1226#L1219-1true assume { :end_inline_reset_delta_events } true; 17#L1520-2true [2023-11-26 12:01:14,016 INFO L750 eck$LassoCheckResult]: Loop: 17#L1520-2true assume !false; 1279#L1521true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 683#L981-1true assume !true; 749#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 450#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 309#L1006-3true assume !(0 == ~M_E~0); 976#L1006-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 735#L1011-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 986#L1016-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 784#L1021-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 460#L1026-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1152#L1031-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 701#L1036-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1222#L1041-3true assume !(0 == ~T8_E~0); 777#L1046-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1107#L1051-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 702#L1056-3true assume 0 == ~E_1~0;~E_1~0 := 1; 175#L1061-3true assume 0 == ~E_2~0;~E_2~0 := 1; 176#L1066-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1239#L1071-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1008#L1076-3true assume 0 == ~E_5~0;~E_5~0 := 1; 69#L1081-3true assume !(0 == ~E_6~0); 1153#L1086-3true assume 0 == ~E_7~0;~E_7~0 := 1; 90#L1091-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1068#L1096-3true assume 0 == ~E_9~0;~E_9~0 := 1; 940#L1101-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1001#L1106-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 480#L484-33true assume 1 == ~m_pc~0; 1190#L485-11true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 412#L495-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 766#is_master_triggered_returnLabel#12true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20#L1245-33true assume !(0 != activate_threads_~tmp~1#1); 636#L1245-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 251#L503-33true assume 1 == ~t1_pc~0; 1191#L504-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 603#L514-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1161#is_transmit1_triggered_returnLabel#12true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209#L1253-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 647#L1253-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506#L522-33true assume !(1 == ~t2_pc~0); 1169#L522-35true is_transmit2_triggered_~__retres1~2#1 := 0; 86#L533-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 716#is_transmit2_triggered_returnLabel#12true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 813#L1261-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 524#L1261-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 887#L541-33true assume 1 == ~t3_pc~0; 96#L542-11true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19#L552-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101#is_transmit3_triggered_returnLabel#12true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 500#L1269-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 944#L1269-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 698#L560-33true assume 1 == ~t4_pc~0; 414#L561-11true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58#L571-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1013#is_transmit4_triggered_returnLabel#12true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1090#L1277-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 673#L1277-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14#L579-33true assume 1 == ~t5_pc~0; 456#L580-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1053#L590-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1100#is_transmit5_triggered_returnLabel#12true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 553#L1285-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 575#L1285-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1055#L598-33true assume !(1 == ~t6_pc~0); 386#L598-35true is_transmit6_triggered_~__retres1~6#1 := 0; 263#L609-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 376#is_transmit6_triggered_returnLabel#12true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 189#L1293-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 913#L1293-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1166#L617-33true assume 1 == ~t7_pc~0; 932#L618-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 782#L628-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 823#is_transmit7_triggered_returnLabel#12true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1140#L1301-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1010#L1301-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52#L636-33true assume !(1 == ~t8_pc~0); 1029#L636-35true is_transmit8_triggered_~__retres1~8#1 := 0; 666#L647-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 525#is_transmit8_triggered_returnLabel#12true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1071#L1309-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 654#L1309-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1269#L655-33true assume !(1 == ~t9_pc~0); 1198#L655-35true is_transmit9_triggered_~__retres1~9#1 := 0; 238#L666-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 720#is_transmit9_triggered_returnLabel#12true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 756#L1317-33true assume !(0 != activate_threads_~tmp___8~0#1); 1019#L1317-35true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 342#L674-33true assume !(1 == ~t10_pc~0); 1049#L674-35true is_transmit10_triggered_~__retres1~10#1 := 0; 1082#L685-11true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 835#is_transmit10_triggered_returnLabel#12true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 513#L1325-33true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1076#L1325-35true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1114#L1119-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1120#L1119-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1274#L1124-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1162#L1129-3true assume !(1 == ~T3_E~0); 207#L1134-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 497#L1139-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 335#L1144-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 445#L1149-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1260#L1154-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 710#L1159-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1243#L1164-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1024#L1169-3true assume !(1 == ~E_1~0); 262#L1174-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1104#L1179-3true assume 1 == ~E_3~0;~E_3~0 := 2; 846#L1184-3true assume 1 == ~E_4~0;~E_4~0 := 2; 81#L1189-3true assume 1 == ~E_5~0;~E_5~0 := 2; 851#L1194-3true assume 1 == ~E_6~0;~E_6~0 := 2; 235#L1199-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1278#L1204-3true assume 1 == ~E_8~0;~E_8~0 := 2; 433#L1209-3true assume !(1 == ~E_9~0); 27#L1214-3true assume 1 == ~E_10~0;~E_10~0 := 2; 948#L1219-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 611#L764-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 959#L821-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 256#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 296#L1539true assume !(0 == start_simulation_~tmp~3#1); 501#L1539-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 420#L764-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 876#L821-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 41#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 240#L1494true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 745#L1501true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 470#stop_simulation_returnLabel#1true start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 297#L1552true assume !(0 != start_simulation_~tmp___0~1#1); 17#L1520-2true [2023-11-26 12:01:14,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:14,024 INFO L85 PathProgramCache]: Analyzing trace with hash 1310232617, now seen corresponding path program 1 times [2023-11-26 12:01:14,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:14,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498627426] [2023-11-26 12:01:14,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:14,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:14,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:14,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:14,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:14,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498627426] [2023-11-26 12:01:14,464 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1498627426] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:14,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:14,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:14,466 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504369279] [2023-11-26 12:01:14,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:14,474 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:14,476 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:14,477 INFO L85 PathProgramCache]: Analyzing trace with hash 939086972, now seen corresponding path program 1 times [2023-11-26 12:01:14,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:14,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902165408] [2023-11-26 12:01:14,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:14,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:14,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:14,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:14,612 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:14,613 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902165408] [2023-11-26 12:01:14,613 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902165408] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:14,613 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:14,614 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:01:14,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965149355] [2023-11-26 12:01:14,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:14,616 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:14,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:14,669 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:14,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:14,675 INFO L87 Difference]: Start difference. First operand has 1297 states, 1296 states have (on average 1.5046296296296295) internal successors, (1950), 1296 states have internal predecessors, (1950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:14,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:14,801 INFO L93 Difference]: Finished difference Result 1295 states and 1918 transitions. [2023-11-26 12:01:14,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1295 states and 1918 transitions. [2023-11-26 12:01:14,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:14,838 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1295 states to 1289 states and 1912 transitions. [2023-11-26 12:01:14,839 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-26 12:01:14,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-26 12:01:14,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1912 transitions. [2023-11-26 12:01:14,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:14,856 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1912 transitions. [2023-11-26 12:01:14,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1912 transitions. [2023-11-26 12:01:14,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-26 12:01:14,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4833204034134988) internal successors, (1912), 1288 states have internal predecessors, (1912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:14,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1912 transitions. [2023-11-26 12:01:14,972 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1912 transitions. [2023-11-26 12:01:14,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:14,978 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1912 transitions. [2023-11-26 12:01:14,978 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 12:01:14,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1912 transitions. [2023-11-26 12:01:14,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:14,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:14,990 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:14,993 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:14,994 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:14,994 INFO L748 eck$LassoCheckResult]: Stem: 2961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 2962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3814#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3815#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3882#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3876#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3877#L706-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3130#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2873#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2874#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3783#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3784#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3765#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3766#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3806#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2924#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2925#L1006 assume !(0 == ~M_E~0); 2776#L1006-2 assume !(0 == ~T1_E~0); 2777#L1011-1 assume !(0 == ~T2_E~0); 3831#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3848#L1021-1 assume !(0 == ~T4_E~0); 2654#L1026-1 assume !(0 == ~T5_E~0); 2655#L1031-1 assume !(0 == ~T6_E~0); 3542#L1036-1 assume !(0 == ~T7_E~0); 3539#L1041-1 assume !(0 == ~T8_E~0); 3540#L1046-1 assume !(0 == ~T9_E~0); 2952#L1051-1 assume !(0 == ~T10_E~0); 2953#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3669#L1061-1 assume !(0 == ~E_2~0); 2877#L1066-1 assume !(0 == ~E_3~0); 2878#L1071-1 assume !(0 == ~E_4~0); 3644#L1076-1 assume !(0 == ~E_5~0); 2784#L1081-1 assume !(0 == ~E_6~0); 2785#L1086-1 assume !(0 == ~E_7~0); 3104#L1091-1 assume !(0 == ~E_8~0); 3823#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 3824#L1101-1 assume !(0 == ~E_10~0); 3173#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3174#L484 assume !(1 == ~m_pc~0); 2834#L484-2 is_master_triggered_~__retres1~0#1 := 0; 2833#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3456#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3737#L1245 assume !(0 != activate_threads_~tmp~1#1); 3738#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3529#L503 assume 1 == ~t1_pc~0; 3530#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3549#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2695#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2696#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 2689#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2690#L522 assume !(1 == ~t2_pc~0); 3495#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2888#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2889#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3168#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3785#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3856#L541 assume 1 == ~t3_pc~0; 3438#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3240#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2636#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2637#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3501#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3502#L560 assume !(1 == ~t4_pc~0); 2770#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2769#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2800#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2650#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 2651#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2933#L579 assume 1 == ~t5_pc~0; 2601#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2602#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2715#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3742#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3847#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3866#L598 assume 1 == ~t6_pc~0; 3017#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3018#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3145#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3146#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3575#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3520#L617 assume !(1 == ~t7_pc~0); 2993#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2992#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3886#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3797#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3207#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3208#L636 assume 1 == ~t8_pc~0; 3391#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3392#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3698#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3584#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3340#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3341#L655 assume !(1 == ~t9_pc~0); 3368#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3369#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3254#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3255#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3595#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3596#L674 assume 1 == ~t10_pc~0; 2761#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2762#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3382#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3383#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3329#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3330#L1119 assume !(1 == ~M_E~0); 2860#L1119-2 assume !(1 == ~T1_E~0); 2861#L1124-1 assume !(1 == ~T2_E~0); 2679#L1129-1 assume !(1 == ~T3_E~0); 2680#L1134-1 assume !(1 == ~T4_E~0); 2978#L1139-1 assume !(1 == ~T5_E~0); 2979#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3203#L1149-1 assume !(1 == ~T7_E~0); 2854#L1154-1 assume !(1 == ~T8_E~0); 2855#L1159-1 assume !(1 == ~T9_E~0); 2936#L1164-1 assume !(1 == ~T10_E~0); 3357#L1169-1 assume !(1 == ~E_1~0); 3256#L1174-1 assume !(1 == ~E_2~0); 3030#L1179-1 assume !(1 == ~E_3~0); 2926#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2927#L1189-1 assume !(1 == ~E_5~0); 2976#L1194-1 assume !(1 == ~E_6~0); 3082#L1199-1 assume !(1 == ~E_7~0); 3042#L1204-1 assume !(1 == ~E_8~0); 3043#L1209-1 assume !(1 == ~E_9~0); 3593#L1214-1 assume !(1 == ~E_10~0); 3594#L1219-1 assume { :end_inline_reset_delta_events } true; 2638#L1520-2 [2023-11-26 12:01:14,995 INFO L750 eck$LassoCheckResult]: Loop: 2638#L1520-2 assume !false; 2639#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3430#L981-1 assume !false; 3615#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3616#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2622#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3223#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3224#L836 assume !(0 != eval_~tmp~0#1); 3707#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3399#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3195#L1006-3 assume !(0 == ~M_E~0); 3196#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3693#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3694#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3731#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3410#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3411#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3661#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3662#L1041-3 assume !(0 == ~T8_E~0); 3725#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3726#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3663#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2949#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2950#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2951#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3834#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2743#L1081-3 assume !(0 == ~E_6~0); 2744#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2791#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2792#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3807#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3808#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3432#L484-33 assume !(1 == ~m_pc~0); 3433#L484-35 is_master_triggered_~__retres1~0#1 := 0; 3343#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3344#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2644#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 2645#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3090#L503-33 assume 1 == ~t1_pc~0; 3091#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3578#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3579#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3011#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3012#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3470#L522-33 assume 1 == ~t2_pc~0; 3472#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2781#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2782#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3679#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3493#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3494#L541-33 assume 1 == ~t3_pc~0; 2801#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2642#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2643#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2813#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3462#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3659#L560-33 assume 1 == ~t4_pc~0; 3347#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2719#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2720#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3836#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3638#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2628#L579-33 assume 1 == ~t5_pc~0; 2629#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2881#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3852#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3521#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3522#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3548#L598-33 assume !(1 == ~t6_pc~0); 3304#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3114#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3115#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2973#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2974#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3796#L617-33 assume !(1 == ~t7_pc~0); 2774#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2775#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3730#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3749#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3835#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2709#L636-33 assume 1 == ~t8_pc~0; 2710#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3631#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3491#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3492#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3620#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3621#L655-33 assume 1 == ~t9_pc~0; 3883#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3059#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3060#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3682#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 3711#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3253#L674-33 assume 1 == ~t10_pc~0; 3109#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3110#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3755#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3479#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3480#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3857#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3867#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3869#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3879#L1129-3 assume !(1 == ~T3_E~0); 3004#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3005#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3242#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3243#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3397#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3674#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3675#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3842#L1169-3 assume !(1 == ~E_1~0); 3112#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3113#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3760#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2766#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2767#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3057#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3058#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3381#L1209-3 assume !(1 == ~E_9~0); 2656#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2657#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3583#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2746#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3100#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3101#L1539 assume !(0 == start_simulation_~tmp~3#1); 3171#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3358#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3153#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2685#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2686#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3065#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3419#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3172#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 2638#L1520-2 [2023-11-26 12:01:14,996 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:14,996 INFO L85 PathProgramCache]: Analyzing trace with hash -934325781, now seen corresponding path program 1 times [2023-11-26 12:01:14,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:14,997 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934795748] [2023-11-26 12:01:14,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:14,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:15,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:15,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:15,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:15,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934795748] [2023-11-26 12:01:15,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934795748] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:15,104 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:15,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:15,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071705281] [2023-11-26 12:01:15,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:15,106 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:15,106 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:15,106 INFO L85 PathProgramCache]: Analyzing trace with hash 867756010, now seen corresponding path program 1 times [2023-11-26 12:01:15,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:15,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814321732] [2023-11-26 12:01:15,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:15,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:15,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:15,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:15,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:15,300 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814321732] [2023-11-26 12:01:15,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814321732] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:15,300 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:15,301 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:15,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [145788793] [2023-11-26 12:01:15,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:15,302 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:15,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:15,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:15,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:15,304 INFO L87 Difference]: Start difference. First operand 1289 states and 1912 transitions. cyclomatic complexity: 624 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:15,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:15,356 INFO L93 Difference]: Finished difference Result 1289 states and 1911 transitions. [2023-11-26 12:01:15,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1911 transitions. [2023-11-26 12:01:15,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:15,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1911 transitions. [2023-11-26 12:01:15,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-26 12:01:15,451 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-26 12:01:15,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1911 transitions. [2023-11-26 12:01:15,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:15,460 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1911 transitions. [2023-11-26 12:01:15,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1911 transitions. [2023-11-26 12:01:15,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-26 12:01:15,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.482544608223429) internal successors, (1911), 1288 states have internal predecessors, (1911), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:15,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1911 transitions. [2023-11-26 12:01:15,537 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1911 transitions. [2023-11-26 12:01:15,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:15,541 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1911 transitions. [2023-11-26 12:01:15,542 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 12:01:15,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1911 transitions. [2023-11-26 12:01:15,566 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:15,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:15,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:15,579 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:15,579 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:15,583 INFO L748 eck$LassoCheckResult]: Stem: 5546#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 5547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6399#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6400#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6467#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 6461#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6462#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5715#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5460#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5461#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6368#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6369#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6350#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6351#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6391#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5509#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5510#L1006 assume !(0 == ~M_E~0); 5364#L1006-2 assume !(0 == ~T1_E~0); 5365#L1011-1 assume !(0 == ~T2_E~0); 6416#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6433#L1021-1 assume !(0 == ~T4_E~0); 5239#L1026-1 assume !(0 == ~T5_E~0); 5240#L1031-1 assume !(0 == ~T6_E~0); 6129#L1036-1 assume !(0 == ~T7_E~0); 6124#L1041-1 assume !(0 == ~T8_E~0); 6125#L1046-1 assume !(0 == ~T9_E~0); 5537#L1051-1 assume !(0 == ~T10_E~0); 5538#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6254#L1061-1 assume !(0 == ~E_2~0); 5462#L1066-1 assume !(0 == ~E_3~0); 5463#L1071-1 assume !(0 == ~E_4~0); 6229#L1076-1 assume !(0 == ~E_5~0); 5369#L1081-1 assume !(0 == ~E_6~0); 5370#L1086-1 assume !(0 == ~E_7~0); 5689#L1091-1 assume !(0 == ~E_8~0); 6408#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 6409#L1101-1 assume !(0 == ~E_10~0); 5758#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5759#L484 assume !(1 == ~m_pc~0); 5421#L484-2 is_master_triggered_~__retres1~0#1 := 0; 5420#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6041#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6322#L1245 assume !(0 != activate_threads_~tmp~1#1); 6323#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6114#L503 assume 1 == ~t1_pc~0; 6115#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6136#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5280#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5281#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 5276#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5277#L522 assume !(1 == ~t2_pc~0); 6080#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5474#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5475#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5754#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 6370#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6441#L541 assume 1 == ~t3_pc~0; 6025#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5825#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5221#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5222#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 6090#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6091#L560 assume !(1 == ~t4_pc~0); 5355#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5354#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5385#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5235#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 5236#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5520#L579 assume 1 == ~t5_pc~0; 5186#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5187#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5300#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6327#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 6432#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6451#L598 assume 1 == ~t6_pc~0; 5602#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5603#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5731#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5732#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 6160#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6105#L617 assume !(1 == ~t7_pc~0); 5578#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5577#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6471#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6382#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5795#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5796#L636 assume 1 == ~t8_pc~0; 5976#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5977#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6287#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6170#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 5925#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5926#L655 assume !(1 == ~t9_pc~0); 5955#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5956#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5839#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5840#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 6180#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6181#L674 assume 1 == ~t10_pc~0; 5346#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5347#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5967#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5968#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 5914#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5915#L1119 assume !(1 == ~M_E~0); 5445#L1119-2 assume !(1 == ~T1_E~0); 5446#L1124-1 assume !(1 == ~T2_E~0); 5264#L1129-1 assume !(1 == ~T3_E~0); 5265#L1134-1 assume !(1 == ~T4_E~0); 5563#L1139-1 assume !(1 == ~T5_E~0); 5564#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5791#L1149-1 assume !(1 == ~T7_E~0); 5439#L1154-1 assume !(1 == ~T8_E~0); 5440#L1159-1 assume !(1 == ~T9_E~0); 5521#L1164-1 assume !(1 == ~T10_E~0); 5942#L1169-1 assume !(1 == ~E_1~0); 5842#L1174-1 assume !(1 == ~E_2~0); 5617#L1179-1 assume !(1 == ~E_3~0); 5511#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5512#L1189-1 assume !(1 == ~E_5~0); 5561#L1194-1 assume !(1 == ~E_6~0); 5667#L1199-1 assume !(1 == ~E_7~0); 5627#L1204-1 assume !(1 == ~E_8~0); 5628#L1209-1 assume !(1 == ~E_9~0); 6178#L1214-1 assume !(1 == ~E_10~0); 6179#L1219-1 assume { :end_inline_reset_delta_events } true; 5223#L1520-2 [2023-11-26 12:01:15,584 INFO L750 eck$LassoCheckResult]: Loop: 5223#L1520-2 assume !false; 5224#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6015#L981-1 assume !false; 6200#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6201#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5207#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5808#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5809#L836 assume !(0 != eval_~tmp~0#1); 6292#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5984#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5780#L1006-3 assume !(0 == ~M_E~0); 5781#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6278#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6279#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6316#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5993#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5994#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6246#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6247#L1041-3 assume !(0 == ~T8_E~0); 6308#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6309#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6248#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5534#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5535#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5536#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6419#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5328#L1081-3 assume !(0 == ~E_6~0); 5329#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5374#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5375#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6392#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6393#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6017#L484-33 assume !(1 == ~m_pc~0); 6018#L484-35 is_master_triggered_~__retres1~0#1 := 0; 5928#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5929#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5229#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 5230#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5674#L503-33 assume 1 == ~t1_pc~0; 5675#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6163#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6164#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5594#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5595#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6055#L522-33 assume !(1 == ~t2_pc~0); 6056#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5366#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5367#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6264#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6076#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6077#L541-33 assume 1 == ~t3_pc~0; 5386#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5227#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5228#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5395#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6047#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6244#L560-33 assume 1 == ~t4_pc~0; 5932#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5304#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5305#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6421#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6223#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5216#L579-33 assume 1 == ~t5_pc~0; 5217#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5467#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6437#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6106#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6107#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6135#L598-33 assume !(1 == ~t6_pc~0); 5892#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5699#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5700#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5558#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5559#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6381#L617-33 assume 1 == ~t7_pc~0; 6389#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5360#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6315#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6334#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6420#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5294#L636-33 assume !(1 == ~t8_pc~0); 5296#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 6216#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6078#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6079#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6207#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6208#L655-33 assume 1 == ~t9_pc~0; 6468#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5647#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5648#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6267#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 6296#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5838#L674-33 assume !(1 == ~t10_pc~0); 5696#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 5695#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6340#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6064#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6065#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6442#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6452#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6454#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6464#L1129-3 assume !(1 == ~T3_E~0); 5592#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5593#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5827#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5828#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5982#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6259#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6260#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6428#L1169-3 assume !(1 == ~E_1~0); 5697#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5698#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6345#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5351#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5352#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5642#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5643#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5966#L1209-3 assume !(1 == ~E_9~0); 5243#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5244#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6169#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5331#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5685#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5686#L1539 assume !(0 == start_simulation_~tmp~3#1); 5756#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5943#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5738#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5272#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 5273#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5650#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6004#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5757#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 5223#L1520-2 [2023-11-26 12:01:15,587 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:15,587 INFO L85 PathProgramCache]: Analyzing trace with hash 158309421, now seen corresponding path program 1 times [2023-11-26 12:01:15,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:15,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414538071] [2023-11-26 12:01:15,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:15,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:15,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:15,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:15,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:15,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414538071] [2023-11-26 12:01:15,748 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414538071] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:15,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:15,748 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:15,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [682075165] [2023-11-26 12:01:15,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:15,749 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:15,750 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:15,750 INFO L85 PathProgramCache]: Analyzing trace with hash -1384946584, now seen corresponding path program 1 times [2023-11-26 12:01:15,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:15,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443178957] [2023-11-26 12:01:15,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:15,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:15,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:15,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:15,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:15,844 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1443178957] [2023-11-26 12:01:15,845 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1443178957] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:15,845 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:15,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:15,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991209531] [2023-11-26 12:01:15,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:15,847 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:15,847 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:15,848 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:15,848 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:15,848 INFO L87 Difference]: Start difference. First operand 1289 states and 1911 transitions. cyclomatic complexity: 623 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:15,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:15,896 INFO L93 Difference]: Finished difference Result 1289 states and 1910 transitions. [2023-11-26 12:01:15,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1910 transitions. [2023-11-26 12:01:15,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:15,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1910 transitions. [2023-11-26 12:01:15,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-26 12:01:15,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-26 12:01:15,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1910 transitions. [2023-11-26 12:01:15,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:15,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1910 transitions. [2023-11-26 12:01:15,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1910 transitions. [2023-11-26 12:01:15,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-26 12:01:15,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4817688130333593) internal successors, (1910), 1288 states have internal predecessors, (1910), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:15,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1910 transitions. [2023-11-26 12:01:15,976 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1910 transitions. [2023-11-26 12:01:15,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:15,979 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1910 transitions. [2023-11-26 12:01:15,979 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 12:01:15,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1910 transitions. [2023-11-26 12:01:15,991 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:15,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:15,991 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:15,996 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:15,996 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:15,997 INFO L748 eck$LassoCheckResult]: Stem: 8131#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 8132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9052#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 9046#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9047#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8298#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8043#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8044#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8953#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8954#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8935#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8936#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8976#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8092#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8093#L1006 assume !(0 == ~M_E~0); 7946#L1006-2 assume !(0 == ~T1_E~0); 7947#L1011-1 assume !(0 == ~T2_E~0); 9001#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9018#L1021-1 assume !(0 == ~T4_E~0); 7822#L1026-1 assume !(0 == ~T5_E~0); 7823#L1031-1 assume !(0 == ~T6_E~0); 8712#L1036-1 assume !(0 == ~T7_E~0); 8709#L1041-1 assume !(0 == ~T8_E~0); 8710#L1046-1 assume !(0 == ~T9_E~0); 8122#L1051-1 assume !(0 == ~T10_E~0); 8123#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8839#L1061-1 assume !(0 == ~E_2~0); 8047#L1066-1 assume !(0 == ~E_3~0); 8048#L1071-1 assume !(0 == ~E_4~0); 8814#L1076-1 assume !(0 == ~E_5~0); 7954#L1081-1 assume !(0 == ~E_6~0); 7955#L1086-1 assume !(0 == ~E_7~0); 8272#L1091-1 assume !(0 == ~E_8~0); 8991#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8992#L1101-1 assume !(0 == ~E_10~0); 8343#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8344#L484 assume !(1 == ~m_pc~0); 8004#L484-2 is_master_triggered_~__retres1~0#1 := 0; 8003#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8626#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8907#L1245 assume !(0 != activate_threads_~tmp~1#1); 8908#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8699#L503 assume 1 == ~t1_pc~0; 8700#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8718#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7864#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 7859#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7860#L522 assume !(1 == ~t2_pc~0); 8665#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8058#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8059#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8338#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 8955#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9026#L541 assume 1 == ~t3_pc~0; 8608#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8410#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7806#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7807#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 8671#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8672#L560 assume !(1 == ~t4_pc~0); 7938#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7937#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7970#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7820#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 7821#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8103#L579 assume 1 == ~t5_pc~0; 7771#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7772#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7885#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8912#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 9016#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9036#L598 assume 1 == ~t6_pc~0; 8187#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8188#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8313#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8314#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 8745#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8690#L617 assume !(1 == ~t7_pc~0); 8163#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8162#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9056#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8967#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8377#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8378#L636 assume 1 == ~t8_pc~0; 8561#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8562#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8867#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8753#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 8508#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8509#L655 assume !(1 == ~t9_pc~0); 8536#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8537#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8420#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8421#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 8765#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8766#L674 assume 1 == ~t10_pc~0; 7931#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7932#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8551#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8552#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 8499#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8500#L1119 assume !(1 == ~M_E~0); 8030#L1119-2 assume !(1 == ~T1_E~0); 8031#L1124-1 assume !(1 == ~T2_E~0); 7849#L1129-1 assume !(1 == ~T3_E~0); 7850#L1134-1 assume !(1 == ~T4_E~0); 8147#L1139-1 assume !(1 == ~T5_E~0); 8148#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8373#L1149-1 assume !(1 == ~T7_E~0); 8024#L1154-1 assume !(1 == ~T8_E~0); 8025#L1159-1 assume !(1 == ~T9_E~0); 8106#L1164-1 assume !(1 == ~T10_E~0); 8527#L1169-1 assume !(1 == ~E_1~0); 8426#L1174-1 assume !(1 == ~E_2~0); 8200#L1179-1 assume !(1 == ~E_3~0); 8096#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8097#L1189-1 assume !(1 == ~E_5~0); 8145#L1194-1 assume !(1 == ~E_6~0); 8251#L1199-1 assume !(1 == ~E_7~0); 8212#L1204-1 assume !(1 == ~E_8~0); 8213#L1209-1 assume !(1 == ~E_9~0); 8763#L1214-1 assume !(1 == ~E_10~0); 8764#L1219-1 assume { :end_inline_reset_delta_events } true; 7808#L1520-2 [2023-11-26 12:01:15,998 INFO L750 eck$LassoCheckResult]: Loop: 7808#L1520-2 assume !false; 7809#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8600#L981-1 assume !false; 8785#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8786#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7792#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8390#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8391#L836 assume !(0 != eval_~tmp~0#1); 8877#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8569#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8365#L1006-3 assume !(0 == ~M_E~0); 8366#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8863#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8864#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8901#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8578#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8579#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8831#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8832#L1041-3 assume !(0 == ~T8_E~0); 8893#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8894#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8833#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8119#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8120#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8121#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9004#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7913#L1081-3 assume !(0 == ~E_6~0); 7914#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7959#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7960#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8977#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8978#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8602#L484-33 assume !(1 == ~m_pc~0); 8603#L484-35 is_master_triggered_~__retres1~0#1 := 0; 8513#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8514#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7814#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 7815#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8259#L503-33 assume 1 == ~t1_pc~0; 8260#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8748#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8749#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8181#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8182#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8640#L522-33 assume !(1 == ~t2_pc~0); 8641#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 7951#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7952#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8849#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8661#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8662#L541-33 assume 1 == ~t3_pc~0; 7971#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7812#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7813#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7980#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8632#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8829#L560-33 assume 1 == ~t4_pc~0; 8517#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7889#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7890#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9006#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8808#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7801#L579-33 assume 1 == ~t5_pc~0; 7802#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8052#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9022#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8691#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8692#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8723#L598-33 assume 1 == ~t6_pc~0; 9024#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8284#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8285#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8143#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8144#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8966#L617-33 assume !(1 == ~t7_pc~0); 7944#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7945#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8900#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8919#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9005#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7879#L636-33 assume 1 == ~t8_pc~0; 7880#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8801#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8663#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8664#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8792#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8793#L655-33 assume 1 == ~t9_pc~0; 9053#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8232#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8233#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8852#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 8881#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8425#L674-33 assume 1 == ~t10_pc~0; 8279#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8280#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8925#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8649#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8650#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9027#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9037#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9039#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9049#L1129-3 assume !(1 == ~T3_E~0); 8177#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8178#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8412#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8413#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8567#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8844#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8845#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9013#L1169-3 assume !(1 == ~E_1~0); 8282#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8283#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8930#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7939#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7940#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8227#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8228#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8553#L1209-3 assume !(1 == ~E_9~0); 7828#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7829#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8755#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7916#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8270#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 8271#L1539 assume !(0 == start_simulation_~tmp~3#1); 8341#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8528#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8323#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 7857#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 7858#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8235#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8589#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8342#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 7808#L1520-2 [2023-11-26 12:01:15,999 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:15,999 INFO L85 PathProgramCache]: Analyzing trace with hash 1440481707, now seen corresponding path program 1 times [2023-11-26 12:01:16,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:16,003 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554624383] [2023-11-26 12:01:16,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:16,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:16,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:16,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:16,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:16,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554624383] [2023-11-26 12:01:16,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554624383] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:16,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:16,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:16,096 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188784328] [2023-11-26 12:01:16,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:16,097 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:16,097 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:16,098 INFO L85 PathProgramCache]: Analyzing trace with hash 1365031658, now seen corresponding path program 1 times [2023-11-26 12:01:16,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:16,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468590914] [2023-11-26 12:01:16,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:16,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:16,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:16,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:16,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:16,214 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [468590914] [2023-11-26 12:01:16,214 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [468590914] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:16,215 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:16,215 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:16,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285224893] [2023-11-26 12:01:16,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:16,216 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:16,216 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:16,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:16,217 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:16,217 INFO L87 Difference]: Start difference. First operand 1289 states and 1910 transitions. cyclomatic complexity: 622 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:16,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:16,294 INFO L93 Difference]: Finished difference Result 1289 states and 1909 transitions. [2023-11-26 12:01:16,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1909 transitions. [2023-11-26 12:01:16,308 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:16,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1909 transitions. [2023-11-26 12:01:16,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-26 12:01:16,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-26 12:01:16,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1909 transitions. [2023-11-26 12:01:16,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:16,324 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1909 transitions. [2023-11-26 12:01:16,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1909 transitions. [2023-11-26 12:01:16,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-26 12:01:16,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4809930178432893) internal successors, (1909), 1288 states have internal predecessors, (1909), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:16,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1909 transitions. [2023-11-26 12:01:16,362 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1909 transitions. [2023-11-26 12:01:16,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:16,365 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1909 transitions. [2023-11-26 12:01:16,366 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 12:01:16,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1909 transitions. [2023-11-26 12:01:16,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:16,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:16,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:16,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:16,383 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:16,384 INFO L748 eck$LassoCheckResult]: Stem: 10716#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 10717#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 11569#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11570#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11637#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 11631#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11632#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10883#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10628#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10629#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11538#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11539#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11520#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11521#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11561#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10677#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10678#L1006 assume !(0 == ~M_E~0); 10531#L1006-2 assume !(0 == ~T1_E~0); 10532#L1011-1 assume !(0 == ~T2_E~0); 11586#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11603#L1021-1 assume !(0 == ~T4_E~0); 10407#L1026-1 assume !(0 == ~T5_E~0); 10408#L1031-1 assume !(0 == ~T6_E~0); 11297#L1036-1 assume !(0 == ~T7_E~0); 11294#L1041-1 assume !(0 == ~T8_E~0); 11295#L1046-1 assume !(0 == ~T9_E~0); 10707#L1051-1 assume !(0 == ~T10_E~0); 10708#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 11424#L1061-1 assume !(0 == ~E_2~0); 10632#L1066-1 assume !(0 == ~E_3~0); 10633#L1071-1 assume !(0 == ~E_4~0); 11399#L1076-1 assume !(0 == ~E_5~0); 10539#L1081-1 assume !(0 == ~E_6~0); 10540#L1086-1 assume !(0 == ~E_7~0); 10857#L1091-1 assume !(0 == ~E_8~0); 11576#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 11577#L1101-1 assume !(0 == ~E_10~0); 10928#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10929#L484 assume !(1 == ~m_pc~0); 10589#L484-2 is_master_triggered_~__retres1~0#1 := 0; 10588#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11211#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11492#L1245 assume !(0 != activate_threads_~tmp~1#1); 11493#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11284#L503 assume 1 == ~t1_pc~0; 11285#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11303#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10448#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10449#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 10444#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10445#L522 assume !(1 == ~t2_pc~0); 11250#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10643#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10644#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10923#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 11540#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11611#L541 assume 1 == ~t3_pc~0; 11193#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10995#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10391#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10392#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 11256#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11257#L560 assume !(1 == ~t4_pc~0); 10523#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10522#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10555#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10405#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 10406#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10688#L579 assume 1 == ~t5_pc~0; 10356#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10357#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10470#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11497#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 11601#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11621#L598 assume 1 == ~t6_pc~0; 10772#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10773#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10898#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10899#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 11330#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11275#L617 assume !(1 == ~t7_pc~0); 10748#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10747#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11641#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11552#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10962#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10963#L636 assume 1 == ~t8_pc~0; 11146#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11147#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11452#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11338#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 11093#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11094#L655 assume !(1 == ~t9_pc~0); 11123#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11124#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11005#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11006#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 11350#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11351#L674 assume 1 == ~t10_pc~0; 10516#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10517#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11136#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11137#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 11084#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11085#L1119 assume !(1 == ~M_E~0); 10615#L1119-2 assume !(1 == ~T1_E~0); 10616#L1124-1 assume !(1 == ~T2_E~0); 10434#L1129-1 assume !(1 == ~T3_E~0); 10435#L1134-1 assume !(1 == ~T4_E~0); 10733#L1139-1 assume !(1 == ~T5_E~0); 10734#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10958#L1149-1 assume !(1 == ~T7_E~0); 10609#L1154-1 assume !(1 == ~T8_E~0); 10610#L1159-1 assume !(1 == ~T9_E~0); 10691#L1164-1 assume !(1 == ~T10_E~0); 11112#L1169-1 assume !(1 == ~E_1~0); 11011#L1174-1 assume !(1 == ~E_2~0); 10785#L1179-1 assume !(1 == ~E_3~0); 10681#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10682#L1189-1 assume !(1 == ~E_5~0); 10730#L1194-1 assume !(1 == ~E_6~0); 10836#L1199-1 assume !(1 == ~E_7~0); 10797#L1204-1 assume !(1 == ~E_8~0); 10798#L1209-1 assume !(1 == ~E_9~0); 11348#L1214-1 assume !(1 == ~E_10~0); 11349#L1219-1 assume { :end_inline_reset_delta_events } true; 10393#L1520-2 [2023-11-26 12:01:16,384 INFO L750 eck$LassoCheckResult]: Loop: 10393#L1520-2 assume !false; 10394#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11185#L981-1 assume !false; 11370#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11371#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10377#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10978#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10979#L836 assume !(0 != eval_~tmp~0#1); 11462#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11154#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10950#L1006-3 assume !(0 == ~M_E~0); 10951#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11448#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11449#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11486#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11163#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11164#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11416#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11417#L1041-3 assume !(0 == ~T8_E~0); 11478#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11479#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11418#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10704#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10705#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10706#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11589#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10498#L1081-3 assume !(0 == ~E_6~0); 10499#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10544#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10545#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11562#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11563#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11187#L484-33 assume !(1 == ~m_pc~0); 11188#L484-35 is_master_triggered_~__retres1~0#1 := 0; 11098#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11099#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10399#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 10400#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10844#L503-33 assume 1 == ~t1_pc~0; 10845#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11333#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11334#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10766#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10767#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11225#L522-33 assume !(1 == ~t2_pc~0); 11226#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 10536#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10537#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11434#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11246#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11247#L541-33 assume 1 == ~t3_pc~0; 10556#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10397#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10398#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10565#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11217#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11414#L560-33 assume 1 == ~t4_pc~0; 11102#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10474#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10475#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11591#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11393#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10386#L579-33 assume 1 == ~t5_pc~0; 10387#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10637#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11607#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11276#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11277#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11308#L598-33 assume !(1 == ~t6_pc~0); 11063#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 10869#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10870#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10728#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10729#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11551#L617-33 assume !(1 == ~t7_pc~0); 10529#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 10530#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11485#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11504#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11590#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10464#L636-33 assume 1 == ~t8_pc~0; 10465#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11386#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11248#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11249#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11379#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11380#L655-33 assume 1 == ~t9_pc~0; 11638#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10817#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10818#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11437#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 11466#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11010#L674-33 assume 1 == ~t10_pc~0; 10864#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10865#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11510#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11234#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11235#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11612#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11622#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11624#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11634#L1129-3 assume !(1 == ~T3_E~0); 10762#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10763#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10997#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10998#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11152#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11429#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11430#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11598#L1169-3 assume !(1 == ~E_1~0); 10867#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10868#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11515#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10524#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10525#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10812#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10813#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11138#L1209-3 assume !(1 == ~E_9~0); 10413#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10414#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11340#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10501#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10855#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10856#L1539 assume !(0 == start_simulation_~tmp~3#1); 10927#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11113#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10908#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10440#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 10441#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10820#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11174#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10925#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 10393#L1520-2 [2023-11-26 12:01:16,385 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:16,385 INFO L85 PathProgramCache]: Analyzing trace with hash -1012009875, now seen corresponding path program 1 times [2023-11-26 12:01:16,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:16,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177589073] [2023-11-26 12:01:16,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:16,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:16,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:16,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:16,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:16,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1177589073] [2023-11-26 12:01:16,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1177589073] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:16,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:16,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:16,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063112266] [2023-11-26 12:01:16,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:16,468 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:16,469 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:16,469 INFO L85 PathProgramCache]: Analyzing trace with hash 2069950345, now seen corresponding path program 1 times [2023-11-26 12:01:16,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:16,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533390919] [2023-11-26 12:01:16,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:16,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:16,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:16,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:16,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:16,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533390919] [2023-11-26 12:01:16,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533390919] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:16,562 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:16,562 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:16,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950815722] [2023-11-26 12:01:16,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:16,563 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:16,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:16,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:16,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:16,564 INFO L87 Difference]: Start difference. First operand 1289 states and 1909 transitions. cyclomatic complexity: 621 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:16,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:16,609 INFO L93 Difference]: Finished difference Result 1289 states and 1908 transitions. [2023-11-26 12:01:16,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1908 transitions. [2023-11-26 12:01:16,620 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:16,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1908 transitions. [2023-11-26 12:01:16,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-26 12:01:16,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-26 12:01:16,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1908 transitions. [2023-11-26 12:01:16,635 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:16,636 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1908 transitions. [2023-11-26 12:01:16,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1908 transitions. [2023-11-26 12:01:16,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-26 12:01:16,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4802172226532195) internal successors, (1908), 1288 states have internal predecessors, (1908), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:16,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1908 transitions. [2023-11-26 12:01:16,668 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1908 transitions. [2023-11-26 12:01:16,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:16,671 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1908 transitions. [2023-11-26 12:01:16,671 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 12:01:16,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1908 transitions. [2023-11-26 12:01:16,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:16,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:16,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:16,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:16,682 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:16,682 INFO L748 eck$LassoCheckResult]: Stem: 13301#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 13302#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14154#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14155#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14222#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 14216#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14217#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13470#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13213#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13214#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14123#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14124#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14105#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14106#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14146#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13264#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13265#L1006 assume !(0 == ~M_E~0); 13116#L1006-2 assume !(0 == ~T1_E~0); 13117#L1011-1 assume !(0 == ~T2_E~0); 14171#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14188#L1021-1 assume !(0 == ~T4_E~0); 12994#L1026-1 assume !(0 == ~T5_E~0); 12995#L1031-1 assume !(0 == ~T6_E~0); 13883#L1036-1 assume !(0 == ~T7_E~0); 13879#L1041-1 assume !(0 == ~T8_E~0); 13880#L1046-1 assume !(0 == ~T9_E~0); 13292#L1051-1 assume !(0 == ~T10_E~0); 13293#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14009#L1061-1 assume !(0 == ~E_2~0); 13217#L1066-1 assume !(0 == ~E_3~0); 13218#L1071-1 assume !(0 == ~E_4~0); 13984#L1076-1 assume !(0 == ~E_5~0); 13124#L1081-1 assume !(0 == ~E_6~0); 13125#L1086-1 assume !(0 == ~E_7~0); 13444#L1091-1 assume !(0 == ~E_8~0); 14163#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 14164#L1101-1 assume !(0 == ~E_10~0); 13513#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13514#L484 assume !(1 == ~m_pc~0); 13174#L484-2 is_master_triggered_~__retres1~0#1 := 0; 13173#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13796#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14077#L1245 assume !(0 != activate_threads_~tmp~1#1); 14078#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13869#L503 assume 1 == ~t1_pc~0; 13870#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13889#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13035#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13036#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 13029#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13030#L522 assume !(1 == ~t2_pc~0); 13835#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13228#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13229#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13508#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 14125#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14196#L541 assume 1 == ~t3_pc~0; 13778#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13580#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12976#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12977#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 13841#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13842#L560 assume !(1 == ~t4_pc~0); 13110#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 13109#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12990#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 12991#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13275#L579 assume 1 == ~t5_pc~0; 12941#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12942#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13055#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14082#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 14187#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14206#L598 assume 1 == ~t6_pc~0; 13357#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13358#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13486#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13487#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 13915#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13860#L617 assume !(1 == ~t7_pc~0); 13333#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13332#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14226#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14137#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13548#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13549#L636 assume 1 == ~t8_pc~0; 13731#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13732#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14038#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13924#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 13680#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13681#L655 assume !(1 == ~t9_pc~0); 13708#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13709#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13594#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13595#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 13935#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13936#L674 assume 1 == ~t10_pc~0; 13101#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13102#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13722#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13723#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 13669#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13670#L1119 assume !(1 == ~M_E~0); 13200#L1119-2 assume !(1 == ~T1_E~0); 13201#L1124-1 assume !(1 == ~T2_E~0); 13019#L1129-1 assume !(1 == ~T3_E~0); 13020#L1134-1 assume !(1 == ~T4_E~0); 13318#L1139-1 assume !(1 == ~T5_E~0); 13319#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13543#L1149-1 assume !(1 == ~T7_E~0); 13194#L1154-1 assume !(1 == ~T8_E~0); 13195#L1159-1 assume !(1 == ~T9_E~0); 13276#L1164-1 assume !(1 == ~T10_E~0); 13697#L1169-1 assume !(1 == ~E_1~0); 13596#L1174-1 assume !(1 == ~E_2~0); 13370#L1179-1 assume !(1 == ~E_3~0); 13266#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13267#L1189-1 assume !(1 == ~E_5~0); 13316#L1194-1 assume !(1 == ~E_6~0); 13422#L1199-1 assume !(1 == ~E_7~0); 13382#L1204-1 assume !(1 == ~E_8~0); 13383#L1209-1 assume !(1 == ~E_9~0); 13933#L1214-1 assume !(1 == ~E_10~0); 13934#L1219-1 assume { :end_inline_reset_delta_events } true; 12978#L1520-2 [2023-11-26 12:01:16,683 INFO L750 eck$LassoCheckResult]: Loop: 12978#L1520-2 assume !false; 12979#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13770#L981-1 assume !false; 13955#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13956#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12962#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13563#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13564#L836 assume !(0 != eval_~tmp~0#1); 14047#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13739#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13535#L1006-3 assume !(0 == ~M_E~0); 13536#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14033#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14034#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14071#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13750#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13751#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14001#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14002#L1041-3 assume !(0 == ~T8_E~0); 14065#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14066#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14003#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13289#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13290#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13291#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14174#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13083#L1081-3 assume !(0 == ~E_6~0); 13084#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13131#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13132#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14147#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14148#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13772#L484-33 assume !(1 == ~m_pc~0); 13773#L484-35 is_master_triggered_~__retres1~0#1 := 0; 13683#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13684#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12984#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 12985#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13430#L503-33 assume 1 == ~t1_pc~0; 13431#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13918#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13919#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13351#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13352#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13810#L522-33 assume !(1 == ~t2_pc~0); 13811#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 13121#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13122#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14019#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13831#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13832#L541-33 assume 1 == ~t3_pc~0; 13141#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12982#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12983#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13150#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13802#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13999#L560-33 assume 1 == ~t4_pc~0; 13687#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13059#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13060#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14176#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13978#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12968#L579-33 assume 1 == ~t5_pc~0; 12969#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13222#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14192#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13861#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13862#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13888#L598-33 assume 1 == ~t6_pc~0; 14194#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13454#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13455#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13313#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13314#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14136#L617-33 assume 1 == ~t7_pc~0; 14144#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13115#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14070#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14089#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14175#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13049#L636-33 assume 1 == ~t8_pc~0; 13050#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13971#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13833#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13834#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13962#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13963#L655-33 assume !(1 == ~t9_pc~0); 14224#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 13400#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13401#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14022#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 14051#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13593#L674-33 assume 1 == ~t10_pc~0; 13449#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13450#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14095#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13819#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13820#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14197#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14207#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14209#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14219#L1129-3 assume !(1 == ~T3_E~0); 13344#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13345#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13582#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13583#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13737#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14014#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14015#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14182#L1169-3 assume !(1 == ~E_1~0); 13452#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13453#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14100#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13106#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13107#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13397#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13398#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13721#L1209-3 assume !(1 == ~E_9~0); 12996#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12997#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13923#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13086#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13440#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 13441#L1539 assume !(0 == start_simulation_~tmp~3#1); 13511#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13698#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13493#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13025#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 13026#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13405#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13759#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 13512#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 12978#L1520-2 [2023-11-26 12:01:16,684 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:16,684 INFO L85 PathProgramCache]: Analyzing trace with hash 709992811, now seen corresponding path program 1 times [2023-11-26 12:01:16,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:16,685 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687934283] [2023-11-26 12:01:16,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:16,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:16,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:16,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:16,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:16,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687934283] [2023-11-26 12:01:16,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687934283] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:16,753 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:16,753 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:16,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338693786] [2023-11-26 12:01:16,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:16,754 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:16,755 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:16,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1198674282, now seen corresponding path program 1 times [2023-11-26 12:01:16,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:16,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312399773] [2023-11-26 12:01:16,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:16,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:16,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:16,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:16,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:16,845 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312399773] [2023-11-26 12:01:16,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312399773] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:16,846 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:16,846 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:16,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143076639] [2023-11-26 12:01:16,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:16,847 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:16,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:16,848 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:16,848 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:16,849 INFO L87 Difference]: Start difference. First operand 1289 states and 1908 transitions. cyclomatic complexity: 620 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:16,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:16,889 INFO L93 Difference]: Finished difference Result 1289 states and 1907 transitions. [2023-11-26 12:01:16,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1907 transitions. [2023-11-26 12:01:16,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:16,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1907 transitions. [2023-11-26 12:01:16,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-26 12:01:16,917 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-26 12:01:16,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1907 transitions. [2023-11-26 12:01:16,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:16,920 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1907 transitions. [2023-11-26 12:01:16,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1907 transitions. [2023-11-26 12:01:16,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-26 12:01:16,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4794414274631498) internal successors, (1907), 1288 states have internal predecessors, (1907), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:16,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1907 transitions. [2023-11-26 12:01:16,957 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1907 transitions. [2023-11-26 12:01:16,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:16,959 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1907 transitions. [2023-11-26 12:01:16,960 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 12:01:16,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1907 transitions. [2023-11-26 12:01:16,970 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:16,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:16,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:16,973 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:16,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:16,974 INFO L748 eck$LassoCheckResult]: Stem: 15886#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 15887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 16739#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16740#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16807#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 16801#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16802#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16055#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15800#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15801#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16708#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16709#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16690#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16691#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16731#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15849#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15850#L1006 assume !(0 == ~M_E~0); 15704#L1006-2 assume !(0 == ~T1_E~0); 15705#L1011-1 assume !(0 == ~T2_E~0); 16756#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16773#L1021-1 assume !(0 == ~T4_E~0); 15579#L1026-1 assume !(0 == ~T5_E~0); 15580#L1031-1 assume !(0 == ~T6_E~0); 16469#L1036-1 assume !(0 == ~T7_E~0); 16464#L1041-1 assume !(0 == ~T8_E~0); 16465#L1046-1 assume !(0 == ~T9_E~0); 15877#L1051-1 assume !(0 == ~T10_E~0); 15878#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 16594#L1061-1 assume !(0 == ~E_2~0); 15802#L1066-1 assume !(0 == ~E_3~0); 15803#L1071-1 assume !(0 == ~E_4~0); 16569#L1076-1 assume !(0 == ~E_5~0); 15709#L1081-1 assume !(0 == ~E_6~0); 15710#L1086-1 assume !(0 == ~E_7~0); 16029#L1091-1 assume !(0 == ~E_8~0); 16748#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16749#L1101-1 assume !(0 == ~E_10~0); 16098#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16099#L484 assume !(1 == ~m_pc~0); 15761#L484-2 is_master_triggered_~__retres1~0#1 := 0; 15760#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16381#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16662#L1245 assume !(0 != activate_threads_~tmp~1#1); 16663#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16454#L503 assume 1 == ~t1_pc~0; 16455#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16478#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15620#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15621#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 15616#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15617#L522 assume !(1 == ~t2_pc~0); 16420#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15817#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15818#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16094#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 16710#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16781#L541 assume 1 == ~t3_pc~0; 16365#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16165#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15563#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15564#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 16430#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16431#L560 assume !(1 == ~t4_pc~0); 15695#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15694#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15575#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 15576#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15860#L579 assume 1 == ~t5_pc~0; 15526#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15527#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16667#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 16772#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16791#L598 assume 1 == ~t6_pc~0; 15942#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15943#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16071#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16072#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 16500#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16445#L617 assume !(1 == ~t7_pc~0); 15918#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15917#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16811#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16722#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16135#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16136#L636 assume 1 == ~t8_pc~0; 16316#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16317#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16627#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16508#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 16263#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16264#L655 assume !(1 == ~t9_pc~0); 16291#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 16292#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16175#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16176#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 16520#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16521#L674 assume 1 == ~t10_pc~0; 15686#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15687#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16306#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16307#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 16254#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16255#L1119 assume !(1 == ~M_E~0); 15785#L1119-2 assume !(1 == ~T1_E~0); 15786#L1124-1 assume !(1 == ~T2_E~0); 15604#L1129-1 assume !(1 == ~T3_E~0); 15605#L1134-1 assume !(1 == ~T4_E~0); 15902#L1139-1 assume !(1 == ~T5_E~0); 15903#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16128#L1149-1 assume !(1 == ~T7_E~0); 15779#L1154-1 assume !(1 == ~T8_E~0); 15780#L1159-1 assume !(1 == ~T9_E~0); 15861#L1164-1 assume !(1 == ~T10_E~0); 16282#L1169-1 assume !(1 == ~E_1~0); 16181#L1174-1 assume !(1 == ~E_2~0); 15955#L1179-1 assume !(1 == ~E_3~0); 15851#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15852#L1189-1 assume !(1 == ~E_5~0); 15900#L1194-1 assume !(1 == ~E_6~0); 16006#L1199-1 assume !(1 == ~E_7~0); 15967#L1204-1 assume !(1 == ~E_8~0); 15968#L1209-1 assume !(1 == ~E_9~0); 16518#L1214-1 assume !(1 == ~E_10~0); 16519#L1219-1 assume { :end_inline_reset_delta_events } true; 15561#L1520-2 [2023-11-26 12:01:16,975 INFO L750 eck$LassoCheckResult]: Loop: 15561#L1520-2 assume !false; 15562#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16355#L981-1 assume !false; 16540#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16541#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15547#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16145#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16146#L836 assume !(0 != eval_~tmp~0#1); 16632#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16324#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16120#L1006-3 assume !(0 == ~M_E~0); 16121#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16618#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16619#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16656#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16333#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16334#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16586#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16587#L1041-3 assume !(0 == ~T8_E~0); 16648#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16649#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16588#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15874#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15875#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15876#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16759#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15668#L1081-3 assume !(0 == ~E_6~0); 15669#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15714#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15715#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16732#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16733#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16357#L484-33 assume !(1 == ~m_pc~0); 16358#L484-35 is_master_triggered_~__retres1~0#1 := 0; 16268#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16269#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15569#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 15570#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16014#L503-33 assume !(1 == ~t1_pc~0); 16016#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16503#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16504#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15936#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15937#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16395#L522-33 assume !(1 == ~t2_pc~0); 16396#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 15706#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15707#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16604#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16416#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16417#L541-33 assume 1 == ~t3_pc~0; 15726#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15567#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15568#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15735#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16387#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16584#L560-33 assume 1 == ~t4_pc~0; 16272#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15644#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15645#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16761#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16563#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15556#L579-33 assume 1 == ~t5_pc~0; 15557#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15807#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16777#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16446#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16447#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16477#L598-33 assume !(1 == ~t6_pc~0); 16232#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 16039#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16040#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15898#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15899#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16721#L617-33 assume !(1 == ~t7_pc~0); 15699#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 15700#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16655#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16674#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16760#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15634#L636-33 assume 1 == ~t8_pc~0; 15635#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16556#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16418#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16419#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16547#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16548#L655-33 assume 1 == ~t9_pc~0; 16808#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15987#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15988#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16607#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 16636#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16180#L674-33 assume 1 == ~t10_pc~0; 16034#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16035#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16680#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16404#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16405#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16782#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16792#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16794#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16804#L1129-3 assume !(1 == ~T3_E~0); 15932#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15933#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16167#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16168#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16322#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16599#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16600#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16768#L1169-3 assume !(1 == ~E_1~0); 16037#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16038#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16685#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15691#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15692#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15982#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15983#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16308#L1209-3 assume !(1 == ~E_9~0); 15583#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15584#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16510#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15671#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16025#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16026#L1539 assume !(0 == start_simulation_~tmp~3#1); 16096#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16283#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16078#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 15612#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 15613#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15990#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16344#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 16097#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 15561#L1520-2 [2023-11-26 12:01:16,977 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:16,977 INFO L85 PathProgramCache]: Analyzing trace with hash 1042635949, now seen corresponding path program 1 times [2023-11-26 12:01:16,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:16,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763159568] [2023-11-26 12:01:16,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:16,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:16,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:17,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:17,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:17,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763159568] [2023-11-26 12:01:17,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763159568] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:17,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:17,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:17,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267942593] [2023-11-26 12:01:17,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:17,055 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:17,055 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:17,056 INFO L85 PathProgramCache]: Analyzing trace with hash -1952021528, now seen corresponding path program 1 times [2023-11-26 12:01:17,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:17,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693081845] [2023-11-26 12:01:17,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:17,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:17,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:17,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:17,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:17,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [693081845] [2023-11-26 12:01:17,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [693081845] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:17,165 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:17,166 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:17,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888690868] [2023-11-26 12:01:17,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:17,167 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:17,167 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:17,167 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:17,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:17,168 INFO L87 Difference]: Start difference. First operand 1289 states and 1907 transitions. cyclomatic complexity: 619 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:17,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:17,212 INFO L93 Difference]: Finished difference Result 1289 states and 1906 transitions. [2023-11-26 12:01:17,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1906 transitions. [2023-11-26 12:01:17,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:17,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1906 transitions. [2023-11-26 12:01:17,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-26 12:01:17,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-26 12:01:17,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1906 transitions. [2023-11-26 12:01:17,246 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:17,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1906 transitions. [2023-11-26 12:01:17,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1906 transitions. [2023-11-26 12:01:17,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-26 12:01:17,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.47866563227308) internal successors, (1906), 1288 states have internal predecessors, (1906), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:17,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1906 transitions. [2023-11-26 12:01:17,284 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1906 transitions. [2023-11-26 12:01:17,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:17,287 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1906 transitions. [2023-11-26 12:01:17,287 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 12:01:17,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1906 transitions. [2023-11-26 12:01:17,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:17,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:17,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:17,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:17,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:17,302 INFO L748 eck$LassoCheckResult]: Stem: 18471#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 18472#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19323#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19324#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19392#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 19386#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19387#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18638#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18383#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18384#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19293#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19294#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19275#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19276#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19316#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18432#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18433#L1006 assume !(0 == ~M_E~0); 18286#L1006-2 assume !(0 == ~T1_E~0); 18287#L1011-1 assume !(0 == ~T2_E~0); 19341#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19358#L1021-1 assume !(0 == ~T4_E~0); 18162#L1026-1 assume !(0 == ~T5_E~0); 18163#L1031-1 assume !(0 == ~T6_E~0); 19052#L1036-1 assume !(0 == ~T7_E~0); 19049#L1041-1 assume !(0 == ~T8_E~0); 19050#L1046-1 assume !(0 == ~T9_E~0); 18462#L1051-1 assume !(0 == ~T10_E~0); 18463#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 19179#L1061-1 assume !(0 == ~E_2~0); 18387#L1066-1 assume !(0 == ~E_3~0); 18388#L1071-1 assume !(0 == ~E_4~0); 19154#L1076-1 assume !(0 == ~E_5~0); 18294#L1081-1 assume !(0 == ~E_6~0); 18295#L1086-1 assume !(0 == ~E_7~0); 18612#L1091-1 assume !(0 == ~E_8~0); 19331#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 19332#L1101-1 assume !(0 == ~E_10~0); 18683#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18684#L484 assume !(1 == ~m_pc~0); 18344#L484-2 is_master_triggered_~__retres1~0#1 := 0; 18343#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18966#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19247#L1245 assume !(0 != activate_threads_~tmp~1#1); 19248#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19039#L503 assume 1 == ~t1_pc~0; 19040#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19058#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18204#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 18199#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18200#L522 assume !(1 == ~t2_pc~0); 19005#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18398#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18399#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18678#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 19295#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19366#L541 assume 1 == ~t3_pc~0; 18948#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18750#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18146#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18147#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 19011#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19012#L560 assume !(1 == ~t4_pc~0); 18278#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18277#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18310#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18160#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 18161#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18443#L579 assume 1 == ~t5_pc~0; 18111#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18112#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18225#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19252#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 19356#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19376#L598 assume 1 == ~t6_pc~0; 18527#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18528#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18653#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18654#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 19085#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19030#L617 assume !(1 == ~t7_pc~0); 18503#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18502#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19396#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19307#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18717#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18718#L636 assume 1 == ~t8_pc~0; 18901#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18902#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19207#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19093#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 18848#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18849#L655 assume !(1 == ~t9_pc~0); 18876#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18877#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18760#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18761#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 19105#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19106#L674 assume 1 == ~t10_pc~0; 18271#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18272#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18891#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18892#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 18839#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18840#L1119 assume !(1 == ~M_E~0); 18370#L1119-2 assume !(1 == ~T1_E~0); 18371#L1124-1 assume !(1 == ~T2_E~0); 18189#L1129-1 assume !(1 == ~T3_E~0); 18190#L1134-1 assume !(1 == ~T4_E~0); 18487#L1139-1 assume !(1 == ~T5_E~0); 18488#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18713#L1149-1 assume !(1 == ~T7_E~0); 18364#L1154-1 assume !(1 == ~T8_E~0); 18365#L1159-1 assume !(1 == ~T9_E~0); 18446#L1164-1 assume !(1 == ~T10_E~0); 18867#L1169-1 assume !(1 == ~E_1~0); 18766#L1174-1 assume !(1 == ~E_2~0); 18540#L1179-1 assume !(1 == ~E_3~0); 18436#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18437#L1189-1 assume !(1 == ~E_5~0); 18485#L1194-1 assume !(1 == ~E_6~0); 18591#L1199-1 assume !(1 == ~E_7~0); 18552#L1204-1 assume !(1 == ~E_8~0); 18553#L1209-1 assume !(1 == ~E_9~0); 19103#L1214-1 assume !(1 == ~E_10~0); 19104#L1219-1 assume { :end_inline_reset_delta_events } true; 18148#L1520-2 [2023-11-26 12:01:17,303 INFO L750 eck$LassoCheckResult]: Loop: 18148#L1520-2 assume !false; 18149#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18940#L981-1 assume !false; 19125#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19126#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18132#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18730#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18731#L836 assume !(0 != eval_~tmp~0#1); 19217#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18909#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18705#L1006-3 assume !(0 == ~M_E~0); 18706#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19203#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19204#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19241#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18918#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18919#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19171#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19172#L1041-3 assume !(0 == ~T8_E~0); 19233#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19234#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19173#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18459#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18460#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18461#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19344#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18253#L1081-3 assume !(0 == ~E_6~0); 18254#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18299#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18300#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19317#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19318#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18942#L484-33 assume 1 == ~m_pc~0; 18944#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18853#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18854#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18154#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 18155#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18599#L503-33 assume 1 == ~t1_pc~0; 18600#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19088#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19089#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18521#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18522#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18980#L522-33 assume !(1 == ~t2_pc~0); 18981#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 18291#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18292#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19189#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19001#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19002#L541-33 assume 1 == ~t3_pc~0; 18311#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18152#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18153#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18320#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18972#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19169#L560-33 assume 1 == ~t4_pc~0; 18857#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18229#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18230#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19346#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19148#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18141#L579-33 assume 1 == ~t5_pc~0; 18142#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18392#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19362#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19031#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19032#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19063#L598-33 assume !(1 == ~t6_pc~0); 18817#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 18624#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18625#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18483#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18484#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19306#L617-33 assume 1 == ~t7_pc~0; 19314#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18285#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19240#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19259#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19345#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18219#L636-33 assume 1 == ~t8_pc~0; 18220#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19141#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19003#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19004#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19132#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19133#L655-33 assume 1 == ~t9_pc~0; 19393#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18572#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18573#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19192#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 19221#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18765#L674-33 assume 1 == ~t10_pc~0; 18619#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18620#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19265#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18989#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18990#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19367#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19377#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19379#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19389#L1129-3 assume !(1 == ~T3_E~0); 18517#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18518#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18752#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18753#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18907#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19184#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19185#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19353#L1169-3 assume !(1 == ~E_1~0); 18622#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18623#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19270#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18279#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18280#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18567#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18568#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18893#L1209-3 assume !(1 == ~E_9~0); 18168#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18169#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19095#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18256#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18610#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 18611#L1539 assume !(0 == start_simulation_~tmp~3#1); 18681#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18868#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18663#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18197#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 18198#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18575#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18929#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 18682#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 18148#L1520-2 [2023-11-26 12:01:17,304 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:17,304 INFO L85 PathProgramCache]: Analyzing trace with hash -886296277, now seen corresponding path program 1 times [2023-11-26 12:01:17,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:17,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561942311] [2023-11-26 12:01:17,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:17,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:17,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:17,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:17,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:17,368 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1561942311] [2023-11-26 12:01:17,369 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1561942311] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:17,369 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:17,369 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:17,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644531818] [2023-11-26 12:01:17,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:17,375 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:17,375 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:17,376 INFO L85 PathProgramCache]: Analyzing trace with hash -80312693, now seen corresponding path program 1 times [2023-11-26 12:01:17,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:17,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670044769] [2023-11-26 12:01:17,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:17,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:17,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:17,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:17,483 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:17,483 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670044769] [2023-11-26 12:01:17,483 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670044769] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:17,487 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:17,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:17,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774834905] [2023-11-26 12:01:17,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:17,488 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:17,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:17,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:17,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:17,489 INFO L87 Difference]: Start difference. First operand 1289 states and 1906 transitions. cyclomatic complexity: 618 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:17,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:17,541 INFO L93 Difference]: Finished difference Result 1289 states and 1905 transitions. [2023-11-26 12:01:17,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1905 transitions. [2023-11-26 12:01:17,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:17,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1905 transitions. [2023-11-26 12:01:17,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-26 12:01:17,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-26 12:01:17,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1905 transitions. [2023-11-26 12:01:17,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:17,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1905 transitions. [2023-11-26 12:01:17,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1905 transitions. [2023-11-26 12:01:17,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-26 12:01:17,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.47788983708301) internal successors, (1905), 1288 states have internal predecessors, (1905), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:17,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1905 transitions. [2023-11-26 12:01:17,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1905 transitions. [2023-11-26 12:01:17,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:17,616 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1905 transitions. [2023-11-26 12:01:17,616 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 12:01:17,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1905 transitions. [2023-11-26 12:01:17,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:17,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:17,625 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:17,627 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:17,628 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:17,628 INFO L748 eck$LassoCheckResult]: Stem: 21056#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 21057#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 21909#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21910#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21977#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 21971#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21972#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21223#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20968#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20969#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21878#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21879#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21860#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21861#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21901#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21019#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21020#L1006 assume !(0 == ~M_E~0); 20871#L1006-2 assume !(0 == ~T1_E~0); 20872#L1011-1 assume !(0 == ~T2_E~0); 21926#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21943#L1021-1 assume !(0 == ~T4_E~0); 20749#L1026-1 assume !(0 == ~T5_E~0); 20750#L1031-1 assume !(0 == ~T6_E~0); 21637#L1036-1 assume !(0 == ~T7_E~0); 21634#L1041-1 assume !(0 == ~T8_E~0); 21635#L1046-1 assume !(0 == ~T9_E~0); 21047#L1051-1 assume !(0 == ~T10_E~0); 21048#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 21764#L1061-1 assume !(0 == ~E_2~0); 20972#L1066-1 assume !(0 == ~E_3~0); 20973#L1071-1 assume !(0 == ~E_4~0); 21739#L1076-1 assume !(0 == ~E_5~0); 20879#L1081-1 assume !(0 == ~E_6~0); 20880#L1086-1 assume !(0 == ~E_7~0); 21197#L1091-1 assume !(0 == ~E_8~0); 21916#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 21917#L1101-1 assume !(0 == ~E_10~0); 21268#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21269#L484 assume !(1 == ~m_pc~0); 20929#L484-2 is_master_triggered_~__retres1~0#1 := 0; 20928#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21551#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21832#L1245 assume !(0 != activate_threads_~tmp~1#1); 21833#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21624#L503 assume 1 == ~t1_pc~0; 21625#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21643#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20789#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 20784#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20785#L522 assume !(1 == ~t2_pc~0); 21590#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20983#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20984#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21263#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 21880#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21951#L541 assume 1 == ~t3_pc~0; 21533#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21335#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20731#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20732#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 21596#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21597#L560 assume !(1 == ~t4_pc~0); 20865#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20864#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20895#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20745#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 20746#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21028#L579 assume 1 == ~t5_pc~0; 20696#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20697#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20810#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21837#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 21941#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21961#L598 assume 1 == ~t6_pc~0; 21112#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21113#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21238#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21239#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 21670#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21615#L617 assume !(1 == ~t7_pc~0); 21088#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21087#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21981#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21892#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21302#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21303#L636 assume 1 == ~t8_pc~0; 21486#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21487#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21792#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21679#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 21433#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21434#L655 assume !(1 == ~t9_pc~0); 21463#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21464#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21346#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21347#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 21690#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21691#L674 assume 1 == ~t10_pc~0; 20856#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20857#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21477#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21478#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 21424#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21425#L1119 assume !(1 == ~M_E~0); 20955#L1119-2 assume !(1 == ~T1_E~0); 20956#L1124-1 assume !(1 == ~T2_E~0); 20774#L1129-1 assume !(1 == ~T3_E~0); 20775#L1134-1 assume !(1 == ~T4_E~0); 21073#L1139-1 assume !(1 == ~T5_E~0); 21074#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21298#L1149-1 assume !(1 == ~T7_E~0); 20949#L1154-1 assume !(1 == ~T8_E~0); 20950#L1159-1 assume !(1 == ~T9_E~0); 21031#L1164-1 assume !(1 == ~T10_E~0); 21452#L1169-1 assume !(1 == ~E_1~0); 21351#L1174-1 assume !(1 == ~E_2~0); 21125#L1179-1 assume !(1 == ~E_3~0); 21021#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21022#L1189-1 assume !(1 == ~E_5~0); 21070#L1194-1 assume !(1 == ~E_6~0); 21176#L1199-1 assume !(1 == ~E_7~0); 21137#L1204-1 assume !(1 == ~E_8~0); 21138#L1209-1 assume !(1 == ~E_9~0); 21688#L1214-1 assume !(1 == ~E_10~0); 21689#L1219-1 assume { :end_inline_reset_delta_events } true; 20733#L1520-2 [2023-11-26 12:01:17,629 INFO L750 eck$LassoCheckResult]: Loop: 20733#L1520-2 assume !false; 20734#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21525#L981-1 assume !false; 21710#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21711#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20717#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21318#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21319#L836 assume !(0 != eval_~tmp~0#1); 21802#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21494#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21290#L1006-3 assume !(0 == ~M_E~0); 21291#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21788#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21789#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21826#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21503#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21504#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21756#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21757#L1041-3 assume !(0 == ~T8_E~0); 21818#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21819#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21758#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21044#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21045#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21046#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21929#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20838#L1081-3 assume !(0 == ~E_6~0); 20839#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20884#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20885#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21902#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21903#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21527#L484-33 assume !(1 == ~m_pc~0); 21528#L484-35 is_master_triggered_~__retres1~0#1 := 0; 21438#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21439#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20739#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 20740#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21184#L503-33 assume 1 == ~t1_pc~0; 21185#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21673#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21674#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21106#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21107#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21565#L522-33 assume !(1 == ~t2_pc~0); 21566#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 20876#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20877#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21774#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21588#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21589#L541-33 assume 1 == ~t3_pc~0; 20896#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20737#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20738#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20905#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21557#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21754#L560-33 assume 1 == ~t4_pc~0; 21442#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20814#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20815#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21931#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21733#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20726#L579-33 assume 1 == ~t5_pc~0; 20727#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20977#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21947#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21616#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21617#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21648#L598-33 assume !(1 == ~t6_pc~0); 21403#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 21209#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21210#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21068#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21069#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21891#L617-33 assume !(1 == ~t7_pc~0); 20869#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 20870#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21825#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21844#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21930#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20801#L636-33 assume 1 == ~t8_pc~0; 20802#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21726#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21586#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21587#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21715#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21716#L655-33 assume 1 == ~t9_pc~0; 21978#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21154#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21155#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21777#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 21805#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21345#L674-33 assume 1 == ~t10_pc~0; 21204#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21205#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21849#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21574#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21575#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21952#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21962#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21964#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21974#L1129-3 assume !(1 == ~T3_E~0); 21099#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21100#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21337#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21338#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21492#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21769#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21770#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21937#L1169-3 assume !(1 == ~E_1~0); 21207#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21208#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21855#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20861#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20862#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21152#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21153#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21476#L1209-3 assume !(1 == ~E_9~0); 20751#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20752#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21678#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20841#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21195#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 21196#L1539 assume !(0 == start_simulation_~tmp~3#1); 21266#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21453#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21248#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20780#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 20781#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21160#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21514#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 21267#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 20733#L1520-2 [2023-11-26 12:01:17,630 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:17,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1406784749, now seen corresponding path program 1 times [2023-11-26 12:01:17,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:17,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280913337] [2023-11-26 12:01:17,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:17,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:17,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:17,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:17,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:17,694 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280913337] [2023-11-26 12:01:17,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280913337] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:17,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:17,695 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:17,695 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809865654] [2023-11-26 12:01:17,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:17,696 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:17,697 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:17,697 INFO L85 PathProgramCache]: Analyzing trace with hash 2069950345, now seen corresponding path program 2 times [2023-11-26 12:01:17,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:17,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129744301] [2023-11-26 12:01:17,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:17,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:17,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:17,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:17,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:17,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129744301] [2023-11-26 12:01:17,777 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129744301] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:17,778 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:17,778 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:17,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779053765] [2023-11-26 12:01:17,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:17,779 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:17,779 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:17,780 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:17,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:17,780 INFO L87 Difference]: Start difference. First operand 1289 states and 1905 transitions. cyclomatic complexity: 617 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:17,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:17,826 INFO L93 Difference]: Finished difference Result 1289 states and 1904 transitions. [2023-11-26 12:01:17,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1904 transitions. [2023-11-26 12:01:17,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:17,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1904 transitions. [2023-11-26 12:01:17,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-26 12:01:17,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-26 12:01:17,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1904 transitions. [2023-11-26 12:01:17,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:17,857 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1904 transitions. [2023-11-26 12:01:17,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1904 transitions. [2023-11-26 12:01:17,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-26 12:01:17,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4771140418929403) internal successors, (1904), 1288 states have internal predecessors, (1904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:17,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1904 transitions. [2023-11-26 12:01:17,896 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1904 transitions. [2023-11-26 12:01:17,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:17,898 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1904 transitions. [2023-11-26 12:01:17,898 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 12:01:17,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1904 transitions. [2023-11-26 12:01:17,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-26 12:01:17,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:17,907 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:17,910 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:17,911 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:17,911 INFO L748 eck$LassoCheckResult]: Stem: 23641#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 23642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24494#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24495#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24562#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 24556#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24557#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23810#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23553#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23554#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24463#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24464#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24445#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24446#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24486#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 23604#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23605#L1006 assume !(0 == ~M_E~0); 23456#L1006-2 assume !(0 == ~T1_E~0); 23457#L1011-1 assume !(0 == ~T2_E~0); 24511#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24528#L1021-1 assume !(0 == ~T4_E~0); 23334#L1026-1 assume !(0 == ~T5_E~0); 23335#L1031-1 assume !(0 == ~T6_E~0); 24223#L1036-1 assume !(0 == ~T7_E~0); 24219#L1041-1 assume !(0 == ~T8_E~0); 24220#L1046-1 assume !(0 == ~T9_E~0); 23632#L1051-1 assume !(0 == ~T10_E~0); 23633#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 24349#L1061-1 assume !(0 == ~E_2~0); 23557#L1066-1 assume !(0 == ~E_3~0); 23558#L1071-1 assume !(0 == ~E_4~0); 24324#L1076-1 assume !(0 == ~E_5~0); 23464#L1081-1 assume !(0 == ~E_6~0); 23465#L1086-1 assume !(0 == ~E_7~0); 23784#L1091-1 assume !(0 == ~E_8~0); 24503#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24504#L1101-1 assume !(0 == ~E_10~0); 23853#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23854#L484 assume !(1 == ~m_pc~0); 23516#L484-2 is_master_triggered_~__retres1~0#1 := 0; 23515#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24136#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24417#L1245 assume !(0 != activate_threads_~tmp~1#1); 24418#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24209#L503 assume 1 == ~t1_pc~0; 24210#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24229#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23375#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23376#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 23369#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23370#L522 assume !(1 == ~t2_pc~0); 24175#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23569#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23570#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23849#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 24465#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24536#L541 assume 1 == ~t3_pc~0; 24118#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23920#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23316#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23317#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 24181#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24182#L560 assume !(1 == ~t4_pc~0); 23450#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23449#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23480#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23330#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 23331#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23615#L579 assume 1 == ~t5_pc~0; 23281#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23282#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23395#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24422#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 24527#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24546#L598 assume 1 == ~t6_pc~0; 23697#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23698#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23826#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23827#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 24255#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24200#L617 assume !(1 == ~t7_pc~0); 23673#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 23672#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24566#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24477#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23888#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23889#L636 assume 1 == ~t8_pc~0; 24071#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24072#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24378#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24264#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 24020#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24021#L655 assume !(1 == ~t9_pc~0); 24049#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24050#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23934#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23935#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 24275#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24276#L674 assume 1 == ~t10_pc~0; 23441#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23442#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24062#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24063#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 24009#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24010#L1119 assume !(1 == ~M_E~0); 23540#L1119-2 assume !(1 == ~T1_E~0); 23541#L1124-1 assume !(1 == ~T2_E~0); 23359#L1129-1 assume !(1 == ~T3_E~0); 23360#L1134-1 assume !(1 == ~T4_E~0); 23658#L1139-1 assume !(1 == ~T5_E~0); 23659#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23883#L1149-1 assume !(1 == ~T7_E~0); 23534#L1154-1 assume !(1 == ~T8_E~0); 23535#L1159-1 assume !(1 == ~T9_E~0); 23616#L1164-1 assume !(1 == ~T10_E~0); 24037#L1169-1 assume !(1 == ~E_1~0); 23936#L1174-1 assume !(1 == ~E_2~0); 23710#L1179-1 assume !(1 == ~E_3~0); 23606#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 23607#L1189-1 assume !(1 == ~E_5~0); 23656#L1194-1 assume !(1 == ~E_6~0); 23762#L1199-1 assume !(1 == ~E_7~0); 23722#L1204-1 assume !(1 == ~E_8~0); 23723#L1209-1 assume !(1 == ~E_9~0); 24273#L1214-1 assume !(1 == ~E_10~0); 24274#L1219-1 assume { :end_inline_reset_delta_events } true; 23318#L1520-2 [2023-11-26 12:01:17,912 INFO L750 eck$LassoCheckResult]: Loop: 23318#L1520-2 assume !false; 23319#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24110#L981-1 assume !false; 24295#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24296#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23302#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23903#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23904#L836 assume !(0 != eval_~tmp~0#1); 24387#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24079#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23875#L1006-3 assume !(0 == ~M_E~0); 23876#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24373#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24374#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24411#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24090#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24091#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24341#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24342#L1041-3 assume !(0 == ~T8_E~0); 24405#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24406#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24343#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23629#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23630#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23631#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24514#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23423#L1081-3 assume !(0 == ~E_6~0); 23424#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23473#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23474#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24487#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24488#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24113#L484-33 assume !(1 == ~m_pc~0); 24114#L484-35 is_master_triggered_~__retres1~0#1 := 0; 24023#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24024#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23324#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 23325#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23766#L503-33 assume 1 == ~t1_pc~0; 23767#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24258#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24259#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23689#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23690#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24147#L522-33 assume !(1 == ~t2_pc~0); 24148#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 23461#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23462#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24359#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24171#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24172#L541-33 assume 1 == ~t3_pc~0; 23481#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23322#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23323#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23490#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24142#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24339#L560-33 assume 1 == ~t4_pc~0; 24027#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23399#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23400#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24516#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24318#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23311#L579-33 assume 1 == ~t5_pc~0; 23312#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23562#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24532#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24201#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24202#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24228#L598-33 assume !(1 == ~t6_pc~0); 23986#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 23794#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23795#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23653#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23654#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24476#L617-33 assume 1 == ~t7_pc~0; 24484#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23455#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24410#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24429#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24515#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23389#L636-33 assume 1 == ~t8_pc~0; 23390#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24311#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24173#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24174#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24302#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24303#L655-33 assume 1 == ~t9_pc~0; 24563#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23740#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23741#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24362#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 24391#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23933#L674-33 assume 1 == ~t10_pc~0; 23789#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23790#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24435#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24159#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24160#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24537#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24547#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24549#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24559#L1129-3 assume !(1 == ~T3_E~0); 23684#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23685#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23922#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23923#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24077#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24354#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24355#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24522#L1169-3 assume !(1 == ~E_1~0); 23792#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23793#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24440#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23446#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23447#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23737#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23738#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24061#L1209-3 assume !(1 == ~E_9~0); 23336#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23337#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24263#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23426#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23780#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23781#L1539 assume !(0 == start_simulation_~tmp~3#1); 23851#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24038#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23833#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23367#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23368#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23745#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24099#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23852#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 23318#L1520-2 [2023-11-26 12:01:17,913 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:17,913 INFO L85 PathProgramCache]: Analyzing trace with hash 935428399, now seen corresponding path program 1 times [2023-11-26 12:01:17,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:17,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080385700] [2023-11-26 12:01:17,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:17,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:17,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:18,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:18,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:18,050 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080385700] [2023-11-26 12:01:18,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080385700] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:18,051 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:18,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:18,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116252510] [2023-11-26 12:01:18,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:18,053 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:18,053 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:18,054 INFO L85 PathProgramCache]: Analyzing trace with hash -1083369558, now seen corresponding path program 1 times [2023-11-26 12:01:18,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:18,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1626386016] [2023-11-26 12:01:18,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:18,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:18,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:18,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:18,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:18,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1626386016] [2023-11-26 12:01:18,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1626386016] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:18,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:18,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:18,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859984165] [2023-11-26 12:01:18,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:18,126 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:18,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:18,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:01:18,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:01:18,127 INFO L87 Difference]: Start difference. First operand 1289 states and 1904 transitions. cyclomatic complexity: 616 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:18,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:18,379 INFO L93 Difference]: Finished difference Result 2460 states and 3626 transitions. [2023-11-26 12:01:18,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2460 states and 3626 transitions. [2023-11-26 12:01:18,400 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2304 [2023-11-26 12:01:18,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2460 states to 2460 states and 3626 transitions. [2023-11-26 12:01:18,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2460 [2023-11-26 12:01:18,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2460 [2023-11-26 12:01:18,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2460 states and 3626 transitions. [2023-11-26 12:01:18,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:18,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2460 states and 3626 transitions. [2023-11-26 12:01:18,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2460 states and 3626 transitions. [2023-11-26 12:01:18,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2460 to 2460. [2023-11-26 12:01:18,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2460 states, 2460 states have (on average 1.4739837398373983) internal successors, (3626), 2459 states have internal predecessors, (3626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:18,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2460 states to 2460 states and 3626 transitions. [2023-11-26 12:01:18,507 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2460 states and 3626 transitions. [2023-11-26 12:01:18,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:01:18,508 INFO L428 stractBuchiCegarLoop]: Abstraction has 2460 states and 3626 transitions. [2023-11-26 12:01:18,508 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 12:01:18,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2460 states and 3626 transitions. [2023-11-26 12:01:18,522 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2304 [2023-11-26 12:01:18,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:18,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:18,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:18,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:18,527 INFO L748 eck$LassoCheckResult]: Stem: 27404#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 27405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 28273#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28369#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 28359#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28360#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27571#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27315#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27316#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28241#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28242#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28223#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28224#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28265#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 27365#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27366#L1006 assume !(0 == ~M_E~0); 27217#L1006-2 assume !(0 == ~T1_E~0); 27218#L1011-1 assume !(0 == ~T2_E~0); 28296#L1016-1 assume !(0 == ~T3_E~0); 28318#L1021-1 assume !(0 == ~T4_E~0); 27091#L1026-1 assume !(0 == ~T5_E~0); 27092#L1031-1 assume !(0 == ~T6_E~0); 27991#L1036-1 assume !(0 == ~T7_E~0); 27988#L1041-1 assume !(0 == ~T8_E~0); 27989#L1046-1 assume !(0 == ~T9_E~0); 27395#L1051-1 assume !(0 == ~T10_E~0); 27396#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 28125#L1061-1 assume !(0 == ~E_2~0); 27319#L1066-1 assume !(0 == ~E_3~0); 27320#L1071-1 assume !(0 == ~E_4~0); 28100#L1076-1 assume !(0 == ~E_5~0); 27225#L1081-1 assume !(0 == ~E_6~0); 27226#L1086-1 assume !(0 == ~E_7~0); 27545#L1091-1 assume !(0 == ~E_8~0); 28284#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 28285#L1101-1 assume !(0 == ~E_10~0); 27617#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27618#L484 assume !(1 == ~m_pc~0); 27276#L484-2 is_master_triggered_~__retres1~0#1 := 0; 27275#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27901#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28195#L1245 assume !(0 != activate_threads_~tmp~1#1); 28196#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27978#L503 assume 1 == ~t1_pc~0; 27979#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27997#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27133#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27134#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 27129#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27130#L522 assume !(1 == ~t2_pc~0); 27941#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27330#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27612#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 28243#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28330#L541 assume 1 == ~t3_pc~0; 27883#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27684#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27075#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27076#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 27948#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27949#L560 assume !(1 == ~t4_pc~0); 27209#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27208#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27241#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27089#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 27090#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27376#L579 assume 1 == ~t5_pc~0; 27040#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27041#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27155#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28200#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 28316#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28347#L598 assume 1 == ~t6_pc~0; 27460#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27461#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27586#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27587#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 28026#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27969#L617 assume !(1 == ~t7_pc~0); 27436#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27435#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28373#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28256#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27651#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27652#L636 assume 1 == ~t8_pc~0; 27836#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27837#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28153#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28034#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 27783#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27784#L655 assume !(1 == ~t9_pc~0); 27811#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27812#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27694#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27695#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 28047#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28048#L674 assume 1 == ~t10_pc~0; 27202#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27203#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27826#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27827#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 27774#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27775#L1119 assume !(1 == ~M_E~0); 27302#L1119-2 assume !(1 == ~T1_E~0); 27303#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27705#L1129-1 assume !(1 == ~T3_E~0); 27119#L1134-1 assume !(1 == ~T4_E~0); 28729#L1139-1 assume !(1 == ~T5_E~0); 28725#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28462#L1149-1 assume !(1 == ~T7_E~0); 28461#L1154-1 assume !(1 == ~T8_E~0); 28459#L1159-1 assume !(1 == ~T9_E~0); 28457#L1164-1 assume !(1 == ~T10_E~0); 28456#L1169-1 assume !(1 == ~E_1~0); 28452#L1174-1 assume !(1 == ~E_2~0); 28450#L1179-1 assume !(1 == ~E_3~0); 28448#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28447#L1189-1 assume !(1 == ~E_5~0); 28435#L1194-1 assume !(1 == ~E_6~0); 28433#L1199-1 assume !(1 == ~E_7~0); 28431#L1204-1 assume !(1 == ~E_8~0); 28429#L1209-1 assume !(1 == ~E_9~0); 28427#L1214-1 assume !(1 == ~E_10~0); 28414#L1219-1 assume { :end_inline_reset_delta_events } true; 28410#L1520-2 [2023-11-26 12:01:18,527 INFO L750 eck$LassoCheckResult]: Loop: 28410#L1520-2 assume !false; 28406#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28404#L981-1 assume !false; 28403#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28394#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28391#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28390#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28389#L836 assume !(0 != eval_~tmp~0#1); 28388#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28387#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28386#L1006-3 assume !(0 == ~M_E~0); 28385#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28384#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28293#L1016-3 assume !(0 == ~T3_E~0); 28188#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27853#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27854#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28117#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28118#L1041-3 assume !(0 == ~T8_E~0); 28180#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28181#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28119#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27392#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27393#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27394#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28300#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27184#L1081-3 assume !(0 == ~E_6~0); 27185#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29088#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29086#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29084#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29082#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29081#L484-33 assume 1 == ~m_pc~0; 29079#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29076#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29074#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29072#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 29070#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29068#L503-33 assume 1 == ~t1_pc~0; 29065#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29064#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29063#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29062#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29059#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29057#L522-33 assume 1 == ~t2_pc~0; 29054#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29052#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29050#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29048#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29045#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29043#L541-33 assume !(1 == ~t3_pc~0); 29040#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 29037#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29035#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29032#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29030#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29028#L560-33 assume !(1 == ~t4_pc~0); 29025#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 29023#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29021#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29018#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29016#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29014#L579-33 assume 1 == ~t5_pc~0; 29011#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28324#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28325#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27970#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27971#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28002#L598-33 assume !(1 == ~t6_pc~0); 28994#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 28992#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28990#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28988#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28986#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28983#L617-33 assume 1 == ~t7_pc~0; 28980#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28978#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28976#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28974#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28972#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28969#L636-33 assume !(1 == ~t8_pc~0); 28966#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 28964#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28962#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28960#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28958#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28956#L655-33 assume 1 == ~t9_pc~0; 28953#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28952#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28951#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28949#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 28947#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28945#L674-33 assume 1 == ~t10_pc~0; 28942#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28940#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28938#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28936#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28934#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28932#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28930#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28928#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28382#L1129-3 assume !(1 == ~T3_E~0); 28364#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28925#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28924#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28923#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28922#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28921#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28920#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28919#L1169-3 assume !(1 == ~E_1~0); 28917#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28343#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28218#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27210#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27211#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27500#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27501#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27828#L1209-3 assume !(1 == ~E_9~0); 27097#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27098#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28036#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 27187#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 28723#L1539 assume !(0 == start_simulation_~tmp~3#1); 28719#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28446#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28434#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28432#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 28430#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28428#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28426#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 28413#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 28410#L1520-2 [2023-11-26 12:01:18,528 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:18,529 INFO L85 PathProgramCache]: Analyzing trace with hash -388783629, now seen corresponding path program 1 times [2023-11-26 12:01:18,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:18,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757508119] [2023-11-26 12:01:18,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:18,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:18,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:18,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:18,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:18,625 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757508119] [2023-11-26 12:01:18,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [757508119] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:18,626 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:18,626 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:18,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [444071458] [2023-11-26 12:01:18,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:18,627 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:18,627 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:18,628 INFO L85 PathProgramCache]: Analyzing trace with hash -876991093, now seen corresponding path program 1 times [2023-11-26 12:01:18,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:18,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450096114] [2023-11-26 12:01:18,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:18,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:18,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:18,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:18,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:18,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450096114] [2023-11-26 12:01:18,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450096114] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:18,714 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:18,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:18,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521594804] [2023-11-26 12:01:18,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:18,715 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:18,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:18,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:01:18,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:01:18,717 INFO L87 Difference]: Start difference. First operand 2460 states and 3626 transitions. cyclomatic complexity: 1168 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:18,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:18,996 INFO L93 Difference]: Finished difference Result 4636 states and 6829 transitions. [2023-11-26 12:01:18,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4636 states and 6829 transitions. [2023-11-26 12:01:19,059 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4448 [2023-11-26 12:01:19,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4636 states to 4636 states and 6829 transitions. [2023-11-26 12:01:19,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4636 [2023-11-26 12:01:19,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4636 [2023-11-26 12:01:19,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4636 states and 6829 transitions. [2023-11-26 12:01:19,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:19,121 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4636 states and 6829 transitions. [2023-11-26 12:01:19,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4636 states and 6829 transitions. [2023-11-26 12:01:19,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4636 to 4632. [2023-11-26 12:01:19,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4632 states, 4632 states have (on average 1.4734455958549222) internal successors, (6825), 4631 states have internal predecessors, (6825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:19,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4632 states to 4632 states and 6825 transitions. [2023-11-26 12:01:19,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4632 states and 6825 transitions. [2023-11-26 12:01:19,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:01:19,268 INFO L428 stractBuchiCegarLoop]: Abstraction has 4632 states and 6825 transitions. [2023-11-26 12:01:19,269 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 12:01:19,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4632 states and 6825 transitions. [2023-11-26 12:01:19,297 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4448 [2023-11-26 12:01:19,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:19,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:19,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:19,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:19,302 INFO L748 eck$LassoCheckResult]: Stem: 34509#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 34510#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 35379#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35380#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35455#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 35448#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35449#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34676#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34420#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34421#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35347#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35348#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35329#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35330#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35371#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34472#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34473#L1006 assume !(0 == ~M_E~0); 34322#L1006-2 assume !(0 == ~T1_E~0); 34323#L1011-1 assume !(0 == ~T2_E~0); 35396#L1016-1 assume !(0 == ~T3_E~0); 35415#L1021-1 assume !(0 == ~T4_E~0); 34199#L1026-1 assume !(0 == ~T5_E~0); 34200#L1031-1 assume !(0 == ~T6_E~0); 35097#L1036-1 assume !(0 == ~T7_E~0); 35094#L1041-1 assume !(0 == ~T8_E~0); 35095#L1046-1 assume !(0 == ~T9_E~0); 34500#L1051-1 assume !(0 == ~T10_E~0); 34501#L1056-1 assume !(0 == ~E_1~0); 35229#L1061-1 assume !(0 == ~E_2~0); 34424#L1066-1 assume !(0 == ~E_3~0); 34425#L1071-1 assume !(0 == ~E_4~0); 35203#L1076-1 assume !(0 == ~E_5~0); 34330#L1081-1 assume !(0 == ~E_6~0); 34331#L1086-1 assume !(0 == ~E_7~0); 34650#L1091-1 assume !(0 == ~E_8~0); 35388#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 35389#L1101-1 assume !(0 == ~E_10~0); 34721#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34722#L484 assume !(1 == ~m_pc~0); 34381#L484-2 is_master_triggered_~__retres1~0#1 := 0; 34380#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35008#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35297#L1245 assume !(0 != activate_threads_~tmp~1#1); 35298#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35084#L503 assume 1 == ~t1_pc~0; 35085#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35103#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34240#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34241#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 34234#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34235#L522 assume !(1 == ~t2_pc~0); 35047#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34435#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34436#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34716#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 35349#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35424#L541 assume 1 == ~t3_pc~0; 34990#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34789#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34181#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34182#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 35053#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35054#L560 assume !(1 == ~t4_pc~0); 34316#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34315#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34346#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34195#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 34196#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34481#L579 assume 1 == ~t5_pc~0; 34146#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34147#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34260#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35302#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 35413#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35438#L598 assume 1 == ~t6_pc~0; 34565#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34566#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34691#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34692#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 35132#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35075#L617 assume !(1 == ~t7_pc~0); 34541#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34540#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35459#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35361#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34756#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34757#L636 assume 1 == ~t8_pc~0; 34943#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34944#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35257#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35142#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 34888#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34889#L655 assume !(1 == ~t9_pc~0); 34919#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 34920#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34803#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34804#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 35153#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35154#L674 assume 1 == ~t10_pc~0; 34307#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34308#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34934#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34935#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 34879#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34880#L1119 assume !(1 == ~M_E~0); 34407#L1119-2 assume !(1 == ~T1_E~0); 34408#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34224#L1129-1 assume !(1 == ~T3_E~0); 34225#L1134-1 assume !(1 == ~T4_E~0); 35064#L1139-1 assume !(1 == ~T5_E~0); 34751#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34752#L1149-1 assume !(1 == ~T7_E~0); 34401#L1154-1 assume !(1 == ~T8_E~0); 34402#L1159-1 assume !(1 == ~T9_E~0); 34484#L1164-1 assume !(1 == ~T10_E~0); 35563#L1169-1 assume !(1 == ~E_1~0); 35559#L1174-1 assume !(1 == ~E_2~0); 35558#L1179-1 assume !(1 == ~E_3~0); 35556#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 35554#L1189-1 assume !(1 == ~E_5~0); 35552#L1194-1 assume !(1 == ~E_6~0); 35551#L1199-1 assume !(1 == ~E_7~0); 35533#L1204-1 assume !(1 == ~E_8~0); 35521#L1209-1 assume !(1 == ~E_9~0); 35512#L1214-1 assume !(1 == ~E_10~0); 35504#L1219-1 assume { :end_inline_reset_delta_events } true; 35498#L1520-2 [2023-11-26 12:01:19,303 INFO L750 eck$LassoCheckResult]: Loop: 35498#L1520-2 assume !false; 35493#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35491#L981-1 assume !false; 35490#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35481#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35478#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35477#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35475#L836 assume !(0 != eval_~tmp~0#1); 35474#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35473#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35472#L1006-3 assume !(0 == ~M_E~0); 35471#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35469#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35470#L1016-3 assume !(0 == ~T3_E~0); 36980#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36943#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36851#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36849#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36847#L1041-3 assume !(0 == ~T8_E~0); 36845#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36843#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36841#L1056-3 assume !(0 == ~E_1~0); 36839#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36837#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36832#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36826#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36820#L1081-3 assume !(0 == ~E_6~0); 36815#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36810#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36805#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36799#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36793#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36787#L484-33 assume 1 == ~m_pc~0; 36781#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 36776#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36772#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36767#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 36761#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36757#L503-33 assume 1 == ~t1_pc~0; 36752#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36748#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36743#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36736#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36729#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36724#L522-33 assume 1 == ~t2_pc~0; 36718#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36713#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36708#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36701#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36694#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36689#L541-33 assume 1 == ~t3_pc~0; 36683#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36678#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36673#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36666#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36659#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36654#L560-33 assume !(1 == ~t4_pc~0); 36648#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 36644#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36640#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36634#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36269#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36266#L579-33 assume 1 == ~t5_pc~0; 36263#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36261#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36259#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36257#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36255#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36252#L598-33 assume !(1 == ~t6_pc~0); 36249#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 36247#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36245#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36243#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36241#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36238#L617-33 assume 1 == ~t7_pc~0; 36208#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36206#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36203#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36201#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36198#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36196#L636-33 assume !(1 == ~t8_pc~0); 36193#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 36191#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36190#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35938#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35936#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35933#L655-33 assume 1 == ~t9_pc~0; 35929#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35927#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35925#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35923#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 35920#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35918#L674-33 assume 1 == ~t10_pc~0; 35913#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35911#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35908#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35684#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35681#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35677#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35673#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35669#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35467#L1129-3 assume !(1 == ~T3_E~0); 35662#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35659#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35656#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35653#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35650#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35647#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35643#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35639#L1169-3 assume !(1 == ~E_1~0); 35637#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35635#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35633#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35631#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35628#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35626#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35625#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35623#L1209-3 assume !(1 == ~E_9~0); 35621#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35619#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35617#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35605#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35603#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 35600#L1539 assume !(0 == start_simulation_~tmp~3#1); 35598#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35597#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35584#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35550#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 35532#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35520#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35511#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 35503#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 35498#L1520-2 [2023-11-26 12:01:19,304 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:19,304 INFO L85 PathProgramCache]: Analyzing trace with hash 642257269, now seen corresponding path program 1 times [2023-11-26 12:01:19,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:19,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317715734] [2023-11-26 12:01:19,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:19,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:19,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:19,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:19,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:19,453 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317715734] [2023-11-26 12:01:19,454 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317715734] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:19,454 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:19,454 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:19,454 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [801136454] [2023-11-26 12:01:19,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:19,455 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:19,456 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:19,456 INFO L85 PathProgramCache]: Analyzing trace with hash -539525330, now seen corresponding path program 1 times [2023-11-26 12:01:19,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:19,457 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904511742] [2023-11-26 12:01:19,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:19,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:19,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:19,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:19,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:19,529 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904511742] [2023-11-26 12:01:19,529 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904511742] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:19,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:19,530 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:19,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523670898] [2023-11-26 12:01:19,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:19,531 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:19,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:19,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:01:19,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:01:19,532 INFO L87 Difference]: Start difference. First operand 4632 states and 6825 transitions. cyclomatic complexity: 2197 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:19,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:19,800 INFO L93 Difference]: Finished difference Result 8784 states and 12922 transitions. [2023-11-26 12:01:19,800 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8784 states and 12922 transitions. [2023-11-26 12:01:19,863 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8580 [2023-11-26 12:01:19,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8784 states to 8784 states and 12922 transitions. [2023-11-26 12:01:19,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8784 [2023-11-26 12:01:19,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8784 [2023-11-26 12:01:19,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8784 states and 12922 transitions. [2023-11-26 12:01:19,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:19,953 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8784 states and 12922 transitions. [2023-11-26 12:01:19,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8784 states and 12922 transitions. [2023-11-26 12:01:20,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8784 to 8780. [2023-11-26 12:01:20,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8780 states, 8780 states have (on average 1.4712984054669704) internal successors, (12918), 8779 states have internal predecessors, (12918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:20,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8780 states to 8780 states and 12918 transitions. [2023-11-26 12:01:20,312 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8780 states and 12918 transitions. [2023-11-26 12:01:20,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:01:20,313 INFO L428 stractBuchiCegarLoop]: Abstraction has 8780 states and 12918 transitions. [2023-11-26 12:01:20,313 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 12:01:20,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8780 states and 12918 transitions. [2023-11-26 12:01:20,360 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8580 [2023-11-26 12:01:20,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:20,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:20,364 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:20,364 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:20,364 INFO L748 eck$LassoCheckResult]: Stem: 47932#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 47933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 48803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48804#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48883#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 48875#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48876#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48100#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47844#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47845#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48771#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48772#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48753#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48754#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48795#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47893#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47894#L1006 assume !(0 == ~M_E~0); 47747#L1006-2 assume !(0 == ~T1_E~0); 47748#L1011-1 assume !(0 == ~T2_E~0); 48822#L1016-1 assume !(0 == ~T3_E~0); 48841#L1021-1 assume !(0 == ~T4_E~0); 47623#L1026-1 assume !(0 == ~T5_E~0); 47624#L1031-1 assume !(0 == ~T6_E~0); 48524#L1036-1 assume !(0 == ~T7_E~0); 48521#L1041-1 assume !(0 == ~T8_E~0); 48522#L1046-1 assume !(0 == ~T9_E~0); 47923#L1051-1 assume !(0 == ~T10_E~0); 47924#L1056-1 assume !(0 == ~E_1~0); 48653#L1061-1 assume !(0 == ~E_2~0); 47848#L1066-1 assume !(0 == ~E_3~0); 47849#L1071-1 assume !(0 == ~E_4~0); 48628#L1076-1 assume !(0 == ~E_5~0); 47755#L1081-1 assume !(0 == ~E_6~0); 47756#L1086-1 assume !(0 == ~E_7~0); 48074#L1091-1 assume !(0 == ~E_8~0); 48811#L1096-1 assume !(0 == ~E_9~0); 48812#L1101-1 assume !(0 == ~E_10~0); 48146#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48147#L484 assume !(1 == ~m_pc~0); 47805#L484-2 is_master_triggered_~__retres1~0#1 := 0; 47804#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48434#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48725#L1245 assume !(0 != activate_threads_~tmp~1#1); 48726#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48511#L503 assume 1 == ~t1_pc~0; 48512#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48530#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47664#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47665#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 47660#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47661#L522 assume !(1 == ~t2_pc~0); 48474#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47859#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48140#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 48773#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48850#L541 assume 1 == ~t3_pc~0; 48416#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48213#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47607#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47608#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 48480#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48481#L560 assume !(1 == ~t4_pc~0); 47739#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47738#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47771#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47621#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 47622#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47904#L579 assume 1 == ~t5_pc~0; 47572#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47573#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47686#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48730#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 48839#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48860#L598 assume 1 == ~t6_pc~0; 47989#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47990#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48115#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48116#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 48558#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48502#L617 assume !(1 == ~t7_pc~0); 47965#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 47964#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48887#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48786#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48180#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48181#L636 assume 1 == ~t8_pc~0; 48368#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48369#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48685#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48567#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 48312#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48313#L655 assume !(1 == ~t9_pc~0); 48341#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 48342#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48223#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48224#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 48579#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48580#L674 assume 1 == ~t10_pc~0; 47732#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47733#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48356#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48357#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 48303#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48304#L1119 assume !(1 == ~M_E~0); 47831#L1119-2 assume !(1 == ~T1_E~0); 47832#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47650#L1129-1 assume !(1 == ~T3_E~0); 47651#L1134-1 assume !(1 == ~T4_E~0); 47948#L1139-1 assume !(1 == ~T5_E~0); 47949#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48176#L1149-1 assume !(1 == ~T7_E~0); 47825#L1154-1 assume !(1 == ~T8_E~0); 47826#L1159-1 assume !(1 == ~T9_E~0); 47907#L1164-1 assume !(1 == ~T10_E~0); 48889#L1169-1 assume !(1 == ~E_1~0); 49018#L1174-1 assume !(1 == ~E_2~0); 48972#L1179-1 assume !(1 == ~E_3~0); 48970#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 48968#L1189-1 assume !(1 == ~E_5~0); 48967#L1194-1 assume !(1 == ~E_6~0); 48965#L1199-1 assume !(1 == ~E_7~0); 48963#L1204-1 assume !(1 == ~E_8~0); 48949#L1209-1 assume !(1 == ~E_9~0); 48938#L1214-1 assume !(1 == ~E_10~0); 48930#L1219-1 assume { :end_inline_reset_delta_events } true; 48924#L1520-2 [2023-11-26 12:01:20,365 INFO L750 eck$LassoCheckResult]: Loop: 48924#L1520-2 assume !false; 48919#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48917#L981-1 assume !false; 48916#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48907#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48904#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48903#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 48901#L836 assume !(0 != eval_~tmp~0#1); 48900#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48899#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48898#L1006-3 assume !(0 == ~M_E~0); 48897#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48895#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48896#L1016-3 assume !(0 == ~T3_E~0); 49813#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49804#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49797#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49790#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49781#L1041-3 assume !(0 == ~T8_E~0); 49774#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49766#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49758#L1056-3 assume !(0 == ~E_1~0); 49751#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49744#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49734#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49727#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49719#L1081-3 assume !(0 == ~E_6~0); 49710#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49703#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49696#L1096-3 assume !(0 == ~E_9~0); 49686#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49679#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49671#L484-33 assume 1 == ~m_pc~0; 49661#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49654#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49647#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49637#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 49630#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49622#L503-33 assume 1 == ~t1_pc~0; 49612#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49605#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49598#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49588#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49581#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49573#L522-33 assume 1 == ~t2_pc~0; 49563#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49556#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49549#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49539#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49532#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49524#L541-33 assume 1 == ~t3_pc~0; 49514#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49507#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49501#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49456#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49454#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49452#L560-33 assume !(1 == ~t4_pc~0); 49449#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 49447#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49444#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49442#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49440#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49438#L579-33 assume 1 == ~t5_pc~0; 49433#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49431#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49429#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49427#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49425#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49422#L598-33 assume !(1 == ~t6_pc~0); 49419#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 49417#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49415#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49413#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49411#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49410#L617-33 assume 1 == ~t7_pc~0; 49406#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49404#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49402#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49400#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49398#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49396#L636-33 assume !(1 == ~t8_pc~0); 49394#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 49391#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49389#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49387#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49385#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49383#L655-33 assume 1 == ~t9_pc~0; 49379#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49377#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49375#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49373#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 49371#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49368#L674-33 assume 1 == ~t10_pc~0; 49342#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49335#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49328#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49321#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49314#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49307#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49300#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49293#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48893#L1129-3 assume !(1 == ~T3_E~0); 49282#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49278#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49273#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49267#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49262#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49257#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49252#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49246#L1169-3 assume !(1 == ~E_1~0); 49243#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49239#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49236#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49233#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49230#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49227#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49224#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49219#L1209-3 assume !(1 == ~E_9~0); 49217#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49215#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 49211#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 49198#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 49196#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 49194#L1539 assume !(0 == start_simulation_~tmp~3#1); 49191#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48991#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48977#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48975#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 48961#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48946#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48937#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 48929#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 48924#L1520-2 [2023-11-26 12:01:20,366 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:20,366 INFO L85 PathProgramCache]: Analyzing trace with hash -1298324745, now seen corresponding path program 1 times [2023-11-26 12:01:20,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:20,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040771137] [2023-11-26 12:01:20,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:20,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:20,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:20,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:20,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:20,565 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040771137] [2023-11-26 12:01:20,565 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040771137] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:20,565 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:20,565 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:01:20,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824593931] [2023-11-26 12:01:20,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:20,566 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:20,567 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:20,567 INFO L85 PathProgramCache]: Analyzing trace with hash 1722047920, now seen corresponding path program 1 times [2023-11-26 12:01:20,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:20,567 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322444840] [2023-11-26 12:01:20,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:20,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:20,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:20,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:20,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:20,634 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1322444840] [2023-11-26 12:01:20,634 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1322444840] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:20,634 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:20,634 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:20,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715136909] [2023-11-26 12:01:20,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:20,635 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:20,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:20,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:20,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:20,637 INFO L87 Difference]: Start difference. First operand 8780 states and 12918 transitions. cyclomatic complexity: 4146 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:20,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:20,815 INFO L93 Difference]: Finished difference Result 16639 states and 24352 transitions. [2023-11-26 12:01:20,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16639 states and 24352 transitions. [2023-11-26 12:01:20,902 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16424 [2023-11-26 12:01:21,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16639 states to 16639 states and 24352 transitions. [2023-11-26 12:01:21,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16639 [2023-11-26 12:01:21,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16639 [2023-11-26 12:01:21,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16639 states and 24352 transitions. [2023-11-26 12:01:21,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:21,080 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16639 states and 24352 transitions. [2023-11-26 12:01:21,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16639 states and 24352 transitions. [2023-11-26 12:01:21,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16639 to 16623. [2023-11-26 12:01:21,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16623 states, 16623 states have (on average 1.4639956686518678) internal successors, (24336), 16622 states have internal predecessors, (24336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:21,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16623 states to 16623 states and 24336 transitions. [2023-11-26 12:01:21,506 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16623 states and 24336 transitions. [2023-11-26 12:01:21,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:21,507 INFO L428 stractBuchiCegarLoop]: Abstraction has 16623 states and 24336 transitions. [2023-11-26 12:01:21,507 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 12:01:21,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16623 states and 24336 transitions. [2023-11-26 12:01:21,590 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16408 [2023-11-26 12:01:21,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:21,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:21,594 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:21,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:21,595 INFO L748 eck$LassoCheckResult]: Stem: 73361#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 73362#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 74253#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74254#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74357#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 74347#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74348#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73530#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73271#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73272#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74218#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74219#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 74199#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 74200#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 74245#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 73323#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73324#L1006 assume !(0 == ~M_E~0); 73174#L1006-2 assume !(0 == ~T1_E~0); 73175#L1011-1 assume !(0 == ~T2_E~0); 74273#L1016-1 assume !(0 == ~T3_E~0); 74292#L1021-1 assume !(0 == ~T4_E~0); 73051#L1026-1 assume !(0 == ~T5_E~0); 73052#L1031-1 assume !(0 == ~T6_E~0); 73952#L1036-1 assume !(0 == ~T7_E~0); 73948#L1041-1 assume !(0 == ~T8_E~0); 73949#L1046-1 assume !(0 == ~T9_E~0); 73352#L1051-1 assume !(0 == ~T10_E~0); 73353#L1056-1 assume !(0 == ~E_1~0); 74086#L1061-1 assume !(0 == ~E_2~0); 73275#L1066-1 assume !(0 == ~E_3~0); 73276#L1071-1 assume !(0 == ~E_4~0); 74061#L1076-1 assume !(0 == ~E_5~0); 73181#L1081-1 assume !(0 == ~E_6~0); 73182#L1086-1 assume !(0 == ~E_7~0); 73502#L1091-1 assume !(0 == ~E_8~0); 74264#L1096-1 assume !(0 == ~E_9~0); 74265#L1101-1 assume !(0 == ~E_10~0); 73573#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73574#L484 assume !(1 == ~m_pc~0); 73232#L484-2 is_master_triggered_~__retres1~0#1 := 0; 73231#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73862#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 74170#L1245 assume !(0 != activate_threads_~tmp~1#1); 74171#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73939#L503 assume !(1 == ~t1_pc~0); 73940#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74121#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73092#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 73093#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 73086#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73087#L522 assume !(1 == ~t2_pc~0); 73901#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 73286#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73287#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73568#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 74220#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74304#L541 assume 1 == ~t3_pc~0; 73843#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 73640#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73035#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73036#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 73907#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73908#L560 assume !(1 == ~t4_pc~0); 73168#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 73167#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73197#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73047#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 73048#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73332#L579 assume 1 == ~t5_pc~0; 72998#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 72999#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73112#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74175#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 74291#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74328#L598 assume 1 == ~t6_pc~0; 73416#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73417#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73545#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73546#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 73986#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73930#L617 assume !(1 == ~t7_pc~0); 73392#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 73391#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 74365#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74235#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 73608#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73609#L636 assume 1 == ~t8_pc~0; 73792#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 73793#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74122#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 73995#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 73738#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 73739#L655 assume !(1 == ~t9_pc~0); 73769#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 73770#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73654#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 73655#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 74005#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74006#L674 assume 1 == ~t10_pc~0; 73159#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 73160#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 73783#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 73784#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 73729#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73730#L1119 assume !(1 == ~M_E~0); 73258#L1119-2 assume !(1 == ~T1_E~0); 73259#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73076#L1129-1 assume !(1 == ~T3_E~0); 73077#L1134-1 assume !(1 == ~T4_E~0); 84233#L1139-1 assume !(1 == ~T5_E~0); 84231#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84229#L1149-1 assume !(1 == ~T7_E~0); 84227#L1154-1 assume !(1 == ~T8_E~0); 73335#L1159-1 assume !(1 == ~T9_E~0); 73336#L1164-1 assume !(1 == ~T10_E~0); 73757#L1169-1 assume !(1 == ~E_1~0); 73758#L1174-1 assume !(1 == ~E_2~0); 86381#L1179-1 assume !(1 == ~E_3~0); 86379#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 86377#L1189-1 assume !(1 == ~E_5~0); 86375#L1194-1 assume !(1 == ~E_6~0); 86372#L1199-1 assume !(1 == ~E_7~0); 86370#L1204-1 assume !(1 == ~E_8~0); 86252#L1209-1 assume !(1 == ~E_9~0); 86240#L1214-1 assume !(1 == ~E_10~0); 86230#L1219-1 assume { :end_inline_reset_delta_events } true; 86223#L1520-2 [2023-11-26 12:01:21,596 INFO L750 eck$LassoCheckResult]: Loop: 86223#L1520-2 assume !false; 86217#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86214#L981-1 assume !false; 86213#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 86203#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 86198#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 86196#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 86193#L836 assume !(0 != eval_~tmp~0#1); 86194#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88270#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 88268#L1006-3 assume !(0 == ~M_E~0); 88266#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 88264#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88261#L1016-3 assume !(0 == ~T3_E~0); 88259#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 88257#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88255#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88253#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88251#L1041-3 assume !(0 == ~T8_E~0); 88248#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 88246#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88244#L1056-3 assume !(0 == ~E_1~0); 88242#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88240#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88238#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 88235#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88233#L1081-3 assume !(0 == ~E_6~0); 88231#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 88229#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 88227#L1096-3 assume !(0 == ~E_9~0); 88225#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 88222#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88220#L484-33 assume 1 == ~m_pc~0; 88217#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 88215#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88213#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88212#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 88211#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88208#L503-33 assume !(1 == ~t1_pc~0); 88206#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 88204#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88203#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88175#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88167#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88145#L522-33 assume !(1 == ~t2_pc~0); 87121#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 87116#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87114#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87112#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87111#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87108#L541-33 assume !(1 == ~t3_pc~0); 87104#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 87099#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87095#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87091#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87087#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87082#L560-33 assume !(1 == ~t4_pc~0); 87079#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 87077#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87076#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87075#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87074#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87073#L579-33 assume !(1 == ~t5_pc~0); 87072#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 87070#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87069#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87068#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87067#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87066#L598-33 assume 1 == ~t6_pc~0; 87065#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 87052#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87050#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87048#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87045#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87043#L617-33 assume !(1 == ~t7_pc~0); 87041#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 87038#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87036#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87034#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 87032#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87030#L636-33 assume !(1 == ~t8_pc~0); 87027#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 87025#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87023#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87021#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 87019#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87017#L655-33 assume !(1 == ~t9_pc~0); 87015#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 87012#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87010#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87008#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 87006#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87004#L674-33 assume 1 == ~t10_pc~0; 87001#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 86999#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86997#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86995#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86993#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86991#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 86988#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86986#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 74373#L1129-3 assume !(1 == ~T3_E~0); 74352#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86982#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86980#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 86978#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86976#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86974#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86972#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86970#L1169-3 assume !(1 == ~E_1~0); 83080#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86966#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86964#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86962#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86960#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86958#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86956#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86732#L1209-3 assume !(1 == ~E_9~0); 86730#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86728#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 86726#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 86714#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 86712#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 86708#L1539 assume !(0 == start_simulation_~tmp~3#1); 86705#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 86703#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 86689#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 86685#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 86350#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86249#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86239#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 86229#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 86223#L1520-2 [2023-11-26 12:01:21,596 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:21,597 INFO L85 PathProgramCache]: Analyzing trace with hash 1011813846, now seen corresponding path program 1 times [2023-11-26 12:01:21,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:21,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [769655816] [2023-11-26 12:01:21,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:21,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:21,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:21,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:21,702 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:21,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [769655816] [2023-11-26 12:01:21,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [769655816] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:21,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:21,703 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:01:21,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593532551] [2023-11-26 12:01:21,703 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:21,704 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:21,705 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:21,705 INFO L85 PathProgramCache]: Analyzing trace with hash -1035405429, now seen corresponding path program 1 times [2023-11-26 12:01:21,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:21,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498834784] [2023-11-26 12:01:21,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:21,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:21,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:21,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:21,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:21,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498834784] [2023-11-26 12:01:21,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1498834784] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:21,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:21,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:01:21,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383327161] [2023-11-26 12:01:21,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:21,824 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:21,825 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:21,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:21,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:21,826 INFO L87 Difference]: Start difference. First operand 16623 states and 24336 transitions. cyclomatic complexity: 7729 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:22,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:22,200 INFO L93 Difference]: Finished difference Result 31606 states and 46055 transitions. [2023-11-26 12:01:22,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31606 states and 46055 transitions. [2023-11-26 12:01:22,381 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31360 [2023-11-26 12:01:22,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31606 states to 31606 states and 46055 transitions. [2023-11-26 12:01:22,513 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31606 [2023-11-26 12:01:22,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31606 [2023-11-26 12:01:22,561 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31606 states and 46055 transitions. [2023-11-26 12:01:22,613 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:22,613 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31606 states and 46055 transitions. [2023-11-26 12:01:22,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31606 states and 46055 transitions. [2023-11-26 12:01:23,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31606 to 31574. [2023-11-26 12:01:23,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31574 states, 31574 states have (on average 1.4576233609932223) internal successors, (46023), 31573 states have internal predecessors, (46023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:23,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31574 states to 31574 states and 46023 transitions. [2023-11-26 12:01:23,470 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31574 states and 46023 transitions. [2023-11-26 12:01:23,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:23,471 INFO L428 stractBuchiCegarLoop]: Abstraction has 31574 states and 46023 transitions. [2023-11-26 12:01:23,472 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 12:01:23,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31574 states and 46023 transitions. [2023-11-26 12:01:23,594 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31328 [2023-11-26 12:01:23,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:23,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:23,597 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:23,598 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:23,598 INFO L748 eck$LassoCheckResult]: Stem: 121598#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 121599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 122507#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122508#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122614#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 122606#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122607#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 121767#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121509#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121510#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122467#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 122468#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122447#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 122448#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 122497#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 121559#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 121560#L1006 assume !(0 == ~M_E~0); 121411#L1006-2 assume !(0 == ~T1_E~0); 121412#L1011-1 assume !(0 == ~T2_E~0); 122533#L1016-1 assume !(0 == ~T3_E~0); 122556#L1021-1 assume !(0 == ~T4_E~0); 121287#L1026-1 assume !(0 == ~T5_E~0); 121288#L1031-1 assume !(0 == ~T6_E~0); 122190#L1036-1 assume !(0 == ~T7_E~0); 122187#L1041-1 assume !(0 == ~T8_E~0); 122188#L1046-1 assume !(0 == ~T9_E~0); 121589#L1051-1 assume !(0 == ~T10_E~0); 121590#L1056-1 assume !(0 == ~E_1~0); 122331#L1061-1 assume !(0 == ~E_2~0); 121513#L1066-1 assume !(0 == ~E_3~0); 121514#L1071-1 assume !(0 == ~E_4~0); 122306#L1076-1 assume !(0 == ~E_5~0); 121419#L1081-1 assume !(0 == ~E_6~0); 121420#L1086-1 assume !(0 == ~E_7~0); 121741#L1091-1 assume !(0 == ~E_8~0); 122519#L1096-1 assume !(0 == ~E_9~0); 122520#L1101-1 assume !(0 == ~E_10~0); 121812#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121813#L484 assume !(1 == ~m_pc~0); 121469#L484-2 is_master_triggered_~__retres1~0#1 := 0; 121468#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122101#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 122412#L1245 assume !(0 != activate_threads_~tmp~1#1); 122413#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122178#L503 assume !(1 == ~t1_pc~0); 122179#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 122361#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121328#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121329#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 121324#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121325#L522 assume !(1 == ~t2_pc~0); 122141#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 121524#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121525#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 121807#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 122469#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122567#L541 assume !(1 == ~t3_pc~0); 121878#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 121879#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121271#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121272#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 122147#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122148#L560 assume !(1 == ~t4_pc~0); 121403#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 121402#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121435#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 121285#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 121286#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121570#L579 assume 1 == ~t5_pc~0; 121236#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 121237#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 121350#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 122417#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 122554#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122586#L598 assume 1 == ~t6_pc~0; 121653#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 121654#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121782#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 121783#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 122225#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122169#L617 assume !(1 == ~t7_pc~0); 121629#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 121628#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 122618#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 122482#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 121846#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 121847#L636 assume 1 == ~t8_pc~0; 122034#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 122035#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 122362#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122236#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 121979#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 121980#L655 assume !(1 == ~t9_pc~0); 122009#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 122010#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 121889#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121890#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 122249#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 122250#L674 assume 1 == ~t10_pc~0; 121396#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 121397#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 122024#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 122025#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 121970#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121971#L1119 assume !(1 == ~M_E~0); 121495#L1119-2 assume !(1 == ~T1_E~0); 121496#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121314#L1129-1 assume !(1 == ~T3_E~0); 121315#L1134-1 assume !(1 == ~T4_E~0); 131815#L1139-1 assume !(1 == ~T5_E~0); 131813#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 131811#L1149-1 assume !(1 == ~T7_E~0); 131809#L1154-1 assume !(1 == ~T8_E~0); 131807#L1159-1 assume !(1 == ~T9_E~0); 131805#L1164-1 assume !(1 == ~T10_E~0); 131802#L1169-1 assume !(1 == ~E_1~0); 131800#L1174-1 assume !(1 == ~E_2~0); 131798#L1179-1 assume !(1 == ~E_3~0); 131796#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 131794#L1189-1 assume !(1 == ~E_5~0); 131792#L1194-1 assume !(1 == ~E_6~0); 131789#L1199-1 assume !(1 == ~E_7~0); 131787#L1204-1 assume !(1 == ~E_8~0); 131048#L1209-1 assume !(1 == ~E_9~0); 131044#L1214-1 assume !(1 == ~E_10~0); 129090#L1219-1 assume { :end_inline_reset_delta_events } true; 128252#L1520-2 [2023-11-26 12:01:23,599 INFO L750 eck$LassoCheckResult]: Loop: 128252#L1520-2 assume !false; 127836#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 127834#L981-1 assume !false; 127833#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 127289#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 127285#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 126986#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 126983#L836 assume !(0 != eval_~tmp~0#1); 126984#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 134817#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 134816#L1006-3 assume !(0 == ~M_E~0); 134815#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 134814#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 134813#L1016-3 assume !(0 == ~T3_E~0); 134812#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 134811#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 134810#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 134809#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 134808#L1041-3 assume !(0 == ~T8_E~0); 134807#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 134806#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 134805#L1056-3 assume !(0 == ~E_1~0); 134804#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 134803#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 134801#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 134798#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 134796#L1081-3 assume !(0 == ~E_6~0); 134794#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 134792#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 134790#L1096-3 assume !(0 == ~E_9~0); 134788#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 134786#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134784#L484-33 assume !(1 == ~m_pc~0); 134782#L484-35 is_master_triggered_~__retres1~0#1 := 0; 134779#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134777#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 134775#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 134772#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134770#L503-33 assume !(1 == ~t1_pc~0); 134768#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 134766#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134764#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 134762#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 134760#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134758#L522-33 assume 1 == ~t2_pc~0; 134755#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 134753#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134751#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 134749#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 134746#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134744#L541-33 assume !(1 == ~t3_pc~0); 134742#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 134740#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134738#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134736#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 134733#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134731#L560-33 assume !(1 == ~t4_pc~0); 134728#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 134726#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134724#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 134722#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 134719#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134717#L579-33 assume 1 == ~t5_pc~0; 134714#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 134712#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 134710#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 134708#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 134705#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134703#L598-33 assume !(1 == ~t6_pc~0); 134700#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 134698#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 134696#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 134694#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 134691#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 134689#L617-33 assume 1 == ~t7_pc~0; 134686#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 134684#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 134682#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 134680#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 134677#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 134675#L636-33 assume !(1 == ~t8_pc~0); 134672#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 134670#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 134668#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 134666#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 134663#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 134661#L655-33 assume 1 == ~t9_pc~0; 134658#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 134656#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 134654#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 134653#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 134649#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 134647#L674-33 assume 1 == ~t10_pc~0; 134644#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 134643#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 134640#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 134636#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 134632#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134628#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 134624#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 134620#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 124268#L1129-3 assume !(1 == ~T3_E~0); 133510#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133224#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 133222#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 133219#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 133217#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 133215#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 133213#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 133205#L1169-3 assume !(1 == ~E_1~0); 132937#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 132935#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 132933#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 132931#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 132929#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 132926#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 132924#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 132548#L1209-3 assume !(1 == ~E_9~0); 132546#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 132545#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 131855#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 131096#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 131091#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 131087#L1539 assume !(0 == start_simulation_~tmp~3#1); 131084#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 131081#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 131070#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 131069#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 131068#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 129100#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129096#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 129089#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 128252#L1520-2 [2023-11-26 12:01:23,599 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:23,600 INFO L85 PathProgramCache]: Analyzing trace with hash 1918570293, now seen corresponding path program 1 times [2023-11-26 12:01:23,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:23,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770577021] [2023-11-26 12:01:23,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:23,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:23,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:23,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:23,684 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:23,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770577021] [2023-11-26 12:01:23,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770577021] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:23,685 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:23,685 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:01:23,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259599734] [2023-11-26 12:01:23,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:23,686 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:23,686 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:23,686 INFO L85 PathProgramCache]: Analyzing trace with hash -992842227, now seen corresponding path program 1 times [2023-11-26 12:01:23,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:23,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1871232300] [2023-11-26 12:01:23,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:23,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:23,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:23,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:23,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:23,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1871232300] [2023-11-26 12:01:23,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1871232300] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:23,747 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:23,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:23,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987887543] [2023-11-26 12:01:23,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:23,748 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:23,748 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:23,749 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:23,749 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:23,749 INFO L87 Difference]: Start difference. First operand 31574 states and 46023 transitions. cyclomatic complexity: 14481 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:24,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:24,365 INFO L93 Difference]: Finished difference Result 60133 states and 87304 transitions. [2023-11-26 12:01:24,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60133 states and 87304 transitions. [2023-11-26 12:01:24,929 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59776 [2023-11-26 12:01:25,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60133 states to 60133 states and 87304 transitions. [2023-11-26 12:01:25,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60133 [2023-11-26 12:01:25,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60133 [2023-11-26 12:01:25,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60133 states and 87304 transitions. [2023-11-26 12:01:25,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:25,376 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60133 states and 87304 transitions. [2023-11-26 12:01:25,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60133 states and 87304 transitions. [2023-11-26 12:01:26,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60133 to 60069. [2023-11-26 12:01:26,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60069 states, 60069 states have (on average 1.4523298207061879) internal successors, (87240), 60068 states have internal predecessors, (87240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:26,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60069 states to 60069 states and 87240 transitions. [2023-11-26 12:01:26,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60069 states and 87240 transitions. [2023-11-26 12:01:26,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:26,827 INFO L428 stractBuchiCegarLoop]: Abstraction has 60069 states and 87240 transitions. [2023-11-26 12:01:26,827 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 12:01:26,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60069 states and 87240 transitions. [2023-11-26 12:01:27,047 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59712 [2023-11-26 12:01:27,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:27,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:27,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:27,051 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:27,051 INFO L748 eck$LassoCheckResult]: Stem: 213312#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 213313#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 214245#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 214246#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 214358#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 214350#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 214351#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 213486#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 213221#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 213222#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 214206#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 214207#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 214180#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 214181#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 214237#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 213272#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 213273#L1006 assume !(0 == ~M_E~0); 213122#L1006-2 assume !(0 == ~T1_E~0); 213123#L1011-1 assume !(0 == ~T2_E~0); 214276#L1016-1 assume !(0 == ~T3_E~0); 214297#L1021-1 assume !(0 == ~T4_E~0); 212997#L1026-1 assume !(0 == ~T5_E~0); 212998#L1031-1 assume !(0 == ~T6_E~0); 213921#L1036-1 assume !(0 == ~T7_E~0); 213917#L1041-1 assume !(0 == ~T8_E~0); 213918#L1046-1 assume !(0 == ~T9_E~0); 213303#L1051-1 assume !(0 == ~T10_E~0); 213304#L1056-1 assume !(0 == ~E_1~0); 214062#L1061-1 assume !(0 == ~E_2~0); 213225#L1066-1 assume !(0 == ~E_3~0); 213226#L1071-1 assume !(0 == ~E_4~0); 214037#L1076-1 assume !(0 == ~E_5~0); 213130#L1081-1 assume !(0 == ~E_6~0); 213131#L1086-1 assume !(0 == ~E_7~0); 213460#L1091-1 assume !(0 == ~E_8~0); 214259#L1096-1 assume !(0 == ~E_9~0); 214260#L1101-1 assume !(0 == ~E_10~0); 213534#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 213535#L484 assume !(1 == ~m_pc~0); 213182#L484-2 is_master_triggered_~__retres1~0#1 := 0; 213181#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 213830#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 214146#L1245 assume !(0 != activate_threads_~tmp~1#1); 214147#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 213908#L503 assume !(1 == ~t1_pc~0); 213909#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 214095#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 213038#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 213039#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 213034#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213035#L522 assume !(1 == ~t2_pc~0); 213870#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 213238#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 213528#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 214208#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214309#L541 assume !(1 == ~t3_pc~0); 213600#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 213601#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 212981#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 212982#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 213876#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 213877#L560 assume !(1 == ~t4_pc~0); 213114#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 213113#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 213146#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 212995#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 212996#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 213283#L579 assume !(1 == ~t5_pc~0); 213284#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 213060#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 213061#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 214153#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 214295#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 214330#L598 assume 1 == ~t6_pc~0; 213372#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 213373#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213502#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 213503#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 213959#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 213899#L617 assume !(1 == ~t7_pc~0); 213348#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 213347#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 214364#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 214222#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 213568#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 213569#L636 assume 1 == ~t8_pc~0; 213757#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 213758#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 214096#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 213969#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 213703#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 213704#L655 assume !(1 == ~t9_pc~0); 213731#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 213732#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 213612#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 213613#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 213983#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 213984#L674 assume 1 == ~t10_pc~0; 213107#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 213108#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 213746#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 213747#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 213694#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 213695#L1119 assume !(1 == ~M_E~0); 213208#L1119-2 assume !(1 == ~T1_E~0); 213209#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 213024#L1129-1 assume !(1 == ~T3_E~0); 213025#L1134-1 assume !(1 == ~T4_E~0); 213331#L1139-1 assume !(1 == ~T5_E~0); 213332#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 213564#L1149-1 assume !(1 == ~T7_E~0); 213202#L1154-1 assume !(1 == ~T8_E~0); 213203#L1159-1 assume !(1 == ~T9_E~0); 242061#L1164-1 assume !(1 == ~T10_E~0); 213722#L1169-1 assume !(1 == ~E_1~0); 213618#L1174-1 assume !(1 == ~E_2~0); 213386#L1179-1 assume !(1 == ~E_3~0); 213276#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 213277#L1189-1 assume !(1 == ~E_5~0); 213328#L1194-1 assume !(1 == ~E_6~0); 213440#L1199-1 assume !(1 == ~E_7~0); 213398#L1204-1 assume !(1 == ~E_8~0); 213399#L1209-1 assume !(1 == ~E_9~0); 213980#L1214-1 assume !(1 == ~E_10~0); 213981#L1219-1 assume { :end_inline_reset_delta_events } true; 214370#L1520-2 [2023-11-26 12:01:27,052 INFO L750 eck$LassoCheckResult]: Loop: 214370#L1520-2 assume !false; 250651#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 250648#L981-1 assume !false; 250645#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 250621#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 250617#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 250614#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 250612#L836 assume !(0 != eval_~tmp~0#1); 250613#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 257052#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 257050#L1006-3 assume !(0 == ~M_E~0); 257047#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 257045#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 257043#L1016-3 assume !(0 == ~T3_E~0); 257041#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 257039#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 257037#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 257035#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 257033#L1041-3 assume !(0 == ~T8_E~0); 257032#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 257031#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 257029#L1056-3 assume !(0 == ~E_1~0); 257027#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 257025#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 257023#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 257021#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 257019#L1081-3 assume !(0 == ~E_6~0); 257017#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 257016#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 257014#L1096-3 assume !(0 == ~E_9~0); 257012#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 257010#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 257008#L484-33 assume !(1 == ~m_pc~0); 257006#L484-35 is_master_triggered_~__retres1~0#1 := 0; 257003#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 257001#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 257000#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 256999#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 256998#L503-33 assume !(1 == ~t1_pc~0); 256997#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 256996#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 256995#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 256994#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 256993#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 256992#L522-33 assume !(1 == ~t2_pc~0); 256991#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 256989#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 256988#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 256987#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 256986#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 256985#L541-33 assume !(1 == ~t3_pc~0); 256984#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 256983#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 256982#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 256981#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 256980#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 256979#L560-33 assume 1 == ~t4_pc~0; 256978#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 256976#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 256975#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 256974#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 256973#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 256972#L579-33 assume !(1 == ~t5_pc~0); 256970#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 256967#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 256965#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 256963#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 256961#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 256959#L598-33 assume 1 == ~t6_pc~0; 256957#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 256954#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 256952#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 256950#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 256948#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 256946#L617-33 assume !(1 == ~t7_pc~0); 256944#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 256940#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 256938#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 256936#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 256934#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 256932#L636-33 assume 1 == ~t8_pc~0; 256930#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 256927#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 256925#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 256923#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 256921#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 256919#L655-33 assume !(1 == ~t9_pc~0); 256917#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 256913#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 256911#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 256909#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 256907#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 256905#L674-33 assume !(1 == ~t10_pc~0); 256903#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 256900#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 256898#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 256896#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 256894#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 256892#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 256890#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 256887#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 243376#L1129-3 assume !(1 == ~T3_E~0); 248958#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 256883#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 256881#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 256879#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 256876#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 256874#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 256872#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 256870#L1169-3 assume !(1 == ~E_1~0); 255494#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 256867#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 256864#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 256862#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 256860#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 256858#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 256856#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 256854#L1209-3 assume !(1 == ~E_9~0); 256277#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 256850#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 256848#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 256836#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 256834#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 256831#L1539 assume !(0 == start_simulation_~tmp~3#1); 256827#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 256825#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 256813#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 256811#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 256809#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 256808#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 256804#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 256802#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 214370#L1520-2 [2023-11-26 12:01:27,053 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,053 INFO L85 PathProgramCache]: Analyzing trace with hash 776922900, now seen corresponding path program 1 times [2023-11-26 12:01:27,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1896879865] [2023-11-26 12:01:27,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:27,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:27,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:27,132 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1896879865] [2023-11-26 12:01:27,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1896879865] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:27,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:27,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:01:27,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131860101] [2023-11-26 12:01:27,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:27,134 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:27,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:27,135 INFO L85 PathProgramCache]: Analyzing trace with hash -1016020725, now seen corresponding path program 1 times [2023-11-26 12:01:27,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:27,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308505161] [2023-11-26 12:01:27,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:27,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:27,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:27,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:27,383 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:27,383 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308505161] [2023-11-26 12:01:27,384 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308505161] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:27,384 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:27,384 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:01:27,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726347612] [2023-11-26 12:01:27,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:27,385 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:27,385 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:27,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:27,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:27,386 INFO L87 Difference]: Start difference. First operand 60069 states and 87240 transitions. cyclomatic complexity: 27235 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:28,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:28,095 INFO L93 Difference]: Finished difference Result 114372 states and 165517 transitions. [2023-11-26 12:01:28,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114372 states and 165517 transitions. [2023-11-26 12:01:28,908 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 113728 [2023-11-26 12:01:29,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114372 states to 114372 states and 165517 transitions. [2023-11-26 12:01:29,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 114372 [2023-11-26 12:01:29,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 114372 [2023-11-26 12:01:29,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114372 states and 165517 transitions. [2023-11-26 12:01:29,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:29,794 INFO L218 hiAutomatonCegarLoop]: Abstraction has 114372 states and 165517 transitions. [2023-11-26 12:01:29,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114372 states and 165517 transitions. [2023-11-26 12:01:31,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114372 to 114244. [2023-11-26 12:01:31,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 114244 states, 114244 states have (on average 1.447682153986205) internal successors, (165389), 114243 states have internal predecessors, (165389), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:31,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114244 states to 114244 states and 165389 transitions. [2023-11-26 12:01:31,964 INFO L240 hiAutomatonCegarLoop]: Abstraction has 114244 states and 165389 transitions. [2023-11-26 12:01:31,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:31,965 INFO L428 stractBuchiCegarLoop]: Abstraction has 114244 states and 165389 transitions. [2023-11-26 12:01:31,966 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 12:01:31,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114244 states and 165389 transitions. [2023-11-26 12:01:32,786 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 113600 [2023-11-26 12:01:32,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:32,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:32,811 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:32,811 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:32,811 INFO L748 eck$LassoCheckResult]: Stem: 387766#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 387767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 388696#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 388697#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 388803#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 388796#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 388797#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 387930#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 387675#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 387676#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 388659#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 388660#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 388639#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 388640#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 388686#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 387726#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 387727#L1006 assume !(0 == ~M_E~0); 387576#L1006-2 assume !(0 == ~T1_E~0); 387577#L1011-1 assume !(0 == ~T2_E~0); 388727#L1016-1 assume !(0 == ~T3_E~0); 388748#L1021-1 assume !(0 == ~T4_E~0); 387448#L1026-1 assume !(0 == ~T5_E~0); 387449#L1031-1 assume !(0 == ~T6_E~0); 388367#L1036-1 assume !(0 == ~T7_E~0); 388363#L1041-1 assume !(0 == ~T8_E~0); 388364#L1046-1 assume !(0 == ~T9_E~0); 387757#L1051-1 assume !(0 == ~T10_E~0); 387758#L1056-1 assume !(0 == ~E_1~0); 388507#L1061-1 assume !(0 == ~E_2~0); 387679#L1066-1 assume !(0 == ~E_3~0); 387680#L1071-1 assume !(0 == ~E_4~0); 388478#L1076-1 assume !(0 == ~E_5~0); 387583#L1081-1 assume !(0 == ~E_6~0); 387584#L1086-1 assume !(0 == ~E_7~0); 387904#L1091-1 assume !(0 == ~E_8~0); 388706#L1096-1 assume !(0 == ~E_9~0); 388707#L1101-1 assume !(0 == ~E_10~0); 387978#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 387979#L484 assume !(1 == ~m_pc~0); 387635#L484-2 is_master_triggered_~__retres1~0#1 := 0; 387634#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 388271#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 388598#L1245 assume !(0 != activate_threads_~tmp~1#1); 388599#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 388354#L503 assume !(1 == ~t1_pc~0); 388355#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 388543#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 387489#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 387490#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 387485#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 387486#L522 assume !(1 == ~t2_pc~0); 388313#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 387690#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 387691#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 387972#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 388661#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 388760#L541 assume !(1 == ~t3_pc~0); 388045#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 388046#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 387432#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 387433#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 388319#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 388320#L560 assume !(1 == ~t4_pc~0); 387568#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 387567#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 387599#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 387446#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 387447#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 387737#L579 assume !(1 == ~t5_pc~0); 387738#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 387511#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 387512#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 388603#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 388746#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 388779#L598 assume !(1 == ~t6_pc~0); 388522#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 388140#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 387945#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 387946#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 388403#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 388345#L617 assume !(1 == ~t7_pc~0); 387798#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 387797#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 388810#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 388676#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 388012#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 388013#L636 assume 1 == ~t8_pc~0; 388202#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 388203#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 388544#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 388411#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 388147#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 388148#L655 assume !(1 == ~t9_pc~0); 388176#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 388177#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 388056#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 388057#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 388422#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 388423#L674 assume 1 == ~t10_pc~0; 387561#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 387562#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 388191#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 388192#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 388137#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 388138#L1119 assume !(1 == ~M_E~0); 387661#L1119-2 assume !(1 == ~T1_E~0); 387662#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 387475#L1129-1 assume !(1 == ~T3_E~0); 387476#L1134-1 assume !(1 == ~T4_E~0); 451329#L1139-1 assume !(1 == ~T5_E~0); 451327#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 451325#L1149-1 assume !(1 == ~T7_E~0); 451322#L1154-1 assume !(1 == ~T8_E~0); 451320#L1159-1 assume !(1 == ~T9_E~0); 451318#L1164-1 assume !(1 == ~T10_E~0); 451316#L1169-1 assume !(1 == ~E_1~0); 451314#L1174-1 assume !(1 == ~E_2~0); 451312#L1179-1 assume !(1 == ~E_3~0); 451310#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 451308#L1189-1 assume !(1 == ~E_5~0); 451306#L1194-1 assume !(1 == ~E_6~0); 451303#L1199-1 assume !(1 == ~E_7~0); 387842#L1204-1 assume !(1 == ~E_8~0); 387843#L1209-1 assume !(1 == ~E_9~0); 388792#L1214-1 assume !(1 == ~E_10~0); 474210#L1219-1 assume { :end_inline_reset_delta_events } true; 474206#L1520-2 [2023-11-26 12:01:32,812 INFO L750 eck$LassoCheckResult]: Loop: 474206#L1520-2 assume !false; 473223#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 473219#L981-1 assume !false; 473217#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 473205#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 473200#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 473198#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 473195#L836 assume !(0 != eval_~tmp~0#1); 473196#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 474617#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 474615#L1006-3 assume !(0 == ~M_E~0); 474613#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 474611#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 474609#L1016-3 assume !(0 == ~T3_E~0); 474607#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 474605#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 474603#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 474601#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 474599#L1041-3 assume !(0 == ~T8_E~0); 474597#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 474595#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 474592#L1056-3 assume !(0 == ~E_1~0); 474590#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 474588#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 474586#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 474584#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 474582#L1081-3 assume !(0 == ~E_6~0); 474579#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 474577#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 474575#L1096-3 assume !(0 == ~E_9~0); 474573#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 474571#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 474569#L484-33 assume !(1 == ~m_pc~0); 474566#L484-35 is_master_triggered_~__retres1~0#1 := 0; 474563#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 474561#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 474559#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 474557#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 474555#L503-33 assume !(1 == ~t1_pc~0); 474552#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 474550#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 474548#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 474546#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 474544#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 474543#L522-33 assume !(1 == ~t2_pc~0); 474539#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 474536#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 474534#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 474533#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 474530#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 474529#L541-33 assume !(1 == ~t3_pc~0); 474528#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 474525#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 474521#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 474517#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 474512#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 474510#L560-33 assume 1 == ~t4_pc~0; 474508#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 474506#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 474505#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 474504#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 474503#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 474502#L579-33 assume !(1 == ~t5_pc~0); 474501#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 474500#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 474499#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 474498#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 474486#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 474484#L598-33 assume !(1 == ~t6_pc~0); 474482#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 474480#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 474478#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 474476#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 474474#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 474472#L617-33 assume !(1 == ~t7_pc~0); 474470#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 474467#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 474465#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 474463#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 474461#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 474459#L636-33 assume 1 == ~t8_pc~0; 474457#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 474454#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 474452#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 474450#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 474448#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 474446#L655-33 assume !(1 == ~t9_pc~0); 474444#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 474441#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 474439#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 474437#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 474435#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 474433#L674-33 assume !(1 == ~t10_pc~0); 474431#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 474428#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 474426#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 474423#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 474421#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 474419#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 474417#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 474415#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 417805#L1129-3 assume !(1 == ~T3_E~0); 443071#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 474411#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 474409#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 474407#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 474405#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 474403#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 474400#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 474274#L1169-3 assume !(1 == ~E_1~0); 474272#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 474270#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 474268#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 474266#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 474264#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 474261#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 474259#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 474257#L1209-3 assume !(1 == ~E_9~0); 473706#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 474254#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 474252#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 474239#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 474237#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 474234#L1539 assume !(0 == start_simulation_~tmp~3#1); 474231#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 474229#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 474218#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 474217#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 474216#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 474215#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 474214#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 474209#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 474206#L1520-2 [2023-11-26 12:01:32,813 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:32,813 INFO L85 PathProgramCache]: Analyzing trace with hash 75354675, now seen corresponding path program 1 times [2023-11-26 12:01:32,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:32,813 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825648857] [2023-11-26 12:01:32,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:32,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:32,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:32,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:32,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:32,921 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [825648857] [2023-11-26 12:01:32,921 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [825648857] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:32,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:32,921 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:01:32,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1625722290] [2023-11-26 12:01:32,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:32,922 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:32,923 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:32,923 INFO L85 PathProgramCache]: Analyzing trace with hash -311102038, now seen corresponding path program 1 times [2023-11-26 12:01:32,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:32,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2034946617] [2023-11-26 12:01:32,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:32,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:32,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:33,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:33,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:33,010 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2034946617] [2023-11-26 12:01:33,010 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2034946617] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:33,010 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:33,010 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:01:33,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1544570492] [2023-11-26 12:01:33,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:33,011 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:33,011 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:33,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 12:01:33,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 12:01:33,012 INFO L87 Difference]: Start difference. First operand 114244 states and 165389 transitions. cyclomatic complexity: 51273 Second operand has 5 states, 5 states have (on average 25.2) internal successors, (126), 5 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:34,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:34,586 INFO L93 Difference]: Finished difference Result 250312 states and 359488 transitions. [2023-11-26 12:01:34,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 250312 states and 359488 transitions. [2023-11-26 12:01:36,312 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 249088 [2023-11-26 12:01:37,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 250312 states to 250312 states and 359488 transitions. [2023-11-26 12:01:37,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 250312 [2023-11-26 12:01:37,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 250312 [2023-11-26 12:01:37,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 250312 states and 359488 transitions. [2023-11-26 12:01:37,782 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:37,782 INFO L218 hiAutomatonCegarLoop]: Abstraction has 250312 states and 359488 transitions. [2023-11-26 12:01:37,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250312 states and 359488 transitions. [2023-11-26 12:01:39,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250312 to 117703. [2023-11-26 12:01:39,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117703 states, 117703 states have (on average 1.4345258829426608) internal successors, (168848), 117702 states have internal predecessors, (168848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:40,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117703 states to 117703 states and 168848 transitions. [2023-11-26 12:01:40,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117703 states and 168848 transitions. [2023-11-26 12:01:40,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 12:01:40,729 INFO L428 stractBuchiCegarLoop]: Abstraction has 117703 states and 168848 transitions. [2023-11-26 12:01:40,729 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 12:01:40,729 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117703 states and 168848 transitions. [2023-11-26 12:01:40,990 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 117056 [2023-11-26 12:01:40,990 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:40,990 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:40,992 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:40,993 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:40,993 INFO L748 eck$LassoCheckResult]: Stem: 752336#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 752337#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 753289#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 753290#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 753410#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 753391#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 753392#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 752506#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 752245#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 752246#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 753252#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 753253#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 753227#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 753228#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 753280#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 752298#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 752299#L1006 assume !(0 == ~M_E~0); 752146#L1006-2 assume !(0 == ~T1_E~0); 752147#L1011-1 assume !(0 == ~T2_E~0); 753316#L1016-1 assume !(0 == ~T3_E~0); 753344#L1021-1 assume !(0 == ~T4_E~0); 752021#L1026-1 assume !(0 == ~T5_E~0); 752022#L1031-1 assume !(0 == ~T6_E~0); 752950#L1036-1 assume !(0 == ~T7_E~0); 752945#L1041-1 assume !(0 == ~T8_E~0); 752946#L1046-1 assume !(0 == ~T9_E~0); 752327#L1051-1 assume !(0 == ~T10_E~0); 752328#L1056-1 assume !(0 == ~E_1~0); 753094#L1061-1 assume !(0 == ~E_2~0); 752247#L1066-1 assume !(0 == ~E_3~0); 752248#L1071-1 assume !(0 == ~E_4~0); 753066#L1076-1 assume !(0 == ~E_5~0); 752151#L1081-1 assume !(0 == ~E_6~0); 752152#L1086-1 assume !(0 == ~E_7~0); 752480#L1091-1 assume !(0 == ~E_8~0); 753301#L1096-1 assume !(0 == ~E_9~0); 753302#L1101-1 assume !(0 == ~E_10~0); 752554#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 752555#L484 assume !(1 == ~m_pc~0); 752204#L484-2 is_master_triggered_~__retres1~0#1 := 0; 752203#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 752858#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 753185#L1245 assume !(0 != activate_threads_~tmp~1#1); 753186#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 752935#L503 assume !(1 == ~t1_pc~0); 752936#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 753137#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 752062#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 752063#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 752058#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 752059#L522 assume !(1 == ~t2_pc~0); 752901#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 752264#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 752265#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 752550#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 753254#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 753355#L541 assume !(1 == ~t3_pc~0); 752620#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 752621#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 752005#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 752006#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 752911#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 752912#L560 assume !(1 == ~t4_pc~0); 752138#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 752137#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 752167#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 752017#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 752018#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 752309#L579 assume !(1 == ~t5_pc~0); 752310#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 752082#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 752083#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 753191#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 753343#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 753373#L598 assume !(1 == ~t6_pc~0); 753109#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 752730#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752524#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 752525#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 752983#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 752926#L617 assume !(1 == ~t7_pc~0); 752369#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 752806#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 753416#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 753268#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 752591#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 752592#L636 assume 1 == ~t8_pc~0; 752788#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 752789#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 753138#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 752996#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 752736#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 752737#L655 assume !(1 == ~t9_pc~0); 752767#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 752768#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 752636#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 752637#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 753005#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 753006#L674 assume 1 == ~t10_pc~0; 752129#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 752130#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 752779#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 752780#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 752724#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 752725#L1119 assume !(1 == ~M_E~0); 752228#L1119-2 assume !(1 == ~T1_E~0); 752229#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 752046#L1129-1 assume !(1 == ~T3_E~0); 752047#L1134-1 assume !(1 == ~T4_E~0); 752354#L1139-1 assume !(1 == ~T5_E~0); 752355#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 752587#L1149-1 assume !(1 == ~T7_E~0); 752222#L1154-1 assume !(1 == ~T8_E~0); 752223#L1159-1 assume !(1 == ~T9_E~0); 752311#L1164-1 assume !(1 == ~T10_E~0); 752754#L1169-1 assume !(1 == ~E_1~0); 752639#L1174-1 assume !(1 == ~E_2~0); 752405#L1179-1 assume !(1 == ~E_3~0); 752300#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 752301#L1189-1 assume !(1 == ~E_5~0); 752352#L1194-1 assume !(1 == ~E_6~0); 752457#L1199-1 assume !(1 == ~E_7~0); 752415#L1204-1 assume !(1 == ~E_8~0); 752416#L1209-1 assume !(1 == ~E_9~0); 753385#L1214-1 assume !(1 == ~E_10~0); 784230#L1219-1 assume { :end_inline_reset_delta_events } true; 784219#L1520-2 [2023-11-26 12:01:40,994 INFO L750 eck$LassoCheckResult]: Loop: 784219#L1520-2 assume !false; 784129#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 784118#L981-1 assume !false; 784112#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 784077#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 784073#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 784071#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 784068#L836 assume !(0 != eval_~tmp~0#1); 784069#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 785977#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 785976#L1006-3 assume !(0 == ~M_E~0); 785975#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 785974#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 785973#L1016-3 assume !(0 == ~T3_E~0); 785972#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 785971#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 785970#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 785969#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 785968#L1041-3 assume !(0 == ~T8_E~0); 785967#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 785966#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 785965#L1056-3 assume !(0 == ~E_1~0); 785964#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 785963#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 785962#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 785961#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 785960#L1081-3 assume !(0 == ~E_6~0); 785959#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 785958#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 785957#L1096-3 assume !(0 == ~E_9~0); 785956#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 785955#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 785954#L484-33 assume !(1 == ~m_pc~0); 785953#L484-35 is_master_triggered_~__retres1~0#1 := 0; 785951#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 785950#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 785949#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 785948#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 785947#L503-33 assume !(1 == ~t1_pc~0); 785946#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 785945#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 785944#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 785943#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 785942#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 785941#L522-33 assume 1 == ~t2_pc~0; 785939#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 785938#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 785937#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 785936#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 785935#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 785934#L541-33 assume !(1 == ~t3_pc~0); 785933#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 785932#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 785931#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 785930#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 785929#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 785928#L560-33 assume 1 == ~t4_pc~0; 785927#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 785925#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 785924#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 785923#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 785922#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 785921#L579-33 assume !(1 == ~t5_pc~0); 785920#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 785919#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 785918#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 785917#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 785916#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 785915#L598-33 assume !(1 == ~t6_pc~0); 785914#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 785913#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 785912#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 785911#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 785910#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 785909#L617-33 assume 1 == ~t7_pc~0; 785907#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 785905#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 785903#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 785901#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 784650#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 784648#L636-33 assume 1 == ~t8_pc~0; 784646#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 784642#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 784640#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 784638#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 784636#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 784634#L655-33 assume !(1 == ~t9_pc~0); 784632#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 784628#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 784626#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 784624#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 784622#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 784620#L674-33 assume !(1 == ~t10_pc~0); 784618#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 784614#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 784612#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 784592#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 784407#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 784402#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 784397#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 784392#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 776347#L1129-3 assume !(1 == ~T3_E~0); 784379#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 784374#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 784369#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 784361#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 784355#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 784350#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 784345#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 784339#L1169-3 assume !(1 == ~E_1~0); 784335#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 784331#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 784321#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 784305#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 784301#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 784299#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 784297#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 784295#L1209-3 assume !(1 == ~E_9~0); 776275#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 784292#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 784290#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 784278#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 784276#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 784274#L1539 assume !(0 == start_simulation_~tmp~3#1); 784272#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 784271#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 784260#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 784258#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 784252#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 784244#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 784236#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 784229#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 784219#L1520-2 [2023-11-26 12:01:40,994 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:40,994 INFO L85 PathProgramCache]: Analyzing trace with hash 323501169, now seen corresponding path program 1 times [2023-11-26 12:01:40,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:40,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996554489] [2023-11-26 12:01:40,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:40,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:41,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:41,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:41,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:41,063 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996554489] [2023-11-26 12:01:41,063 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1996554489] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:41,063 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:41,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:01:41,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669479616] [2023-11-26 12:01:41,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:41,064 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:41,064 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:41,064 INFO L85 PathProgramCache]: Analyzing trace with hash -371648980, now seen corresponding path program 1 times [2023-11-26 12:01:41,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:41,065 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278514302] [2023-11-26 12:01:41,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:41,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:41,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:41,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:41,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:41,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1278514302] [2023-11-26 12:01:41,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1278514302] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:41,149 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:41,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:01:41,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [183131436] [2023-11-26 12:01:41,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:41,151 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:41,151 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:41,151 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:41,151 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:41,152 INFO L87 Difference]: Start difference. First operand 117703 states and 168848 transitions. cyclomatic complexity: 51273 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:42,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:01:42,541 INFO L93 Difference]: Finished difference Result 228870 states and 326877 transitions. [2023-11-26 12:01:42,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 228870 states and 326877 transitions. [2023-11-26 12:01:43,483 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 227520 [2023-11-26 12:01:44,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 228870 states to 228870 states and 326877 transitions. [2023-11-26 12:01:44,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 228870 [2023-11-26 12:01:44,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 228870 [2023-11-26 12:01:44,836 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228870 states and 326877 transitions. [2023-11-26 12:01:44,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:01:44,917 INFO L218 hiAutomatonCegarLoop]: Abstraction has 228870 states and 326877 transitions. [2023-11-26 12:01:45,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228870 states and 326877 transitions. [2023-11-26 12:01:47,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228870 to 228614. [2023-11-26 12:01:47,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 228614 states, 228614 states have (on average 1.4287007794798219) internal successors, (326621), 228613 states have internal predecessors, (326621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:01:48,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228614 states to 228614 states and 326621 transitions. [2023-11-26 12:01:48,706 INFO L240 hiAutomatonCegarLoop]: Abstraction has 228614 states and 326621 transitions. [2023-11-26 12:01:48,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:01:48,707 INFO L428 stractBuchiCegarLoop]: Abstraction has 228614 states and 326621 transitions. [2023-11-26 12:01:48,707 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 12:01:48,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 228614 states and 326621 transitions. [2023-11-26 12:01:49,316 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 227264 [2023-11-26 12:01:49,316 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:01:49,316 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:01:49,319 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:49,319 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:01:49,319 INFO L748 eck$LassoCheckResult]: Stem: 1098917#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1098918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1099908#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1099909#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1100057#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 1100045#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1100046#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1099082#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1098823#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1098824#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1099859#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1099860#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1099836#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1099837#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1099896#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1098877#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1098878#L1006 assume !(0 == ~M_E~0); 1098724#L1006-2 assume !(0 == ~T1_E~0); 1098725#L1011-1 assume !(0 == ~T2_E~0); 1099948#L1016-1 assume !(0 == ~T3_E~0); 1099977#L1021-1 assume !(0 == ~T4_E~0); 1098602#L1026-1 assume !(0 == ~T5_E~0); 1098603#L1031-1 assume !(0 == ~T6_E~0); 1099534#L1036-1 assume !(0 == ~T7_E~0); 1099531#L1041-1 assume !(0 == ~T8_E~0); 1099532#L1046-1 assume !(0 == ~T9_E~0); 1098908#L1051-1 assume !(0 == ~T10_E~0); 1098909#L1056-1 assume !(0 == ~E_1~0); 1099684#L1061-1 assume !(0 == ~E_2~0); 1098827#L1066-1 assume !(0 == ~E_3~0); 1098828#L1071-1 assume !(0 == ~E_4~0); 1099657#L1076-1 assume !(0 == ~E_5~0); 1098731#L1081-1 assume !(0 == ~E_6~0); 1098732#L1086-1 assume !(0 == ~E_7~0); 1099056#L1091-1 assume !(0 == ~E_8~0); 1099926#L1096-1 assume !(0 == ~E_9~0); 1099927#L1101-1 assume !(0 == ~E_10~0); 1099130#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1099131#L484 assume !(1 == ~m_pc~0); 1098783#L484-2 is_master_triggered_~__retres1~0#1 := 0; 1098782#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1099439#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1099787#L1245 assume !(0 != activate_threads_~tmp~1#1); 1099788#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1099522#L503 assume !(1 == ~t1_pc~0); 1099523#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1099724#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1098642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1098643#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 1098636#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1098637#L522 assume !(1 == ~t2_pc~0); 1099486#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1098839#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1098840#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1099125#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 1099861#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1099991#L541 assume !(1 == ~t3_pc~0); 1099198#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1099199#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1098586#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1098587#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 1099492#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1099493#L560 assume !(1 == ~t4_pc~0); 1098718#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1098717#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1098747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1098598#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 1098599#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1098886#L579 assume !(1 == ~t5_pc~0); 1098887#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1098661#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1098662#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1099796#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 1099975#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1100017#L598 assume !(1 == ~t6_pc~0); 1099699#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1099305#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1099098#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1099099#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 1099572#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1099513#L617 assume !(1 == ~t7_pc~0); 1098949#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1099384#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1100072#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1099882#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 1099165#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1099166#L636 assume !(1 == ~t8_pc~0); 1099569#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1099780#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1099725#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1099584#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 1099312#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1099313#L655 assume !(1 == ~t9_pc~0); 1099344#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1099345#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1099213#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1099214#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 1099596#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1099597#L674 assume 1 == ~t10_pc~0; 1098709#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1098710#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1099359#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1099360#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 1099302#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1099303#L1119 assume !(1 == ~M_E~0); 1098809#L1119-2 assume !(1 == ~T1_E~0); 1098810#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1098626#L1129-1 assume !(1 == ~T3_E~0); 1098627#L1134-1 assume !(1 == ~T4_E~0); 1098934#L1139-1 assume !(1 == ~T5_E~0); 1098935#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1099161#L1149-1 assume !(1 == ~T7_E~0); 1098803#L1154-1 assume !(1 == ~T8_E~0); 1098804#L1159-1 assume !(1 == ~T9_E~0); 1098890#L1164-1 assume !(1 == ~T10_E~0); 1099333#L1169-1 assume !(1 == ~E_1~0); 1099215#L1174-1 assume !(1 == ~E_2~0); 1098985#L1179-1 assume !(1 == ~E_3~0); 1098879#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1098880#L1189-1 assume !(1 == ~E_5~0); 1098931#L1194-1 assume !(1 == ~E_6~0); 1099036#L1199-1 assume !(1 == ~E_7~0); 1098996#L1204-1 assume !(1 == ~E_8~0); 1098997#L1209-1 assume !(1 == ~E_9~0); 1100034#L1214-1 assume !(1 == ~E_10~0); 1195759#L1219-1 assume { :end_inline_reset_delta_events } true; 1195756#L1520-2 [2023-11-26 12:01:49,320 INFO L750 eck$LassoCheckResult]: Loop: 1195756#L1520-2 assume !false; 1195379#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1195376#L981-1 assume !false; 1195374#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1195350#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1195346#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1195344#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1195340#L836 assume !(0 != eval_~tmp~0#1); 1195341#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1196018#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1196016#L1006-3 assume !(0 == ~M_E~0); 1196014#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1196012#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1196010#L1016-3 assume !(0 == ~T3_E~0); 1196008#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1196006#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1196004#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1196001#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1195999#L1041-3 assume !(0 == ~T8_E~0); 1195997#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1195995#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1195993#L1056-3 assume !(0 == ~E_1~0); 1195991#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1195989#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1195987#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1195985#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1195983#L1081-3 assume !(0 == ~E_6~0); 1195981#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1195979#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1195977#L1096-3 assume !(0 == ~E_9~0); 1195975#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1195973#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1195971#L484-33 assume 1 == ~m_pc~0; 1195968#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1195966#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1195963#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1195961#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 1195959#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1195956#L503-33 assume !(1 == ~t1_pc~0); 1195954#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1195952#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1195950#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1195948#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1195946#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1195944#L522-33 assume !(1 == ~t2_pc~0); 1195942#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1195939#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1195936#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1195934#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1195932#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1195930#L541-33 assume !(1 == ~t3_pc~0); 1195928#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1195926#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1195923#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1195921#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1195919#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1195917#L560-33 assume !(1 == ~t4_pc~0); 1195914#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1195912#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1195910#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1195908#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1195907#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1195906#L579-33 assume !(1 == ~t5_pc~0); 1195904#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1195902#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1195900#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1195898#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1195896#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1195894#L598-33 assume !(1 == ~t6_pc~0); 1195892#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1195891#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1195889#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1195887#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1195885#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1195883#L617-33 assume !(1 == ~t7_pc~0); 1195879#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1195877#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1195875#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1195874#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 1195872#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1195871#L636-33 assume !(1 == ~t8_pc~0); 1195870#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1195869#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1195868#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1195867#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1195866#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1195865#L655-33 assume 1 == ~t9_pc~0; 1195863#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1195862#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1195861#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1195860#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 1195859#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1195858#L674-33 assume 1 == ~t10_pc~0; 1195856#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1195855#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1195854#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1195852#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1195849#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1195847#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1195845#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1195843#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1166306#L1129-3 assume !(1 == ~T3_E~0); 1195124#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1195839#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1195837#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1195835#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1195833#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1195831#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1195829#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1195826#L1169-3 assume !(1 == ~E_1~0); 1167652#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1195823#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1195821#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1195819#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1195817#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1195815#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1195813#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1195811#L1209-3 assume !(1 == ~E_9~0); 1194372#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1195808#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1195806#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1195793#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1195791#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1195788#L1539 assume !(0 == start_simulation_~tmp~3#1); 1195785#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1195783#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1195771#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1195769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1195767#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1195765#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1195763#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1195758#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 1195756#L1520-2 [2023-11-26 12:01:49,321 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:49,321 INFO L85 PathProgramCache]: Analyzing trace with hash 723492368, now seen corresponding path program 1 times [2023-11-26 12:01:49,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:49,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205418956] [2023-11-26 12:01:49,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:49,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:49,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:49,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:49,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:49,390 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205418956] [2023-11-26 12:01:49,390 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1205418956] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:49,390 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:49,391 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:01:49,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427375628] [2023-11-26 12:01:49,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:49,392 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:01:49,392 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:01:49,393 INFO L85 PathProgramCache]: Analyzing trace with hash 1853537033, now seen corresponding path program 1 times [2023-11-26 12:01:49,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:01:49,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64740332] [2023-11-26 12:01:49,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:01:49,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:01:49,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:01:49,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:01:49,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:01:49,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64740332] [2023-11-26 12:01:49,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [64740332] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:01:49,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:01:49,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:01:49,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796433652] [2023-11-26 12:01:49,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:01:49,447 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:01:49,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:01:49,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:01:49,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:01:49,448 INFO L87 Difference]: Start difference. First operand 228614 states and 326621 transitions. cyclomatic complexity: 98263 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)