./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:51:47,033 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:51:47,167 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:51:47,180 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:51:47,181 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:51:47,229 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:51:47,230 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:51:47,231 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:51:47,232 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:51:47,237 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:51:47,238 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:51:47,239 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:51:47,239 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:51:47,241 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:51:47,242 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:51:47,242 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:51:47,242 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:51:47,243 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:51:47,243 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:51:47,244 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:51:47,244 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:51:47,245 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:51:47,245 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:51:47,246 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:51:47,246 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:51:47,246 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:51:47,247 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:51:47,247 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:51:47,247 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:51:47,248 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:51:47,249 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:51:47,249 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:51:47,250 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:51:47,250 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:51:47,250 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:51:47,250 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:51:47,250 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:51:47,251 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:51:47,251 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb [2023-11-26 11:51:47,531 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:51:47,564 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:51:47,567 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:51:47,569 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:51:47,569 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:51:47,571 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/kundu.cil.c [2023-11-26 11:51:50,587 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:51:50,888 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:51:50,889 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/sv-benchmarks/c/systemc/kundu.cil.c [2023-11-26 11:51:50,901 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/data/26437aaf4/28759ef1731344368336b3e87c9f279c/FLAGfc5f95a07 [2023-11-26 11:51:50,916 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/data/26437aaf4/28759ef1731344368336b3e87c9f279c [2023-11-26 11:51:50,919 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:51:50,921 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:51:50,922 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:51:50,922 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:51:50,929 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:51:50,930 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:51:50" (1/1) ... [2023-11-26 11:51:50,931 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@73a68cce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:50, skipping insertion in model container [2023-11-26 11:51:50,931 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:51:50" (1/1) ... [2023-11-26 11:51:50,972 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:51:51,263 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:51:51,285 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:51:51,349 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:51:51,373 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:51:51,374 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51 WrapperNode [2023-11-26 11:51:51,374 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:51:51,376 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:51:51,376 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:51:51,376 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:51:51,385 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,393 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,438 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 540 [2023-11-26 11:51:51,439 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:51:51,439 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:51:51,440 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:51:51,440 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:51:51,456 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,457 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,461 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,490 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 11:51:51,490 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,490 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,501 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,513 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,515 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,518 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,522 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:51:51,523 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:51:51,523 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:51:51,523 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:51:51,524 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (1/1) ... [2023-11-26 11:51:51,532 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:51,550 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:51,576 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:51,604 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:51:51,631 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:51:51,632 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:51:51,632 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:51:51,632 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:51:51,775 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:51:51,779 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:51:52,526 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:51:52,542 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:51:52,543 INFO L309 CfgBuilder]: Removed 5 assume(true) statements. [2023-11-26 11:51:52,571 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:51:52 BoogieIcfgContainer [2023-11-26 11:51:52,571 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:51:52,572 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:51:52,573 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:51:52,577 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:51:52,578 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:51:52,579 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:51:50" (1/3) ... [2023-11-26 11:51:52,580 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@9aef84b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:51:52, skipping insertion in model container [2023-11-26 11:51:52,580 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:51:52,583 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:51" (2/3) ... [2023-11-26 11:51:52,585 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@9aef84b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:51:52, skipping insertion in model container [2023-11-26 11:51:52,585 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:51:52,586 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:51:52" (3/3) ... [2023-11-26 11:51:52,587 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu.cil.c [2023-11-26 11:51:52,675 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:51:52,675 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:51:52,675 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:51:52,675 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:51:52,675 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:51:52,675 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:51:52,676 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:51:52,676 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:51:52,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 195 states, 194 states have (on average 1.4948453608247423) internal successors, (290), 194 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:52,716 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 158 [2023-11-26 11:51:52,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:52,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:52,726 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:52,727 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:52,727 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:51:52,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 195 states, 194 states have (on average 1.4948453608247423) internal successors, (290), 194 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:52,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 158 [2023-11-26 11:51:52,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:52,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:52,743 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:52,743 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:52,752 INFO L748 eck$LassoCheckResult]: Stem: 128#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 136#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 190#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 146#L305true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 184#L305-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 152#L310-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 186#L315-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 165#L118true assume !(1 == ~P_1_pc~0); 54#L118-2true is_P_1_triggered_~__retres1~0#1 := 0; 181#L129true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 47#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4#L491true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 185#L491-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 58#L186true assume 1 == ~P_2_pc~0; 95#L187true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 60#L197true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 89#is_P_2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 45#L499true assume !(0 != activate_threads_~tmp___0~1#1); 143#L499-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 120#L268true assume 1 == ~C_1_pc~0; 56#L269true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 132#L289true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 189#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 121#L507true assume !(0 != activate_threads_~tmp___1~1#1); 30#L507-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 179#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 39#L561-2true [2023-11-26 11:51:52,754 INFO L750 eck$LassoCheckResult]: Loop: 39#L561-2true assume !false; 157#L562true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 97#L397true assume false; 67#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 182#L118-6true assume !(1 == ~P_1_pc~0); 5#L118-8true is_P_1_triggered_~__retres1~0#1 := 0; 16#L129-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 42#is_P_1_triggered_returnLabel#3true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 83#L491-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 28#L491-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 57#L186-6true assume !(1 == ~P_2_pc~0); 29#L186-8true is_P_2_triggered_~__retres1~1#1 := 0; 178#L197-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 193#is_P_2_triggered_returnLabel#3true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 129#L499-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 127#L499-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 11#L268-6true assume 1 == ~C_1_pc~0; 102#L269-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 117#L289-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 99#is_C_1_triggered_returnLabel#3true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22#L507-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 161#L507-8true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 62#L328-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 66#L345-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 167#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2#L580true assume !(0 == start_simulation_~tmp~3#1); 13#L580-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 59#L328-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 183#L345-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 35#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 160#L535true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 111#L542true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 63#L593true assume !(0 != start_simulation_~tmp___0~2#1); 39#L561-2true [2023-11-26 11:51:52,760 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:52,761 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2023-11-26 11:51:52,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:52,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327048201] [2023-11-26 11:51:52,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:52,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:52,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:52,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:52,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:52,982 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327048201] [2023-11-26 11:51:52,983 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [327048201] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:52,983 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:52,983 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:52,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624663306] [2023-11-26 11:51:52,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:52,990 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:52,991 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:52,992 INFO L85 PathProgramCache]: Analyzing trace with hash -1388386939, now seen corresponding path program 1 times [2023-11-26 11:51:52,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:52,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109127898] [2023-11-26 11:51:52,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:52,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:53,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:53,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:53,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:53,026 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109127898] [2023-11-26 11:51:53,026 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109127898] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:53,026 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:53,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:51:53,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1409484235] [2023-11-26 11:51:53,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:53,028 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:53,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:53,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:53,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:53,082 INFO L87 Difference]: Start difference. First operand has 195 states, 194 states have (on average 1.4948453608247423) internal successors, (290), 194 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:53,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:53,135 INFO L93 Difference]: Finished difference Result 187 states and 270 transitions. [2023-11-26 11:51:53,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 187 states and 270 transitions. [2023-11-26 11:51:53,142 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2023-11-26 11:51:53,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 187 states to 179 states and 262 transitions. [2023-11-26 11:51:53,150 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2023-11-26 11:51:53,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2023-11-26 11:51:53,152 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 262 transitions. [2023-11-26 11:51:53,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:53,154 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2023-11-26 11:51:53,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 262 transitions. [2023-11-26 11:51:53,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2023-11-26 11:51:53,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.4636871508379887) internal successors, (262), 178 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:53,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 262 transitions. [2023-11-26 11:51:53,200 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2023-11-26 11:51:53,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:53,206 INFO L428 stractBuchiCegarLoop]: Abstraction has 179 states and 262 transitions. [2023-11-26 11:51:53,207 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:51:53,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 262 transitions. [2023-11-26 11:51:53,211 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2023-11-26 11:51:53,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:53,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:53,214 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:53,214 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:53,215 INFO L748 eck$LassoCheckResult]: Stem: 490#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 516#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 508#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 509#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 536#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 549#L310-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 550#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 561#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 559#L118 assume !(1 == ~P_1_pc~0); 530#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 531#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 526#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 400#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 401#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 538#L186 assume 1 == ~P_2_pc~0; 539#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 423#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 543#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 522#L499 assume !(0 != activate_threads_~tmp___0~1#1); 523#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 465#L268 assume 1 == ~C_1_pc~0; 467#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 500#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 501#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 468#L507 assume !(0 != activate_threads_~tmp___1~1#1); 469#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 482#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 511#L561-2 [2023-11-26 11:51:53,215 INFO L750 eck$LassoCheckResult]: Loop: 511#L561-2 assume !false; 512#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 418#L397 assume !false; 441#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 442#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 484#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 437#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 438#L362 assume !(0 != eval_~tmp___2~0#1); 554#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 513#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 514#L118-6 assume !(1 == ~P_1_pc~0); 402#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 403#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 436#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 518#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 476#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 477#L186-6 assume 1 == ~P_2_pc~0; 537#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 479#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 569#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 492#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 489#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 426#L268-6 assume 1 == ~C_1_pc~0; 427#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 443#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 444#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 458#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 459#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 556#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 547#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 405#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 552#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 391#L580 assume !(0 == start_simulation_~tmp~3#1); 392#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 433#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 541#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 502#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 503#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 411#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 412#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 548#L593 assume !(0 != start_simulation_~tmp___0~2#1); 511#L561-2 [2023-11-26 11:51:53,217 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:53,217 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2023-11-26 11:51:53,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:53,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007604423] [2023-11-26 11:51:53,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:53,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:53,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:53,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:53,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:53,307 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007604423] [2023-11-26 11:51:53,307 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007604423] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:53,308 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:53,308 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:53,308 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [371713333] [2023-11-26 11:51:53,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:53,309 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:53,310 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:53,310 INFO L85 PathProgramCache]: Analyzing trace with hash 169210142, now seen corresponding path program 1 times [2023-11-26 11:51:53,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:53,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1634237963] [2023-11-26 11:51:53,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:53,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:53,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:53,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:53,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:53,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1634237963] [2023-11-26 11:51:53,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1634237963] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:53,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:53,444 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:53,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605370781] [2023-11-26 11:51:53,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:53,445 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:53,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:53,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:53,447 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:53,448 INFO L87 Difference]: Start difference. First operand 179 states and 262 transitions. cyclomatic complexity: 84 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:53,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:53,486 INFO L93 Difference]: Finished difference Result 179 states and 261 transitions. [2023-11-26 11:51:53,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179 states and 261 transitions. [2023-11-26 11:51:53,489 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2023-11-26 11:51:53,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179 states to 179 states and 261 transitions. [2023-11-26 11:51:53,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2023-11-26 11:51:53,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2023-11-26 11:51:53,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 261 transitions. [2023-11-26 11:51:53,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:53,502 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2023-11-26 11:51:53,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 261 transitions. [2023-11-26 11:51:53,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2023-11-26 11:51:53,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.458100558659218) internal successors, (261), 178 states have internal predecessors, (261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:53,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 261 transitions. [2023-11-26 11:51:53,519 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2023-11-26 11:51:53,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:53,520 INFO L428 stractBuchiCegarLoop]: Abstraction has 179 states and 261 transitions. [2023-11-26 11:51:53,520 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:51:53,521 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 261 transitions. [2023-11-26 11:51:53,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2023-11-26 11:51:53,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:53,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:53,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:53,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:53,525 INFO L748 eck$LassoCheckResult]: Stem: 857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 882#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 874#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 875#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 903#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 916#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 917#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 928#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 926#L118 assume !(1 == ~P_1_pc~0); 897#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 898#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 893#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 765#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 766#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 905#L186 assume 1 == ~P_2_pc~0; 906#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 785#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 910#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 888#L499 assume !(0 != activate_threads_~tmp___0~1#1); 889#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 831#L268 assume 1 == ~C_1_pc~0; 833#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 867#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 868#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 834#L507 assume !(0 != activate_threads_~tmp___1~1#1); 835#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 847#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 877#L561-2 [2023-11-26 11:51:53,525 INFO L750 eck$LassoCheckResult]: Loop: 877#L561-2 assume !false; 878#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 787#L397 assume !false; 806#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 807#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 849#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 803#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 804#L362 assume !(0 != eval_~tmp___2~0#1); 921#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 922#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 880#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 881#L118-6 assume !(1 == ~P_1_pc~0); 769#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 770#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 805#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 885#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 843#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 844#L186-6 assume 1 == ~P_2_pc~0; 904#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 846#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 936#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 859#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 856#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 793#L268-6 assume 1 == ~C_1_pc~0; 794#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 810#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 811#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 825#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 826#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 923#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 914#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 772#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 919#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 758#L580 assume !(0 == start_simulation_~tmp~3#1); 759#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 800#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 908#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 869#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 870#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 778#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 779#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 915#L593 assume !(0 != start_simulation_~tmp___0~2#1); 877#L561-2 [2023-11-26 11:51:53,526 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:53,526 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2023-11-26 11:51:53,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:53,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780445904] [2023-11-26 11:51:53,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:53,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:53,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:53,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:53,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:53,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1780445904] [2023-11-26 11:51:53,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1780445904] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:53,651 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:53,651 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:53,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432971713] [2023-11-26 11:51:53,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:53,652 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:53,656 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:53,656 INFO L85 PathProgramCache]: Analyzing trace with hash 169210142, now seen corresponding path program 2 times [2023-11-26 11:51:53,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:53,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331285663] [2023-11-26 11:51:53,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:53,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:53,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:53,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:53,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:53,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [331285663] [2023-11-26 11:51:53,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [331285663] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:53,763 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:53,763 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:53,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830279305] [2023-11-26 11:51:53,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:53,764 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:53,765 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:53,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:51:53,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:51:53,765 INFO L87 Difference]: Start difference. First operand 179 states and 261 transitions. cyclomatic complexity: 83 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:54,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:54,000 INFO L93 Difference]: Finished difference Result 405 states and 588 transitions. [2023-11-26 11:51:54,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 405 states and 588 transitions. [2023-11-26 11:51:54,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 334 [2023-11-26 11:51:54,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 405 states to 405 states and 588 transitions. [2023-11-26 11:51:54,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 405 [2023-11-26 11:51:54,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 405 [2023-11-26 11:51:54,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 405 states and 588 transitions. [2023-11-26 11:51:54,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:54,013 INFO L218 hiAutomatonCegarLoop]: Abstraction has 405 states and 588 transitions. [2023-11-26 11:51:54,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states and 588 transitions. [2023-11-26 11:51:54,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 191. [2023-11-26 11:51:54,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191 states, 191 states have (on average 1.4293193717277486) internal successors, (273), 190 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:54,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 273 transitions. [2023-11-26 11:51:54,028 INFO L240 hiAutomatonCegarLoop]: Abstraction has 191 states and 273 transitions. [2023-11-26 11:51:54,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:51:54,029 INFO L428 stractBuchiCegarLoop]: Abstraction has 191 states and 273 transitions. [2023-11-26 11:51:54,030 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:51:54,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states and 273 transitions. [2023-11-26 11:51:54,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 155 [2023-11-26 11:51:54,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:54,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:54,034 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:54,034 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:54,034 INFO L748 eck$LassoCheckResult]: Stem: 1456#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1457#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1484#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1475#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1476#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1507#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1521#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1522#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1533#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1531#L118 assume !(1 == ~P_1_pc~0); 1501#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 1502#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1546#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1366#L491 assume !(0 != activate_threads_~tmp~1#1); 1367#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1509#L186 assume 1 == ~P_2_pc~0; 1510#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1389#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1515#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1492#L499 assume !(0 != activate_threads_~tmp___0~1#1); 1493#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1431#L268 assume 1 == ~C_1_pc~0; 1433#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1467#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1468#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1434#L507 assume !(0 != activate_threads_~tmp___1~1#1); 1435#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1451#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1478#L561-2 [2023-11-26 11:51:54,034 INFO L750 eck$LassoCheckResult]: Loop: 1478#L561-2 assume !false; 1479#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1384#L397 assume !false; 1405#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1406#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1447#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1402#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1403#L362 assume !(0 != eval_~tmp___2~0#1); 1526#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1481#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1482#L118-6 assume 1 == ~P_1_pc~0; 1490#L119-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 1491#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1486#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1487#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1442#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1443#L186-6 assume !(1 == ~P_2_pc~0); 1444#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 1445#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1545#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1458#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1455#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1392#L268-6 assume 1 == ~C_1_pc~0; 1393#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1409#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1410#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1424#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1425#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1528#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1519#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1371#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1524#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1357#L580 assume !(0 == start_simulation_~tmp~3#1); 1358#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1399#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1513#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1469#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1470#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1377#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1378#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1520#L593 assume !(0 != start_simulation_~tmp___0~2#1); 1478#L561-2 [2023-11-26 11:51:54,035 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:54,035 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2023-11-26 11:51:54,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:54,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211083962] [2023-11-26 11:51:54,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:54,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:54,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:54,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:54,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:54,091 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211083962] [2023-11-26 11:51:54,091 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1211083962] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:54,091 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:54,091 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 11:51:54,092 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094322448] [2023-11-26 11:51:54,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:54,092 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:54,093 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:54,093 INFO L85 PathProgramCache]: Analyzing trace with hash -116922914, now seen corresponding path program 1 times [2023-11-26 11:51:54,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:54,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359061226] [2023-11-26 11:51:54,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:54,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:54,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:54,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:54,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:54,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359061226] [2023-11-26 11:51:54,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359061226] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:54,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:54,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:54,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [532688304] [2023-11-26 11:51:54,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:54,149 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:54,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:54,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:51:54,150 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:51:54,150 INFO L87 Difference]: Start difference. First operand 191 states and 273 transitions. cyclomatic complexity: 83 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:54,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:54,277 INFO L93 Difference]: Finished difference Result 478 states and 671 transitions. [2023-11-26 11:51:54,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 671 transitions. [2023-11-26 11:51:54,283 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 415 [2023-11-26 11:51:54,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 478 states and 671 transitions. [2023-11-26 11:51:54,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 478 [2023-11-26 11:51:54,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 478 [2023-11-26 11:51:54,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 478 states and 671 transitions. [2023-11-26 11:51:54,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:54,292 INFO L218 hiAutomatonCegarLoop]: Abstraction has 478 states and 671 transitions. [2023-11-26 11:51:54,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states and 671 transitions. [2023-11-26 11:51:54,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 436. [2023-11-26 11:51:54,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 436 states, 436 states have (on average 1.4128440366972477) internal successors, (616), 435 states have internal predecessors, (616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:54,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 616 transitions. [2023-11-26 11:51:54,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 436 states and 616 transitions. [2023-11-26 11:51:54,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:51:54,332 INFO L428 stractBuchiCegarLoop]: Abstraction has 436 states and 616 transitions. [2023-11-26 11:51:54,334 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:51:54,335 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 436 states and 616 transitions. [2023-11-26 11:51:54,339 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 399 [2023-11-26 11:51:54,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:54,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:54,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:54,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:54,341 INFO L748 eck$LassoCheckResult]: Stem: 2140#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 2165#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2157#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2158#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2190#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 2202#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2203#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2217#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2216#L118 assume !(1 == ~P_1_pc~0); 2184#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 2185#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2178#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2046#L491 assume !(0 != activate_threads_~tmp~1#1); 2047#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2191#L186 assume !(1 == ~P_2_pc~0); 2065#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 2066#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2195#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2171#L499 assume !(0 != activate_threads_~tmp___0~1#1); 2172#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2114#L268 assume 1 == ~C_1_pc~0; 2116#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2150#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2151#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2117#L507 assume !(0 != activate_threads_~tmp___1~1#1); 2118#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2130#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 2160#L561-2 [2023-11-26 11:51:54,342 INFO L750 eck$LassoCheckResult]: Loop: 2160#L561-2 assume !false; 2161#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2068#L397 assume !false; 2089#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2090#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2132#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2086#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2087#L362 assume !(0 != eval_~tmp___2~0#1); 2210#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2211#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2163#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2164#L118-6 assume !(1 == ~P_1_pc~0); 2050#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 2051#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2088#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2168#L491-6 assume !(0 != activate_threads_~tmp~1#1); 2126#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2127#L186-6 assume !(1 == ~P_2_pc~0); 2128#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 2129#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2229#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2142#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 2139#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2075#L268-6 assume 1 == ~C_1_pc~0; 2076#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2093#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2094#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2108#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2109#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2212#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2199#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2053#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2205#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2039#L580 assume !(0 == start_simulation_~tmp~3#1); 2040#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2457#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2453#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2152#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2153#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2059#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2060#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2200#L593 assume !(0 != start_simulation_~tmp___0~2#1); 2160#L561-2 [2023-11-26 11:51:54,342 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:54,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2023-11-26 11:51:54,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:54,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92577238] [2023-11-26 11:51:54,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:54,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:54,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:54,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:54,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:54,415 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92577238] [2023-11-26 11:51:54,415 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [92577238] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:54,415 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:54,415 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 11:51:54,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1050912951] [2023-11-26 11:51:54,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:54,416 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:54,417 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:54,417 INFO L85 PathProgramCache]: Analyzing trace with hash 34834145, now seen corresponding path program 1 times [2023-11-26 11:51:54,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:54,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364546127] [2023-11-26 11:51:54,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:54,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:54,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:54,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:54,475 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:54,475 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364546127] [2023-11-26 11:51:54,475 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364546127] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:54,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:54,476 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:54,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775884131] [2023-11-26 11:51:54,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:54,477 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:54,477 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:54,477 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:51:54,478 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:51:54,478 INFO L87 Difference]: Start difference. First operand 436 states and 616 transitions. cyclomatic complexity: 182 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:54,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:54,628 INFO L93 Difference]: Finished difference Result 1188 states and 1642 transitions. [2023-11-26 11:51:54,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1188 states and 1642 transitions. [2023-11-26 11:51:54,640 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1108 [2023-11-26 11:51:54,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1188 states to 1188 states and 1642 transitions. [2023-11-26 11:51:54,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1188 [2023-11-26 11:51:54,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1188 [2023-11-26 11:51:54,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1188 states and 1642 transitions. [2023-11-26 11:51:54,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:54,656 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1188 states and 1642 transitions. [2023-11-26 11:51:54,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1188 states and 1642 transitions. [2023-11-26 11:51:54,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1188 to 1129. [2023-11-26 11:51:54,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1129 states, 1129 states have (on average 1.3906111603188662) internal successors, (1570), 1128 states have internal predecessors, (1570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:54,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 1129 states and 1570 transitions. [2023-11-26 11:51:54,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2023-11-26 11:51:54,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:51:54,690 INFO L428 stractBuchiCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2023-11-26 11:51:54,690 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:51:54,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1129 states and 1570 transitions. [2023-11-26 11:51:54,699 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1087 [2023-11-26 11:51:54,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:54,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:54,700 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:54,700 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:54,701 INFO L748 eck$LassoCheckResult]: Stem: 3777#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3778#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3804#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3796#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3797#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3831#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3844#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3845#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3862#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3861#L118 assume !(1 == ~P_1_pc~0); 3825#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 3826#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3819#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3683#L491 assume !(0 != activate_threads_~tmp~1#1); 3684#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3832#L186 assume !(1 == ~P_2_pc~0); 3702#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 3703#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3836#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3812#L499 assume !(0 != activate_threads_~tmp___0~1#1); 3813#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3751#L268 assume !(1 == ~C_1_pc~0); 3752#L268-2 assume 2 == ~C_1_pc~0; 3822#L279 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3788#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3789#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3753#L507 assume !(0 != activate_threads_~tmp___1~1#1); 3754#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3767#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 3880#L561-2 [2023-11-26 11:51:54,701 INFO L750 eck$LassoCheckResult]: Loop: 3880#L561-2 assume !false; 4652#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 3705#L397 assume !false; 4645#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3871#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3769#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3722#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3723#L362 assume !(0 != eval_~tmp___2~0#1); 3888#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4774#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4772#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4770#L118-6 assume !(1 == ~P_1_pc~0); 4768#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 4767#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4766#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4759#L491-6 assume !(0 != activate_threads_~tmp~1#1); 4758#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 4748#L186-6 assume !(1 == ~P_2_pc~0); 4747#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 4746#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 4745#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4744#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 4743#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 4742#L268-6 assume !(1 == ~C_1_pc~0); 4741#L268-8 assume !(2 == ~C_1_pc~0); 4739#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 4738#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 4737#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4736#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4735#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4734#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4731#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3847#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3848#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3676#L580 assume !(0 == start_simulation_~tmp~3#1); 3677#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3719#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3834#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3790#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3791#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3696#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3697#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4659#L593 assume !(0 != start_simulation_~tmp___0~2#1); 3880#L561-2 [2023-11-26 11:51:54,702 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:54,702 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2023-11-26 11:51:54,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:54,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456432506] [2023-11-26 11:51:54,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:54,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:54,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:54,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:54,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:54,795 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456432506] [2023-11-26 11:51:54,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456432506] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:54,795 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:54,795 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:54,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330557283] [2023-11-26 11:51:54,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:54,796 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:54,797 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:54,797 INFO L85 PathProgramCache]: Analyzing trace with hash -597585727, now seen corresponding path program 1 times [2023-11-26 11:51:54,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:54,798 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930435174] [2023-11-26 11:51:54,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:54,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:54,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:54,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:54,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:54,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930435174] [2023-11-26 11:51:54,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930435174] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:54,846 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:54,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:54,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652996643] [2023-11-26 11:51:54,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:54,847 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:54,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:54,848 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:54,848 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:54,849 INFO L87 Difference]: Start difference. First operand 1129 states and 1570 transitions. cyclomatic complexity: 445 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:54,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:54,938 INFO L93 Difference]: Finished difference Result 1500 states and 2055 transitions. [2023-11-26 11:51:54,939 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1500 states and 2055 transitions. [2023-11-26 11:51:54,953 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2023-11-26 11:51:54,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1500 states to 1500 states and 2055 transitions. [2023-11-26 11:51:54,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1500 [2023-11-26 11:51:54,978 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1500 [2023-11-26 11:51:54,979 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1500 states and 2055 transitions. [2023-11-26 11:51:54,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:54,981 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2055 transitions. [2023-11-26 11:51:54,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1500 states and 2055 transitions. [2023-11-26 11:51:55,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1500 to 1476. [2023-11-26 11:51:55,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.3719512195121952) internal successors, (2025), 1475 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:55,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2025 transitions. [2023-11-26 11:51:55,021 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2023-11-26 11:51:55,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:55,022 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2023-11-26 11:51:55,022 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:51:55,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2025 transitions. [2023-11-26 11:51:55,035 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1429 [2023-11-26 11:51:55,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:55,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:55,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:55,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:55,039 INFO L748 eck$LassoCheckResult]: Stem: 6410#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6411#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6439#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6430#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6431#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6468#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6484#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6485#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6500#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6499#L118 assume !(1 == ~P_1_pc~0); 6463#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 6464#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6455#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6321#L491 assume !(0 != activate_threads_~tmp~1#1); 6322#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6470#L186 assume !(1 == ~P_2_pc~0); 6339#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 6340#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6476#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6448#L499 assume !(0 != activate_threads_~tmp___0~1#1); 6449#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6384#L268 assume !(1 == ~C_1_pc~0); 6385#L268-2 assume !(2 == ~C_1_pc~0); 6508#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 6423#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6424#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6386#L507 assume !(0 != activate_threads_~tmp___1~1#1); 6387#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6399#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 6480#L561-2 [2023-11-26 11:51:55,040 INFO L750 eck$LassoCheckResult]: Loop: 6480#L561-2 assume !false; 6488#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 6342#L397 assume !false; 6359#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6360#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6401#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6356#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6357#L362 assume !(0 != eval_~tmp___2~0#1); 7716#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7787#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7786#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 7785#L118-6 assume !(1 == ~P_1_pc~0); 7784#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 7783#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 7782#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7781#L491-6 assume !(0 != activate_threads_~tmp~1#1); 7780#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 7779#L186-6 assume !(1 == ~P_2_pc~0); 7778#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 7777#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 7776#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7775#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 7774#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6347#L268-6 assume !(1 == ~C_1_pc~0); 6348#L268-8 assume !(2 == ~C_1_pc~0); 6459#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 6363#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6364#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7681#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 7682#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7748#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7744#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7741#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7740#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7738#L580 assume !(0 == start_simulation_~tmp~3#1); 7736#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6473#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6474#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6425#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6426#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 6333#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6334#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6479#L593 assume !(0 != start_simulation_~tmp___0~2#1); 6480#L561-2 [2023-11-26 11:51:55,040 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:55,047 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2023-11-26 11:51:55,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:55,047 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274970025] [2023-11-26 11:51:55,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:55,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:55,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:55,059 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:55,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:55,091 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:55,091 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:55,092 INFO L85 PathProgramCache]: Analyzing trace with hash -597585727, now seen corresponding path program 2 times [2023-11-26 11:51:55,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:55,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227169035] [2023-11-26 11:51:55,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:55,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:55,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:55,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:55,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:55,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227169035] [2023-11-26 11:51:55,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227169035] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:55,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:55,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:55,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844036272] [2023-11-26 11:51:55,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:55,143 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:55,143 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:55,143 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:51:55,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:51:55,144 INFO L87 Difference]: Start difference. First operand 1476 states and 2025 transitions. cyclomatic complexity: 553 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:55,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:55,269 INFO L93 Difference]: Finished difference Result 2613 states and 3559 transitions. [2023-11-26 11:51:55,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2613 states and 3559 transitions. [2023-11-26 11:51:55,293 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2548 [2023-11-26 11:51:55,315 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2613 states to 2613 states and 3559 transitions. [2023-11-26 11:51:55,315 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2613 [2023-11-26 11:51:55,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2613 [2023-11-26 11:51:55,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2613 states and 3559 transitions. [2023-11-26 11:51:55,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:55,323 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2613 states and 3559 transitions. [2023-11-26 11:51:55,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2613 states and 3559 transitions. [2023-11-26 11:51:55,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2613 to 1512. [2023-11-26 11:51:55,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1512 states, 1512 states have (on average 1.3630952380952381) internal successors, (2061), 1511 states have internal predecessors, (2061), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:55,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1512 states to 1512 states and 2061 transitions. [2023-11-26 11:51:55,368 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2023-11-26 11:51:55,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 11:51:55,370 INFO L428 stractBuchiCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2023-11-26 11:51:55,370 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:51:55,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1512 states and 2061 transitions. [2023-11-26 11:51:55,380 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1465 [2023-11-26 11:51:55,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:55,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:55,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:55,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:55,382 INFO L748 eck$LassoCheckResult]: Stem: 10519#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 10520#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 10549#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10540#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10541#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 10578#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 10594#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 10595#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10613#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10612#L118 assume !(1 == ~P_1_pc~0); 10573#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 10574#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10562#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10429#L491 assume !(0 != activate_threads_~tmp~1#1); 10430#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10582#L186 assume !(1 == ~P_2_pc~0); 10450#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 10451#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10587#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10558#L499 assume !(0 != activate_threads_~tmp___0~1#1); 10559#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10494#L268 assume !(1 == ~C_1_pc~0); 10495#L268-2 assume !(2 == ~C_1_pc~0); 10621#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 10532#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10533#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10496#L507 assume !(0 != activate_threads_~tmp___1~1#1); 10497#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10513#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 10636#L561-2 [2023-11-26 11:51:55,382 INFO L750 eck$LassoCheckResult]: Loop: 10636#L561-2 assume !false; 11892#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 10448#L397 assume !false; 11881#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11879#L328 assume !(0 == ~P_1_st~0); 11880#L332 assume !(0 == ~P_2_st~0); 11878#L336 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 11875#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11870#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11756#L362 assume !(0 != eval_~tmp___2~0#1); 10606#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10607#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10546#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10547#L118-6 assume !(1 == ~P_1_pc~0); 10431#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 10432#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10551#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10552#L491-6 assume !(0 != activate_threads_~tmp~1#1); 10504#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10505#L186-6 assume !(1 == ~P_2_pc~0); 10506#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 10507#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10660#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10661#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 10517#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10518#L268-6 assume !(1 == ~C_1_pc~0); 10604#L268-8 assume !(2 == ~C_1_pc~0); 10605#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 10471#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10472#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10486#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10487#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10615#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10616#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11903#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11902#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11901#L580 assume !(0 == start_simulation_~tmp~3#1); 10456#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10457#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11898#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11897#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 11896#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11895#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11894#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 11893#L593 assume !(0 != start_simulation_~tmp___0~2#1); 10636#L561-2 [2023-11-26 11:51:55,383 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:55,383 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2023-11-26 11:51:55,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:55,384 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58741554] [2023-11-26 11:51:55,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:55,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:55,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:55,393 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:55,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:55,406 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:55,407 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:55,407 INFO L85 PathProgramCache]: Analyzing trace with hash 162746408, now seen corresponding path program 1 times [2023-11-26 11:51:55,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:55,408 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184184928] [2023-11-26 11:51:55,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:55,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:55,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:55,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:55,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:55,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184184928] [2023-11-26 11:51:55,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184184928] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:55,436 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:55,436 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:55,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690728494] [2023-11-26 11:51:55,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:55,437 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:55,438 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:55,438 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:55,438 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:55,438 INFO L87 Difference]: Start difference. First operand 1512 states and 2061 transitions. cyclomatic complexity: 553 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:55,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:55,486 INFO L93 Difference]: Finished difference Result 2343 states and 3154 transitions. [2023-11-26 11:51:55,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2343 states and 3154 transitions. [2023-11-26 11:51:55,508 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2023-11-26 11:51:55,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2343 states to 2343 states and 3154 transitions. [2023-11-26 11:51:55,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2343 [2023-11-26 11:51:55,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2343 [2023-11-26 11:51:55,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2343 states and 3154 transitions. [2023-11-26 11:51:55,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:55,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2023-11-26 11:51:55,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2343 states and 3154 transitions. [2023-11-26 11:51:55,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2343 to 2343. [2023-11-26 11:51:55,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2343 states, 2343 states have (on average 1.3461374306444729) internal successors, (3154), 2342 states have internal predecessors, (3154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:55,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2343 states to 2343 states and 3154 transitions. [2023-11-26 11:51:55,625 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2023-11-26 11:51:55,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:55,629 INFO L428 stractBuchiCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2023-11-26 11:51:55,629 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 11:51:55,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2343 states and 3154 transitions. [2023-11-26 11:51:55,645 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2023-11-26 11:51:55,645 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:55,645 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:55,647 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:55,648 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:55,648 INFO L748 eck$LassoCheckResult]: Stem: 14378#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 14379#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 14406#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14398#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14399#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 14433#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 14448#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 14449#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14470#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 14469#L118 assume !(1 == ~P_1_pc~0); 14428#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 14429#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 14420#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14290#L491 assume !(0 != activate_threads_~tmp~1#1); 14291#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 14436#L186 assume !(1 == ~P_2_pc~0); 14311#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 14312#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 14441#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14416#L499 assume !(0 != activate_threads_~tmp___0~1#1); 14417#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 14354#L268 assume !(1 == ~C_1_pc~0); 14355#L268-2 assume !(2 == ~C_1_pc~0); 14476#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 14390#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 14391#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14356#L507 assume !(0 != activate_threads_~tmp___1~1#1); 14357#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14373#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 14489#L561-2 assume !false; 16128#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 16123#L397 [2023-11-26 11:51:55,648 INFO L750 eck$LassoCheckResult]: Loop: 16123#L397 assume !false; 16118#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16115#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16113#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16111#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16110#L362 assume 0 != eval_~tmp___2~0#1; 16104#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 16101#L371 assume !(0 != eval_~tmp~0#1); 16097#L367 assume !(0 == ~P_2_st~0); 16094#L382 assume !(0 == ~C_1_st~0); 16123#L397 [2023-11-26 11:51:55,650 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:55,650 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2023-11-26 11:51:55,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:55,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458702390] [2023-11-26 11:51:55,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:55,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:55,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:55,662 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:55,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:55,685 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:55,685 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:55,686 INFO L85 PathProgramCache]: Analyzing trace with hash -658298241, now seen corresponding path program 1 times [2023-11-26 11:51:55,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:55,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657512799] [2023-11-26 11:51:55,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:55,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:55,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:55,692 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:55,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:55,702 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:55,703 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:55,704 INFO L85 PathProgramCache]: Analyzing trace with hash -1216568596, now seen corresponding path program 1 times [2023-11-26 11:51:55,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:55,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230348163] [2023-11-26 11:51:55,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:55,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:55,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:55,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:55,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:55,752 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230348163] [2023-11-26 11:51:55,752 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230348163] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:55,752 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:55,752 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:55,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457492760] [2023-11-26 11:51:55,753 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:55,832 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:55,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:55,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:55,833 INFO L87 Difference]: Start difference. First operand 2343 states and 3154 transitions. cyclomatic complexity: 818 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:55,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:55,905 INFO L93 Difference]: Finished difference Result 3913 states and 5192 transitions. [2023-11-26 11:51:55,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3913 states and 5192 transitions. [2023-11-26 11:51:55,938 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3761 [2023-11-26 11:51:55,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3913 states to 3913 states and 5192 transitions. [2023-11-26 11:51:55,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3913 [2023-11-26 11:51:55,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3913 [2023-11-26 11:51:55,973 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3913 states and 5192 transitions. [2023-11-26 11:51:55,979 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:55,979 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3913 states and 5192 transitions. [2023-11-26 11:51:55,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3913 states and 5192 transitions. [2023-11-26 11:51:56,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3913 to 3829. [2023-11-26 11:51:56,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3829 states, 3829 states have (on average 1.329328806476887) internal successors, (5090), 3828 states have internal predecessors, (5090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:56,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3829 states to 3829 states and 5090 transitions. [2023-11-26 11:51:56,073 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2023-11-26 11:51:56,073 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:56,074 INFO L428 stractBuchiCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2023-11-26 11:51:56,074 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 11:51:56,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3829 states and 5090 transitions. [2023-11-26 11:51:56,091 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2023-11-26 11:51:56,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:56,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:56,093 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:56,093 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:56,094 INFO L748 eck$LassoCheckResult]: Stem: 20642#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 20643#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 20671#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20662#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20663#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 20699#L305-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 20764#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 22851#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22850#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 22849#L118 assume !(1 == ~P_1_pc~0); 22848#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 22847#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 22846#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 22845#L491 assume !(0 != activate_threads_~tmp~1#1); 22844#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 22843#L186 assume !(1 == ~P_2_pc~0); 22842#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 22841#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 22840#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22839#L499 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 20679#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 20617#L268 assume !(1 == ~C_1_pc~0); 20618#L268-2 assume !(2 == ~C_1_pc~0); 20747#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 20655#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 20656#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20619#L507 assume !(0 != activate_threads_~tmp___1~1#1); 20620#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20633#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 20761#L561-2 assume !false; 23706#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 23707#L397 [2023-11-26 11:51:56,094 INFO L750 eck$LassoCheckResult]: Loop: 23707#L397 assume !false; 23745#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 23744#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 23699#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 23700#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23365#L362 assume 0 != eval_~tmp___2~0#1; 23366#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 23521#L371 assume !(0 != eval_~tmp~0#1); 23560#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 23553#L386 assume !(0 != eval_~tmp___0~0#1); 23559#L382 assume !(0 == ~C_1_st~0); 23707#L397 [2023-11-26 11:51:56,095 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:56,095 INFO L85 PathProgramCache]: Analyzing trace with hash -131921874, now seen corresponding path program 1 times [2023-11-26 11:51:56,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:56,095 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251059212] [2023-11-26 11:51:56,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:56,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:56,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:56,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:56,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:56,133 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251059212] [2023-11-26 11:51:56,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1251059212] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:56,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:56,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:56,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410513032] [2023-11-26 11:51:56,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:56,135 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:56,135 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:56,135 INFO L85 PathProgramCache]: Analyzing trace with hash 1067448397, now seen corresponding path program 1 times [2023-11-26 11:51:56,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:56,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903879584] [2023-11-26 11:51:56,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:56,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:56,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:56,141 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:56,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:56,146 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:56,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:56,227 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:56,227 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:56,227 INFO L87 Difference]: Start difference. First operand 3829 states and 5090 transitions. cyclomatic complexity: 1268 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:56,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:56,278 INFO L93 Difference]: Finished difference Result 3804 states and 5062 transitions. [2023-11-26 11:51:56,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3804 states and 5062 transitions. [2023-11-26 11:51:56,302 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2023-11-26 11:51:56,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3804 states to 3804 states and 5062 transitions. [2023-11-26 11:51:56,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3804 [2023-11-26 11:51:56,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3804 [2023-11-26 11:51:56,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3804 states and 5062 transitions. [2023-11-26 11:51:56,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:56,348 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2023-11-26 11:51:56,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3804 states and 5062 transitions. [2023-11-26 11:51:56,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3804 to 3804. [2023-11-26 11:51:56,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3804 states, 3804 states have (on average 1.3307045215562565) internal successors, (5062), 3803 states have internal predecessors, (5062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:56,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3804 states to 3804 states and 5062 transitions. [2023-11-26 11:51:56,429 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2023-11-26 11:51:56,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:56,430 INFO L428 stractBuchiCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2023-11-26 11:51:56,430 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 11:51:56,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3804 states and 5062 transitions. [2023-11-26 11:51:56,446 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2023-11-26 11:51:56,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:56,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:56,447 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:56,447 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:56,448 INFO L748 eck$LassoCheckResult]: Stem: 28281#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 28282#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 28310#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28302#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28303#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 28338#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 28354#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 28355#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28373#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 28372#L118 assume !(1 == ~P_1_pc~0); 28333#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 28334#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 28324#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28193#L491 assume !(0 != activate_threads_~tmp~1#1); 28194#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 28342#L186 assume !(1 == ~P_2_pc~0); 28214#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 28215#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 28346#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28320#L499 assume !(0 != activate_threads_~tmp___0~1#1); 28321#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 28257#L268 assume !(1 == ~C_1_pc~0); 28258#L268-2 assume !(2 == ~C_1_pc~0); 28379#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 28293#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 28294#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28259#L507 assume !(0 != activate_threads_~tmp___1~1#1); 28260#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28276#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 28390#L561-2 assume !false; 31242#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 31237#L397 [2023-11-26 11:51:56,448 INFO L750 eck$LassoCheckResult]: Loop: 31237#L397 assume !false; 31235#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31234#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31233#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31231#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31225#L362 assume 0 != eval_~tmp___2~0#1; 31222#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 31217#L371 assume !(0 != eval_~tmp~0#1); 31215#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 31192#L386 assume !(0 != eval_~tmp___0~0#1); 31211#L382 assume !(0 == ~C_1_st~0); 31237#L397 [2023-11-26 11:51:56,448 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:56,448 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 2 times [2023-11-26 11:51:56,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:56,450 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827757609] [2023-11-26 11:51:56,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:56,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:56,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:56,458 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:56,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:56,476 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:56,477 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:56,477 INFO L85 PathProgramCache]: Analyzing trace with hash 1067448397, now seen corresponding path program 2 times [2023-11-26 11:51:56,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:56,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188230464] [2023-11-26 11:51:56,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:56,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:56,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:56,483 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:56,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:56,489 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:56,490 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:56,490 INFO L85 PathProgramCache]: Analyzing trace with hash 940936576, now seen corresponding path program 1 times [2023-11-26 11:51:56,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:56,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011879650] [2023-11-26 11:51:56,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:56,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:56,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:56,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:56,525 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:56,525 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2011879650] [2023-11-26 11:51:56,525 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2011879650] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:56,525 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:56,526 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:51:56,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892597150] [2023-11-26 11:51:56,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:56,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:56,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:56,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:56,602 INFO L87 Difference]: Start difference. First operand 3804 states and 5062 transitions. cyclomatic complexity: 1265 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:56,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:56,669 INFO L93 Difference]: Finished difference Result 6650 states and 8776 transitions. [2023-11-26 11:51:56,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6650 states and 8776 transitions. [2023-11-26 11:51:56,707 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2023-11-26 11:51:56,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6650 states to 6650 states and 8776 transitions. [2023-11-26 11:51:56,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6650 [2023-11-26 11:51:56,794 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6650 [2023-11-26 11:51:56,794 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6650 states and 8776 transitions. [2023-11-26 11:51:56,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:56,806 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2023-11-26 11:51:56,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6650 states and 8776 transitions. [2023-11-26 11:51:56,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6650 to 6650. [2023-11-26 11:51:56,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6650 states, 6650 states have (on average 1.3196992481203007) internal successors, (8776), 6649 states have internal predecessors, (8776), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:57,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6650 states to 6650 states and 8776 transitions. [2023-11-26 11:51:57,011 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2023-11-26 11:51:57,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:57,013 INFO L428 stractBuchiCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2023-11-26 11:51:57,013 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 11:51:57,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6650 states and 8776 transitions. [2023-11-26 11:51:57,041 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2023-11-26 11:51:57,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:57,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:57,042 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:57,042 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:57,043 INFO L748 eck$LassoCheckResult]: Stem: 38742#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 38743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 38774#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38765#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38766#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 38799#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 38812#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 38813#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38837#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 38836#L118 assume !(1 == ~P_1_pc~0); 38794#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 38795#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38785#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38655#L491 assume !(0 != activate_threads_~tmp~1#1); 38656#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 38803#L186 assume !(1 == ~P_2_pc~0); 38676#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 38677#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 38806#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38781#L499 assume !(0 != activate_threads_~tmp___0~1#1); 38782#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38718#L268 assume !(1 == ~C_1_pc~0); 38719#L268-2 assume !(2 == ~C_1_pc~0); 38848#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 38756#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 38757#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38720#L507 assume !(0 != activate_threads_~tmp___1~1#1); 38721#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38737#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 38860#L561-2 assume !false; 39668#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 39669#L397 [2023-11-26 11:51:57,043 INFO L750 eck$LassoCheckResult]: Loop: 39669#L397 assume !false; 42520#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 42518#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 42517#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 42516#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42515#L362 assume 0 != eval_~tmp___2~0#1; 42513#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 42511#L371 assume !(0 != eval_~tmp~0#1); 42510#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 42496#L386 assume !(0 != eval_~tmp___0~0#1); 42443#L382 assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 42442#L401 assume !(0 != eval_~tmp___1~0#1); 39669#L397 [2023-11-26 11:51:57,043 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:57,043 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 3 times [2023-11-26 11:51:57,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:57,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463548028] [2023-11-26 11:51:57,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:57,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:57,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:57,053 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:57,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:57,074 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:57,076 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:57,076 INFO L85 PathProgramCache]: Analyzing trace with hash -1268840153, now seen corresponding path program 1 times [2023-11-26 11:51:57,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:57,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129236902] [2023-11-26 11:51:57,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:57,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:57,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:57,082 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:57,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:57,087 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:57,088 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:57,088 INFO L85 PathProgramCache]: Analyzing trace with hash -895739308, now seen corresponding path program 1 times [2023-11-26 11:51:57,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:57,088 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588647752] [2023-11-26 11:51:57,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:57,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:57,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:57,097 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:57,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:57,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:58,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:58,410 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:58,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:58,565 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.11 11:51:58 BoogieIcfgContainer [2023-11-26 11:51:58,565 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-26 11:51:58,566 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-26 11:51:58,566 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-26 11:51:58,566 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-26 11:51:58,567 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:51:52" (3/4) ... [2023-11-26 11:51:58,569 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-26 11:51:58,678 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/witness.graphml [2023-11-26 11:51:58,678 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-26 11:51:58,679 INFO L158 Benchmark]: Toolchain (without parser) took 7758.55ms. Allocated memory was 130.0MB in the beginning and 211.8MB in the end (delta: 81.8MB). Free memory was 99.1MB in the beginning and 115.7MB in the end (delta: -16.6MB). Peak memory consumption was 67.3MB. Max. memory is 16.1GB. [2023-11-26 11:51:58,679 INFO L158 Benchmark]: CDTParser took 0.26ms. Allocated memory is still 104.9MB. Free memory is still 59.2MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 11:51:58,680 INFO L158 Benchmark]: CACSL2BoogieTranslator took 452.58ms. Allocated memory is still 130.0MB. Free memory was 98.7MB in the beginning and 84.4MB in the end (delta: 14.3MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-26 11:51:58,680 INFO L158 Benchmark]: Boogie Procedure Inliner took 63.01ms. Allocated memory is still 130.0MB. Free memory was 84.4MB in the beginning and 81.6MB in the end (delta: 2.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-26 11:51:58,680 INFO L158 Benchmark]: Boogie Preprocessor took 82.75ms. Allocated memory is still 130.0MB. Free memory was 81.6MB in the beginning and 78.2MB in the end (delta: 3.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 11:51:58,681 INFO L158 Benchmark]: RCFGBuilder took 1048.41ms. Allocated memory is still 130.0MB. Free memory was 78.2MB in the beginning and 100.2MB in the end (delta: -21.9MB). Peak memory consumption was 33.3MB. Max. memory is 16.1GB. [2023-11-26 11:51:58,681 INFO L158 Benchmark]: BuchiAutomizer took 5993.24ms. Allocated memory was 130.0MB in the beginning and 211.8MB in the end (delta: 81.8MB). Free memory was 100.0MB in the beginning and 120.9MB in the end (delta: -20.9MB). Peak memory consumption was 59.1MB. Max. memory is 16.1GB. [2023-11-26 11:51:58,681 INFO L158 Benchmark]: Witness Printer took 112.40ms. Allocated memory is still 211.8MB. Free memory was 120.9MB in the beginning and 115.7MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-26 11:51:58,684 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.26ms. Allocated memory is still 104.9MB. Free memory is still 59.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 452.58ms. Allocated memory is still 130.0MB. Free memory was 98.7MB in the beginning and 84.4MB in the end (delta: 14.3MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 63.01ms. Allocated memory is still 130.0MB. Free memory was 84.4MB in the beginning and 81.6MB in the end (delta: 2.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 82.75ms. Allocated memory is still 130.0MB. Free memory was 81.6MB in the beginning and 78.2MB in the end (delta: 3.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1048.41ms. Allocated memory is still 130.0MB. Free memory was 78.2MB in the beginning and 100.2MB in the end (delta: -21.9MB). Peak memory consumption was 33.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 5993.24ms. Allocated memory was 130.0MB in the beginning and 211.8MB in the end (delta: 81.8MB). Free memory was 100.0MB in the beginning and 120.9MB in the end (delta: -20.9MB). Peak memory consumption was 59.1MB. Max. memory is 16.1GB. * Witness Printer took 112.40ms. Allocated memory is still 211.8MB. Free memory was 120.9MB in the beginning and 115.7MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6650 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.8s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 3.1s. Construction of modules took 0.4s. Büchi inclusion checks took 1.8s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.7s AutomataMinimizationTime, 11 MinimizatonAttempts, 1524 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3338 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3338 mSDsluCounter, 6273 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3359 mSDsCounter, 115 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 309 IncrementalHoareTripleChecker+Invalid, 424 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 115 mSolverCounterUnsat, 2914 mSDtfsCounter, 309 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 357]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L128] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L130] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L196] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L198] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0, tmp___0=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L288] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L290] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=8, num=0, timer=0] [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 357]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L128] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L130] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L196] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L198] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0, tmp___0=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L288] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L290] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=8, num=0, timer=0] [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-26 11:51:58,761 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7933b9fe-f7a0-41ec-96f2-f1e32136bc26/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)