./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:51:07,372 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:51:07,439 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:51:07,445 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:51:07,445 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:51:07,471 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:51:07,471 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:51:07,472 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:51:07,473 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:51:07,473 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:51:07,474 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:51:07,475 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:51:07,475 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:51:07,476 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:51:07,477 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:51:07,477 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:51:07,478 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:51:07,478 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:51:07,479 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:51:07,479 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:51:07,480 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:51:07,481 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:51:07,481 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:51:07,482 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:51:07,482 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:51:07,483 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:51:07,483 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:51:07,484 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:51:07,484 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:51:07,485 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:51:07,486 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:51:07,486 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:51:07,487 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:51:07,487 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:51:07,488 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:51:07,488 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:51:07,489 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:51:07,490 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:51:07,490 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 [2023-11-26 11:51:07,731 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:51:07,765 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:51:07,767 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:51:07,769 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:51:07,769 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:51:07,771 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2023-11-26 11:51:10,816 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:51:11,118 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:51:11,118 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2023-11-26 11:51:11,134 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/data/4e6bce0ac/62c557ea943d4be090ecaf6e2f28f124/FLAGa5def7ae2 [2023-11-26 11:51:11,149 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/data/4e6bce0ac/62c557ea943d4be090ecaf6e2f28f124 [2023-11-26 11:51:11,152 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:51:11,154 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:51:11,156 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:51:11,156 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:51:11,161 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:51:11,162 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,163 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@74e5889d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11, skipping insertion in model container [2023-11-26 11:51:11,163 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,222 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:51:11,472 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:51:11,488 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:51:11,572 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:51:11,597 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:51:11,598 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11 WrapperNode [2023-11-26 11:51:11,598 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:51:11,599 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:51:11,599 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:51:11,600 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:51:11,606 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,619 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,687 INFO L138 Inliner]: procedures = 38, calls = 48, calls flagged for inlining = 43, calls inlined = 97, statements flattened = 1368 [2023-11-26 11:51:11,688 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:51:11,688 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:51:11,689 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:51:11,689 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:51:11,704 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,704 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,711 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,746 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 11:51:11,747 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,747 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,779 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,831 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,834 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,840 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,857 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:51:11,858 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:51:11,858 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:51:11,859 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:51:11,859 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (1/1) ... [2023-11-26 11:51:11,868 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:11,885 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:11,916 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:11,964 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:51:11,965 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:51:11,966 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:51:11,966 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:51:11,942 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:51:12,115 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:51:12,117 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:51:13,336 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:51:13,362 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:51:13,362 INFO L309 CfgBuilder]: Removed 8 assume(true) statements. [2023-11-26 11:51:13,364 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:51:13 BoogieIcfgContainer [2023-11-26 11:51:13,365 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:51:13,366 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:51:13,366 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:51:13,370 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:51:13,371 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:51:13,371 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:51:11" (1/3) ... [2023-11-26 11:51:13,373 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@295909f1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:51:13, skipping insertion in model container [2023-11-26 11:51:13,373 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:51:13,373 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:51:11" (2/3) ... [2023-11-26 11:51:13,373 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@295909f1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:51:13, skipping insertion in model container [2023-11-26 11:51:13,374 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:51:13,374 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:51:13" (3/3) ... [2023-11-26 11:51:13,375 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2023-11-26 11:51:13,452 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:51:13,452 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:51:13,453 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:51:13,453 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:51:13,453 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:51:13,453 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:51:13,453 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:51:13,454 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:51:13,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:13,513 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 484 [2023-11-26 11:51:13,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:13,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:13,527 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:13,527 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:13,527 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:51:13,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:13,545 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 484 [2023-11-26 11:51:13,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:13,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:13,551 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:13,552 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:13,564 INFO L748 eck$LassoCheckResult]: Stem: 192#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 472#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 279#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 469#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 265#L426true assume !(1 == ~m_i~0);~m_st~0 := 2; 328#L426-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 153#L431-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 323#L436-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 138#L441-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 507#L446-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 364#L451-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 209#L611true assume 0 == ~M_E~0;~M_E~0 := 1; 385#L611-2true assume !(0 == ~T1_E~0); 382#L616-1true assume !(0 == ~T2_E~0); 390#L621-1true assume !(0 == ~T3_E~0); 65#L626-1true assume !(0 == ~T4_E~0); 354#L631-1true assume !(0 == ~T5_E~0); 177#L636-1true assume !(0 == ~E_M~0); 91#L641-1true assume !(0 == ~E_1~0); 188#L646-1true assume 0 == ~E_2~0;~E_2~0 := 1; 498#L651-1true assume !(0 == ~E_3~0); 444#L656-1true assume !(0 == ~E_4~0); 362#L661-1true assume !(0 == ~E_5~0); 407#L666-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 530#L304true assume !(1 == ~m_pc~0); 104#L304-2true is_master_triggered_~__retres1~0#1 := 0; 52#L315true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 156#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27#L755true assume !(0 != activate_threads_~tmp~1#1); 553#L755-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6#L323true assume 1 == ~t1_pc~0; 309#L324true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35#L334true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 499#L763true assume !(0 != activate_threads_~tmp___0~0#1); 510#L763-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37#L342true assume 1 == ~t2_pc~0; 524#L343true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 110#L353true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 532#L771true assume !(0 != activate_threads_~tmp___1~0#1); 355#L771-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238#L361true assume !(1 == ~t3_pc~0); 256#L361-2true is_transmit3_triggered_~__retres1~3#1 := 0; 463#L372true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 435#L779true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45#L779-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237#L380true assume 1 == ~t4_pc~0; 77#L381true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 375#L391true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270#L787true assume !(0 != activate_threads_~tmp___3~0#1); 522#L787-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78#L399true assume !(1 == ~t5_pc~0); 159#L399-2true is_transmit5_triggered_~__retres1~5#1 := 0; 387#L410true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 154#L795true assume !(0 != activate_threads_~tmp___4~0#1); 458#L795-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 533#L679true assume !(1 == ~M_E~0); 206#L679-2true assume !(1 == ~T1_E~0); 117#L684-1true assume !(1 == ~T2_E~0); 244#L689-1true assume !(1 == ~T3_E~0); 544#L694-1true assume !(1 == ~T4_E~0); 243#L699-1true assume !(1 == ~T5_E~0); 363#L704-1true assume !(1 == ~E_M~0); 224#L709-1true assume 1 == ~E_1~0;~E_1~0 := 2; 180#L714-1true assume !(1 == ~E_2~0); 344#L719-1true assume !(1 == ~E_3~0); 483#L724-1true assume !(1 == ~E_4~0); 59#L729-1true assume !(1 == ~E_5~0); 465#L734-1true assume { :end_inline_reset_delta_events } true; 333#L940-2true [2023-11-26 11:51:13,566 INFO L750 eck$LassoCheckResult]: Loop: 333#L940-2true assume !false; 402#L941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 447#L586-1true assume false; 96#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 412#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 303#L611-3true assume 0 == ~M_E~0;~M_E~0 := 1; 60#L611-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 319#L616-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 57#L621-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 30#L626-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 563#L631-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 31#L636-3true assume 0 == ~E_M~0;~E_M~0 := 1; 66#L641-3true assume !(0 == ~E_1~0); 240#L646-3true assume 0 == ~E_2~0;~E_2~0 := 1; 72#L651-3true assume 0 == ~E_3~0;~E_3~0 := 1; 218#L656-3true assume 0 == ~E_4~0;~E_4~0 := 1; 500#L661-3true assume 0 == ~E_5~0;~E_5~0 := 1; 512#L666-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157#L304-21true assume 1 == ~m_pc~0; 519#L305-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 267#L315-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 197#L755-21true assume !(0 != activate_threads_~tmp~1#1); 220#L755-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 495#L323-21true assume !(1 == ~t1_pc~0); 372#L323-23true is_transmit1_triggered_~__retres1~1#1 := 0; 408#L334-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 403#L763-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 423#L763-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560#L342-21true assume 1 == ~t2_pc~0; 25#L343-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 261#L353-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 205#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 357#L771-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79#L771-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 478#L361-21true assume !(1 == ~t3_pc~0); 460#L361-23true is_transmit3_triggered_~__retres1~3#1 := 0; 482#L372-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 178#L779-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29#L779-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 518#L380-21true assume 1 == ~t4_pc~0; 432#L381-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99#L391-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 454#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 343#L787-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 271#L787-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144#L399-21true assume 1 == ~t5_pc~0; 129#L400-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 286#L410-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 255#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 505#L795-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 451#L795-23true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26#L679-3true assume 1 == ~M_E~0;~M_E~0 := 2; 185#L679-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 230#L684-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 2#L689-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 168#L694-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 21#L699-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 307#L704-3true assume !(1 == ~E_M~0); 400#L709-3true assume 1 == ~E_1~0;~E_1~0 := 2; 291#L714-3true assume 1 == ~E_2~0;~E_2~0 := 2; 162#L719-3true assume 1 == ~E_3~0;~E_3~0 := 2; 20#L724-3true assume 1 == ~E_4~0;~E_4~0 := 2; 276#L729-3true assume 1 == ~E_5~0;~E_5~0 := 2; 326#L734-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 34#L464-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 219#L496-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 250#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 253#L959true assume !(0 == start_simulation_~tmp~3#1); 517#L959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 182#L464-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 384#L496-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 373#L914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128#L921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 422#stop_simulation_returnLabel#1true start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 308#L972true assume !(0 != start_simulation_~tmp___0~1#1); 333#L940-2true [2023-11-26 11:51:13,573 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:13,573 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2023-11-26 11:51:13,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:13,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425423683] [2023-11-26 11:51:13,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:13,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:13,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:13,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:13,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:13,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425423683] [2023-11-26 11:51:13,892 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425423683] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:13,892 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:13,892 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:13,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1739352891] [2023-11-26 11:51:13,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:13,899 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:13,900 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:13,900 INFO L85 PathProgramCache]: Analyzing trace with hash -2069699191, now seen corresponding path program 1 times [2023-11-26 11:51:13,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:13,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [419158509] [2023-11-26 11:51:13,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:13,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:13,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:13,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:13,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:13,981 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [419158509] [2023-11-26 11:51:13,982 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [419158509] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:13,982 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:13,982 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:51:13,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [512958023] [2023-11-26 11:51:13,983 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:13,984 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:13,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:14,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:14,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:14,045 INFO L87 Difference]: Start difference. First operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:14,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:14,136 INFO L93 Difference]: Finished difference Result 563 states and 839 transitions. [2023-11-26 11:51:14,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 563 states and 839 transitions. [2023-11-26 11:51:14,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-26 11:51:14,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 563 states to 557 states and 833 transitions. [2023-11-26 11:51:14,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-26 11:51:14,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-26 11:51:14,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 833 transitions. [2023-11-26 11:51:14,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:14,182 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 833 transitions. [2023-11-26 11:51:14,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 833 transitions. [2023-11-26 11:51:14,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2023-11-26 11:51:14,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4955116696588868) internal successors, (833), 556 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:14,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 833 transitions. [2023-11-26 11:51:14,282 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 833 transitions. [2023-11-26 11:51:14,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:14,293 INFO L428 stractBuchiCegarLoop]: Abstraction has 557 states and 833 transitions. [2023-11-26 11:51:14,294 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:51:14,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 833 transitions. [2023-11-26 11:51:14,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-26 11:51:14,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:14,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:14,311 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:14,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:14,314 INFO L748 eck$LassoCheckResult]: Stem: 1478#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1479#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1578#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1579#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1564#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1565#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1421#L431-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1422#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1399#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1400#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1630#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1502#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 1503#L611-2 assume !(0 == ~T1_E~0); 1642#L616-1 assume !(0 == ~T2_E~0); 1643#L621-1 assume !(0 == ~T3_E~0); 1267#L626-1 assume !(0 == ~T4_E~0); 1268#L631-1 assume !(0 == ~T5_E~0); 1459#L636-1 assume !(0 == ~E_M~0); 1319#L641-1 assume !(0 == ~E_1~0); 1320#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1476#L651-1 assume !(0 == ~E_3~0); 1671#L656-1 assume !(0 == ~E_4~0); 1628#L661-1 assume !(0 == ~E_5~0); 1629#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1655#L304 assume !(1 == ~m_pc~0); 1345#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1242#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1243#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1193#L755 assume !(0 != activate_threads_~tmp~1#1); 1194#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1149#L323 assume 1 == ~t1_pc~0; 1150#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1212#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1213#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1228#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1691#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1215#L342 assume 1 == ~t2_pc~0; 1216#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1351#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1352#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1580#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1625#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1535#L361 assume !(1 == ~t3_pc~0); 1536#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1560#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1165#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1166#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1233#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1234#L380 assume 1 == ~t4_pc~0; 1289#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1290#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1314#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1315#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1567#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1292#L399 assume !(1 == ~t5_pc~0); 1293#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1431#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1436#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1423#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1424#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1680#L679 assume !(1 == ~M_E~0); 1500#L679-2 assume !(1 == ~T1_E~0); 1364#L684-1 assume !(1 == ~T2_E~0); 1365#L689-1 assume !(1 == ~T3_E~0); 1543#L694-1 assume !(1 == ~T4_E~0); 1541#L699-1 assume !(1 == ~T5_E~0); 1542#L704-1 assume !(1 == ~E_M~0); 1525#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1466#L714-1 assume !(1 == ~E_2~0); 1467#L719-1 assume !(1 == ~E_3~0); 1621#L724-1 assume !(1 == ~E_4~0); 1253#L729-1 assume !(1 == ~E_5~0); 1254#L734-1 assume { :end_inline_reset_delta_events } true; 1597#L940-2 [2023-11-26 11:51:14,315 INFO L750 eck$LassoCheckResult]: Loop: 1597#L940-2 assume !false; 1611#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1327#L586-1 assume !false; 1674#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1677#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1538#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1539#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1534#L511 assume !(0 != eval_~tmp~0#1); 1330#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1331#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1591#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1255#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1256#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1251#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1200#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1201#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1202#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1203#L641-3 assume !(0 == ~E_1~0); 1269#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1279#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1280#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1519#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1692#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1428#L304-21 assume !(1 == ~m_pc~0); 1282#L304-23 is_master_triggered_~__retres1~0#1 := 0; 1283#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1358#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1359#L755-21 assume !(0 != activate_threads_~tmp~1#1); 1487#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1521#L323-21 assume 1 == ~t1_pc~0; 1162#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1163#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1301#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1302#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1653#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1664#L342-21 assume 1 == ~t2_pc~0; 1188#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1189#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1498#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1499#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1295#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1296#L361-21 assume !(1 == ~t3_pc~0); 1681#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 1682#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1686#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1462#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1198#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1199#L380-21 assume 1 == ~t4_pc~0; 1670#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1262#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1337#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1618#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1568#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1409#L399-21 assume !(1 == ~t5_pc~0); 1265#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 1266#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1558#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1559#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1676#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1191#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1192#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1472#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1139#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1140#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1180#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1181#L704-3 assume !(1 == ~E_M~0); 1595#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1586#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1433#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1178#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1179#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1574#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1209#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1210#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1520#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1553#L959 assume !(0 == start_simulation_~tmp~3#1); 1557#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1463#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1464#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1224#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1225#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1383#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1384#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1596#L972 assume !(0 != start_simulation_~tmp___0~1#1); 1597#L940-2 [2023-11-26 11:51:14,316 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:14,316 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2023-11-26 11:51:14,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:14,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544864277] [2023-11-26 11:51:14,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:14,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:14,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:14,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:14,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:14,464 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544864277] [2023-11-26 11:51:14,464 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1544864277] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:14,465 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:14,465 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:14,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [68612076] [2023-11-26 11:51:14,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:14,466 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:14,466 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:14,467 INFO L85 PathProgramCache]: Analyzing trace with hash -803035657, now seen corresponding path program 1 times [2023-11-26 11:51:14,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:14,467 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557953373] [2023-11-26 11:51:14,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:14,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:14,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:14,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:14,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:14,580 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557953373] [2023-11-26 11:51:14,580 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557953373] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:14,580 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:14,580 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:14,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262239647] [2023-11-26 11:51:14,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:14,581 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:14,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:14,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:14,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:14,583 INFO L87 Difference]: Start difference. First operand 557 states and 833 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:14,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:14,605 INFO L93 Difference]: Finished difference Result 557 states and 832 transitions. [2023-11-26 11:51:14,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 832 transitions. [2023-11-26 11:51:14,610 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-26 11:51:14,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 832 transitions. [2023-11-26 11:51:14,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-26 11:51:14,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-26 11:51:14,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 832 transitions. [2023-11-26 11:51:14,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:14,618 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 832 transitions. [2023-11-26 11:51:14,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 832 transitions. [2023-11-26 11:51:14,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2023-11-26 11:51:14,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4937163375224416) internal successors, (832), 556 states have internal predecessors, (832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:14,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 832 transitions. [2023-11-26 11:51:14,634 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 832 transitions. [2023-11-26 11:51:14,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:14,636 INFO L428 stractBuchiCegarLoop]: Abstraction has 557 states and 832 transitions. [2023-11-26 11:51:14,636 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:51:14,636 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 832 transitions. [2023-11-26 11:51:14,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-26 11:51:14,640 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:14,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:14,642 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:14,642 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:14,643 INFO L748 eck$LassoCheckResult]: Stem: 2599#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2600#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2685#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 2686#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2542#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2543#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2520#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2521#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2751#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2623#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 2624#L611-2 assume !(0 == ~T1_E~0); 2763#L616-1 assume !(0 == ~T2_E~0); 2764#L621-1 assume !(0 == ~T3_E~0); 2388#L626-1 assume !(0 == ~T4_E~0); 2389#L631-1 assume !(0 == ~T5_E~0); 2583#L636-1 assume !(0 == ~E_M~0); 2440#L641-1 assume !(0 == ~E_1~0); 2441#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2597#L651-1 assume !(0 == ~E_3~0); 2792#L656-1 assume !(0 == ~E_4~0); 2749#L661-1 assume !(0 == ~E_5~0); 2750#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2776#L304 assume !(1 == ~m_pc~0); 2467#L304-2 is_master_triggered_~__retres1~0#1 := 0; 2363#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2364#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2316#L755 assume !(0 != activate_threads_~tmp~1#1); 2317#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2270#L323 assume 1 == ~t1_pc~0; 2271#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2333#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2334#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2349#L763 assume !(0 != activate_threads_~tmp___0~0#1); 2812#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2340#L342 assume 1 == ~t2_pc~0; 2341#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2472#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2473#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2701#L771 assume !(0 != activate_threads_~tmp___1~0#1); 2746#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2656#L361 assume !(1 == ~t3_pc~0); 2657#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2681#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2286#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2287#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2354#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2355#L380 assume 1 == ~t4_pc~0; 2410#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2411#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2436#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2437#L787 assume !(0 != activate_threads_~tmp___3~0#1); 2688#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2413#L399 assume !(1 == ~t5_pc~0); 2414#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2552#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2557#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2544#L795 assume !(0 != activate_threads_~tmp___4~0#1); 2545#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2801#L679 assume !(1 == ~M_E~0); 2621#L679-2 assume !(1 == ~T1_E~0); 2485#L684-1 assume !(1 == ~T2_E~0); 2486#L689-1 assume !(1 == ~T3_E~0); 2664#L694-1 assume !(1 == ~T4_E~0); 2662#L699-1 assume !(1 == ~T5_E~0); 2663#L704-1 assume !(1 == ~E_M~0); 2646#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2587#L714-1 assume !(1 == ~E_2~0); 2588#L719-1 assume !(1 == ~E_3~0); 2742#L724-1 assume !(1 == ~E_4~0); 2374#L729-1 assume !(1 == ~E_5~0); 2375#L734-1 assume { :end_inline_reset_delta_events } true; 2718#L940-2 [2023-11-26 11:51:14,643 INFO L750 eck$LassoCheckResult]: Loop: 2718#L940-2 assume !false; 2732#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2448#L586-1 assume !false; 2795#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2798#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2659#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2660#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2655#L511 assume !(0 != eval_~tmp~0#1); 2451#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2452#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2712#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2376#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2377#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2373#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2321#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2322#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2323#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2324#L641-3 assume !(0 == ~E_1~0); 2390#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2400#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2401#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2640#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2813#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2549#L304-21 assume !(1 == ~m_pc~0); 2403#L304-23 is_master_triggered_~__retres1~0#1 := 0; 2404#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2479#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2480#L755-21 assume !(0 != activate_threads_~tmp~1#1); 2608#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2642#L323-21 assume 1 == ~t1_pc~0; 2283#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2284#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2422#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2423#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2774#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2785#L342-21 assume 1 == ~t2_pc~0; 2309#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2310#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2617#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2618#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2416#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2417#L361-21 assume !(1 == ~t3_pc~0); 2802#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2803#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2807#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2582#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2314#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2315#L380-21 assume 1 == ~t4_pc~0; 2791#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2381#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2456#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2739#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2689#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2530#L399-21 assume !(1 == ~t5_pc~0); 2386#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 2387#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2679#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2680#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2797#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2312#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2313#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2593#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2260#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2261#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2301#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2302#L704-3 assume !(1 == ~E_M~0); 2716#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2707#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2554#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2299#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2300#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2695#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2330#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2331#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2641#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2674#L959 assume !(0 == start_simulation_~tmp~3#1); 2678#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2584#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2585#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2345#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2346#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2504#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2505#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2717#L972 assume !(0 != start_simulation_~tmp___0~1#1); 2718#L940-2 [2023-11-26 11:51:14,644 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:14,644 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2023-11-26 11:51:14,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:14,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089744911] [2023-11-26 11:51:14,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:14,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:14,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:14,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:14,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:14,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089744911] [2023-11-26 11:51:14,701 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089744911] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:14,702 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:14,702 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:14,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [432100787] [2023-11-26 11:51:14,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:14,703 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:14,703 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:14,703 INFO L85 PathProgramCache]: Analyzing trace with hash -803035657, now seen corresponding path program 2 times [2023-11-26 11:51:14,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:14,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757641879] [2023-11-26 11:51:14,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:14,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:14,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:14,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:14,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:14,771 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757641879] [2023-11-26 11:51:14,771 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757641879] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:14,771 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:14,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:14,772 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44221472] [2023-11-26 11:51:14,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:14,772 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:14,773 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:14,773 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:14,773 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:14,774 INFO L87 Difference]: Start difference. First operand 557 states and 832 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:14,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:14,806 INFO L93 Difference]: Finished difference Result 557 states and 831 transitions. [2023-11-26 11:51:14,807 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 831 transitions. [2023-11-26 11:51:14,812 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-26 11:51:14,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 831 transitions. [2023-11-26 11:51:14,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-26 11:51:14,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-26 11:51:14,818 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 831 transitions. [2023-11-26 11:51:14,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:14,820 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 831 transitions. [2023-11-26 11:51:14,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 831 transitions. [2023-11-26 11:51:14,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2023-11-26 11:51:14,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4919210053859964) internal successors, (831), 556 states have internal predecessors, (831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:14,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 831 transitions. [2023-11-26 11:51:14,835 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 831 transitions. [2023-11-26 11:51:14,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:14,838 INFO L428 stractBuchiCegarLoop]: Abstraction has 557 states and 831 transitions. [2023-11-26 11:51:14,838 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:51:14,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 831 transitions. [2023-11-26 11:51:14,844 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-26 11:51:14,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:14,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:14,847 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:14,847 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:14,849 INFO L748 eck$LassoCheckResult]: Stem: 3720#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3820#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3821#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3806#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 3807#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3663#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3664#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3641#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3642#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3872#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3744#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 3745#L611-2 assume !(0 == ~T1_E~0); 3885#L616-1 assume !(0 == ~T2_E~0); 3886#L621-1 assume !(0 == ~T3_E~0); 3509#L626-1 assume !(0 == ~T4_E~0); 3510#L631-1 assume !(0 == ~T5_E~0); 3704#L636-1 assume !(0 == ~E_M~0); 3561#L641-1 assume !(0 == ~E_1~0); 3562#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3718#L651-1 assume !(0 == ~E_3~0); 3913#L656-1 assume !(0 == ~E_4~0); 3870#L661-1 assume !(0 == ~E_5~0); 3871#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3897#L304 assume !(1 == ~m_pc~0); 3590#L304-2 is_master_triggered_~__retres1~0#1 := 0; 3484#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3485#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3437#L755 assume !(0 != activate_threads_~tmp~1#1); 3438#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3391#L323 assume 1 == ~t1_pc~0; 3392#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3454#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3455#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3470#L763 assume !(0 != activate_threads_~tmp___0~0#1); 3933#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3461#L342 assume 1 == ~t2_pc~0; 3462#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3593#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3594#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3822#L771 assume !(0 != activate_threads_~tmp___1~0#1); 3867#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3777#L361 assume !(1 == ~t3_pc~0); 3778#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3802#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3407#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3408#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3475#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3476#L380 assume 1 == ~t4_pc~0; 3531#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3532#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3557#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3558#L787 assume !(0 != activate_threads_~tmp___3~0#1); 3809#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3534#L399 assume !(1 == ~t5_pc~0); 3535#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3674#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3678#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3665#L795 assume !(0 != activate_threads_~tmp___4~0#1); 3666#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3922#L679 assume !(1 == ~M_E~0); 3743#L679-2 assume !(1 == ~T1_E~0); 3606#L684-1 assume !(1 == ~T2_E~0); 3607#L689-1 assume !(1 == ~T3_E~0); 3785#L694-1 assume !(1 == ~T4_E~0); 3783#L699-1 assume !(1 == ~T5_E~0); 3784#L704-1 assume !(1 == ~E_M~0); 3767#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3708#L714-1 assume !(1 == ~E_2~0); 3709#L719-1 assume !(1 == ~E_3~0); 3863#L724-1 assume !(1 == ~E_4~0); 3495#L729-1 assume !(1 == ~E_5~0); 3496#L734-1 assume { :end_inline_reset_delta_events } true; 3839#L940-2 [2023-11-26 11:51:14,850 INFO L750 eck$LassoCheckResult]: Loop: 3839#L940-2 assume !false; 3853#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3569#L586-1 assume !false; 3916#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3919#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3780#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3781#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3776#L511 assume !(0 != eval_~tmp~0#1); 3572#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3573#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3833#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3497#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3498#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3494#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3442#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3443#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3444#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3445#L641-3 assume !(0 == ~E_1~0); 3511#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3521#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3522#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3761#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3934#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3670#L304-21 assume !(1 == ~m_pc~0); 3524#L304-23 is_master_triggered_~__retres1~0#1 := 0; 3525#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3600#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3601#L755-21 assume !(0 != activate_threads_~tmp~1#1); 3729#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3763#L323-21 assume 1 == ~t1_pc~0; 3404#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3405#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3543#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3544#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3895#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3906#L342-21 assume 1 == ~t2_pc~0; 3430#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3431#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3738#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3739#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3537#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3538#L361-21 assume !(1 == ~t3_pc~0); 3923#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 3924#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3928#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3703#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3435#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3436#L380-21 assume 1 == ~t4_pc~0; 3912#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3504#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3577#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3861#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3810#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3651#L399-21 assume !(1 == ~t5_pc~0); 3507#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 3508#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3800#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3801#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3918#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3433#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3434#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3714#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3381#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3382#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3422#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3423#L704-3 assume !(1 == ~E_M~0); 3837#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3828#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3675#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3420#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3421#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3818#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3451#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3452#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3762#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3795#L959 assume !(0 == start_simulation_~tmp~3#1); 3799#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3705#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3706#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3466#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3467#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3625#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3626#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3838#L972 assume !(0 != start_simulation_~tmp___0~1#1); 3839#L940-2 [2023-11-26 11:51:14,850 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:14,851 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2023-11-26 11:51:14,851 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:14,853 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [835462148] [2023-11-26 11:51:14,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:14,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:14,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:14,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:14,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:14,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [835462148] [2023-11-26 11:51:14,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [835462148] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:14,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:14,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:14,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631869928] [2023-11-26 11:51:14,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:14,951 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:14,952 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:14,952 INFO L85 PathProgramCache]: Analyzing trace with hash -803035657, now seen corresponding path program 3 times [2023-11-26 11:51:14,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:14,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364180830] [2023-11-26 11:51:14,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:14,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:14,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:15,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:15,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:15,035 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364180830] [2023-11-26 11:51:15,035 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364180830] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:15,036 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:15,036 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:15,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749814490] [2023-11-26 11:51:15,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:15,037 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:15,037 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:15,038 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:15,038 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:15,038 INFO L87 Difference]: Start difference. First operand 557 states and 831 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:15,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:15,059 INFO L93 Difference]: Finished difference Result 557 states and 830 transitions. [2023-11-26 11:51:15,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 830 transitions. [2023-11-26 11:51:15,064 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-26 11:51:15,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 830 transitions. [2023-11-26 11:51:15,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-26 11:51:15,071 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-26 11:51:15,071 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 830 transitions. [2023-11-26 11:51:15,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:15,073 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 830 transitions. [2023-11-26 11:51:15,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 830 transitions. [2023-11-26 11:51:15,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2023-11-26 11:51:15,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4901256732495511) internal successors, (830), 556 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:15,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 830 transitions. [2023-11-26 11:51:15,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 830 transitions. [2023-11-26 11:51:15,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:15,090 INFO L428 stractBuchiCegarLoop]: Abstraction has 557 states and 830 transitions. [2023-11-26 11:51:15,091 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:51:15,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 830 transitions. [2023-11-26 11:51:15,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-26 11:51:15,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:15,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:15,103 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:15,106 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:15,106 INFO L748 eck$LassoCheckResult]: Stem: 4841#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4941#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4942#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4927#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 4928#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4784#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4785#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4762#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4763#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4993#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4865#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 4866#L611-2 assume !(0 == ~T1_E~0); 5006#L616-1 assume !(0 == ~T2_E~0); 5007#L621-1 assume !(0 == ~T3_E~0); 4634#L626-1 assume !(0 == ~T4_E~0); 4635#L631-1 assume !(0 == ~T5_E~0); 4825#L636-1 assume !(0 == ~E_M~0); 4685#L641-1 assume !(0 == ~E_1~0); 4686#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4839#L651-1 assume !(0 == ~E_3~0); 5034#L656-1 assume !(0 == ~E_4~0); 4991#L661-1 assume !(0 == ~E_5~0); 4992#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5018#L304 assume !(1 == ~m_pc~0); 4712#L304-2 is_master_triggered_~__retres1~0#1 := 0; 4605#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4606#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4558#L755 assume !(0 != activate_threads_~tmp~1#1); 4559#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4514#L323 assume 1 == ~t1_pc~0; 4515#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4575#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4576#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4591#L763 assume !(0 != activate_threads_~tmp___0~0#1); 5054#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4584#L342 assume 1 == ~t2_pc~0; 4585#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4714#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4715#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4943#L771 assume !(0 != activate_threads_~tmp___1~0#1); 4988#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4898#L361 assume !(1 == ~t3_pc~0); 4899#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4923#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4528#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4529#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4596#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4597#L380 assume 1 == ~t4_pc~0; 4652#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4653#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4680#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4681#L787 assume !(0 != activate_threads_~tmp___3~0#1); 4930#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4655#L399 assume !(1 == ~t5_pc~0); 4656#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4795#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4799#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4786#L795 assume !(0 != activate_threads_~tmp___4~0#1); 4787#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5043#L679 assume !(1 == ~M_E~0); 4864#L679-2 assume !(1 == ~T1_E~0); 4727#L684-1 assume !(1 == ~T2_E~0); 4728#L689-1 assume !(1 == ~T3_E~0); 4906#L694-1 assume !(1 == ~T4_E~0); 4904#L699-1 assume !(1 == ~T5_E~0); 4905#L704-1 assume !(1 == ~E_M~0); 4888#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4830#L714-1 assume !(1 == ~E_2~0); 4831#L719-1 assume !(1 == ~E_3~0); 4984#L724-1 assume !(1 == ~E_4~0); 4616#L729-1 assume !(1 == ~E_5~0); 4617#L734-1 assume { :end_inline_reset_delta_events } true; 4961#L940-2 [2023-11-26 11:51:15,106 INFO L750 eck$LassoCheckResult]: Loop: 4961#L940-2 assume !false; 4974#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4690#L586-1 assume !false; 5037#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5040#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4901#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4902#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4897#L511 assume !(0 != eval_~tmp~0#1); 4693#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4694#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4954#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4618#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4619#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4615#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4563#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4564#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4565#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4566#L641-3 assume !(0 == ~E_1~0); 4628#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4642#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4643#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4881#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5055#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4791#L304-21 assume !(1 == ~m_pc~0); 4645#L304-23 is_master_triggered_~__retres1~0#1 := 0; 4646#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4721#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4722#L755-21 assume !(0 != activate_threads_~tmp~1#1); 4850#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4884#L323-21 assume 1 == ~t1_pc~0; 4525#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4526#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4664#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4665#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5016#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5027#L342-21 assume 1 == ~t2_pc~0; 4551#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4552#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4861#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4862#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4658#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4659#L361-21 assume !(1 == ~t3_pc~0); 5044#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 5045#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5049#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4824#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4556#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4557#L380-21 assume !(1 == ~t4_pc~0); 4624#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4625#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4698#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4982#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4931#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4772#L399-21 assume !(1 == ~t5_pc~0); 4632#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4633#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4921#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4922#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5039#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4554#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4555#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4835#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4502#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4503#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4543#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4544#L704-3 assume !(1 == ~E_M~0); 4959#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4949#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4796#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4541#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4542#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4939#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4572#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4573#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4883#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4916#L959 assume !(0 == start_simulation_~tmp~3#1); 4920#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4827#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4828#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4589#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4590#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4746#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4747#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4960#L972 assume !(0 != start_simulation_~tmp___0~1#1); 4961#L940-2 [2023-11-26 11:51:15,107 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:15,107 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2023-11-26 11:51:15,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:15,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95860002] [2023-11-26 11:51:15,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:15,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:15,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:15,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:15,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:15,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [95860002] [2023-11-26 11:51:15,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [95860002] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:15,174 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:15,174 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:15,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1616617528] [2023-11-26 11:51:15,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:15,176 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:15,176 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:15,177 INFO L85 PathProgramCache]: Analyzing trace with hash 322224312, now seen corresponding path program 1 times [2023-11-26 11:51:15,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:15,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623528126] [2023-11-26 11:51:15,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:15,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:15,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:15,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:15,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:15,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1623528126] [2023-11-26 11:51:15,262 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1623528126] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:15,262 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:15,262 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:15,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55282535] [2023-11-26 11:51:15,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:15,263 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:15,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:15,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:15,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:15,264 INFO L87 Difference]: Start difference. First operand 557 states and 830 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:15,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:15,286 INFO L93 Difference]: Finished difference Result 557 states and 829 transitions. [2023-11-26 11:51:15,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 829 transitions. [2023-11-26 11:51:15,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-26 11:51:15,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 829 transitions. [2023-11-26 11:51:15,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-26 11:51:15,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-26 11:51:15,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 829 transitions. [2023-11-26 11:51:15,299 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:15,300 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 829 transitions. [2023-11-26 11:51:15,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 829 transitions. [2023-11-26 11:51:15,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2023-11-26 11:51:15,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.488330341113106) internal successors, (829), 556 states have internal predecessors, (829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:15,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 829 transitions. [2023-11-26 11:51:15,314 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 829 transitions. [2023-11-26 11:51:15,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:15,317 INFO L428 stractBuchiCegarLoop]: Abstraction has 557 states and 829 transitions. [2023-11-26 11:51:15,317 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:51:15,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 829 transitions. [2023-11-26 11:51:15,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2023-11-26 11:51:15,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:15,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:15,324 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:15,325 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:15,325 INFO L748 eck$LassoCheckResult]: Stem: 5962#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5963#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6062#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6063#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6048#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 6049#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5905#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5906#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5883#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5884#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6114#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5986#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 5987#L611-2 assume !(0 == ~T1_E~0); 6127#L616-1 assume !(0 == ~T2_E~0); 6128#L621-1 assume !(0 == ~T3_E~0); 5755#L626-1 assume !(0 == ~T4_E~0); 5756#L631-1 assume !(0 == ~T5_E~0); 5946#L636-1 assume !(0 == ~E_M~0); 5806#L641-1 assume !(0 == ~E_1~0); 5807#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5960#L651-1 assume !(0 == ~E_3~0); 6155#L656-1 assume !(0 == ~E_4~0); 6112#L661-1 assume !(0 == ~E_5~0); 6113#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6139#L304 assume !(1 == ~m_pc~0); 5833#L304-2 is_master_triggered_~__retres1~0#1 := 0; 5726#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5727#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5682#L755 assume !(0 != activate_threads_~tmp~1#1); 5683#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5635#L323 assume 1 == ~t1_pc~0; 5636#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5696#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5697#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5712#L763 assume !(0 != activate_threads_~tmp___0~0#1); 6175#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5705#L342 assume 1 == ~t2_pc~0; 5706#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5835#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5836#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6064#L771 assume !(0 != activate_threads_~tmp___1~0#1); 6109#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6019#L361 assume !(1 == ~t3_pc~0); 6020#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6044#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5649#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5650#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5717#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5718#L380 assume 1 == ~t4_pc~0; 5776#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5777#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5798#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5799#L787 assume !(0 != activate_threads_~tmp___3~0#1); 6051#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5773#L399 assume !(1 == ~t5_pc~0); 5774#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5915#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5920#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5907#L795 assume !(0 != activate_threads_~tmp___4~0#1); 5908#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6164#L679 assume !(1 == ~M_E~0); 5984#L679-2 assume !(1 == ~T1_E~0); 5848#L684-1 assume !(1 == ~T2_E~0); 5849#L689-1 assume !(1 == ~T3_E~0); 6027#L694-1 assume !(1 == ~T4_E~0); 6025#L699-1 assume !(1 == ~T5_E~0); 6026#L704-1 assume !(1 == ~E_M~0); 6009#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5947#L714-1 assume !(1 == ~E_2~0); 5948#L719-1 assume !(1 == ~E_3~0); 6105#L724-1 assume !(1 == ~E_4~0); 5737#L729-1 assume !(1 == ~E_5~0); 5738#L734-1 assume { :end_inline_reset_delta_events } true; 6082#L940-2 [2023-11-26 11:51:15,325 INFO L750 eck$LassoCheckResult]: Loop: 6082#L940-2 assume !false; 6095#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5811#L586-1 assume !false; 6157#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6161#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6022#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6023#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6018#L511 assume !(0 != eval_~tmp~0#1); 5814#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5815#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6075#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5739#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5740#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5735#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5684#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5685#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5686#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5687#L641-3 assume !(0 == ~E_1~0); 5749#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5763#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5764#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6003#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6176#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5912#L304-21 assume !(1 == ~m_pc~0); 5766#L304-23 is_master_triggered_~__retres1~0#1 := 0; 5767#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5842#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5843#L755-21 assume !(0 != activate_threads_~tmp~1#1); 5971#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6005#L323-21 assume !(1 == ~t1_pc~0); 5648#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 5647#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5785#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5786#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6137#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6148#L342-21 assume 1 == ~t2_pc~0; 5672#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5673#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5982#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5983#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5779#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5780#L361-21 assume !(1 == ~t3_pc~0); 6165#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 6166#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6170#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5945#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5680#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5681#L380-21 assume !(1 == ~t4_pc~0); 5745#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5746#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5819#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6104#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6052#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5893#L399-21 assume !(1 == ~t5_pc~0); 5753#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5754#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6042#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6043#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6160#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5675#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5676#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5956#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5623#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5624#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5664#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5665#L704-3 assume !(1 == ~E_M~0); 6080#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6070#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5917#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5662#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5663#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6060#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5693#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5694#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6004#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6037#L959 assume !(0 == start_simulation_~tmp~3#1); 6041#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5950#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5951#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5711#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5867#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5868#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6081#L972 assume !(0 != start_simulation_~tmp___0~1#1); 6082#L940-2 [2023-11-26 11:51:15,326 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:15,326 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2023-11-26 11:51:15,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:15,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088585164] [2023-11-26 11:51:15,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:15,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:15,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:15,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:15,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:15,433 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088585164] [2023-11-26 11:51:15,438 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088585164] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:15,438 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:15,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:51:15,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039563657] [2023-11-26 11:51:15,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:15,439 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:15,439 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:15,439 INFO L85 PathProgramCache]: Analyzing trace with hash -785904327, now seen corresponding path program 1 times [2023-11-26 11:51:15,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:15,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704222965] [2023-11-26 11:51:15,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:15,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:15,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:15,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:15,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:15,492 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704222965] [2023-11-26 11:51:15,492 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [704222965] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:15,492 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:15,492 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:15,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071672654] [2023-11-26 11:51:15,492 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:15,493 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:15,493 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:15,494 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:15,494 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:15,494 INFO L87 Difference]: Start difference. First operand 557 states and 829 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:15,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:15,562 INFO L93 Difference]: Finished difference Result 991 states and 1469 transitions. [2023-11-26 11:51:15,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 991 states and 1469 transitions. [2023-11-26 11:51:15,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2023-11-26 11:51:15,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 991 states to 991 states and 1469 transitions. [2023-11-26 11:51:15,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 991 [2023-11-26 11:51:15,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 991 [2023-11-26 11:51:15,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 991 states and 1469 transitions. [2023-11-26 11:51:15,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:15,584 INFO L218 hiAutomatonCegarLoop]: Abstraction has 991 states and 1469 transitions. [2023-11-26 11:51:15,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states and 1469 transitions. [2023-11-26 11:51:15,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 991. [2023-11-26 11:51:15,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 991 states, 991 states have (on average 1.4823410696266397) internal successors, (1469), 990 states have internal predecessors, (1469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:15,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 991 states to 991 states and 1469 transitions. [2023-11-26 11:51:15,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 991 states and 1469 transitions. [2023-11-26 11:51:15,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:15,615 INFO L428 stractBuchiCegarLoop]: Abstraction has 991 states and 1469 transitions. [2023-11-26 11:51:15,616 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:51:15,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 991 states and 1469 transitions. [2023-11-26 11:51:15,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2023-11-26 11:51:15,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:15,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:15,624 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:15,624 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:15,624 INFO L748 eck$LassoCheckResult]: Stem: 7520#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7623#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7624#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7609#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 7610#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7461#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7462#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7439#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7440#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7688#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7544#L611 assume !(0 == ~M_E~0); 7545#L611-2 assume !(0 == ~T1_E~0); 7701#L616-1 assume !(0 == ~T2_E~0); 7702#L621-1 assume !(0 == ~T3_E~0); 7304#L626-1 assume !(0 == ~T4_E~0); 7305#L631-1 assume !(0 == ~T5_E~0); 7500#L636-1 assume !(0 == ~E_M~0); 7359#L641-1 assume !(0 == ~E_1~0); 7360#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7518#L651-1 assume !(0 == ~E_3~0); 7739#L656-1 assume !(0 == ~E_4~0); 7686#L661-1 assume !(0 == ~E_5~0); 7687#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7718#L304 assume !(1 == ~m_pc~0); 7385#L304-2 is_master_triggered_~__retres1~0#1 := 0; 7281#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7282#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7232#L755 assume !(0 != activate_threads_~tmp~1#1); 7233#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7186#L323 assume 1 == ~t1_pc~0; 7187#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7251#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7252#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7267#L763 assume !(0 != activate_threads_~tmp___0~0#1); 7766#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7254#L342 assume 1 == ~t2_pc~0; 7255#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7391#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7392#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7625#L771 assume !(0 != activate_threads_~tmp___1~0#1); 7681#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7579#L361 assume !(1 == ~t3_pc~0); 7580#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7604#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7204#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7205#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7270#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7271#L380 assume 1 == ~t4_pc~0; 7328#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7329#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7354#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7355#L787 assume !(0 != activate_threads_~tmp___3~0#1); 7612#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7331#L399 assume !(1 == ~t5_pc~0); 7332#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7471#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7476#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7463#L795 assume !(0 != activate_threads_~tmp___4~0#1); 7464#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7751#L679 assume !(1 == ~M_E~0); 7542#L679-2 assume !(1 == ~T1_E~0); 7404#L684-1 assume !(1 == ~T2_E~0); 7405#L689-1 assume !(1 == ~T3_E~0); 7587#L694-1 assume !(1 == ~T4_E~0); 7585#L699-1 assume !(1 == ~T5_E~0); 7586#L704-1 assume !(1 == ~E_M~0); 7568#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7504#L714-1 assume !(1 == ~E_2~0); 7505#L719-1 assume !(1 == ~E_3~0); 7676#L724-1 assume !(1 == ~E_4~0); 7292#L729-1 assume !(1 == ~E_5~0); 7293#L734-1 assume { :end_inline_reset_delta_events } true; 7647#L940-2 [2023-11-26 11:51:15,625 INFO L750 eck$LassoCheckResult]: Loop: 7647#L940-2 assume !false; 7715#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7367#L586-1 assume !false; 7784#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7780#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7777#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7638#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7577#L511 assume !(0 != eval_~tmp~0#1); 7370#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7371#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7640#L611-3 assume !(0 == ~M_E~0); 7294#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7295#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7290#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7239#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7240#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7241#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7242#L641-3 assume !(0 == ~E_1~0); 7306#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7318#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7319#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7562#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7767#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7468#L304-21 assume !(1 == ~m_pc~0); 7321#L304-23 is_master_triggered_~__retres1~0#1 := 0; 7322#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7398#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7399#L755-21 assume !(0 != activate_threads_~tmp~1#1); 7529#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7564#L323-21 assume 1 == ~t1_pc~0; 7201#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7202#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7341#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7342#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7716#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7731#L342-21 assume 1 == ~t2_pc~0; 7227#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7228#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7540#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7541#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7334#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7335#L361-21 assume !(1 == ~t3_pc~0); 7752#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 7753#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7760#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7503#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7237#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7238#L380-21 assume !(1 == ~t4_pc~0); 7300#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7301#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7375#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7675#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7613#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7449#L399-21 assume 1 == ~t5_pc~0; 7425#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7311#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7602#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7603#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7745#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7230#L679-3 assume !(1 == ~M_E~0); 7231#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8141#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8140#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8139#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8138#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8137#L704-3 assume !(1 == ~E_M~0); 8136#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8135#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8134#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8133#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8132#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8131#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 8118#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 8114#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 8113#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 8112#L959 assume !(0 == start_simulation_~tmp~3#1); 8110#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 8106#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 8103#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7265#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7266#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7423#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7424#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7646#L972 assume !(0 != start_simulation_~tmp___0~1#1); 7647#L940-2 [2023-11-26 11:51:15,626 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:15,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2023-11-26 11:51:15,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:15,626 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111378757] [2023-11-26 11:51:15,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:15,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:15,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:15,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:15,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:15,677 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [111378757] [2023-11-26 11:51:15,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [111378757] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:15,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:15,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:51:15,679 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [49641822] [2023-11-26 11:51:15,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:15,680 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:15,680 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:15,680 INFO L85 PathProgramCache]: Analyzing trace with hash -1173500553, now seen corresponding path program 1 times [2023-11-26 11:51:15,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:15,681 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1547248033] [2023-11-26 11:51:15,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:15,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:15,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:15,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:15,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:15,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1547248033] [2023-11-26 11:51:15,728 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1547248033] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:15,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:15,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:15,728 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1708257728] [2023-11-26 11:51:15,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:15,729 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:15,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:15,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:15,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:15,730 INFO L87 Difference]: Start difference. First operand 991 states and 1469 transitions. cyclomatic complexity: 479 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:15,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:15,787 INFO L93 Difference]: Finished difference Result 991 states and 1447 transitions. [2023-11-26 11:51:15,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 991 states and 1447 transitions. [2023-11-26 11:51:15,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2023-11-26 11:51:15,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 991 states to 991 states and 1447 transitions. [2023-11-26 11:51:15,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 991 [2023-11-26 11:51:15,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 991 [2023-11-26 11:51:15,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 991 states and 1447 transitions. [2023-11-26 11:51:15,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:15,807 INFO L218 hiAutomatonCegarLoop]: Abstraction has 991 states and 1447 transitions. [2023-11-26 11:51:15,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states and 1447 transitions. [2023-11-26 11:51:15,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 991. [2023-11-26 11:51:15,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 991 states, 991 states have (on average 1.4601412714429869) internal successors, (1447), 990 states have internal predecessors, (1447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:15,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 991 states to 991 states and 1447 transitions. [2023-11-26 11:51:15,836 INFO L240 hiAutomatonCegarLoop]: Abstraction has 991 states and 1447 transitions. [2023-11-26 11:51:15,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:15,839 INFO L428 stractBuchiCegarLoop]: Abstraction has 991 states and 1447 transitions. [2023-11-26 11:51:15,839 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:51:15,840 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 991 states and 1447 transitions. [2023-11-26 11:51:15,846 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2023-11-26 11:51:15,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:15,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:15,847 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:15,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:15,848 INFO L748 eck$LassoCheckResult]: Stem: 9508#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9509#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9612#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9613#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9598#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 9599#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9449#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9450#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9427#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9428#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9677#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9532#L611 assume !(0 == ~M_E~0); 9533#L611-2 assume !(0 == ~T1_E~0); 9691#L616-1 assume !(0 == ~T2_E~0); 9692#L621-1 assume !(0 == ~T3_E~0); 9298#L626-1 assume !(0 == ~T4_E~0); 9299#L631-1 assume !(0 == ~T5_E~0); 9488#L636-1 assume !(0 == ~E_M~0); 9347#L641-1 assume !(0 == ~E_1~0); 9348#L646-1 assume !(0 == ~E_2~0); 9506#L651-1 assume !(0 == ~E_3~0); 9730#L656-1 assume !(0 == ~E_4~0); 9675#L661-1 assume !(0 == ~E_5~0); 9676#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9709#L304 assume !(1 == ~m_pc~0); 9373#L304-2 is_master_triggered_~__retres1~0#1 := 0; 9269#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9270#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9220#L755 assume !(0 != activate_threads_~tmp~1#1); 9221#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9175#L323 assume 1 == ~t1_pc~0; 9176#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9239#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9240#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9255#L763 assume !(0 != activate_threads_~tmp___0~0#1); 9756#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9242#L342 assume !(1 == ~t2_pc~0); 9244#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9379#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9380#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9614#L771 assume !(0 != activate_threads_~tmp___1~0#1); 9671#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9567#L361 assume !(1 == ~t3_pc~0); 9568#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9592#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9193#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9194#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9258#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9259#L380 assume 1 == ~t4_pc~0; 9316#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9317#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9342#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9343#L787 assume !(0 != activate_threads_~tmp___3~0#1); 9601#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9319#L399 assume !(1 == ~t5_pc~0); 9320#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9459#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9464#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9451#L795 assume !(0 != activate_threads_~tmp___4~0#1); 9452#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9741#L679 assume !(1 == ~M_E~0); 9530#L679-2 assume !(1 == ~T1_E~0); 9392#L684-1 assume !(1 == ~T2_E~0); 9393#L689-1 assume !(1 == ~T3_E~0); 9575#L694-1 assume !(1 == ~T4_E~0); 9573#L699-1 assume !(1 == ~T5_E~0); 9574#L704-1 assume !(1 == ~E_M~0); 9556#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9492#L714-1 assume !(1 == ~E_2~0); 9493#L719-1 assume !(1 == ~E_3~0); 9665#L724-1 assume !(1 == ~E_4~0); 9280#L729-1 assume !(1 == ~E_5~0); 9281#L734-1 assume { :end_inline_reset_delta_events } true; 9635#L940-2 [2023-11-26 11:51:15,849 INFO L750 eck$LassoCheckResult]: Loop: 9635#L940-2 assume !false; 9704#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9355#L586-1 assume !false; 9732#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9736#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9570#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9571#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9766#L511 assume !(0 != eval_~tmp~0#1); 9358#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9359#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9628#L611-3 assume !(0 == ~M_E~0); 9282#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9283#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9278#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9227#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9228#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9229#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9230#L641-3 assume !(0 == ~E_1~0); 9292#L646-3 assume !(0 == ~E_2~0); 9306#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9307#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9550#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9757#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9456#L304-21 assume 1 == ~m_pc~0; 9457#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9310#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9386#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9387#L755-21 assume !(0 != activate_threads_~tmp~1#1); 9517#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9552#L323-21 assume 1 == ~t1_pc~0; 9190#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9191#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9329#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9330#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9705#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9722#L342-21 assume !(1 == ~t2_pc~0); 9217#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9596#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9528#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9529#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9322#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9323#L361-21 assume 1 == ~t3_pc~0; 9748#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9743#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9749#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9491#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9225#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9226#L380-21 assume 1 == ~t4_pc~0; 9728#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9289#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9363#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9664#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9602#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9437#L399-21 assume !(1 == ~t5_pc~0); 9296#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 9297#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9618#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10041#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9735#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9218#L679-3 assume !(1 == ~M_E~0); 9219#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10080#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10079#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10078#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10077#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10076#L704-3 assume !(1 == ~E_M~0); 10075#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10074#L714-3 assume !(1 == ~E_2~0); 10073#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10072#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10071#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10070#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10057#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10053#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 10052#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 10051#L959 assume !(0 == start_simulation_~tmp~3#1); 10049#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10045#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10042#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9253#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9254#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9411#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9412#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9634#L972 assume !(0 != start_simulation_~tmp___0~1#1); 9635#L940-2 [2023-11-26 11:51:15,849 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:15,850 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2023-11-26 11:51:15,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:15,851 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049091698] [2023-11-26 11:51:15,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:15,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:15,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:15,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:15,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:15,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049091698] [2023-11-26 11:51:15,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049091698] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:15,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:15,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:51:15,905 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310145020] [2023-11-26 11:51:15,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:15,905 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:15,905 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:15,906 INFO L85 PathProgramCache]: Analyzing trace with hash 740528630, now seen corresponding path program 1 times [2023-11-26 11:51:15,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:15,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760530393] [2023-11-26 11:51:15,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:15,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:15,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:15,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:15,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:15,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760530393] [2023-11-26 11:51:15,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760530393] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:15,975 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:15,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:15,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [85410274] [2023-11-26 11:51:15,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:15,975 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:15,976 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:15,976 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:15,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:15,976 INFO L87 Difference]: Start difference. First operand 991 states and 1447 transitions. cyclomatic complexity: 457 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:16,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:16,064 INFO L93 Difference]: Finished difference Result 1799 states and 2607 transitions. [2023-11-26 11:51:16,065 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1799 states and 2607 transitions. [2023-11-26 11:51:16,080 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1717 [2023-11-26 11:51:16,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1799 states to 1799 states and 2607 transitions. [2023-11-26 11:51:16,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1799 [2023-11-26 11:51:16,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1799 [2023-11-26 11:51:16,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1799 states and 2607 transitions. [2023-11-26 11:51:16,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:16,100 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1799 states and 2607 transitions. [2023-11-26 11:51:16,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1799 states and 2607 transitions. [2023-11-26 11:51:16,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1799 to 1795. [2023-11-26 11:51:16,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1795 states, 1795 states have (on average 1.4501392757660168) internal successors, (2603), 1794 states have internal predecessors, (2603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:16,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1795 states to 1795 states and 2603 transitions. [2023-11-26 11:51:16,171 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1795 states and 2603 transitions. [2023-11-26 11:51:16,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:16,174 INFO L428 stractBuchiCegarLoop]: Abstraction has 1795 states and 2603 transitions. [2023-11-26 11:51:16,174 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 11:51:16,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1795 states and 2603 transitions. [2023-11-26 11:51:16,186 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1713 [2023-11-26 11:51:16,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:16,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:16,187 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:16,187 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:16,188 INFO L748 eck$LassoCheckResult]: Stem: 12314#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12410#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 12411#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12253#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12254#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12230#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12231#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12501#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12341#L611 assume !(0 == ~M_E~0); 12342#L611-2 assume !(0 == ~T1_E~0); 12519#L616-1 assume !(0 == ~T2_E~0); 12520#L621-1 assume !(0 == ~T3_E~0); 12090#L626-1 assume !(0 == ~T4_E~0); 12091#L631-1 assume !(0 == ~T5_E~0); 12293#L636-1 assume !(0 == ~E_M~0); 12145#L641-1 assume !(0 == ~E_1~0); 12146#L646-1 assume !(0 == ~E_2~0); 12311#L651-1 assume !(0 == ~E_3~0); 12568#L656-1 assume !(0 == ~E_4~0); 12499#L661-1 assume !(0 == ~E_5~0); 12500#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12541#L304 assume !(1 == ~m_pc~0); 12172#L304-2 is_master_triggered_~__retres1~0#1 := 0; 12066#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12067#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12016#L755 assume !(0 != activate_threads_~tmp~1#1); 12017#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11972#L323 assume !(1 == ~t1_pc~0); 11973#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12035#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12036#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12051#L763 assume !(0 != activate_threads_~tmp___0~0#1); 12606#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12038#L342 assume !(1 == ~t2_pc~0); 12040#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12178#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12179#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12427#L771 assume !(0 != activate_threads_~tmp___1~0#1); 12492#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12377#L361 assume !(1 == ~t3_pc~0); 12378#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12404#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11989#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11990#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12054#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12055#L380 assume 1 == ~t4_pc~0; 12114#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12115#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12141#L787 assume !(0 != activate_threads_~tmp___3~0#1); 12413#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12117#L399 assume !(1 == ~t5_pc~0); 12118#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12263#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12269#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12255#L795 assume !(0 != activate_threads_~tmp___4~0#1); 12256#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12580#L679 assume !(1 == ~M_E~0); 12339#L679-2 assume !(1 == ~T1_E~0); 12191#L684-1 assume !(1 == ~T2_E~0); 12192#L689-1 assume !(1 == ~T3_E~0); 12385#L694-1 assume !(1 == ~T4_E~0); 12383#L699-1 assume !(1 == ~T5_E~0); 12384#L704-1 assume !(1 == ~E_M~0); 12365#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12297#L714-1 assume !(1 == ~E_2~0); 12298#L719-1 assume !(1 == ~E_3~0); 12487#L724-1 assume !(1 == ~E_4~0); 12078#L729-1 assume !(1 == ~E_5~0); 12079#L734-1 assume { :end_inline_reset_delta_events } true; 12585#L940-2 [2023-11-26 11:51:16,188 INFO L750 eck$LassoCheckResult]: Loop: 12585#L940-2 assume !false; 12876#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12682#L586-1 assume !false; 12683#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12669#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12667#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12661#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12662#L511 assume !(0 != eval_~tmp~0#1); 13373#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12546#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12448#L611-3 assume !(0 == ~M_E~0); 12080#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12081#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12075#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12023#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12024#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12025#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12026#L641-3 assume !(0 == ~E_1~0); 12092#L646-3 assume !(0 == ~E_2~0); 12104#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12105#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12358#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12608#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12260#L304-21 assume 1 == ~m_pc~0; 12261#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12108#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12185#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12186#L755-21 assume !(0 != activate_threads_~tmp~1#1); 12323#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12361#L323-21 assume !(1 == ~t1_pc~0); 12508#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 12509#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12127#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12128#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12538#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12553#L342-21 assume !(1 == ~t2_pc~0); 12013#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 12408#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12337#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12338#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12120#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12121#L361-21 assume 1 == ~t3_pc~0; 12593#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12582#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12595#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12296#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12021#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12022#L380-21 assume 1 == ~t4_pc~0; 12560#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12087#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12162#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12486#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12414#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12240#L399-21 assume !(1 == ~t5_pc~0); 12096#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 12097#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12402#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12403#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12573#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12014#L679-3 assume !(1 == ~M_E~0); 12015#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13564#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13563#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13562#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13561#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13560#L704-3 assume !(1 == ~E_M~0); 13559#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13558#L714-3 assume !(1 == ~E_2~0); 13557#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13556#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13555#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13554#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13550#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13547#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13546#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 13545#L959 assume !(0 == start_simulation_~tmp~3#1); 13543#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12898#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12894#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12892#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 12890#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12885#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12881#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 12882#L972 assume !(0 != start_simulation_~tmp___0~1#1); 12585#L940-2 [2023-11-26 11:51:16,189 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:16,189 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2023-11-26 11:51:16,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:16,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312221338] [2023-11-26 11:51:16,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:16,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:16,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:16,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:16,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:16,274 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312221338] [2023-11-26 11:51:16,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312221338] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:16,275 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:16,275 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:16,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780031053] [2023-11-26 11:51:16,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:16,275 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:16,276 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:16,276 INFO L85 PathProgramCache]: Analyzing trace with hash -367600009, now seen corresponding path program 1 times [2023-11-26 11:51:16,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:16,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351398106] [2023-11-26 11:51:16,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:16,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:16,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:16,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:16,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:16,342 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351398106] [2023-11-26 11:51:16,342 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1351398106] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:16,342 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:16,342 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:16,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1966780015] [2023-11-26 11:51:16,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:16,343 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:16,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:16,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:51:16,343 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:51:16,343 INFO L87 Difference]: Start difference. First operand 1795 states and 2603 transitions. cyclomatic complexity: 810 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:16,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:16,660 INFO L93 Difference]: Finished difference Result 3894 states and 5580 transitions. [2023-11-26 11:51:16,660 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3894 states and 5580 transitions. [2023-11-26 11:51:16,694 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3762 [2023-11-26 11:51:16,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3894 states to 3894 states and 5580 transitions. [2023-11-26 11:51:16,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3894 [2023-11-26 11:51:16,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3894 [2023-11-26 11:51:16,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3894 states and 5580 transitions. [2023-11-26 11:51:16,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:16,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3894 states and 5580 transitions. [2023-11-26 11:51:16,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3894 states and 5580 transitions. [2023-11-26 11:51:16,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3894 to 1882. [2023-11-26 11:51:16,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1882 states, 1882 states have (on average 1.4293304994686504) internal successors, (2690), 1881 states have internal predecessors, (2690), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:16,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1882 states to 1882 states and 2690 transitions. [2023-11-26 11:51:16,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1882 states and 2690 transitions. [2023-11-26 11:51:16,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:51:16,803 INFO L428 stractBuchiCegarLoop]: Abstraction has 1882 states and 2690 transitions. [2023-11-26 11:51:16,803 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 11:51:16,803 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1882 states and 2690 transitions. [2023-11-26 11:51:16,817 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1797 [2023-11-26 11:51:16,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:16,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:16,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:16,819 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:16,820 INFO L748 eck$LassoCheckResult]: Stem: 18025#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 18026#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 18144#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18145#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18129#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 18130#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17962#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17963#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17940#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17941#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18230#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18052#L611 assume !(0 == ~M_E~0); 18053#L611-2 assume !(0 == ~T1_E~0); 18246#L616-1 assume !(0 == ~T2_E~0); 18247#L621-1 assume !(0 == ~T3_E~0); 17795#L626-1 assume !(0 == ~T4_E~0); 17796#L631-1 assume !(0 == ~T5_E~0); 18005#L636-1 assume !(0 == ~E_M~0); 17848#L641-1 assume !(0 == ~E_1~0); 17849#L646-1 assume !(0 == ~E_2~0); 18023#L651-1 assume !(0 == ~E_3~0); 18307#L656-1 assume !(0 == ~E_4~0); 18228#L661-1 assume !(0 == ~E_5~0); 18229#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18271#L304 assume !(1 == ~m_pc~0); 17879#L304-2 is_master_triggered_~__retres1~0#1 := 0; 17769#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17770#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17723#L755 assume !(0 != activate_threads_~tmp~1#1); 17724#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17676#L323 assume !(1 == ~t1_pc~0); 17677#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17737#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17754#L763 assume !(0 != activate_threads_~tmp___0~0#1); 18360#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17747#L342 assume !(1 == ~t2_pc~0); 17749#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17885#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17886#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18146#L771 assume !(0 != activate_threads_~tmp___1~0#1); 18220#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18091#L361 assume !(1 == ~t3_pc~0); 18092#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18119#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18327#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18303#L779 assume !(0 != activate_threads_~tmp___2~0#1); 17759#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17760#L380 assume 1 == ~t4_pc~0; 17817#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17818#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17846#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17847#L787 assume !(0 != activate_threads_~tmp___3~0#1); 18133#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17820#L399 assume !(1 == ~t5_pc~0); 17821#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17974#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17978#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17964#L795 assume !(0 != activate_threads_~tmp___4~0#1); 17965#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18321#L679 assume !(1 == ~M_E~0); 18051#L679-2 assume !(1 == ~T1_E~0); 17900#L684-1 assume !(1 == ~T2_E~0); 17901#L689-1 assume !(1 == ~T3_E~0); 18100#L694-1 assume !(1 == ~T4_E~0); 18098#L699-1 assume !(1 == ~T5_E~0); 18099#L704-1 assume !(1 == ~E_M~0); 18079#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18009#L714-1 assume !(1 == ~E_2~0); 18010#L719-1 assume !(1 == ~E_3~0); 18209#L724-1 assume !(1 == ~E_4~0); 17780#L729-1 assume !(1 == ~E_5~0); 17781#L734-1 assume { :end_inline_reset_delta_events } true; 18170#L940-2 [2023-11-26 11:51:16,820 INFO L750 eck$LassoCheckResult]: Loop: 18170#L940-2 assume !false; 18266#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17856#L586-1 assume !false; 18309#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18737#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18734#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18733#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18732#L511 assume !(0 != eval_~tmp~0#1); 18731#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18730#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18729#L611-3 assume !(0 == ~M_E~0); 18728#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18727#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18726#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18725#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18724#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18723#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18722#L641-3 assume !(0 == ~E_1~0); 18721#L646-3 assume !(0 == ~E_2~0); 18720#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18719#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18718#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18717#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18716#L304-21 assume 1 == ~m_pc~0; 18714#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18713#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18712#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18711#L755-21 assume !(0 != activate_threads_~tmp~1#1); 18710#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18355#L323-21 assume !(1 == ~t1_pc~0); 18356#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 18845#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18844#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18843#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18842#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18841#L342-21 assume !(1 == ~t2_pc~0); 18839#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 18838#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18834#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18833#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18829#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18828#L361-21 assume 1 == ~t3_pc~0; 18826#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18824#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18822#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18820#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18688#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18686#L380-21 assume !(1 == ~t4_pc~0); 18683#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 18680#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18678#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18676#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18674#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18672#L399-21 assume 1 == ~t5_pc~0; 18669#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18666#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18664#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18662#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18660#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18658#L679-3 assume !(1 == ~M_E~0); 18657#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18650#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18651#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18641#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18642#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18633#L704-3 assume !(1 == ~E_M~0); 18634#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18629#L714-3 assume !(1 == ~E_2~0); 18630#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18568#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18569#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18564#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18565#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18787#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18786#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 18785#L959 assume !(0 == start_simulation_~tmp~3#1); 18782#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18011#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18012#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 17752#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 17753#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17921#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17922#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 18169#L972 assume !(0 != start_simulation_~tmp___0~1#1); 18170#L940-2 [2023-11-26 11:51:16,821 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:16,821 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2023-11-26 11:51:16,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:16,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295376395] [2023-11-26 11:51:16,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:16,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:16,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:16,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:16,877 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:16,877 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295376395] [2023-11-26 11:51:16,877 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295376395] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:16,877 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:16,877 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:51:16,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292509990] [2023-11-26 11:51:16,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:16,879 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:16,879 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:16,880 INFO L85 PathProgramCache]: Analyzing trace with hash -1765836361, now seen corresponding path program 1 times [2023-11-26 11:51:16,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:16,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967105264] [2023-11-26 11:51:16,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:16,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:16,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:16,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:16,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:16,922 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1967105264] [2023-11-26 11:51:16,922 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1967105264] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:16,922 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:16,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:16,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1077634296] [2023-11-26 11:51:16,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:16,923 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:16,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:16,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:16,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:16,924 INFO L87 Difference]: Start difference. First operand 1882 states and 2690 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:17,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:17,059 INFO L93 Difference]: Finished difference Result 3468 states and 4930 transitions. [2023-11-26 11:51:17,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3468 states and 4930 transitions. [2023-11-26 11:51:17,085 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3372 [2023-11-26 11:51:17,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3468 states to 3468 states and 4930 transitions. [2023-11-26 11:51:17,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3468 [2023-11-26 11:51:17,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3468 [2023-11-26 11:51:17,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3468 states and 4930 transitions. [2023-11-26 11:51:17,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:17,123 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3468 states and 4930 transitions. [2023-11-26 11:51:17,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3468 states and 4930 transitions. [2023-11-26 11:51:17,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3468 to 3460. [2023-11-26 11:51:17,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3460 states, 3460 states have (on average 1.4225433526011562) internal successors, (4922), 3459 states have internal predecessors, (4922), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:17,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 4922 transitions. [2023-11-26 11:51:17,217 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3460 states and 4922 transitions. [2023-11-26 11:51:17,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:17,218 INFO L428 stractBuchiCegarLoop]: Abstraction has 3460 states and 4922 transitions. [2023-11-26 11:51:17,218 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 11:51:17,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3460 states and 4922 transitions. [2023-11-26 11:51:17,236 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3364 [2023-11-26 11:51:17,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:17,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:17,238 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:17,239 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:17,239 INFO L748 eck$LassoCheckResult]: Stem: 23368#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 23369#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 23475#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23476#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23462#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 23463#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23303#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23304#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23281#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23282#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23543#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23392#L611 assume !(0 == ~M_E~0); 23393#L611-2 assume !(0 == ~T1_E~0); 23558#L616-1 assume !(0 == ~T2_E~0); 23559#L621-1 assume !(0 == ~T3_E~0); 23147#L626-1 assume !(0 == ~T4_E~0); 23148#L631-1 assume !(0 == ~T5_E~0); 23344#L636-1 assume !(0 == ~E_M~0); 23200#L641-1 assume !(0 == ~E_1~0); 23201#L646-1 assume !(0 == ~E_2~0); 23364#L651-1 assume !(0 == ~E_3~0); 23604#L656-1 assume !(0 == ~E_4~0); 23541#L661-1 assume !(0 == ~E_5~0); 23542#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23575#L304 assume !(1 == ~m_pc~0); 23226#L304-2 is_master_triggered_~__retres1~0#1 := 0; 23124#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23125#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23075#L755 assume !(0 != activate_threads_~tmp~1#1); 23076#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23031#L323 assume !(1 == ~t1_pc~0); 23032#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23093#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23094#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23110#L763 assume !(0 != activate_threads_~tmp___0~0#1); 23636#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23097#L342 assume !(1 == ~t2_pc~0); 23099#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23232#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23233#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23478#L771 assume !(0 != activate_threads_~tmp___1~0#1); 23537#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23429#L361 assume !(1 == ~t3_pc~0); 23430#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23455#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23049#L779 assume !(0 != activate_threads_~tmp___2~0#1); 23113#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23114#L380 assume !(1 == ~t4_pc~0); 23428#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23551#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23193#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23194#L787 assume !(0 != activate_threads_~tmp___3~0#1); 23464#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23171#L399 assume !(1 == ~t5_pc~0); 23172#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 23313#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23319#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23305#L795 assume !(0 != activate_threads_~tmp___4~0#1); 23306#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23614#L679 assume !(1 == ~M_E~0); 23390#L679-2 assume !(1 == ~T1_E~0); 23245#L684-1 assume !(1 == ~T2_E~0); 23246#L689-1 assume !(1 == ~T3_E~0); 23437#L694-1 assume !(1 == ~T4_E~0); 23435#L699-1 assume !(1 == ~T5_E~0); 23436#L704-1 assume !(1 == ~E_M~0); 23417#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 23349#L714-1 assume !(1 == ~E_2~0); 23350#L719-1 assume !(1 == ~E_3~0); 23533#L724-1 assume !(1 == ~E_4~0); 23135#L729-1 assume !(1 == ~E_5~0); 23136#L734-1 assume { :end_inline_reset_delta_events } true; 23618#L940-2 [2023-11-26 11:51:17,240 INFO L750 eck$LassoCheckResult]: Loop: 23618#L940-2 assume !false; 25371#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25369#L586-1 assume !false; 25367#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 25349#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25342#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25337#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25329#L511 assume !(0 != eval_~tmp~0#1); 25330#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25812#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25810#L611-3 assume !(0 == ~M_E~0); 25807#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25805#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25803#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25801#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25799#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25795#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25793#L641-3 assume !(0 == ~E_1~0); 25791#L646-3 assume !(0 == ~E_2~0); 25790#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25789#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25771#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25763#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25756#L304-21 assume 1 == ~m_pc~0; 25748#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25743#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25741#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25739#L755-21 assume !(0 != activate_threads_~tmp~1#1); 25732#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25730#L323-21 assume !(1 == ~t1_pc~0); 25728#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 25725#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25723#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25721#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25719#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25717#L342-21 assume !(1 == ~t2_pc~0); 25714#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 25712#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25709#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25707#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25705#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25703#L361-21 assume 1 == ~t3_pc~0; 25700#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25697#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25694#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25691#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25689#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25687#L380-21 assume !(1 == ~t4_pc~0); 25684#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 25682#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25680#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25677#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25674#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25671#L399-21 assume 1 == ~t5_pc~0; 25667#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25607#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25603#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25601#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25599#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25597#L679-3 assume !(1 == ~M_E~0); 25593#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25591#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25589#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25587#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25585#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25576#L704-3 assume !(1 == ~E_M~0); 25573#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25569#L714-3 assume !(1 == ~E_2~0); 25565#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25559#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25555#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25553#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 25517#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25510#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25505#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 25498#L959 assume !(0 == start_simulation_~tmp~3#1); 25493#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 25442#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25434#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25428#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 25422#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25416#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25410#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 25406#L972 assume !(0 != start_simulation_~tmp___0~1#1); 23618#L940-2 [2023-11-26 11:51:17,240 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:17,240 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2023-11-26 11:51:17,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:17,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486192262] [2023-11-26 11:51:17,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:17,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:17,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:17,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:17,303 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:17,303 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [486192262] [2023-11-26 11:51:17,303 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [486192262] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:17,304 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:17,304 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:17,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [603357261] [2023-11-26 11:51:17,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:17,304 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:17,305 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:17,305 INFO L85 PathProgramCache]: Analyzing trace with hash -1765836361, now seen corresponding path program 2 times [2023-11-26 11:51:17,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:17,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285797790] [2023-11-26 11:51:17,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:17,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:17,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:17,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:17,350 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:17,350 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285797790] [2023-11-26 11:51:17,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285797790] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:17,350 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:17,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:17,351 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466227793] [2023-11-26 11:51:17,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:17,351 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:17,351 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:17,352 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:51:17,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:51:17,354 INFO L87 Difference]: Start difference. First operand 3460 states and 4922 transitions. cyclomatic complexity: 1466 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:17,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:17,498 INFO L93 Difference]: Finished difference Result 5489 states and 7747 transitions. [2023-11-26 11:51:17,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5489 states and 7747 transitions. [2023-11-26 11:51:17,530 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5284 [2023-11-26 11:51:17,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5489 states to 5489 states and 7747 transitions. [2023-11-26 11:51:17,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5489 [2023-11-26 11:51:17,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5489 [2023-11-26 11:51:17,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5489 states and 7747 transitions. [2023-11-26 11:51:17,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:17,584 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5489 states and 7747 transitions. [2023-11-26 11:51:17,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5489 states and 7747 transitions. [2023-11-26 11:51:17,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5489 to 3972. [2023-11-26 11:51:17,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3972 states, 3972 states have (on average 1.4149043303121853) internal successors, (5620), 3971 states have internal predecessors, (5620), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:17,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3972 states to 3972 states and 5620 transitions. [2023-11-26 11:51:17,673 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3972 states and 5620 transitions. [2023-11-26 11:51:17,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:51:17,674 INFO L428 stractBuchiCegarLoop]: Abstraction has 3972 states and 5620 transitions. [2023-11-26 11:51:17,674 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 11:51:17,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3972 states and 5620 transitions. [2023-11-26 11:51:17,692 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3820 [2023-11-26 11:51:17,692 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:17,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:17,693 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:17,694 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:17,694 INFO L748 eck$LassoCheckResult]: Stem: 32333#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 32334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 32447#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32448#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32430#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 32431#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32269#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32270#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32246#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32247#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32514#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32357#L611 assume !(0 == ~M_E~0); 32358#L611-2 assume !(0 == ~T1_E~0); 32531#L616-1 assume !(0 == ~T2_E~0); 32532#L621-1 assume !(0 == ~T3_E~0); 32108#L626-1 assume !(0 == ~T4_E~0); 32109#L631-1 assume !(0 == ~T5_E~0); 32312#L636-1 assume !(0 == ~E_M~0); 32162#L641-1 assume 0 == ~E_1~0;~E_1~0 := 1; 32163#L646-1 assume !(0 == ~E_2~0); 32330#L651-1 assume !(0 == ~E_3~0); 32571#L656-1 assume !(0 == ~E_4~0); 32572#L661-1 assume !(0 == ~E_5~0); 32548#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32549#L304 assume !(1 == ~m_pc~0); 32189#L304-2 is_master_triggered_~__retres1~0#1 := 0; 32190#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32276#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32277#L755 assume !(0 != activate_threads_~tmp~1#1); 32638#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32639#L323 assume !(1 == ~t1_pc~0); 32381#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32382#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32068#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32069#L763 assume !(0 != activate_threads_~tmp___0~0#1); 32612#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32613#L342 assume !(1 == ~t2_pc~0); 32510#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32511#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32449#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32450#L771 assume !(0 != activate_threads_~tmp___1~0#1); 32507#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32395#L361 assume !(1 == ~t3_pc~0); 32396#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32423#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32587#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32569#L779 assume !(0 != activate_threads_~tmp___2~0#1); 32072#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32073#L380 assume !(1 == ~t4_pc~0); 32394#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32661#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32155#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32156#L787 assume !(0 != activate_threads_~tmp___3~0#1); 32660#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32133#L399 assume !(1 == ~t5_pc~0); 32134#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32659#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32288#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32289#L795 assume !(0 != activate_threads_~tmp___4~0#1); 32658#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32628#L679 assume !(1 == ~M_E~0); 32355#L679-2 assume !(1 == ~T1_E~0); 32210#L684-1 assume !(1 == ~T2_E~0); 32211#L689-1 assume !(1 == ~T3_E~0); 32404#L694-1 assume !(1 == ~T4_E~0); 32654#L699-1 assume !(1 == ~T5_E~0); 32653#L704-1 assume !(1 == ~E_M~0); 32652#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 32316#L714-1 assume !(1 == ~E_2~0); 32317#L719-1 assume !(1 == ~E_3~0); 32502#L724-1 assume !(1 == ~E_4~0); 32096#L729-1 assume !(1 == ~E_5~0); 32097#L734-1 assume { :end_inline_reset_delta_events } true; 32588#L940-2 [2023-11-26 11:51:17,694 INFO L750 eck$LassoCheckResult]: Loop: 32588#L940-2 assume !false; 33830#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33825#L586-1 assume !false; 33822#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 33789#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 33782#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 33777#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33772#L511 assume !(0 != eval_~tmp~0#1); 33768#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33763#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33759#L611-3 assume !(0 == ~M_E~0); 33755#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33752#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33748#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33743#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33740#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33736#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33731#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33730#L646-3 assume !(0 == ~E_2~0); 33729#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33728#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33727#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33726#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33725#L304-21 assume 1 == ~m_pc~0; 33723#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33722#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33721#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33720#L755-21 assume !(0 != activate_threads_~tmp~1#1); 33719#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33718#L323-21 assume !(1 == ~t1_pc~0); 33717#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 33716#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33715#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33714#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33713#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33712#L342-21 assume !(1 == ~t2_pc~0); 33710#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 33709#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33708#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33707#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33706#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33705#L361-21 assume 1 == ~t3_pc~0; 33703#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33701#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33699#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33697#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33696#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33695#L380-21 assume !(1 == ~t4_pc~0); 33694#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 33693#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33692#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33691#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33690#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33689#L399-21 assume 1 == ~t5_pc~0; 33687#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33686#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33685#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33684#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33683#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33682#L679-3 assume !(1 == ~M_E~0); 33397#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33681#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33680#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33679#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33678#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33677#L704-3 assume !(1 == ~E_M~0); 33675#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33673#L714-3 assume !(1 == ~E_2~0); 33671#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33669#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33620#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33619#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 32734#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 32723#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 32719#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 32715#L959 assume !(0 == start_simulation_~tmp~3#1); 32716#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 33897#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 33894#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 33893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 33889#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33887#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33883#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 33872#L972 assume !(0 != start_simulation_~tmp___0~1#1); 32588#L940-2 [2023-11-26 11:51:17,695 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:17,695 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2023-11-26 11:51:17,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:17,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943267660] [2023-11-26 11:51:17,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:17,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:17,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:17,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:17,774 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:17,774 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1943267660] [2023-11-26 11:51:17,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1943267660] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:17,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:17,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:17,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395873097] [2023-11-26 11:51:17,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:17,775 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:17,775 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:17,776 INFO L85 PathProgramCache]: Analyzing trace with hash -549682635, now seen corresponding path program 1 times [2023-11-26 11:51:17,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:17,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919480469] [2023-11-26 11:51:17,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:17,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:17,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:17,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:17,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:17,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1919480469] [2023-11-26 11:51:17,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1919480469] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:17,825 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:17,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:17,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271593378] [2023-11-26 11:51:17,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:17,826 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:17,826 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:17,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:51:17,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:51:17,827 INFO L87 Difference]: Start difference. First operand 3972 states and 5620 transitions. cyclomatic complexity: 1652 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:17,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:17,922 INFO L93 Difference]: Finished difference Result 4826 states and 6797 transitions. [2023-11-26 11:51:17,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4826 states and 6797 transitions. [2023-11-26 11:51:17,947 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4682 [2023-11-26 11:51:17,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4826 states to 4826 states and 6797 transitions. [2023-11-26 11:51:17,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4826 [2023-11-26 11:51:17,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4826 [2023-11-26 11:51:17,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4826 states and 6797 transitions. [2023-11-26 11:51:17,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:17,995 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4826 states and 6797 transitions. [2023-11-26 11:51:18,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4826 states and 6797 transitions. [2023-11-26 11:51:18,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4826 to 3460. [2023-11-26 11:51:18,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3460 states, 3460 states have (on average 1.408092485549133) internal successors, (4872), 3459 states have internal predecessors, (4872), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:18,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 4872 transitions. [2023-11-26 11:51:18,081 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3460 states and 4872 transitions. [2023-11-26 11:51:18,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:51:18,082 INFO L428 stractBuchiCegarLoop]: Abstraction has 3460 states and 4872 transitions. [2023-11-26 11:51:18,082 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 11:51:18,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3460 states and 4872 transitions. [2023-11-26 11:51:18,097 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3364 [2023-11-26 11:51:18,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:18,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:18,098 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:18,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:18,099 INFO L748 eck$LassoCheckResult]: Stem: 41132#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 41133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 41239#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41240#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41227#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 41228#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41072#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41073#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41048#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41049#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41301#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41156#L611 assume !(0 == ~M_E~0); 41157#L611-2 assume !(0 == ~T1_E~0); 41315#L616-1 assume !(0 == ~T2_E~0); 41316#L621-1 assume !(0 == ~T3_E~0); 40914#L626-1 assume !(0 == ~T4_E~0); 40915#L631-1 assume !(0 == ~T5_E~0); 41110#L636-1 assume !(0 == ~E_M~0); 40965#L641-1 assume !(0 == ~E_1~0); 40966#L646-1 assume !(0 == ~E_2~0); 41129#L651-1 assume !(0 == ~E_3~0); 41362#L656-1 assume !(0 == ~E_4~0); 41299#L661-1 assume !(0 == ~E_5~0); 41300#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41333#L304 assume !(1 == ~m_pc~0); 40991#L304-2 is_master_triggered_~__retres1~0#1 := 0; 40891#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40892#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40841#L755 assume !(0 != activate_threads_~tmp~1#1); 40842#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40798#L323 assume !(1 == ~t1_pc~0); 40799#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40860#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40877#L763 assume !(0 != activate_threads_~tmp___0~0#1); 41397#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40864#L342 assume !(1 == ~t2_pc~0); 40866#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40997#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40998#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41241#L771 assume !(0 != activate_threads_~tmp___1~0#1); 41295#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41192#L361 assume !(1 == ~t3_pc~0); 41193#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41218#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40815#L779 assume !(0 != activate_threads_~tmp___2~0#1); 40880#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40881#L380 assume !(1 == ~t4_pc~0); 41191#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41308#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40960#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40961#L787 assume !(0 != activate_threads_~tmp___3~0#1); 41229#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40938#L399 assume !(1 == ~t5_pc~0); 40939#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41082#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41087#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41074#L795 assume !(0 != activate_threads_~tmp___4~0#1); 41075#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41375#L679 assume !(1 == ~M_E~0); 41154#L679-2 assume !(1 == ~T1_E~0); 41010#L684-1 assume !(1 == ~T2_E~0); 41011#L689-1 assume !(1 == ~T3_E~0); 41200#L694-1 assume !(1 == ~T4_E~0); 41198#L699-1 assume !(1 == ~T5_E~0); 41199#L704-1 assume !(1 == ~E_M~0); 41180#L709-1 assume !(1 == ~E_1~0); 41115#L714-1 assume !(1 == ~E_2~0); 41116#L719-1 assume !(1 == ~E_3~0); 41290#L724-1 assume !(1 == ~E_4~0); 40902#L729-1 assume !(1 == ~E_5~0); 40903#L734-1 assume { :end_inline_reset_delta_events } true; 41379#L940-2 [2023-11-26 11:51:18,099 INFO L750 eck$LassoCheckResult]: Loop: 41379#L940-2 assume !false; 42750#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42748#L586-1 assume !false; 42746#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 42733#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 42729#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42681#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 42679#L511 assume !(0 != eval_~tmp~0#1); 42680#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42921#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42918#L611-3 assume !(0 == ~M_E~0); 42916#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42914#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42912#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42910#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42908#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42906#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42903#L641-3 assume !(0 == ~E_1~0); 42901#L646-3 assume !(0 == ~E_2~0); 42899#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42896#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42894#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42892#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42890#L304-21 assume 1 == ~m_pc~0; 42887#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 42885#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42883#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 42881#L755-21 assume !(0 != activate_threads_~tmp~1#1); 42879#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42876#L323-21 assume !(1 == ~t1_pc~0); 42874#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 42872#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42870#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42868#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42867#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42866#L342-21 assume !(1 == ~t2_pc~0); 42861#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 42859#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42857#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42856#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42855#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42588#L361-21 assume !(1 == ~t3_pc~0); 42585#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 42581#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42579#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42577#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 42575#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42574#L380-21 assume !(1 == ~t4_pc~0); 42573#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 42533#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42525#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42517#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42514#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42513#L399-21 assume !(1 == ~t5_pc~0); 42512#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 42510#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42509#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42507#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42505#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42503#L679-3 assume !(1 == ~M_E~0); 42316#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42499#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42497#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42495#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42493#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42491#L704-3 assume !(1 == ~E_M~0); 42490#L709-3 assume !(1 == ~E_1~0); 42486#L714-3 assume !(1 == ~E_2~0); 42484#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42482#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42481#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42478#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 42465#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 42416#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42415#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 41461#L959 assume !(0 == start_simulation_~tmp~3#1); 41463#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 42839#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 42834#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42832#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 42830#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42828#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42826#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 42824#L972 assume !(0 != start_simulation_~tmp___0~1#1); 41379#L940-2 [2023-11-26 11:51:18,100 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:18,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2023-11-26 11:51:18,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:18,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476014664] [2023-11-26 11:51:18,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:18,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:18,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:18,115 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:18,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:18,174 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:18,175 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:18,175 INFO L85 PathProgramCache]: Analyzing trace with hash -1183321607, now seen corresponding path program 1 times [2023-11-26 11:51:18,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:18,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243075518] [2023-11-26 11:51:18,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:18,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:18,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:18,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:18,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:18,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243075518] [2023-11-26 11:51:18,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243075518] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:18,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:18,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:18,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032133854] [2023-11-26 11:51:18,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:18,220 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:18,220 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:18,221 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:18,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:18,221 INFO L87 Difference]: Start difference. First operand 3460 states and 4872 transitions. cyclomatic complexity: 1416 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:18,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:18,324 INFO L93 Difference]: Finished difference Result 6232 states and 8688 transitions. [2023-11-26 11:51:18,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6232 states and 8688 transitions. [2023-11-26 11:51:18,359 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6064 [2023-11-26 11:51:18,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6232 states to 6232 states and 8688 transitions. [2023-11-26 11:51:18,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6232 [2023-11-26 11:51:18,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6232 [2023-11-26 11:51:18,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6232 states and 8688 transitions. [2023-11-26 11:51:18,405 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:18,405 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6232 states and 8688 transitions. [2023-11-26 11:51:18,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6232 states and 8688 transitions. [2023-11-26 11:51:18,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6232 to 6224. [2023-11-26 11:51:18,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6224 states, 6224 states have (on average 1.3946015424164524) internal successors, (8680), 6223 states have internal predecessors, (8680), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:18,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6224 states to 6224 states and 8680 transitions. [2023-11-26 11:51:18,568 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6224 states and 8680 transitions. [2023-11-26 11:51:18,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:18,569 INFO L428 stractBuchiCegarLoop]: Abstraction has 6224 states and 8680 transitions. [2023-11-26 11:51:18,569 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 11:51:18,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6224 states and 8680 transitions. [2023-11-26 11:51:18,596 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6056 [2023-11-26 11:51:18,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:18,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:18,598 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:18,598 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:18,598 INFO L748 eck$LassoCheckResult]: Stem: 50837#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 50838#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 50949#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50950#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50935#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 50936#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50771#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50772#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50747#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50748#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51016#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50861#L611 assume !(0 == ~M_E~0); 50862#L611-2 assume !(0 == ~T1_E~0); 51032#L616-1 assume !(0 == ~T2_E~0); 51033#L621-1 assume !(0 == ~T3_E~0); 50614#L626-1 assume !(0 == ~T4_E~0); 50615#L631-1 assume !(0 == ~T5_E~0); 50814#L636-1 assume 0 == ~E_M~0;~E_M~0 := 1; 50662#L641-1 assume !(0 == ~E_1~0); 50663#L646-1 assume !(0 == ~E_2~0); 51106#L651-1 assume !(0 == ~E_3~0); 51107#L656-1 assume !(0 == ~E_4~0); 51014#L661-1 assume !(0 == ~E_5~0); 51015#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51119#L304 assume !(1 == ~m_pc~0); 50693#L304-2 is_master_triggered_~__retres1~0#1 := 0; 50587#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50588#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50543#L755 assume !(0 != activate_threads_~tmp~1#1); 50544#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50496#L323 assume !(1 == ~t1_pc~0); 50497#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50885#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51167#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51166#L763 assume !(0 != activate_threads_~tmp___0~0#1); 51164#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50564#L342 assume !(1 == ~t2_pc~0); 50566#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51161#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50951#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50952#L771 assume !(0 != activate_threads_~tmp___1~0#1); 51009#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50899#L361 assume !(1 == ~t3_pc~0); 50900#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50928#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50512#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50513#L779 assume !(0 != activate_threads_~tmp___2~0#1); 50578#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50579#L380 assume !(1 == ~t4_pc~0); 50898#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51149#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51148#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50938#L787 assume !(0 != activate_threads_~tmp___3~0#1); 50939#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50633#L399 assume !(1 == ~t5_pc~0); 50634#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 50782#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50786#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50773#L795 assume !(0 != activate_threads_~tmp___4~0#1); 50774#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51087#L679 assume !(1 == ~M_E~0); 51139#L679-2 assume !(1 == ~T1_E~0); 51138#L684-1 assume !(1 == ~T2_E~0); 51137#L689-1 assume !(1 == ~T3_E~0); 51127#L694-1 assume !(1 == ~T4_E~0); 50905#L699-1 assume !(1 == ~T5_E~0); 50906#L704-1 assume 1 == ~E_M~0;~E_M~0 := 2; 50884#L709-1 assume !(1 == ~E_1~0); 50816#L714-1 assume !(1 == ~E_2~0); 50817#L719-1 assume !(1 == ~E_3~0); 51004#L724-1 assume !(1 == ~E_4~0); 50598#L729-1 assume !(1 == ~E_5~0); 50599#L734-1 assume { :end_inline_reset_delta_events } true; 51092#L940-2 [2023-11-26 11:51:18,599 INFO L750 eck$LassoCheckResult]: Loop: 51092#L940-2 assume !false; 52553#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52549#L586-1 assume !false; 52544#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 52461#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 52457#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 52455#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 52452#L511 assume !(0 != eval_~tmp~0#1); 52453#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52897#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52895#L611-3 assume !(0 == ~M_E~0); 52893#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52891#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52889#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52887#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52884#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52882#L636-3 assume !(0 == ~E_M~0); 52880#L641-3 assume !(0 == ~E_1~0); 52878#L646-3 assume !(0 == ~E_2~0); 52876#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52874#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52870#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52868#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52866#L304-21 assume 1 == ~m_pc~0; 52865#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 50627#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50703#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50704#L755-21 assume !(0 != activate_threads_~tmp~1#1); 50847#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50879#L323-21 assume !(1 == ~t1_pc~0); 51022#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 51023#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50642#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50643#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51044#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51058#L342-21 assume !(1 == ~t2_pc~0); 50536#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 50933#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50856#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50857#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50636#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50637#L361-21 assume !(1 == ~t3_pc~0); 51088#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 51089#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51099#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50813#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 50539#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50540#L380-21 assume !(1 == ~t4_pc~0); 50604#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 50605#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50678#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 51001#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50940#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50756#L399-21 assume !(1 == ~t5_pc~0); 50610#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 50611#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50926#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50927#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51082#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50537#L679-3 assume !(1 == ~M_E~0); 50538#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50827#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50887#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56488#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56487#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52775#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 52772#L709-3 assume !(1 == ~E_1~0); 52769#L714-3 assume !(1 == ~E_2~0); 52767#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 52765#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52764#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52763#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 51250#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 51248#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 51312#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 51313#L959 assume !(0 == start_simulation_~tmp~3#1); 52646#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 52607#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 52599#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 52593#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 52587#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 52579#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52572#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 52566#L972 assume !(0 != start_simulation_~tmp___0~1#1); 51092#L940-2 [2023-11-26 11:51:18,599 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:18,599 INFO L85 PathProgramCache]: Analyzing trace with hash -814901243, now seen corresponding path program 1 times [2023-11-26 11:51:18,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:18,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501220617] [2023-11-26 11:51:18,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:18,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:18,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:18,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:18,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:18,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501220617] [2023-11-26 11:51:18,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501220617] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:18,651 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:18,652 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:18,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74240359] [2023-11-26 11:51:18,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:18,652 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:18,653 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:18,653 INFO L85 PathProgramCache]: Analyzing trace with hash 1459562293, now seen corresponding path program 1 times [2023-11-26 11:51:18,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:18,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887151864] [2023-11-26 11:51:18,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:18,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:18,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:18,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:18,712 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:18,712 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887151864] [2023-11-26 11:51:18,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1887151864] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:18,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:18,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:18,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1745870299] [2023-11-26 11:51:18,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:18,714 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:18,714 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:18,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:51:18,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:51:18,715 INFO L87 Difference]: Start difference. First operand 6224 states and 8680 transitions. cyclomatic complexity: 2460 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:18,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:18,867 INFO L93 Difference]: Finished difference Result 8837 states and 12305 transitions. [2023-11-26 11:51:18,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8837 states and 12305 transitions. [2023-11-26 11:51:18,917 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8388 [2023-11-26 11:51:18,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8837 states to 8837 states and 12305 transitions. [2023-11-26 11:51:18,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8837 [2023-11-26 11:51:18,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8837 [2023-11-26 11:51:18,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8837 states and 12305 transitions. [2023-11-26 11:51:18,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:18,971 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8837 states and 12305 transitions. [2023-11-26 11:51:18,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8837 states and 12305 transitions. [2023-11-26 11:51:19,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8837 to 6215. [2023-11-26 11:51:19,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6215 states, 6215 states have (on average 1.3930812550281577) internal successors, (8658), 6214 states have internal predecessors, (8658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:19,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6215 states to 6215 states and 8658 transitions. [2023-11-26 11:51:19,289 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6215 states and 8658 transitions. [2023-11-26 11:51:19,289 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:51:19,290 INFO L428 stractBuchiCegarLoop]: Abstraction has 6215 states and 8658 transitions. [2023-11-26 11:51:19,290 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 11:51:19,290 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6215 states and 8658 transitions. [2023-11-26 11:51:19,316 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6056 [2023-11-26 11:51:19,316 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:19,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:19,318 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:19,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:19,319 INFO L748 eck$LassoCheckResult]: Stem: 65907#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 65908#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 66021#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66022#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66006#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 66007#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65842#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65843#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65818#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65819#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66083#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65932#L611 assume !(0 == ~M_E~0); 65933#L611-2 assume !(0 == ~T1_E~0); 66099#L616-1 assume !(0 == ~T2_E~0); 66100#L621-1 assume !(0 == ~T3_E~0); 65684#L626-1 assume !(0 == ~T4_E~0); 65685#L631-1 assume !(0 == ~T5_E~0); 65884#L636-1 assume !(0 == ~E_M~0); 65736#L641-1 assume !(0 == ~E_1~0); 65737#L646-1 assume !(0 == ~E_2~0); 65904#L651-1 assume !(0 == ~E_3~0); 66144#L656-1 assume !(0 == ~E_4~0); 66080#L661-1 assume !(0 == ~E_5~0); 66081#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66117#L304 assume !(1 == ~m_pc~0); 65762#L304-2 is_master_triggered_~__retres1~0#1 := 0; 65661#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65662#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65612#L755 assume !(0 != activate_threads_~tmp~1#1); 65613#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65569#L323 assume !(1 == ~t1_pc~0); 65570#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65629#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65630#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66177#L763 assume !(0 != activate_threads_~tmp___0~0#1); 66178#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65633#L342 assume !(1 == ~t2_pc~0); 65635#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 65769#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65770#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66191#L771 assume !(0 != activate_threads_~tmp___1~0#1); 66192#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65972#L361 assume !(1 == ~t3_pc~0); 65973#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 66214#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66215#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66140#L779 assume !(0 != activate_threads_~tmp___2~0#1); 66141#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65970#L380 assume !(1 == ~t4_pc~0); 65971#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 66091#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66092#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 66008#L787 assume !(0 != activate_threads_~tmp___3~0#1); 66009#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66188#L399 assume !(1 == ~t5_pc~0); 65854#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 65855#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65860#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65861#L795 assume !(0 != activate_threads_~tmp___4~0#1); 66154#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66155#L679 assume !(1 == ~M_E~0); 65929#L679-2 assume !(1 == ~T1_E~0); 65930#L684-1 assume !(1 == ~T2_E~0); 66213#L689-1 assume !(1 == ~T3_E~0); 66198#L694-1 assume !(1 == ~T4_E~0); 65978#L699-1 assume !(1 == ~T5_E~0); 65979#L704-1 assume !(1 == ~E_M~0); 65956#L709-1 assume !(1 == ~E_1~0); 65889#L714-1 assume !(1 == ~E_2~0); 65890#L719-1 assume !(1 == ~E_3~0); 66069#L724-1 assume !(1 == ~E_4~0); 65672#L729-1 assume !(1 == ~E_5~0); 65673#L734-1 assume { :end_inline_reset_delta_events } true; 66162#L940-2 [2023-11-26 11:51:19,319 INFO L750 eck$LassoCheckResult]: Loop: 66162#L940-2 assume !false; 68319#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68318#L586-1 assume !false; 68317#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 68309#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 68305#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 68303#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 68300#L511 assume !(0 != eval_~tmp~0#1); 68297#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68295#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68293#L611-3 assume !(0 == ~M_E~0); 68291#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68289#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68287#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68283#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68281#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68279#L636-3 assume !(0 == ~E_M~0); 68277#L641-3 assume !(0 == ~E_1~0); 68274#L646-3 assume !(0 == ~E_2~0); 68272#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68270#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 68267#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 68265#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68263#L304-21 assume !(1 == ~m_pc~0); 68259#L304-23 is_master_triggered_~__retres1~0#1 := 0; 68257#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68255#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68252#L755-21 assume !(0 != activate_threads_~tmp~1#1); 68247#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68246#L323-21 assume !(1 == ~t1_pc~0); 68245#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 68244#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68243#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68241#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68240#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68239#L342-21 assume !(1 == ~t2_pc~0); 68237#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 68236#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68235#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68232#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68230#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68226#L361-21 assume 1 == ~t3_pc~0; 68224#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68225#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68242#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68213#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68211#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68209#L380-21 assume !(1 == ~t4_pc~0); 68207#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 68206#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68205#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68203#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68201#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68191#L399-21 assume 1 == ~t5_pc~0; 68187#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 68185#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68183#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 67092#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 67086#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66407#L679-3 assume !(1 == ~M_E~0); 66398#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66392#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66385#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66379#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66373#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66369#L704-3 assume !(1 == ~E_M~0); 66366#L709-3 assume !(1 == ~E_1~0); 66363#L714-3 assume !(1 == ~E_2~0); 66360#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66357#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66355#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66354#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 66342#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 66332#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 66330#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 66266#L959 assume !(0 == start_simulation_~tmp~3#1); 66268#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 68544#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 68540#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 68537#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 68535#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68533#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68531#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 68529#L972 assume !(0 != start_simulation_~tmp___0~1#1); 66162#L940-2 [2023-11-26 11:51:19,383 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:19,383 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2023-11-26 11:51:19,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:19,384 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149951276] [2023-11-26 11:51:19,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:19,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:19,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:19,398 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:19,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:19,427 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:19,428 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:19,428 INFO L85 PathProgramCache]: Analyzing trace with hash -1777508748, now seen corresponding path program 1 times [2023-11-26 11:51:19,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:19,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092418155] [2023-11-26 11:51:19,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:19,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:19,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:19,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:19,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:19,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1092418155] [2023-11-26 11:51:19,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1092418155] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:19,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:19,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:19,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937236622] [2023-11-26 11:51:19,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:19,502 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:19,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:19,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:51:19,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:51:19,503 INFO L87 Difference]: Start difference. First operand 6215 states and 8658 transitions. cyclomatic complexity: 2447 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:19,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:19,700 INFO L93 Difference]: Finished difference Result 11183 states and 15430 transitions. [2023-11-26 11:51:19,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11183 states and 15430 transitions. [2023-11-26 11:51:19,767 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10992 [2023-11-26 11:51:19,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11183 states to 11183 states and 15430 transitions. [2023-11-26 11:51:19,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11183 [2023-11-26 11:51:19,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11183 [2023-11-26 11:51:19,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11183 states and 15430 transitions. [2023-11-26 11:51:19,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:19,843 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11183 states and 15430 transitions. [2023-11-26 11:51:19,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11183 states and 15430 transitions. [2023-11-26 11:51:19,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11183 to 6263. [2023-11-26 11:51:19,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6263 states, 6263 states have (on average 1.3900686571930385) internal successors, (8706), 6262 states have internal predecessors, (8706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:20,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6263 states to 6263 states and 8706 transitions. [2023-11-26 11:51:20,005 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6263 states and 8706 transitions. [2023-11-26 11:51:20,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 11:51:20,006 INFO L428 stractBuchiCegarLoop]: Abstraction has 6263 states and 8706 transitions. [2023-11-26 11:51:20,006 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 11:51:20,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6263 states and 8706 transitions. [2023-11-26 11:51:20,075 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6104 [2023-11-26 11:51:20,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:20,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:20,077 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:20,077 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:20,078 INFO L748 eck$LassoCheckResult]: Stem: 83326#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 83327#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 83443#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 83444#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 83427#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 83428#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83260#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83261#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83237#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83238#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83524#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 83351#L611 assume !(0 == ~M_E~0); 83352#L611-2 assume !(0 == ~T1_E~0); 83541#L616-1 assume !(0 == ~T2_E~0); 83542#L621-1 assume !(0 == ~T3_E~0); 83105#L626-1 assume !(0 == ~T4_E~0); 83106#L631-1 assume !(0 == ~T5_E~0); 83304#L636-1 assume !(0 == ~E_M~0); 83150#L641-1 assume !(0 == ~E_1~0); 83151#L646-1 assume !(0 == ~E_2~0); 83323#L651-1 assume !(0 == ~E_3~0); 83587#L656-1 assume !(0 == ~E_4~0); 83522#L661-1 assume !(0 == ~E_5~0); 83523#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83558#L304 assume !(1 == ~m_pc~0); 83180#L304-2 is_master_triggered_~__retres1~0#1 := 0; 83181#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83269#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 83270#L755 assume !(0 != activate_threads_~tmp~1#1); 83661#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83662#L323 assume !(1 == ~t1_pc~0); 83375#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83376#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83060#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 83061#L763 assume !(0 != activate_threads_~tmp___0~0#1); 83631#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83632#L342 assume !(1 == ~t2_pc~0); 83520#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83521#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83445#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 83446#L771 assume !(0 != activate_threads_~tmp___1~0#1); 83515#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83516#L361 assume !(1 == ~t3_pc~0); 83417#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83418#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83603#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 83680#L779 assume !(0 != activate_threads_~tmp___2~0#1); 83066#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83067#L380 assume !(1 == ~t4_pc~0); 83679#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 83533#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83534#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 83678#L787 assume !(0 != activate_threads_~tmp___3~0#1); 83677#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83676#L399 assume !(1 == ~t5_pc~0); 83674#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 83673#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83672#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 83671#L795 assume !(0 != activate_threads_~tmp___4~0#1); 83670#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83648#L679 assume !(1 == ~M_E~0); 83349#L679-2 assume !(1 == ~T1_E~0); 83198#L684-1 assume !(1 == ~T2_E~0); 83199#L689-1 assume !(1 == ~T3_E~0); 83667#L694-1 assume !(1 == ~T4_E~0); 83666#L699-1 assume !(1 == ~T5_E~0); 83665#L704-1 assume !(1 == ~E_M~0); 83374#L709-1 assume !(1 == ~E_1~0); 83308#L714-1 assume !(1 == ~E_2~0); 83309#L719-1 assume !(1 == ~E_3~0); 83510#L724-1 assume !(1 == ~E_4~0); 83088#L729-1 assume !(1 == ~E_5~0); 83089#L734-1 assume { :end_inline_reset_delta_events } true; 83474#L940-2 [2023-11-26 11:51:20,078 INFO L750 eck$LassoCheckResult]: Loop: 83474#L940-2 assume !false; 83497#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83158#L586-1 assume !false; 83591#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 88106#L464 assume !(0 == ~m_st~0); 88105#L468 assume !(0 == ~t1_st~0); 88096#L472 assume !(0 == ~t2_st~0); 88095#L476 assume !(0 == ~t3_st~0); 88094#L480 assume !(0 == ~t4_st~0); 88093#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 87244#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 86221#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 86222#L511 assume !(0 != eval_~tmp~0#1); 87982#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87980#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87978#L611-3 assume !(0 == ~M_E~0); 87976#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 87974#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87972#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87970#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87968#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87966#L636-3 assume !(0 == ~E_M~0); 87964#L641-3 assume !(0 == ~E_1~0); 87956#L646-3 assume !(0 == ~E_2~0); 87955#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 87937#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 87934#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 87921#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87920#L304-21 assume 1 == ~m_pc~0; 87919#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 87767#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87760#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 87761#L755-21 assume !(0 != activate_threads_~tmp~1#1); 87756#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87757#L323-21 assume !(1 == ~t1_pc~0); 87743#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 87744#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87739#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 87740#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 87735#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87736#L342-21 assume !(1 == ~t2_pc~0); 83627#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 83628#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88964#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88963#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88962#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83609#L361-21 assume !(1 == ~t3_pc~0); 83601#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 83602#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89152#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 83303#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 83027#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83028#L380-21 assume !(1 == ~t4_pc~0); 83094#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 83095#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83166#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88951#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83430#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83431#L399-21 assume 1 == ~t5_pc~0; 88949#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83451#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83452#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 88948#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 83594#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83025#L679-3 assume !(1 == ~M_E~0); 83026#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 83378#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83379#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83287#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83288#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 83470#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 83471#L709-3 assume !(1 == ~E_1~0); 83456#L714-3 assume !(1 == ~E_2~0); 83457#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88812#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88813#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88766#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 88767#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 89024#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 89021#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 89019#L959 assume !(0 == start_simulation_~tmp~3#1); 89013#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 83311#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 83312#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 83058#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 83059#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 83219#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83220#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 83473#L972 assume !(0 != start_simulation_~tmp___0~1#1); 83474#L940-2 [2023-11-26 11:51:20,079 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:20,079 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2023-11-26 11:51:20,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:20,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911993476] [2023-11-26 11:51:20,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:20,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:20,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:20,098 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:20,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:20,131 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:20,132 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:20,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1173042241, now seen corresponding path program 1 times [2023-11-26 11:51:20,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:20,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437130178] [2023-11-26 11:51:20,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:20,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:20,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:20,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:20,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:20,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437130178] [2023-11-26 11:51:20,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437130178] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:20,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:20,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:20,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250765400] [2023-11-26 11:51:20,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:20,178 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:20,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:20,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:20,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:20,179 INFO L87 Difference]: Start difference. First operand 6263 states and 8706 transitions. cyclomatic complexity: 2447 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:20,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:20,277 INFO L93 Difference]: Finished difference Result 11567 states and 15854 transitions. [2023-11-26 11:51:20,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11567 states and 15854 transitions. [2023-11-26 11:51:20,330 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11376 [2023-11-26 11:51:20,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11567 states to 11567 states and 15854 transitions. [2023-11-26 11:51:20,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11567 [2023-11-26 11:51:20,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11567 [2023-11-26 11:51:20,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11567 states and 15854 transitions. [2023-11-26 11:51:20,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:20,397 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11567 states and 15854 transitions. [2023-11-26 11:51:20,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11567 states and 15854 transitions. [2023-11-26 11:51:20,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11567 to 10943. [2023-11-26 11:51:20,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10943 states, 10943 states have (on average 1.3742118249109019) internal successors, (15038), 10942 states have internal predecessors, (15038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:20,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10943 states to 10943 states and 15038 transitions. [2023-11-26 11:51:20,701 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10943 states and 15038 transitions. [2023-11-26 11:51:20,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:20,702 INFO L428 stractBuchiCegarLoop]: Abstraction has 10943 states and 15038 transitions. [2023-11-26 11:51:20,702 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 11:51:20,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10943 states and 15038 transitions. [2023-11-26 11:51:20,735 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10752 [2023-11-26 11:51:20,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:20,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:20,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:20,737 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:20,738 INFO L748 eck$LassoCheckResult]: Stem: 101166#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 101167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 101289#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101290#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 101273#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 101274#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 101100#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 101101#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101075#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 101076#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 101373#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 101193#L611 assume !(0 == ~M_E~0); 101194#L611-2 assume !(0 == ~T1_E~0); 101395#L616-1 assume !(0 == ~T2_E~0); 101396#L621-1 assume !(0 == ~T3_E~0); 100941#L626-1 assume !(0 == ~T4_E~0); 100942#L631-1 assume !(0 == ~T5_E~0); 101147#L636-1 assume !(0 == ~E_M~0); 100987#L641-1 assume !(0 == ~E_1~0); 100988#L646-1 assume !(0 == ~E_2~0); 101162#L651-1 assume !(0 == ~E_3~0); 101450#L656-1 assume !(0 == ~E_4~0); 101371#L661-1 assume !(0 == ~E_5~0); 101372#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101413#L304 assume !(1 == ~m_pc~0); 101019#L304-2 is_master_triggered_~__retres1~0#1 := 0; 101020#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101109#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 101110#L755 assume !(0 != activate_threads_~tmp~1#1); 101524#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101525#L323 assume !(1 == ~t1_pc~0); 101220#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 101221#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100897#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100898#L763 assume !(0 != activate_threads_~tmp___0~0#1); 101496#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101497#L342 assume !(1 == ~t2_pc~0); 101369#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 101370#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101291#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 101292#L771 assume !(0 != activate_threads_~tmp___1~0#1); 101364#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101365#L361 assume !(1 == ~t3_pc~0); 101427#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101468#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101469#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 101544#L779 assume !(0 != activate_threads_~tmp___2~0#1); 100904#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100905#L380 assume !(1 == ~t4_pc~0); 101543#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 101384#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101385#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 101542#L787 assume !(0 != activate_threads_~tmp___3~0#1); 101541#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101540#L399 assume !(1 == ~t5_pc~0); 101538#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 101537#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101536#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 101535#L795 assume !(0 != activate_threads_~tmp___4~0#1); 101534#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101509#L679 assume !(1 == ~M_E~0); 101192#L679-2 assume !(1 == ~T1_E~0); 101036#L684-1 assume !(1 == ~T2_E~0); 101037#L689-1 assume !(1 == ~T3_E~0); 101531#L694-1 assume !(1 == ~T4_E~0); 101530#L699-1 assume !(1 == ~T5_E~0); 101529#L704-1 assume !(1 == ~E_M~0); 101219#L709-1 assume !(1 == ~E_1~0); 101148#L714-1 assume !(1 == ~E_2~0); 101149#L719-1 assume !(1 == ~E_3~0); 101359#L724-1 assume !(1 == ~E_4~0); 100924#L729-1 assume !(1 == ~E_5~0); 100925#L734-1 assume { :end_inline_reset_delta_events } true; 101470#L940-2 [2023-11-26 11:51:20,738 INFO L750 eck$LassoCheckResult]: Loop: 101470#L940-2 assume !false; 105475#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105473#L586-1 assume !false; 105472#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 105467#L464 assume !(0 == ~m_st~0); 105468#L468 assume !(0 == ~t1_st~0); 105957#L472 assume !(0 == ~t2_st~0); 105953#L476 assume !(0 == ~t3_st~0); 105955#L480 assume !(0 == ~t4_st~0); 105956#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 105948#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 105943#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 105944#L511 assume !(0 != eval_~tmp~0#1); 106103#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106102#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 106101#L611-3 assume !(0 == ~M_E~0); 106100#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 106099#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 106098#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 106097#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 106096#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 106095#L636-3 assume !(0 == ~E_M~0); 106094#L641-3 assume !(0 == ~E_1~0); 106093#L646-3 assume !(0 == ~E_2~0); 106092#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 106091#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 106090#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106089#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106088#L304-21 assume !(1 == ~m_pc~0); 106085#L304-23 is_master_triggered_~__retres1~0#1 := 0; 106084#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106082#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 106079#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 106080#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111592#L323-21 assume !(1 == ~t1_pc~0); 111591#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 111590#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111589#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 111588#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 111587#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111586#L342-21 assume !(1 == ~t2_pc~0); 111584#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 111583#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111582#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 111581#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 111580#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111579#L361-21 assume 1 == ~t3_pc~0; 111577#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 111578#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111593#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 111572#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 111571#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111570#L380-21 assume !(1 == ~t4_pc~0); 111569#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 111568#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111567#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 111566#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 111565#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 111564#L399-21 assume !(1 == ~t5_pc~0); 111563#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 111561#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111560#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 111559#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 111558#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111557#L679-3 assume !(1 == ~M_E~0); 104630#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 111556#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 111555#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111554#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 111553#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 111510#L704-3 assume !(1 == ~E_M~0); 111509#L709-3 assume !(1 == ~E_1~0); 111508#L714-3 assume !(1 == ~E_2~0); 111507#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 111506#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 111505#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 111504#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 111503#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 101211#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 101212#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 101733#L959 assume !(0 == start_simulation_~tmp~3#1); 101734#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 105734#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 105728#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 105709#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 105703#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 105693#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 105566#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 105565#L972 assume !(0 != start_simulation_~tmp___0~1#1); 101470#L940-2 [2023-11-26 11:51:20,739 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:20,739 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2023-11-26 11:51:20,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:20,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347993761] [2023-11-26 11:51:20,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:20,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:20,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:20,751 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:20,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:20,772 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:20,773 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:20,773 INFO L85 PathProgramCache]: Analyzing trace with hash -624037890, now seen corresponding path program 1 times [2023-11-26 11:51:20,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:20,773 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104620027] [2023-11-26 11:51:20,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:20,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:20,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:20,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:20,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:20,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [104620027] [2023-11-26 11:51:20,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [104620027] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:20,924 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:20,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:20,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922028475] [2023-11-26 11:51:20,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:20,924 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:20,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:20,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:51:20,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:51:20,925 INFO L87 Difference]: Start difference. First operand 10943 states and 15038 transitions. cyclomatic complexity: 4099 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:21,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:21,213 INFO L93 Difference]: Finished difference Result 18234 states and 24801 transitions. [2023-11-26 11:51:21,213 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18234 states and 24801 transitions. [2023-11-26 11:51:21,296 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 17936 [2023-11-26 11:51:21,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18234 states to 18234 states and 24801 transitions. [2023-11-26 11:51:21,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18234 [2023-11-26 11:51:21,477 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18234 [2023-11-26 11:51:21,477 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18234 states and 24801 transitions. [2023-11-26 11:51:21,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:21,497 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18234 states and 24801 transitions. [2023-11-26 11:51:21,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18234 states and 24801 transitions. [2023-11-26 11:51:21,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18234 to 10823. [2023-11-26 11:51:21,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10823 states, 10823 states have (on average 1.3583110043426037) internal successors, (14701), 10822 states have internal predecessors, (14701), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:21,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10823 states to 10823 states and 14701 transitions. [2023-11-26 11:51:21,851 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10823 states and 14701 transitions. [2023-11-26 11:51:21,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:51:21,852 INFO L428 stractBuchiCegarLoop]: Abstraction has 10823 states and 14701 transitions. [2023-11-26 11:51:21,852 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 11:51:21,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10823 states and 14701 transitions. [2023-11-26 11:51:21,884 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10632 [2023-11-26 11:51:21,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:21,885 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:21,886 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:21,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:21,887 INFO L748 eck$LassoCheckResult]: Stem: 130349#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 130350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 130466#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 130467#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 130448#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 130449#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130289#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 130290#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 130264#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 130265#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 130536#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 130376#L611 assume !(0 == ~M_E~0); 130377#L611-2 assume !(0 == ~T1_E~0); 130551#L616-1 assume !(0 == ~T2_E~0); 130552#L621-1 assume !(0 == ~T3_E~0); 130125#L626-1 assume !(0 == ~T4_E~0); 130126#L631-1 assume !(0 == ~T5_E~0); 130329#L636-1 assume !(0 == ~E_M~0); 130176#L641-1 assume !(0 == ~E_1~0); 130177#L646-1 assume !(0 == ~E_2~0); 130347#L651-1 assume !(0 == ~E_3~0); 130592#L656-1 assume !(0 == ~E_4~0); 130533#L661-1 assume !(0 == ~E_5~0); 130534#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 130571#L304 assume !(1 == ~m_pc~0); 130202#L304-2 is_master_triggered_~__retres1~0#1 := 0; 130203#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130296#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 130297#L755 assume !(0 != activate_threads_~tmp~1#1); 130695#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130694#L323 assume !(1 == ~t1_pc~0); 130693#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 130692#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130691#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 130690#L763 assume !(0 != activate_threads_~tmp___0~0#1); 130689#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130688#L342 assume !(1 == ~t2_pc~0); 130686#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 130685#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130684#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 130683#L771 assume !(0 != activate_threads_~tmp___1~0#1); 130682#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130681#L361 assume !(1 == ~t3_pc~0); 130679#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 130677#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130675#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 130673#L779 assume !(0 != activate_threads_~tmp___2~0#1); 130672#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130671#L380 assume !(1 == ~t4_pc~0); 130670#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 130669#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130668#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 130667#L787 assume !(0 != activate_threads_~tmp___3~0#1); 130666#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130665#L399 assume !(1 == ~t5_pc~0); 130663#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 130662#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130661#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130660#L795 assume !(0 != activate_threads_~tmp___4~0#1); 130659#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130639#L679 assume !(1 == ~M_E~0); 130640#L679-2 assume !(1 == ~T1_E~0); 130658#L684-1 assume !(1 == ~T2_E~0); 130657#L689-1 assume !(1 == ~T3_E~0); 130647#L694-1 assume !(1 == ~T4_E~0); 130419#L699-1 assume !(1 == ~T5_E~0); 130420#L704-1 assume !(1 == ~E_M~0); 130399#L709-1 assume !(1 == ~E_1~0); 130333#L714-1 assume !(1 == ~E_2~0); 130334#L719-1 assume !(1 == ~E_3~0); 130525#L724-1 assume !(1 == ~E_4~0); 130113#L729-1 assume !(1 == ~E_5~0); 130114#L734-1 assume { :end_inline_reset_delta_events } true; 130609#L940-2 [2023-11-26 11:51:21,887 INFO L750 eck$LassoCheckResult]: Loop: 130609#L940-2 assume !false; 131721#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 131722#L586-1 assume !false; 131185#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 131186#L464 assume !(0 == ~m_st~0); 131174#L468 assume !(0 == ~t1_st~0); 131175#L472 assume !(0 == ~t2_st~0); 131160#L476 assume !(0 == ~t3_st~0); 131161#L480 assume !(0 == ~t4_st~0); 131142#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 131144#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 131125#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 131126#L511 assume !(0 != eval_~tmp~0#1); 131107#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 131108#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 131092#L611-3 assume !(0 == ~M_E~0); 131093#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 131077#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 131078#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 131062#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 131063#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 131046#L636-3 assume !(0 == ~E_M~0); 131047#L641-3 assume !(0 == ~E_1~0); 131659#L646-3 assume !(0 == ~E_2~0); 131655#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 131017#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 131010#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 131002#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131003#L304-21 assume 1 == ~m_pc~0; 131590#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 130988#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130987#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 130985#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 130984#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130983#L323-21 assume !(1 == ~t1_pc~0); 130982#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 130981#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130980#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 130979#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 130978#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130977#L342-21 assume !(1 == ~t2_pc~0); 130975#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 130974#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130973#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 130972#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 130971#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130970#L361-21 assume !(1 == ~t3_pc~0); 130969#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 130967#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130965#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 130963#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 130961#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130960#L380-21 assume !(1 == ~t4_pc~0); 130894#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 130859#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130856#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 130853#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 130850#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130847#L399-21 assume 1 == ~t5_pc~0; 130841#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 130842#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130832#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130833#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 130824#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130825#L679-3 assume !(1 == ~M_E~0); 131235#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 131335#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 131334#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 131333#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 131332#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131331#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 131330#L709-3 assume !(1 == ~E_1~0); 131329#L714-3 assume !(1 == ~E_2~0); 131328#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 131327#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 131326#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 131325#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 131323#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 131322#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 131321#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 131319#L959 assume !(0 == start_simulation_~tmp~3#1); 131320#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 132211#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 132209#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 132208#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 132207#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 132069#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 132070#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 131774#L972 assume !(0 != start_simulation_~tmp___0~1#1); 130609#L940-2 [2023-11-26 11:51:21,888 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:21,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2023-11-26 11:51:21,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:21,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905710146] [2023-11-26 11:51:21,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:21,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:21,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:21,902 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:21,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:21,924 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:21,925 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:21,925 INFO L85 PathProgramCache]: Analyzing trace with hash 1861007805, now seen corresponding path program 1 times [2023-11-26 11:51:21,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:21,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464396641] [2023-11-26 11:51:21,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:21,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:21,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:22,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:22,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:22,017 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [464396641] [2023-11-26 11:51:22,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [464396641] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:22,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:22,017 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:22,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282683625] [2023-11-26 11:51:22,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:22,018 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:22,018 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:22,019 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:51:22,019 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:51:22,019 INFO L87 Difference]: Start difference. First operand 10823 states and 14701 transitions. cyclomatic complexity: 3882 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:22,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:22,202 INFO L93 Difference]: Finished difference Result 12323 states and 16551 transitions. [2023-11-26 11:51:22,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12323 states and 16551 transitions. [2023-11-26 11:51:22,270 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12124 [2023-11-26 11:51:22,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12323 states to 12323 states and 16551 transitions. [2023-11-26 11:51:22,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12323 [2023-11-26 11:51:22,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12323 [2023-11-26 11:51:22,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12323 states and 16551 transitions. [2023-11-26 11:51:22,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:22,355 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12323 states and 16551 transitions. [2023-11-26 11:51:22,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12323 states and 16551 transitions. [2023-11-26 11:51:22,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12323 to 10847. [2023-11-26 11:51:22,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10847 states, 10847 states have (on average 1.342583202728865) internal successors, (14563), 10846 states have internal predecessors, (14563), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:22,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10847 states to 10847 states and 14563 transitions. [2023-11-26 11:51:22,670 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10847 states and 14563 transitions. [2023-11-26 11:51:22,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:51:22,671 INFO L428 stractBuchiCegarLoop]: Abstraction has 10847 states and 14563 transitions. [2023-11-26 11:51:22,671 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 11:51:22,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10847 states and 14563 transitions. [2023-11-26 11:51:22,706 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10656 [2023-11-26 11:51:22,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:22,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:22,708 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:22,708 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:22,709 INFO L748 eck$LassoCheckResult]: Stem: 153506#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 153507#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 153631#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 153632#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153614#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 153615#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 153441#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 153442#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 153420#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 153421#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 153713#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 153532#L611 assume !(0 == ~M_E~0); 153533#L611-2 assume !(0 == ~T1_E~0); 153732#L616-1 assume !(0 == ~T2_E~0); 153733#L621-1 assume !(0 == ~T3_E~0); 153284#L626-1 assume !(0 == ~T4_E~0); 153285#L631-1 assume !(0 == ~T5_E~0); 153485#L636-1 assume !(0 == ~E_M~0); 153336#L641-1 assume !(0 == ~E_1~0); 153337#L646-1 assume !(0 == ~E_2~0); 153503#L651-1 assume !(0 == ~E_3~0); 153791#L656-1 assume !(0 == ~E_4~0); 153711#L661-1 assume !(0 == ~E_5~0); 153712#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153756#L304 assume !(1 == ~m_pc~0); 153362#L304-2 is_master_triggered_~__retres1~0#1 := 0; 153260#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153261#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 153210#L755 assume !(0 != activate_threads_~tmp~1#1); 153211#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153167#L323 assume !(1 == ~t1_pc~0); 153168#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 153227#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153228#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 153837#L763 assume !(0 != activate_threads_~tmp___0~0#1); 153838#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153231#L342 assume !(1 == ~t2_pc~0); 153233#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 153370#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153371#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 153862#L771 assume !(0 != activate_threads_~tmp___1~0#1); 153863#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153574#L361 assume !(1 == ~t3_pc~0); 153575#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 153809#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153810#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 153781#L779 assume !(0 != activate_threads_~tmp___2~0#1); 153782#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153572#L380 assume !(1 == ~t4_pc~0); 153573#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 153724#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 153618#L787 assume !(0 != activate_threads_~tmp___3~0#1); 153619#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 153308#L399 assume !(1 == ~t5_pc~0); 153309#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 153895#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 153893#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 153892#L795 assume !(0 != activate_threads_~tmp___4~0#1); 153891#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153864#L679 assume !(1 == ~M_E~0); 153529#L679-2 assume !(1 == ~T1_E~0); 153383#L684-1 assume !(1 == ~T2_E~0); 153384#L689-1 assume !(1 == ~T3_E~0); 153585#L694-1 assume !(1 == ~T4_E~0); 153887#L699-1 assume !(1 == ~T5_E~0); 153886#L704-1 assume !(1 == ~E_M~0); 153556#L709-1 assume !(1 == ~E_1~0); 153489#L714-1 assume !(1 == ~E_2~0); 153490#L719-1 assume !(1 == ~E_3~0); 153697#L724-1 assume !(1 == ~E_4~0); 153272#L729-1 assume !(1 == ~E_5~0); 153273#L734-1 assume { :end_inline_reset_delta_events } true; 153812#L940-2 [2023-11-26 11:51:22,709 INFO L750 eck$LassoCheckResult]: Loop: 153812#L940-2 assume !false; 159200#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 159201#L586-1 assume !false; 159190#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 159191#L464 assume !(0 == ~m_st~0); 159185#L468 assume !(0 == ~t1_st~0); 159184#L472 assume !(0 == ~t2_st~0); 159183#L476 assume !(0 == ~t3_st~0); 159182#L480 assume !(0 == ~t4_st~0); 159180#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 159179#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 159178#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 159176#L511 assume !(0 != eval_~tmp~0#1); 159175#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 159174#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 159173#L611-3 assume !(0 == ~M_E~0); 159172#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 159171#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 159170#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 159169#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 159168#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 159167#L636-3 assume !(0 == ~E_M~0); 159166#L641-3 assume !(0 == ~E_1~0); 159165#L646-3 assume !(0 == ~E_2~0); 159164#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 159163#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 159162#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 159161#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159160#L304-21 assume 1 == ~m_pc~0; 159159#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 153850#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161572#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 161571#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 161567#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 161563#L323-21 assume !(1 == ~t1_pc~0); 161153#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 161114#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 161086#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 160816#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 160259#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160258#L342-21 assume !(1 == ~t2_pc~0); 160255#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 160253#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160249#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 160244#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 160239#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 160234#L361-21 assume 1 == ~t3_pc~0; 160230#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 160224#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160219#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 160209#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 160202#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 160186#L380-21 assume !(1 == ~t4_pc~0); 160164#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 160129#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 160124#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 160118#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 160112#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 160105#L399-21 assume 1 == ~t5_pc~0; 160099#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 160094#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160089#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 160084#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 160079#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160073#L679-3 assume !(1 == ~M_E~0); 157481#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 159208#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 159199#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 159194#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 159189#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 159112#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 159106#L709-3 assume !(1 == ~E_1~0); 159104#L714-3 assume !(1 == ~E_2~0); 159103#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 159092#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 159091#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 159089#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 159090#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 153549#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 153550#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 153597#L959 assume !(0 == start_simulation_~tmp~3#1); 153602#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 159295#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 159296#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 159287#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 159288#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 159282#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 159283#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 159275#L972 assume !(0 != start_simulation_~tmp___0~1#1); 153812#L940-2 [2023-11-26 11:51:22,710 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:22,710 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 6 times [2023-11-26 11:51:22,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:22,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39403918] [2023-11-26 11:51:22,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:22,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:22,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:22,725 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:22,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:22,750 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:22,750 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:22,751 INFO L85 PathProgramCache]: Analyzing trace with hash -220741444, now seen corresponding path program 1 times [2023-11-26 11:51:22,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:22,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074179441] [2023-11-26 11:51:22,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:22,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:22,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:22,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:22,843 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:22,843 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074179441] [2023-11-26 11:51:22,843 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2074179441] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:22,843 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:22,843 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:22,844 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [555995946] [2023-11-26 11:51:22,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:22,845 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:22,845 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:22,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:51:22,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:51:22,846 INFO L87 Difference]: Start difference. First operand 10847 states and 14563 transitions. cyclomatic complexity: 3720 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:23,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:23,032 INFO L93 Difference]: Finished difference Result 14075 states and 18653 transitions. [2023-11-26 11:51:23,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14075 states and 18653 transitions. [2023-11-26 11:51:23,286 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13868 [2023-11-26 11:51:23,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14075 states to 14075 states and 18653 transitions. [2023-11-26 11:51:23,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14075 [2023-11-26 11:51:23,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14075 [2023-11-26 11:51:23,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14075 states and 18653 transitions. [2023-11-26 11:51:23,364 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:23,364 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14075 states and 18653 transitions. [2023-11-26 11:51:23,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14075 states and 18653 transitions. [2023-11-26 11:51:23,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14075 to 10895. [2023-11-26 11:51:23,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10895 states, 10895 states have (on average 1.3269389628269848) internal successors, (14457), 10894 states have internal predecessors, (14457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:23,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10895 states to 10895 states and 14457 transitions. [2023-11-26 11:51:23,529 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10895 states and 14457 transitions. [2023-11-26 11:51:23,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:51:23,530 INFO L428 stractBuchiCegarLoop]: Abstraction has 10895 states and 14457 transitions. [2023-11-26 11:51:23,530 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 11:51:23,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10895 states and 14457 transitions. [2023-11-26 11:51:23,563 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10704 [2023-11-26 11:51:23,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:23,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:23,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:23,566 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:23,566 INFO L748 eck$LassoCheckResult]: Stem: 178455#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 178456#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 178587#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 178588#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 178571#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 178572#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 178384#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 178385#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 178355#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 178356#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 178677#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 178482#L611 assume !(0 == ~M_E~0); 178483#L611-2 assume !(0 == ~T1_E~0); 178695#L616-1 assume !(0 == ~T2_E~0); 178696#L621-1 assume !(0 == ~T3_E~0); 178218#L626-1 assume !(0 == ~T4_E~0); 178219#L631-1 assume !(0 == ~T5_E~0); 178428#L636-1 assume !(0 == ~E_M~0); 178267#L641-1 assume !(0 == ~E_1~0); 178268#L646-1 assume !(0 == ~E_2~0); 178450#L651-1 assume !(0 == ~E_3~0); 178756#L656-1 assume !(0 == ~E_4~0); 178675#L661-1 assume !(0 == ~E_5~0); 178676#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 178720#L304 assume !(1 == ~m_pc~0); 178295#L304-2 is_master_triggered_~__retres1~0#1 := 0; 178194#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 178195#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 178144#L755 assume !(0 != activate_threads_~tmp~1#1); 178145#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 178101#L323 assume !(1 == ~t1_pc~0); 178102#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 178161#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 178162#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 178806#L763 assume !(0 != activate_threads_~tmp___0~0#1); 178807#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 178164#L342 assume !(1 == ~t2_pc~0); 178166#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 178304#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 178305#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 178836#L771 assume !(0 != activate_threads_~tmp___1~0#1); 178837#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 178529#L361 assume !(1 == ~t3_pc~0); 178530#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 178777#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 178778#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 178750#L779 assume !(0 != activate_threads_~tmp___2~0#1); 178751#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 178527#L380 assume !(1 == ~t4_pc~0); 178528#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 178686#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 178687#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 178575#L787 assume !(0 != activate_threads_~tmp___3~0#1); 178576#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 178240#L399 assume !(1 == ~t5_pc~0); 178241#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 178875#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 178873#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 178872#L795 assume !(0 != activate_threads_~tmp___4~0#1); 178871#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178838#L679 assume !(1 == ~M_E~0); 178479#L679-2 assume !(1 == ~T1_E~0); 178317#L684-1 assume !(1 == ~T2_E~0); 178318#L689-1 assume !(1 == ~T3_E~0); 178540#L694-1 assume !(1 == ~T4_E~0); 178867#L699-1 assume !(1 == ~T5_E~0); 178866#L704-1 assume !(1 == ~E_M~0); 178509#L709-1 assume !(1 == ~E_1~0); 178434#L714-1 assume !(1 == ~E_2~0); 178435#L719-1 assume !(1 == ~E_3~0); 178659#L724-1 assume !(1 == ~E_4~0); 178206#L729-1 assume !(1 == ~E_5~0); 178207#L734-1 assume { :end_inline_reset_delta_events } true; 178779#L940-2 [2023-11-26 11:51:23,566 INFO L750 eck$LassoCheckResult]: Loop: 178779#L940-2 assume !false; 182708#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 182701#L586-1 assume !false; 182686#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 182679#L464 assume !(0 == ~m_st~0); 182636#L468 assume !(0 == ~t1_st~0); 179318#L472 assume !(0 == ~t2_st~0); 179319#L476 assume !(0 == ~t3_st~0); 182630#L480 assume !(0 == ~t4_st~0); 182628#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 179288#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 179281#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 179273#L511 assume !(0 != eval_~tmp~0#1); 179275#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 183317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 183316#L611-3 assume !(0 == ~M_E~0); 183315#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 183314#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 183313#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 183312#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 183311#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 179207#L636-3 assume !(0 == ~E_M~0); 179200#L641-3 assume !(0 == ~E_1~0); 179193#L646-3 assume !(0 == ~E_2~0); 179186#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 179178#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 179179#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 183291#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 183289#L304-21 assume 1 == ~m_pc~0; 183288#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 179148#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 179147#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 179145#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 179144#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 179143#L323-21 assume !(1 == ~t1_pc~0); 179142#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 179141#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 179140#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 179139#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 179138#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 179137#L342-21 assume !(1 == ~t2_pc~0); 179135#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 179134#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 179133#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 179132#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 179131#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 179130#L361-21 assume 1 == ~t3_pc~0; 179128#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 179126#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 179124#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 179122#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 179121#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 179119#L380-21 assume !(1 == ~t4_pc~0); 179120#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 179018#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 179019#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 179010#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 179011#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 179001#L399-21 assume 1 == ~t5_pc~0; 179002#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 178991#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 178992#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 178985#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 178986#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178978#L679-3 assume !(1 == ~M_E~0); 178975#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 178974#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 178973#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 178972#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 178971#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 178970#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 178969#L709-3 assume !(1 == ~E_1~0); 178968#L714-3 assume !(1 == ~E_2~0); 178967#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 178966#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 178965#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 178962#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 178957#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 178958#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 181651#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 181648#L959 assume !(0 == start_simulation_~tmp~3#1); 181649#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 182749#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 182747#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 182744#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 182738#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 182732#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 182727#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 182721#L972 assume !(0 != start_simulation_~tmp___0~1#1); 178779#L940-2 [2023-11-26 11:51:23,569 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:23,569 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 7 times [2023-11-26 11:51:23,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:23,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753974874] [2023-11-26 11:51:23,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:23,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:23,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:23,582 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:23,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:23,681 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:23,682 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:23,682 INFO L85 PathProgramCache]: Analyzing trace with hash 672744894, now seen corresponding path program 1 times [2023-11-26 11:51:23,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:23,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624591709] [2023-11-26 11:51:23,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:23,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:23,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:23,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:23,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:23,779 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624591709] [2023-11-26 11:51:23,779 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624591709] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:23,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:23,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:23,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [647666046] [2023-11-26 11:51:23,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:23,780 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:23,780 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:23,781 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:51:23,781 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:51:23,781 INFO L87 Difference]: Start difference. First operand 10895 states and 14457 transitions. cyclomatic complexity: 3566 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:24,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:24,032 INFO L93 Difference]: Finished difference Result 17185 states and 22613 transitions. [2023-11-26 11:51:24,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17185 states and 22613 transitions. [2023-11-26 11:51:24,121 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16978 [2023-11-26 11:51:24,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17185 states to 17185 states and 22613 transitions. [2023-11-26 11:51:24,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17185 [2023-11-26 11:51:24,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17185 [2023-11-26 11:51:24,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17185 states and 22613 transitions. [2023-11-26 11:51:24,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:24,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17185 states and 22613 transitions. [2023-11-26 11:51:24,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17185 states and 22613 transitions. [2023-11-26 11:51:24,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17185 to 11171. [2023-11-26 11:51:24,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11171 states, 11171 states have (on average 1.3118789723390922) internal successors, (14655), 11170 states have internal predecessors, (14655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:24,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11171 states to 11171 states and 14655 transitions. [2023-11-26 11:51:24,520 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11171 states and 14655 transitions. [2023-11-26 11:51:24,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:51:24,521 INFO L428 stractBuchiCegarLoop]: Abstraction has 11171 states and 14655 transitions. [2023-11-26 11:51:24,521 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 11:51:24,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11171 states and 14655 transitions. [2023-11-26 11:51:24,553 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10980 [2023-11-26 11:51:24,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:24,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:24,555 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:24,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:24,556 INFO L748 eck$LassoCheckResult]: Stem: 206536#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 206537#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 206670#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 206671#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 206651#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 206652#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 206471#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 206472#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 206450#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 206451#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 206746#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 206565#L611 assume !(0 == ~M_E~0); 206566#L611-2 assume !(0 == ~T1_E~0); 206766#L616-1 assume !(0 == ~T2_E~0); 206767#L621-1 assume !(0 == ~T3_E~0); 206315#L626-1 assume !(0 == ~T4_E~0); 206316#L631-1 assume !(0 == ~T5_E~0); 206516#L636-1 assume !(0 == ~E_M~0); 206365#L641-1 assume !(0 == ~E_1~0); 206366#L646-1 assume !(0 == ~E_2~0); 206531#L651-1 assume !(0 == ~E_3~0); 206829#L656-1 assume !(0 == ~E_4~0); 206744#L661-1 assume !(0 == ~E_5~0); 206745#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 206791#L304 assume !(1 == ~m_pc~0); 206397#L304-2 is_master_triggered_~__retres1~0#1 := 0; 206398#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 206481#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 206240#L755 assume !(0 != activate_threads_~tmp~1#1); 206241#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 206913#L323 assume !(1 == ~t1_pc~0); 206592#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 206593#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 206269#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 206270#L763 assume !(0 != activate_threads_~tmp___0~0#1); 206880#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 206881#L342 assume !(1 == ~t2_pc~0); 206742#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 206743#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 206672#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 206673#L771 assume !(0 != activate_threads_~tmp___1~0#1); 206737#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 206738#L361 assume !(1 == ~t3_pc~0); 206639#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 206640#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 206934#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 206935#L779 assume !(0 != activate_threads_~tmp___2~0#1); 206276#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 206277#L380 assume !(1 == ~t4_pc~0); 206898#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 206899#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 206360#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 206361#L787 assume !(0 != activate_threads_~tmp___3~0#1); 206930#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 206929#L399 assume !(1 == ~t5_pc~0); 206927#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 206926#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 206925#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 206924#L795 assume !(0 != activate_threads_~tmp___4~0#1); 206923#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 206894#L679 assume !(1 == ~M_E~0); 206564#L679-2 assume !(1 == ~T1_E~0); 206413#L684-1 assume !(1 == ~T2_E~0); 206414#L689-1 assume !(1 == ~T3_E~0); 206920#L694-1 assume !(1 == ~T4_E~0); 206919#L699-1 assume !(1 == ~T5_E~0); 206918#L704-1 assume !(1 == ~E_M~0); 206591#L709-1 assume !(1 == ~E_1~0); 206520#L714-1 assume !(1 == ~E_2~0); 206521#L719-1 assume !(1 == ~E_3~0); 206731#L724-1 assume !(1 == ~E_4~0); 206298#L729-1 assume !(1 == ~E_5~0); 206299#L734-1 assume { :end_inline_reset_delta_events } true; 206852#L940-2 [2023-11-26 11:51:24,556 INFO L750 eck$LassoCheckResult]: Loop: 206852#L940-2 assume !false; 207609#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 207610#L586-1 assume !false; 207587#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 207588#L464 assume !(0 == ~m_st~0); 207553#L468 assume !(0 == ~t1_st~0); 207547#L472 assume !(0 == ~t2_st~0); 207541#L476 assume !(0 == ~t3_st~0); 207535#L480 assume !(0 == ~t4_st~0); 207528#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 207519#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 207511#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 207502#L511 assume !(0 != eval_~tmp~0#1); 207491#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 207483#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 207477#L611-3 assume !(0 == ~M_E~0); 207471#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 207465#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 207459#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 207453#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 207447#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 207441#L636-3 assume !(0 == ~E_M~0); 207435#L641-3 assume !(0 == ~E_1~0); 207427#L646-3 assume !(0 == ~E_2~0); 207421#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 207415#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 207409#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 207403#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 207396#L304-21 assume 1 == ~m_pc~0; 207395#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 207297#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 207295#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 207292#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 207289#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 207287#L323-21 assume !(1 == ~t1_pc~0); 207285#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 207283#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 207281#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 207279#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 207277#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 207275#L342-21 assume !(1 == ~t2_pc~0); 207271#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 207269#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 207267#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 207265#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 207263#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 207261#L361-21 assume !(1 == ~t3_pc~0); 207259#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 207255#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 207251#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 207247#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 207243#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 207241#L380-21 assume !(1 == ~t4_pc~0); 207239#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 207237#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 207235#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 207233#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 207231#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 207229#L399-21 assume !(1 == ~t5_pc~0); 207227#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 207223#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 207221#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 207219#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 207217#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 207215#L679-3 assume !(1 == ~M_E~0); 207207#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 207208#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 207195#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 207196#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 207184#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 207185#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 207176#L709-3 assume !(1 == ~E_1~0); 207177#L714-3 assume !(1 == ~E_2~0); 207168#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 207169#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 207719#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 207157#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 207158#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 207706#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 207702#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 207699#L959 assume !(0 == start_simulation_~tmp~3#1); 207696#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 207691#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 207692#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 207683#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 207684#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 207675#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 207676#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 208748#L972 assume !(0 != start_simulation_~tmp___0~1#1); 206852#L940-2 [2023-11-26 11:51:24,557 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:24,557 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 8 times [2023-11-26 11:51:24,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:24,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433942276] [2023-11-26 11:51:24,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:24,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:24,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:24,569 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:24,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:24,589 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:24,589 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:24,590 INFO L85 PathProgramCache]: Analyzing trace with hash -1117949500, now seen corresponding path program 1 times [2023-11-26 11:51:24,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:24,590 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552914005] [2023-11-26 11:51:24,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:24,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:24,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:24,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:24,666 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:24,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552914005] [2023-11-26 11:51:24,667 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552914005] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:24,667 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:24,667 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:51:24,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56310450] [2023-11-26 11:51:24,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:24,668 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:24,668 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:24,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:51:24,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:51:24,669 INFO L87 Difference]: Start difference. First operand 11171 states and 14655 transitions. cyclomatic complexity: 3488 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:25,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:25,011 INFO L93 Difference]: Finished difference Result 21909 states and 28347 transitions. [2023-11-26 11:51:25,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21909 states and 28347 transitions. [2023-11-26 11:51:25,099 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21624 [2023-11-26 11:51:25,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21909 states to 21909 states and 28347 transitions. [2023-11-26 11:51:25,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21909 [2023-11-26 11:51:25,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21909 [2023-11-26 11:51:25,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21909 states and 28347 transitions. [2023-11-26 11:51:25,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:51:25,198 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21909 states and 28347 transitions. [2023-11-26 11:51:25,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21909 states and 28347 transitions. [2023-11-26 11:51:25,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21909 to 11681. [2023-11-26 11:51:25,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11681 states, 11681 states have (on average 1.2982621350911736) internal successors, (15165), 11680 states have internal predecessors, (15165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:25,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11681 states to 11681 states and 15165 transitions. [2023-11-26 11:51:25,388 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11681 states and 15165 transitions. [2023-11-26 11:51:25,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:51:25,389 INFO L428 stractBuchiCegarLoop]: Abstraction has 11681 states and 15165 transitions. [2023-11-26 11:51:25,389 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 11:51:25,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11681 states and 15165 transitions. [2023-11-26 11:51:25,479 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11484 [2023-11-26 11:51:25,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:25,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:25,481 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:25,482 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:25,482 INFO L748 eck$LassoCheckResult]: Stem: 239629#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 239630#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 239756#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 239757#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 239740#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 239741#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 239564#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 239565#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 239544#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 239545#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 239834#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 239658#L611 assume !(0 == ~M_E~0); 239659#L611-2 assume !(0 == ~T1_E~0); 239855#L616-1 assume !(0 == ~T2_E~0); 239856#L621-1 assume !(0 == ~T3_E~0); 239409#L626-1 assume !(0 == ~T4_E~0); 239410#L631-1 assume !(0 == ~T5_E~0); 239610#L636-1 assume !(0 == ~E_M~0); 239457#L641-1 assume !(0 == ~E_1~0); 239458#L646-1 assume !(0 == ~E_2~0); 239625#L651-1 assume !(0 == ~E_3~0); 239902#L656-1 assume !(0 == ~E_4~0); 239832#L661-1 assume !(0 == ~E_5~0); 239833#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 239873#L304 assume !(1 == ~m_pc~0); 239488#L304-2 is_master_triggered_~__retres1~0#1 := 0; 239381#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 239382#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 239332#L755 assume !(0 != activate_threads_~tmp~1#1); 239333#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 239287#L323 assume !(1 == ~t1_pc~0); 239288#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 239345#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 239346#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 239943#L763 assume !(0 != activate_threads_~tmp___0~0#1); 239944#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 239355#L342 assume !(1 == ~t2_pc~0); 239357#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 239490#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 239491#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 239966#L771 assume !(0 != activate_threads_~tmp___1~0#1); 239967#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 239699#L361 assume !(1 == ~t3_pc~0); 239700#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 239926#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 239927#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 239897#L779 assume !(0 != activate_threads_~tmp___2~0#1); 239898#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 239697#L380 assume !(1 == ~t4_pc~0); 239698#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 239847#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 239848#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 239743#L787 assume !(0 != activate_threads_~tmp___3~0#1); 239744#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 239427#L399 assume !(1 == ~t5_pc~0); 239428#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 240006#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 240004#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 240002#L795 assume !(0 != activate_threads_~tmp___4~0#1); 239917#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 239918#L679 assume !(1 == ~M_E~0); 239656#L679-2 assume !(1 == ~T1_E~0); 239657#L684-1 assume !(1 == ~T2_E~0); 240000#L689-1 assume !(1 == ~T3_E~0); 239999#L694-1 assume !(1 == ~T4_E~0); 239998#L699-1 assume !(1 == ~T5_E~0); 239995#L704-1 assume !(1 == ~E_M~0); 239682#L709-1 assume !(1 == ~E_1~0); 239614#L714-1 assume !(1 == ~E_2~0); 239615#L719-1 assume !(1 == ~E_3~0); 239817#L724-1 assume !(1 == ~E_4~0); 239392#L729-1 assume !(1 == ~E_5~0); 239393#L734-1 assume { :end_inline_reset_delta_events } true; 239928#L940-2 [2023-11-26 11:51:25,482 INFO L750 eck$LassoCheckResult]: Loop: 239928#L940-2 assume !false; 241566#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 241567#L586-1 assume !false; 241542#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 241543#L464 assume !(0 == ~m_st~0); 242335#L468 assume !(0 == ~t1_st~0); 245697#L472 assume !(0 == ~t2_st~0); 245695#L476 assume !(0 == ~t3_st~0); 245696#L480 assume !(0 == ~t4_st~0); 245694#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 245689#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 245684#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 245681#L511 assume !(0 != eval_~tmp~0#1); 245678#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 245675#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 245672#L611-3 assume !(0 == ~M_E~0); 245669#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 245666#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 245662#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 245658#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 245654#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 245650#L636-3 assume !(0 == ~E_M~0); 245647#L641-3 assume !(0 == ~E_1~0); 245644#L646-3 assume !(0 == ~E_2~0); 245641#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 245638#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 245635#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 245632#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 245617#L304-21 assume 1 == ~m_pc~0; 245616#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 242550#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 242549#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 242547#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 242546#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 242545#L323-21 assume !(1 == ~t1_pc~0); 242544#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 242543#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 242542#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 242541#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 242540#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 242539#L342-21 assume !(1 == ~t2_pc~0); 242537#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 242536#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242535#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 242534#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 242533#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 242532#L361-21 assume !(1 == ~t3_pc~0); 242531#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 242529#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 242527#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 242525#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 242523#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 242522#L380-21 assume !(1 == ~t4_pc~0); 242521#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 242520#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 242519#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 242518#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 242517#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 242516#L399-21 assume !(1 == ~t5_pc~0); 242515#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 242513#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 242511#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 242509#L795-21 assume !(0 != activate_threads_~tmp___4~0#1); 242437#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 242433#L679-3 assume !(1 == ~M_E~0); 242429#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 242427#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 242424#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 242421#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 242416#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 242411#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 242407#L709-3 assume !(1 == ~E_1~0); 242403#L714-3 assume !(1 == ~E_2~0); 242399#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 242385#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 242382#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 242380#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 242377#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 242375#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 242373#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 242368#L959 assume !(0 == start_simulation_~tmp~3#1); 242360#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 242356#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 242353#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 242352#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 242351#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 241593#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 241594#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 241588#L972 assume !(0 != start_simulation_~tmp___0~1#1); 239928#L940-2 [2023-11-26 11:51:25,483 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:25,483 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 9 times [2023-11-26 11:51:25,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:25,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946425039] [2023-11-26 11:51:25,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:25,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:25,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:25,496 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:25,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:25,516 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:25,517 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:25,517 INFO L85 PathProgramCache]: Analyzing trace with hash 805278534, now seen corresponding path program 1 times [2023-11-26 11:51:25,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:25,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679934752] [2023-11-26 11:51:25,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:25,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:25,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:25,530 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:25,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:25,550 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:25,550 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:25,550 INFO L85 PathProgramCache]: Analyzing trace with hash -1591372926, now seen corresponding path program 1 times [2023-11-26 11:51:25,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:25,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21642783] [2023-11-26 11:51:25,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:25,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:25,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:25,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:25,616 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:25,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21642783] [2023-11-26 11:51:25,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21642783] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:25,616 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:25,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:25,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246767440] [2023-11-26 11:51:25,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:27,437 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 11:51:27,438 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 11:51:27,438 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 11:51:27,438 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 11:51:27,438 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-26 11:51:27,439 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:27,439 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 11:51:27,439 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 11:51:27,439 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-2.c_Iteration22_Loop [2023-11-26 11:51:27,439 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 11:51:27,440 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 11:51:27,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,476 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,482 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,485 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,491 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,495 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,497 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,500 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,503 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,508 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,512 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,514 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,517 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,520 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,523 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,527 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,533 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,536 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,538 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,541 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,544 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,546 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,556 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,559 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,562 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,567 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,570 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,577 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,584 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,586 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,592 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,595 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,601 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,607 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,610 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,613 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,616 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,618 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,622 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,624 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,627 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,630 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,635 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,647 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,656 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,665 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,668 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,675 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,693 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,710 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:27,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,356 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 11:51:28,357 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-26 11:51:28,359 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:28,360 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:28,363 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:28,374 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:51:28,375 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:51:28,387 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-26 11:51:28,402 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:51:28,402 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:51:28,439 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:28,439 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:28,439 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:28,441 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:28,451 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-26 11:51:28,452 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:51:28,452 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:51:28,475 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:51:28,475 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:51:28,480 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:28,481 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:28,481 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:28,482 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:28,483 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-26 11:51:28,485 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:51:28,485 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:51:28,511 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:51:28,511 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:51:28,520 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:28,520 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:28,521 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:28,522 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:28,527 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-26 11:51:28,528 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:51:28,528 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:51:28,563 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 11:51:28,563 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 11:51:28,591 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:28,591 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:28,591 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:28,595 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:28,612 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-26 11:51:28,614 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 11:51:28,614 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:51:28,644 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:28,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:28,645 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:28,646 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:28,650 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-26 11:51:28,651 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-26 11:51:28,652 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 11:51:28,687 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-26 11:51:28,699 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:28,699 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 11:51:28,699 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 11:51:28,699 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 11:51:28,699 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 11:51:28,699 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-26 11:51:28,700 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:28,700 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 11:51:28,700 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 11:51:28,700 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-2.c_Iteration22_Loop [2023-11-26 11:51:28,700 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 11:51:28,700 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 11:51:28,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,752 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,755 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,758 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,764 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,777 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,782 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,785 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,788 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,795 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,799 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,805 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,807 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,818 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,823 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,834 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,837 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,849 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,853 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,858 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,860 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,866 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,874 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,877 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,886 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,891 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,897 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,911 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,919 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,922 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,924 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,926 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,929 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,931 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,933 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,938 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,940 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,942 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,947 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,953 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,955 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,958 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,961 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:28,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:51:29,516 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 11:51:29,526 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-26 11:51:29,527 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:29,528 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:29,529 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:29,538 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:51:29,551 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-26 11:51:29,551 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:51:29,551 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:51:29,552 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:51:29,552 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:51:29,552 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:51:29,554 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:51:29,554 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:51:29,558 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:51:29,567 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2023-11-26 11:51:29,567 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:29,568 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:29,571 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:29,580 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:51:29,592 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:51:29,592 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:51:29,592 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:51:29,593 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-26 11:51:29,593 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:51:29,595 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-26 11:51:29,596 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:51:29,605 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:51:29,607 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-26 11:51:29,609 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:29,609 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:29,609 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:29,610 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:29,635 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:51:29,647 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:51:29,648 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:51:29,651 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:51:29,651 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:51:29,651 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:51:29,652 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:51:29,652 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:51:29,653 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-26 11:51:29,673 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:51:29,681 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:29,682 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:29,682 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:29,683 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:29,697 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:51:29,710 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:51:29,710 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:51:29,710 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:51:29,710 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:51:29,710 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:51:29,711 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:51:29,711 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:51:29,712 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-26 11:51:29,721 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:51:29,729 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:29,729 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:29,729 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:29,730 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:29,740 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:51:29,752 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:51:29,752 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:51:29,752 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:51:29,752 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:51:29,752 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:51:29,753 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:51:29,754 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:51:29,756 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-26 11:51:29,767 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-26 11:51:29,770 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-26 11:51:29,770 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-26 11:51:29,771 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:51:29,772 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:51:29,801 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:51:29,808 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-26 11:51:29,808 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-26 11:51:29,808 INFO L513 LassoAnalysis]: Proved termination. [2023-11-26 11:51:29,808 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2023-11-26 11:51:29,810 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-26 11:51:29,816 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:29,819 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-26 11:51:29,837 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:29,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:29,885 INFO L262 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-26 11:51:29,888 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:51:30,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:30,032 INFO L262 TraceCheckSpWp]: Trace formula consists of 193 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-26 11:51:30,035 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:51:30,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:30,267 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-26 11:51:30,268 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11681 states and 15165 transitions. cyclomatic complexity: 3488 Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:30,562 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11681 states and 15165 transitions. cyclomatic complexity: 3488. Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 31611 states and 41392 transitions. Complement of second has 5 states. [2023-11-26 11:51:30,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-26 11:51:30,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:30,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 725 transitions. [2023-11-26 11:51:30,567 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 725 transitions. Stem has 73 letters. Loop has 89 letters. [2023-11-26 11:51:30,571 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:51:30,571 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 725 transitions. Stem has 162 letters. Loop has 89 letters. [2023-11-26 11:51:30,573 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:51:30,573 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 725 transitions. Stem has 73 letters. Loop has 178 letters. [2023-11-26 11:51:30,575 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:51:30,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31611 states and 41392 transitions. [2023-11-26 11:51:30,750 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21304 [2023-11-26 11:51:30,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31611 states to 31579 states and 41360 transitions. [2023-11-26 11:51:30,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21598 [2023-11-26 11:51:30,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21647 [2023-11-26 11:51:30,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31579 states and 41360 transitions. [2023-11-26 11:51:30,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:51:30,902 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31579 states and 41360 transitions. [2023-11-26 11:51:30,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31579 states and 41360 transitions. [2023-11-26 11:51:31,319 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66ea506b-d7b3-4803-84b0-bcc30c181a3f/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-26 11:51:31,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31579 to 31498. [2023-11-26 11:51:31,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31498 states, 31498 states have (on average 1.3090037462696045) internal successors, (41231), 31497 states have internal predecessors, (41231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:31,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31498 states to 31498 states and 41231 transitions. [2023-11-26 11:51:31,514 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31498 states and 41231 transitions. [2023-11-26 11:51:31,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:31,514 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:31,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:31,515 INFO L87 Difference]: Start difference. First operand 31498 states and 41231 transitions. Second operand has 3 states, 3 states have (on average 54.0) internal successors, (162), 3 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:31,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:31,898 INFO L93 Difference]: Finished difference Result 32578 states and 42407 transitions. [2023-11-26 11:51:31,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32578 states and 42407 transitions. [2023-11-26 11:51:32,058 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22024 [2023-11-26 11:51:32,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32578 states to 32578 states and 42407 transitions. [2023-11-26 11:51:32,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22286 [2023-11-26 11:51:32,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22286 [2023-11-26 11:51:32,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32578 states and 42407 transitions. [2023-11-26 11:51:32,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:51:32,632 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32578 states and 42407 transitions. [2023-11-26 11:51:32,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32578 states and 42407 transitions. [2023-11-26 11:51:32,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32578 to 31498. [2023-11-26 11:51:32,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31498 states, 31498 states have (on average 1.304432027430313) internal successors, (41087), 31497 states have internal predecessors, (41087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:33,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31498 states to 31498 states and 41087 transitions. [2023-11-26 11:51:33,263 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31498 states and 41087 transitions. [2023-11-26 11:51:33,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:33,265 INFO L428 stractBuchiCegarLoop]: Abstraction has 31498 states and 41087 transitions. [2023-11-26 11:51:33,266 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-26 11:51:33,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31498 states and 41087 transitions. [2023-11-26 11:51:33,359 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21304 [2023-11-26 11:51:33,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:33,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:33,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:33,363 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:33,363 INFO L748 eck$LassoCheckResult]: Stem: 347793#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 347794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 348027#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 348028#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 347995#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 347996#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 347668#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 347669#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 347623#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 347624#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 348188#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 347846#L611 assume !(0 == ~M_E~0); 347847#L611-2 assume !(0 == ~T1_E~0); 348222#L616-1 assume !(0 == ~T2_E~0); 348223#L621-1 assume !(0 == ~T3_E~0); 347373#L626-1 assume !(0 == ~T4_E~0); 347374#L631-1 assume !(0 == ~T5_E~0); 347754#L636-1 assume !(0 == ~E_M~0); 347462#L641-1 assume !(0 == ~E_1~0); 347463#L646-1 assume !(0 == ~E_2~0); 347784#L651-1 assume !(0 == ~E_3~0); 348316#L656-1 assume !(0 == ~E_4~0); 348186#L661-1 assume !(0 == ~E_5~0); 348187#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 348260#L304 assume !(1 == ~m_pc~0); 347519#L304-2 is_master_triggered_~__retres1~0#1 := 0; 347520#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 347683#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 347684#L755 assume !(0 != activate_threads_~tmp~1#1); 348469#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 348470#L323 assume !(1 == ~t1_pc~0); 347897#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 347898#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 347295#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 347296#L763 assume !(0 != activate_threads_~tmp___0~0#1); 348402#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 348403#L342 assume !(1 == ~t2_pc~0); 348184#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 348185#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 348029#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 348030#L771 assume !(0 != activate_threads_~tmp___1~0#1); 348175#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 348176#L361 assume !(1 == ~t3_pc~0); 347976#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 347977#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 348484#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 348485#L779 assume !(0 != activate_threads_~tmp___2~0#1); 347307#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 347308#L380 assume !(1 == ~t4_pc~0); 348446#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 348447#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 347454#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 347455#L787 assume !(0 != activate_threads_~tmp___3~0#1); 348419#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 348420#L399 assume !(1 == ~t5_pc~0); 347689#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 347690#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 348489#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 348490#L795 assume !(0 != activate_threads_~tmp___4~0#1); 348340#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 348341#L679 assume !(1 == ~M_E~0); 347844#L679-2 assume !(1 == ~T1_E~0); 347845#L684-1 assume !(1 == ~T2_E~0); 347934#L689-1 assume !(1 == ~T3_E~0); 347935#L694-1 assume !(1 == ~T4_E~0); 348482#L699-1 assume !(1 == ~T5_E~0); 348481#L704-1 assume !(1 == ~E_M~0); 347896#L709-1 assume !(1 == ~E_1~0); 347765#L714-1 assume !(1 == ~E_2~0); 347766#L719-1 assume !(1 == ~E_3~0); 348162#L724-1 assume !(1 == ~E_4~0); 347340#L729-1 assume !(1 == ~E_5~0); 347341#L734-1 assume { :end_inline_reset_delta_events } true; 348354#L940-2 assume !false; 352356#L941 [2023-11-26 11:51:33,371 INFO L750 eck$LassoCheckResult]: Loop: 352356#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 360682#L586-1 assume !false; 360681#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 360680#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 360679#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 360678#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 360677#L511 assume 0 != eval_~tmp~0#1; 360676#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 360672#L519 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;havoc master_#t~nondet4#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 360668#L68 assume 0 == ~m_pc~0; 360665#L104 assume !false; 360664#L80 havoc master_#t~nondet5#1;~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 360662#L304-3 assume 1 == ~m_pc~0; 360660#L305-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 360661#L315-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 367275#is_master_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 365626#L755-3 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 365622#L755-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 365620#L323-3 assume !(1 == ~t1_pc~0); 365618#L323-5 is_transmit1_triggered_~__retres1~1#1 := 0; 365616#L334-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365613#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 365611#L763-3 assume !(0 != activate_threads_~tmp___0~0#1); 365609#L763-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365607#L342-3 assume !(1 == ~t2_pc~0); 365604#L342-5 is_transmit2_triggered_~__retres1~2#1 := 0; 365602#L353-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 365600#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 365598#L771-3 assume !(0 != activate_threads_~tmp___1~0#1); 365597#L771-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 365593#L361-3 assume !(1 == ~t3_pc~0); 365589#L361-5 is_transmit3_triggered_~__retres1~3#1 := 0; 365587#L372-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 365585#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 365582#L779-3 assume !(0 != activate_threads_~tmp___2~0#1); 365574#L779-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 365572#L380-3 assume !(1 == ~t4_pc~0); 365483#L380-5 is_transmit4_triggered_~__retres1~4#1 := 0; 365479#L391-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 365477#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 365475#L787-3 assume !(0 != activate_threads_~tmp___3~0#1); 365474#L787-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 365473#L399-3 assume 1 == ~t5_pc~0; 365472#L400-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 365470#L410-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 365468#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 365465#L795-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 365464#L795-5 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 360123#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 360121#master_returnLabel#1 havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;assume { :end_inline_master } true; 360118#L519-2 havoc eval_~tmp_ndt_1~0#1; 360116#L516-1 assume !(0 == ~t1_st~0); 360111#L530-1 assume !(0 == ~t2_st~0); 360108#L544-1 assume !(0 == ~t3_st~0); 360107#L558-1 assume !(0 == ~t4_st~0); 360274#L572-1 assume !(0 == ~t5_st~0); 360272#L586-1 assume !false; 360270#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 360268#L464 assume !(0 == ~m_st~0); 360265#L468 assume !(0 == ~t1_st~0); 360266#L472 assume !(0 == ~t2_st~0); 360263#L476 assume !(0 == ~t3_st~0); 360264#L480 assume !(0 == ~t4_st~0); 360261#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 360260#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 360081#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 360078#L511 assume !(0 != eval_~tmp~0#1); 360080#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 361212#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 361210#L611-3 assume !(0 == ~M_E~0); 361208#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 361207#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 361205#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 361203#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 361201#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 361199#L636-3 assume !(0 == ~E_M~0); 361197#L641-3 assume !(0 == ~E_1~0); 361195#L646-3 assume !(0 == ~E_2~0); 361194#L651-3 assume !(0 == ~E_3~0); 361192#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 360065#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 361189#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 361187#L304-21 assume 1 == ~m_pc~0; 360058#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 360056#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 360054#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 360051#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 360049#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 360047#L323-21 assume !(1 == ~t1_pc~0); 360045#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 360043#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 360041#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 360039#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 360037#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 360034#L342-21 assume !(1 == ~t2_pc~0); 360031#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 360030#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 360029#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 360028#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 360027#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 360026#L361-21 assume 1 == ~t3_pc~0; 360025#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 360023#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 360021#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 360018#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 360017#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 360016#L380-21 assume !(1 == ~t4_pc~0); 360014#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 360013#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 360012#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 360011#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 360010#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 360009#L399-21 assume !(1 == ~t5_pc~0); 360005#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 360004#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 360003#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 360002#L795-21 assume !(0 != activate_threads_~tmp___4~0#1); 359999#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 359995#L679-3 assume !(1 == ~M_E~0); 359872#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 359992#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 359990#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 359988#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 359986#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 359984#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 359982#L709-3 assume !(1 == ~E_1~0); 359980#L714-3 assume !(1 == ~E_2~0); 359978#L719-3 assume !(1 == ~E_3~0); 359976#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 359974#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 359972#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 359971#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 359970#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 359969#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 359967#L959 assume !(0 == start_simulation_~tmp~3#1); 359968#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 360920#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 360919#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 360918#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 360915#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 360913#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 360911#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 360909#L972 assume !(0 != start_simulation_~tmp___0~1#1); 360904#L940-2 assume !false; 352356#L941 [2023-11-26 11:51:33,372 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:33,372 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 1 times [2023-11-26 11:51:33,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:33,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699129937] [2023-11-26 11:51:33,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:33,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:33,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:33,387 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:33,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:33,418 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:33,420 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:33,420 INFO L85 PathProgramCache]: Analyzing trace with hash 1925164, now seen corresponding path program 1 times [2023-11-26 11:51:33,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:33,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96264601] [2023-11-26 11:51:33,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:33,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:33,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:33,481 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:33,482 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:33,482 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96264601] [2023-11-26 11:51:33,482 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [96264601] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:33,482 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:33,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:33,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1296538793] [2023-11-26 11:51:33,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:33,483 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:51:33,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:33,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:33,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:33,485 INFO L87 Difference]: Start difference. First operand 31498 states and 41087 transitions. cyclomatic complexity: 9601 Second operand has 3 states, 3 states have (on average 48.0) internal successors, (144), 3 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:33,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:33,695 INFO L93 Difference]: Finished difference Result 36534 states and 47220 transitions. [2023-11-26 11:51:33,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36534 states and 47220 transitions. [2023-11-26 11:51:33,875 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24728 [2023-11-26 11:51:34,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36534 states to 36534 states and 47220 transitions. [2023-11-26 11:51:34,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24972 [2023-11-26 11:51:34,282 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24972 [2023-11-26 11:51:34,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36534 states and 47220 transitions. [2023-11-26 11:51:34,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:51:34,290 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36534 states and 47220 transitions. [2023-11-26 11:51:34,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36534 states and 47220 transitions. [2023-11-26 11:51:34,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36534 to 34182. [2023-11-26 11:51:34,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34182 states, 34182 states have (on average 1.2985781990521328) internal successors, (44388), 34181 states have internal predecessors, (44388), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:34,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34182 states to 34182 states and 44388 transitions. [2023-11-26 11:51:34,919 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34182 states and 44388 transitions. [2023-11-26 11:51:34,920 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:34,920 INFO L428 stractBuchiCegarLoop]: Abstraction has 34182 states and 44388 transitions. [2023-11-26 11:51:34,920 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-26 11:51:34,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34182 states and 44388 transitions. [2023-11-26 11:51:35,049 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23160 [2023-11-26 11:51:35,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:35,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:35,051 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:35,051 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:35,051 INFO L748 eck$LassoCheckResult]: Stem: 415822#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 415823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 416053#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 416054#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 416018#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 416019#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 415706#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 415707#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 415659#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 415660#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 416215#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 415870#L611 assume !(0 == ~M_E~0); 415871#L611-2 assume !(0 == ~T1_E~0); 416253#L616-1 assume !(0 == ~T2_E~0); 416254#L621-1 assume !(0 == ~T3_E~0); 415411#L626-1 assume !(0 == ~T4_E~0); 415412#L631-1 assume !(0 == ~T5_E~0); 415790#L636-1 assume !(0 == ~E_M~0); 415501#L641-1 assume !(0 == ~E_1~0); 415502#L646-1 assume !(0 == ~E_2~0); 415816#L651-1 assume !(0 == ~E_3~0); 416348#L656-1 assume !(0 == ~E_4~0); 416213#L661-1 assume !(0 == ~E_5~0); 416214#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 416292#L304 assume !(1 == ~m_pc~0); 415559#L304-2 is_master_triggered_~__retres1~0#1 := 0; 415362#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 415363#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 415288#L755 assume !(0 != activate_threads_~tmp~1#1); 415289#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 415213#L323 assume !(1 == ~t1_pc~0); 415214#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 415309#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 415310#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 415334#L763 assume !(0 != activate_threads_~tmp___0~0#1); 416438#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 415325#L342 assume !(1 == ~t2_pc~0); 415327#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 415562#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 415563#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 416059#L771 assume !(0 != activate_threads_~tmp___1~0#1); 416202#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 415946#L361 assume !(1 == ~t3_pc~0); 415947#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 416001#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 416388#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 416340#L779 assume !(0 != activate_threads_~tmp___2~0#1); 415345#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 415346#L380 assume !(1 == ~t4_pc~0); 415943#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 416239#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 415493#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 415494#L787 assume !(0 != activate_threads_~tmp___3~0#1); 416025#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 415445#L399 assume !(1 == ~t5_pc~0); 415446#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 415728#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 416257#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 415708#L795 assume !(0 != activate_threads_~tmp___4~0#1); 415709#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 416381#L679 assume !(1 == ~M_E~0); 415869#L679-2 assume !(1 == ~T1_E~0); 415587#L684-1 assume !(1 == ~T2_E~0); 415588#L689-1 assume !(1 == ~T3_E~0); 415959#L694-1 assume !(1 == ~T4_E~0); 415957#L699-1 assume !(1 == ~T5_E~0); 415958#L704-1 assume !(1 == ~E_M~0); 415922#L709-1 assume !(1 == ~E_1~0); 415797#L714-1 assume !(1 == ~E_2~0); 415798#L719-1 assume !(1 == ~E_3~0); 416190#L724-1 assume !(1 == ~E_4~0); 415378#L729-1 assume !(1 == ~E_5~0); 415379#L734-1 assume { :end_inline_reset_delta_events } true; 416389#L940-2 assume !false; 420399#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 430977#L586-1 [2023-11-26 11:51:35,052 INFO L750 eck$LassoCheckResult]: Loop: 430977#L586-1 assume !false; 430975#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 430973#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 430971#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 430969#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 430967#L511 assume 0 != eval_~tmp~0#1; 430965#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 430962#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 430958#L519-2 havoc eval_~tmp_ndt_1~0#1; 430955#L516-1 assume !(0 == ~t1_st~0); 430951#L530-1 assume !(0 == ~t2_st~0); 430952#L544-1 assume !(0 == ~t3_st~0); 430985#L558-1 assume !(0 == ~t4_st~0); 430981#L572-1 assume !(0 == ~t5_st~0); 430977#L586-1 [2023-11-26 11:51:35,052 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:35,053 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 1 times [2023-11-26 11:51:35,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:35,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734476612] [2023-11-26 11:51:35,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:35,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:35,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:35,067 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:35,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:35,097 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:35,098 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:35,098 INFO L85 PathProgramCache]: Analyzing trace with hash -54895709, now seen corresponding path program 1 times [2023-11-26 11:51:35,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:35,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425625708] [2023-11-26 11:51:35,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:35,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:35,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:35,104 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:35,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:35,109 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:35,110 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:35,110 INFO L85 PathProgramCache]: Analyzing trace with hash -1589568855, now seen corresponding path program 1 times [2023-11-26 11:51:35,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:35,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724201768] [2023-11-26 11:51:35,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:35,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:35,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:35,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:35,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:35,164 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1724201768] [2023-11-26 11:51:35,164 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1724201768] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:35,164 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:35,164 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:35,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62468207] [2023-11-26 11:51:35,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:35,245 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:35,246 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:35,247 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:35,247 INFO L87 Difference]: Start difference. First operand 34182 states and 44388 transitions. cyclomatic complexity: 10230 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:35,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:35,817 INFO L93 Difference]: Finished difference Result 58414 states and 75098 transitions. [2023-11-26 11:51:35,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58414 states and 75098 transitions. [2023-11-26 11:51:36,072 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 38796 [2023-11-26 11:51:36,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58414 states to 58414 states and 75098 transitions. [2023-11-26 11:51:36,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40194 [2023-11-26 11:51:36,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40194 [2023-11-26 11:51:36,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58414 states and 75098 transitions. [2023-11-26 11:51:36,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:51:36,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 58414 states and 75098 transitions. [2023-11-26 11:51:36,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58414 states and 75098 transitions. [2023-11-26 11:51:37,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58414 to 58414. [2023-11-26 11:51:37,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58414 states, 58414 states have (on average 1.285616461807101) internal successors, (75098), 58413 states have internal predecessors, (75098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:37,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58414 states to 58414 states and 75098 transitions. [2023-11-26 11:51:37,320 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58414 states and 75098 transitions. [2023-11-26 11:51:37,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:37,321 INFO L428 stractBuchiCegarLoop]: Abstraction has 58414 states and 75098 transitions. [2023-11-26 11:51:37,321 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-26 11:51:37,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58414 states and 75098 transitions. [2023-11-26 11:51:37,498 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 38796 [2023-11-26 11:51:37,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:37,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:37,499 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:37,499 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:37,499 INFO L748 eck$LassoCheckResult]: Stem: 508419#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 508420#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 508650#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 508651#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 508615#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 508616#L426-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 508753#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 508743#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 508744#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 509059#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 509060#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 508471#L611 assume !(0 == ~M_E~0); 508472#L611-2 assume !(0 == ~T1_E~0); 508859#L616-1 assume !(0 == ~T2_E~0); 508860#L621-1 assume !(0 == ~T3_E~0); 508002#L626-1 assume !(0 == ~T4_E~0); 508003#L631-1 assume !(0 == ~T5_E~0); 508374#L636-1 assume !(0 == ~E_M~0); 508375#L641-1 assume !(0 == ~E_1~0); 508410#L646-1 assume !(0 == ~E_2~0); 508411#L651-1 assume !(0 == ~E_3~0); 508963#L656-1 assume !(0 == ~E_4~0); 508964#L661-1 assume !(0 == ~E_5~0); 508902#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 508903#L304 assume !(1 == ~m_pc~0); 508146#L304-2 is_master_triggered_~__retres1~0#1 := 0; 508147#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 508309#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 508310#L755 assume !(0 != activate_threads_~tmp~1#1); 509114#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 509115#L323 assume !(1 == ~t1_pc~0); 508524#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 508525#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 507936#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 507937#L763 assume !(0 != activate_threads_~tmp___0~0#1); 509061#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 509062#L342 assume !(1 == ~t2_pc~0); 508818#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 508819#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 508656#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 508657#L771 assume !(0 != activate_threads_~tmp___1~0#1); 508803#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 508804#L361 assume !(1 == ~t3_pc~0); 508598#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 508599#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 509128#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 509129#L779 assume !(0 != activate_threads_~tmp___2~0#1); 507942#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 507943#L380 assume !(1 == ~t4_pc~0); 509096#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 509097#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 508084#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 508085#L787 assume !(0 != activate_threads_~tmp___3~0#1); 509073#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 509074#L399 assume !(1 == ~t5_pc~0); 508318#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 508319#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 509131#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 509132#L795 assume !(0 != activate_threads_~tmp___4~0#1); 508990#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508991#L679 assume !(1 == ~M_E~0); 508467#L679-2 assume !(1 == ~T1_E~0); 508468#L684-1 assume !(1 == ~T2_E~0); 508562#L689-1 assume !(1 == ~T3_E~0); 508563#L694-1 assume !(1 == ~T4_E~0); 508560#L699-1 assume !(1 == ~T5_E~0); 508561#L704-1 assume !(1 == ~E_M~0); 508523#L709-1 assume !(1 == ~E_1~0); 508385#L714-1 assume !(1 == ~E_2~0); 508386#L719-1 assume !(1 == ~E_3~0); 508788#L724-1 assume !(1 == ~E_4~0); 507980#L729-1 assume !(1 == ~E_5~0); 507981#L734-1 assume { :end_inline_reset_delta_events } true; 510106#L940-2 assume !false; 510108#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 532738#L586-1 [2023-11-26 11:51:37,500 INFO L750 eck$LassoCheckResult]: Loop: 532738#L586-1 assume !false; 532734#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 532732#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 532730#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 532728#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 532725#L511 assume 0 != eval_~tmp~0#1; 532723#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 532718#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 532719#L519-2 havoc eval_~tmp_ndt_1~0#1; 532756#L516-1 assume !(0 == ~t1_st~0); 532753#L530-1 assume !(0 == ~t2_st~0); 532749#L544-1 assume !(0 == ~t3_st~0); 532745#L558-1 assume !(0 == ~t4_st~0); 532741#L572-1 assume !(0 == ~t5_st~0); 532738#L586-1 [2023-11-26 11:51:37,501 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:37,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1586209477, now seen corresponding path program 1 times [2023-11-26 11:51:37,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:37,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [90784201] [2023-11-26 11:51:37,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:37,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:37,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:37,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:37,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:37,528 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [90784201] [2023-11-26 11:51:37,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [90784201] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:37,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:37,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:37,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553723289] [2023-11-26 11:51:37,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:37,529 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:51:37,529 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:37,530 INFO L85 PathProgramCache]: Analyzing trace with hash -54895709, now seen corresponding path program 2 times [2023-11-26 11:51:37,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:37,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609552199] [2023-11-26 11:51:37,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:37,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:37,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:37,538 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:37,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:37,542 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:37,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:37,621 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:37,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:37,621 INFO L87 Difference]: Start difference. First operand 58414 states and 75098 transitions. cyclomatic complexity: 16726 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:37,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:37,761 INFO L93 Difference]: Finished difference Result 36959 states and 47418 transitions. [2023-11-26 11:51:37,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36959 states and 47418 transitions. [2023-11-26 11:51:37,922 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25202 [2023-11-26 11:51:38,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36959 states to 36959 states and 47418 transitions. [2023-11-26 11:51:38,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25442 [2023-11-26 11:51:38,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25442 [2023-11-26 11:51:38,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36959 states and 47418 transitions. [2023-11-26 11:51:38,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:51:38,462 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36959 states and 47418 transitions. [2023-11-26 11:51:38,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36959 states and 47418 transitions. [2023-11-26 11:51:38,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36959 to 36959. [2023-11-26 11:51:38,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36959 states, 36959 states have (on average 1.28298925836738) internal successors, (47418), 36958 states have internal predecessors, (47418), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:38,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36959 states to 36959 states and 47418 transitions. [2023-11-26 11:51:38,904 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36959 states and 47418 transitions. [2023-11-26 11:51:38,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:38,905 INFO L428 stractBuchiCegarLoop]: Abstraction has 36959 states and 47418 transitions. [2023-11-26 11:51:38,905 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-26 11:51:38,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36959 states and 47418 transitions. [2023-11-26 11:51:39,014 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25202 [2023-11-26 11:51:39,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:39,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:39,016 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:39,016 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:39,017 INFO L748 eck$LassoCheckResult]: Stem: 603793#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 603794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 604015#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 604016#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 603984#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 603985#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 603679#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 603680#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 603637#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 603638#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 604167#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 603844#L611 assume !(0 == ~M_E~0); 603845#L611-2 assume !(0 == ~T1_E~0); 604202#L616-1 assume !(0 == ~T2_E~0); 604203#L621-1 assume !(0 == ~T3_E~0); 603390#L626-1 assume !(0 == ~T4_E~0); 603391#L631-1 assume !(0 == ~T5_E~0); 603761#L636-1 assume !(0 == ~E_M~0); 603480#L641-1 assume !(0 == ~E_1~0); 603481#L646-1 assume !(0 == ~E_2~0); 603788#L651-1 assume !(0 == ~E_3~0); 604294#L656-1 assume !(0 == ~E_4~0); 604165#L661-1 assume !(0 == ~E_5~0); 604166#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 604240#L304 assume !(1 == ~m_pc~0); 603537#L304-2 is_master_triggered_~__retres1~0#1 := 0; 603342#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 603343#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 603271#L755 assume !(0 != activate_threads_~tmp~1#1); 603272#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 603196#L323 assume !(1 == ~t1_pc~0); 603197#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 603291#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 603292#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 603316#L763 assume !(0 != activate_threads_~tmp___0~0#1); 604372#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 603307#L342 assume !(1 == ~t2_pc~0); 603309#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 603540#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 603541#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 604017#L771 assume !(0 != activate_threads_~tmp___1~0#1); 604159#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 603918#L361 assume !(1 == ~t3_pc~0); 603919#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 603967#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 604330#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 604286#L779 assume !(0 != activate_threads_~tmp___2~0#1); 603327#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 603328#L380 assume !(1 == ~t4_pc~0); 603917#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 604187#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 603473#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 603474#L787 assume !(0 != activate_threads_~tmp___3~0#1); 603988#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 603425#L399 assume !(1 == ~t5_pc~0); 603426#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 603699#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 604206#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 603681#L795 assume !(0 != activate_threads_~tmp___4~0#1); 603682#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 604320#L679 assume !(1 == ~M_E~0); 603843#L679-2 assume !(1 == ~T1_E~0); 603564#L684-1 assume !(1 == ~T2_E~0); 603565#L689-1 assume !(1 == ~T3_E~0); 603932#L694-1 assume !(1 == ~T4_E~0); 603930#L699-1 assume !(1 == ~T5_E~0); 603931#L704-1 assume !(1 == ~E_M~0); 603897#L709-1 assume !(1 == ~E_1~0); 603768#L714-1 assume !(1 == ~E_2~0); 603769#L719-1 assume !(1 == ~E_3~0); 604145#L724-1 assume !(1 == ~E_4~0); 603358#L729-1 assume !(1 == ~E_5~0); 603359#L734-1 assume { :end_inline_reset_delta_events } true; 604333#L940-2 assume !false; 608869#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 622151#L586-1 [2023-11-26 11:51:39,017 INFO L750 eck$LassoCheckResult]: Loop: 622151#L586-1 assume !false; 622149#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 622147#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 622145#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 622141#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 622139#L511 assume 0 != eval_~tmp~0#1; 622137#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 622134#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 622135#L519-2 havoc eval_~tmp_ndt_1~0#1; 622175#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 622172#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 622170#L533-2 havoc eval_~tmp_ndt_2~0#1; 622167#L530-1 assume !(0 == ~t2_st~0); 622163#L544-1 assume !(0 == ~t3_st~0); 622158#L558-1 assume !(0 == ~t4_st~0); 622154#L572-1 assume !(0 == ~t5_st~0); 622151#L586-1 [2023-11-26 11:51:39,018 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:39,018 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 2 times [2023-11-26 11:51:39,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:39,018 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456565418] [2023-11-26 11:51:39,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:39,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:39,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:39,028 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:39,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:39,051 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:39,053 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:39,053 INFO L85 PathProgramCache]: Analyzing trace with hash -1656247949, now seen corresponding path program 1 times [2023-11-26 11:51:39,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:39,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [769560731] [2023-11-26 11:51:39,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:39,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:39,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:39,057 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:39,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:39,062 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:39,063 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:39,063 INFO L85 PathProgramCache]: Analyzing trace with hash 991608569, now seen corresponding path program 1 times [2023-11-26 11:51:39,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:39,063 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1886213148] [2023-11-26 11:51:39,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:39,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:39,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:39,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:39,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:39,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1886213148] [2023-11-26 11:51:39,112 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1886213148] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:39,112 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:39,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:39,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784524049] [2023-11-26 11:51:39,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:39,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:39,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:39,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:39,199 INFO L87 Difference]: Start difference. First operand 36959 states and 47418 transitions. cyclomatic complexity: 10483 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:39,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:39,817 INFO L93 Difference]: Finished difference Result 66007 states and 84075 transitions. [2023-11-26 11:51:39,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66007 states and 84075 transitions. [2023-11-26 11:51:40,093 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 44406 [2023-11-26 11:51:40,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66007 states to 66007 states and 84075 transitions. [2023-11-26 11:51:40,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44802 [2023-11-26 11:51:40,296 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44802 [2023-11-26 11:51:40,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66007 states and 84075 transitions. [2023-11-26 11:51:40,315 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:51:40,315 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66007 states and 84075 transitions. [2023-11-26 11:51:40,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66007 states and 84075 transitions. [2023-11-26 11:51:41,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66007 to 66007. [2023-11-26 11:51:41,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66007 states, 66007 states have (on average 1.2737285439423092) internal successors, (84075), 66006 states have internal predecessors, (84075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:41,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66007 states to 66007 states and 84075 transitions. [2023-11-26 11:51:41,560 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66007 states and 84075 transitions. [2023-11-26 11:51:41,561 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:41,561 INFO L428 stractBuchiCegarLoop]: Abstraction has 66007 states and 84075 transitions. [2023-11-26 11:51:41,561 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-26 11:51:41,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66007 states and 84075 transitions. [2023-11-26 11:51:41,695 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 44406 [2023-11-26 11:51:41,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:41,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:41,696 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:41,696 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:41,696 INFO L748 eck$LassoCheckResult]: Stem: 706768#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 706769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 706990#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 706991#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 706956#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 706957#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 706651#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 706652#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 706612#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 706613#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 707140#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 706816#L611 assume !(0 == ~M_E~0); 706817#L611-2 assume !(0 == ~T1_E~0); 707172#L616-1 assume !(0 == ~T2_E~0); 707173#L621-1 assume !(0 == ~T3_E~0); 706365#L626-1 assume !(0 == ~T4_E~0); 706366#L631-1 assume !(0 == ~T5_E~0); 706733#L636-1 assume !(0 == ~E_M~0); 706456#L641-1 assume !(0 == ~E_1~0); 706457#L646-1 assume !(0 == ~E_2~0); 706760#L651-1 assume !(0 == ~E_3~0); 707272#L656-1 assume !(0 == ~E_4~0); 707138#L661-1 assume !(0 == ~E_5~0); 707139#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 707215#L304 assume !(1 == ~m_pc~0); 706513#L304-2 is_master_triggered_~__retres1~0#1 := 0; 706316#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 706317#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 706245#L755 assume !(0 != activate_threads_~tmp~1#1); 706246#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 706170#L323 assume !(1 == ~t1_pc~0); 706171#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 706265#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 706266#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 706290#L763 assume !(0 != activate_threads_~tmp___0~0#1); 707339#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 706281#L342 assume !(1 == ~t2_pc~0); 706283#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 706516#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 706517#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 706995#L771 assume !(0 != activate_threads_~tmp___1~0#1); 707130#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 706892#L361 assume !(1 == ~t3_pc~0); 706893#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 706937#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 707300#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 707265#L779 assume !(0 != activate_threads_~tmp___2~0#1); 706301#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 706302#L380 assume !(1 == ~t4_pc~0); 706890#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 707160#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 706448#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 706449#L787 assume !(0 != activate_threads_~tmp___3~0#1); 706962#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 706399#L399 assume !(1 == ~t5_pc~0); 706400#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 706671#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 707181#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 706653#L795 assume !(0 != activate_threads_~tmp___4~0#1); 706654#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 707293#L679 assume !(1 == ~M_E~0); 706815#L679-2 assume !(1 == ~T1_E~0); 706540#L684-1 assume !(1 == ~T2_E~0); 706541#L689-1 assume !(1 == ~T3_E~0); 706906#L694-1 assume !(1 == ~T4_E~0); 706904#L699-1 assume !(1 == ~T5_E~0); 706905#L704-1 assume !(1 == ~E_M~0); 706871#L709-1 assume !(1 == ~E_1~0); 706740#L714-1 assume !(1 == ~E_2~0); 706741#L719-1 assume !(1 == ~E_3~0); 707120#L724-1 assume !(1 == ~E_4~0); 706331#L729-1 assume !(1 == ~E_5~0); 706332#L734-1 assume { :end_inline_reset_delta_events } true; 707305#L940-2 assume !false; 716465#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 751626#L586-1 [2023-11-26 11:51:41,696 INFO L750 eck$LassoCheckResult]: Loop: 751626#L586-1 assume !false; 751624#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 751622#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 751618#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 751616#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 751614#L511 assume 0 != eval_~tmp~0#1; 751612#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 751608#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 751606#L519-2 havoc eval_~tmp_ndt_1~0#1; 751602#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 751599#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 751600#L533-2 havoc eval_~tmp_ndt_2~0#1; 742816#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 742813#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 742814#L547-2 havoc eval_~tmp_ndt_3~0#1; 751637#L544-1 assume !(0 == ~t3_st~0); 751633#L558-1 assume !(0 == ~t4_st~0); 751629#L572-1 assume !(0 == ~t5_st~0); 751626#L586-1 [2023-11-26 11:51:41,697 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:41,697 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 3 times [2023-11-26 11:51:41,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:41,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84172162] [2023-11-26 11:51:41,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:41,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:41,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:41,708 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:41,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:41,729 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:41,729 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:41,729 INFO L85 PathProgramCache]: Analyzing trace with hash 794581347, now seen corresponding path program 1 times [2023-11-26 11:51:41,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:41,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021854075] [2023-11-26 11:51:41,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:41,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:41,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:41,734 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:41,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:41,738 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:41,738 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:41,738 INFO L85 PathProgramCache]: Analyzing trace with hash -1530911383, now seen corresponding path program 1 times [2023-11-26 11:51:41,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:41,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1172423173] [2023-11-26 11:51:41,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:41,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:41,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:41,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:41,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:41,779 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1172423173] [2023-11-26 11:51:41,779 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1172423173] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:41,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:41,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:41,779 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1761766825] [2023-11-26 11:51:41,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:41,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:41,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:41,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:41,859 INFO L87 Difference]: Start difference. First operand 66007 states and 84075 transitions. cyclomatic complexity: 18092 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:42,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:42,313 INFO L93 Difference]: Finished difference Result 120425 states and 153016 transitions. [2023-11-26 11:51:42,314 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120425 states and 153016 transitions. [2023-11-26 11:51:43,428 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 81148 [2023-11-26 11:51:43,753 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120425 states to 120425 states and 153016 transitions. [2023-11-26 11:51:43,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81856 [2023-11-26 11:51:43,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81856 [2023-11-26 11:51:43,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120425 states and 153016 transitions. [2023-11-26 11:51:43,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:51:43,799 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120425 states and 153016 transitions. [2023-11-26 11:51:43,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120425 states and 153016 transitions. [2023-11-26 11:51:44,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120425 to 114353. [2023-11-26 11:51:44,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 114353 states, 114353 states have (on average 1.2741423486922074) internal successors, (145702), 114352 states have internal predecessors, (145702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:45,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114353 states to 114353 states and 145702 transitions. [2023-11-26 11:51:45,187 INFO L240 hiAutomatonCegarLoop]: Abstraction has 114353 states and 145702 transitions. [2023-11-26 11:51:45,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:45,188 INFO L428 stractBuchiCegarLoop]: Abstraction has 114353 states and 145702 transitions. [2023-11-26 11:51:45,188 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-26 11:51:45,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114353 states and 145702 transitions. [2023-11-26 11:51:46,011 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 77100 [2023-11-26 11:51:46,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:46,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:46,026 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:46,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:46,027 INFO L748 eck$LassoCheckResult]: Stem: 893221#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 893222#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 893465#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 893466#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 893428#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 893429#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 893097#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 893098#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 893055#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 893056#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 893637#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 893274#L611 assume !(0 == ~M_E~0); 893275#L611-2 assume !(0 == ~T1_E~0); 893683#L616-1 assume !(0 == ~T2_E~0); 893684#L621-1 assume !(0 == ~T3_E~0); 892802#L626-1 assume !(0 == ~T4_E~0); 892803#L631-1 assume !(0 == ~T5_E~0); 893184#L636-1 assume !(0 == ~E_M~0); 892891#L641-1 assume !(0 == ~E_1~0); 892892#L646-1 assume !(0 == ~E_2~0); 893213#L651-1 assume !(0 == ~E_3~0); 893797#L656-1 assume !(0 == ~E_4~0); 893635#L661-1 assume !(0 == ~E_5~0); 893636#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 893731#L304 assume !(1 == ~m_pc~0); 892953#L304-2 is_master_triggered_~__retres1~0#1 := 0; 892755#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 892756#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 892685#L755 assume !(0 != activate_threads_~tmp~1#1); 892686#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 892610#L323 assume !(1 == ~t1_pc~0); 892611#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 892706#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 892707#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 892731#L763 assume !(0 != activate_threads_~tmp___0~0#1); 893888#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 892722#L342 assume !(1 == ~t2_pc~0); 892724#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 892956#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 892957#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 893471#L771 assume !(0 != activate_threads_~tmp___1~0#1); 893626#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 893359#L361 assume !(1 == ~t3_pc~0); 893360#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 893412#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 893834#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 893788#L779 assume !(0 != activate_threads_~tmp___2~0#1); 892740#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 892741#L380 assume !(1 == ~t4_pc~0); 893357#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 893666#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 892884#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 892885#L787 assume !(0 != activate_threads_~tmp___3~0#1); 893434#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 892836#L399 assume !(1 == ~t5_pc~0); 892837#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 893117#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 893692#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 893099#L795 assume !(0 != activate_threads_~tmp___4~0#1); 893100#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 893826#L679 assume !(1 == ~M_E~0); 893273#L679-2 assume !(1 == ~T1_E~0); 892979#L684-1 assume !(1 == ~T2_E~0); 892980#L689-1 assume !(1 == ~T3_E~0); 893372#L694-1 assume !(1 == ~T4_E~0); 893370#L699-1 assume !(1 == ~T5_E~0); 893371#L704-1 assume !(1 == ~E_M~0); 893334#L709-1 assume !(1 == ~E_1~0); 893191#L714-1 assume !(1 == ~E_2~0); 893192#L719-1 assume !(1 == ~E_3~0); 893614#L724-1 assume !(1 == ~E_4~0); 892770#L729-1 assume !(1 == ~E_5~0); 892771#L734-1 assume { :end_inline_reset_delta_events } true; 893839#L940-2 assume !false; 900883#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 969633#L586-1 [2023-11-26 11:51:46,027 INFO L750 eck$LassoCheckResult]: Loop: 969633#L586-1 assume !false; 986324#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 986323#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 986322#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 986321#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 986320#L511 assume 0 != eval_~tmp~0#1; 986319#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 986317#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 969610#L519-2 havoc eval_~tmp_ndt_1~0#1; 969607#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 969603#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 969605#L533-2 havoc eval_~tmp_ndt_2~0#1; 969598#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 969595#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 969596#L547-2 havoc eval_~tmp_ndt_3~0#1; 984778#L544-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 969666#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 984774#L561-2 havoc eval_~tmp_ndt_4~0#1; 984771#L558-1 assume !(0 == ~t4_st~0); 984772#L572-1 assume !(0 == ~t5_st~0); 969633#L586-1 [2023-11-26 11:51:46,028 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:46,028 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 4 times [2023-11-26 11:51:46,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:46,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1133892728] [2023-11-26 11:51:46,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:46,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:46,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:46,041 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:46,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:46,063 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:46,064 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:46,064 INFO L85 PathProgramCache]: Analyzing trace with hash -1081740493, now seen corresponding path program 1 times [2023-11-26 11:51:46,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:46,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1470846740] [2023-11-26 11:51:46,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:46,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:46,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:46,069 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:46,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:46,073 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:46,074 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:46,074 INFO L85 PathProgramCache]: Analyzing trace with hash 1797707193, now seen corresponding path program 1 times [2023-11-26 11:51:46,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:46,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1146201711] [2023-11-26 11:51:46,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:46,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:46,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:46,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:46,123 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:46,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1146201711] [2023-11-26 11:51:46,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1146201711] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:46,124 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:46,124 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:51:46,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561027179] [2023-11-26 11:51:46,124 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:46,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:46,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:46,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:46,220 INFO L87 Difference]: Start difference. First operand 114353 states and 145702 transitions. cyclomatic complexity: 31373 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:46,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:46,769 INFO L93 Difference]: Finished difference Result 144961 states and 184230 transitions. [2023-11-26 11:51:46,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144961 states and 184230 transitions. [2023-11-26 11:51:47,383 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 98066 [2023-11-26 11:51:48,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144961 states to 144961 states and 184230 transitions. [2023-11-26 11:51:48,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98774 [2023-11-26 11:51:48,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98774 [2023-11-26 11:51:48,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144961 states and 184230 transitions. [2023-11-26 11:51:48,452 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 11:51:48,453 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144961 states and 184230 transitions. [2023-11-26 11:51:48,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144961 states and 184230 transitions. [2023-11-26 11:51:49,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144961 to 141097. [2023-11-26 11:51:49,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 141097 states, 141097 states have (on average 1.272443779811052) internal successors, (179538), 141096 states have internal predecessors, (179538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:50,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141097 states to 141097 states and 179538 transitions. [2023-11-26 11:51:50,226 INFO L240 hiAutomatonCegarLoop]: Abstraction has 141097 states and 179538 transitions. [2023-11-26 11:51:50,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:51:50,227 INFO L428 stractBuchiCegarLoop]: Abstraction has 141097 states and 179538 transitions. [2023-11-26 11:51:50,227 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-26 11:51:50,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 141097 states and 179538 transitions. [2023-11-26 11:51:50,573 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 95490 [2023-11-26 11:51:50,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:51:50,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:51:50,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:50,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:51:50,574 INFO L748 eck$LassoCheckResult]: Stem: 1152542#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1152543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1152781#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1152782#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1152746#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1152747#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1152420#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1152421#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1152374#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1152375#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1152955#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1152592#L611 assume !(0 == ~M_E~0); 1152593#L611-2 assume !(0 == ~T1_E~0); 1153000#L616-1 assume !(0 == ~T2_E~0); 1153001#L621-1 assume !(0 == ~T3_E~0); 1152124#L626-1 assume !(0 == ~T4_E~0); 1152125#L631-1 assume !(0 == ~T5_E~0); 1152505#L636-1 assume !(0 == ~E_M~0); 1152213#L641-1 assume !(0 == ~E_1~0); 1152214#L646-1 assume !(0 == ~E_2~0); 1152534#L651-1 assume !(0 == ~E_3~0); 1153135#L656-1 assume !(0 == ~E_4~0); 1152953#L661-1 assume !(0 == ~E_5~0); 1152954#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1153053#L304 assume !(1 == ~m_pc~0); 1152271#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1152076#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1152077#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1152007#L755 assume !(0 != activate_threads_~tmp~1#1); 1152008#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1151932#L323 assume !(1 == ~t1_pc~0); 1151933#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1152027#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1152028#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1152052#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1153224#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1152043#L342 assume !(1 == ~t2_pc~0); 1152045#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1152274#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1152275#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1152785#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1152942#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1152673#L361 assume !(1 == ~t3_pc~0); 1152674#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1152726#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1153174#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1153117#L779 assume !(0 != activate_threads_~tmp___2~0#1); 1152061#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1152062#L380 assume !(1 == ~t4_pc~0); 1152671#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1152981#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1152206#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1152207#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1152752#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1152157#L399 assume !(1 == ~t5_pc~0); 1152158#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1152441#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1153008#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1152422#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1152423#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1153161#L679 assume !(1 == ~M_E~0); 1152591#L679-2 assume !(1 == ~T1_E~0); 1152298#L684-1 assume !(1 == ~T2_E~0); 1152299#L689-1 assume !(1 == ~T3_E~0); 1152688#L694-1 assume !(1 == ~T4_E~0); 1152686#L699-1 assume !(1 == ~T5_E~0); 1152687#L704-1 assume !(1 == ~E_M~0); 1152648#L709-1 assume !(1 == ~E_1~0); 1152514#L714-1 assume !(1 == ~E_2~0); 1152515#L719-1 assume !(1 == ~E_3~0); 1152931#L724-1 assume !(1 == ~E_4~0); 1152091#L729-1 assume !(1 == ~E_5~0); 1152092#L734-1 assume { :end_inline_reset_delta_events } true; 1153178#L940-2 assume !false; 1160445#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1269291#L586-1 [2023-11-26 11:51:50,575 INFO L750 eck$LassoCheckResult]: Loop: 1269291#L586-1 assume !false; 1269289#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1269287#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1269285#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1269283#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1269279#L511 assume 0 != eval_~tmp~0#1; 1269277#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1269274#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 1269272#L519-2 havoc eval_~tmp_ndt_1~0#1; 1269268#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1269265#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 1269266#L533-2 havoc eval_~tmp_ndt_2~0#1; 1247491#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1247487#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 1247488#L547-2 havoc eval_~tmp_ndt_3~0#1; 1269309#L544-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1269306#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 1269304#L561-2 havoc eval_~tmp_ndt_4~0#1; 1269302#L558-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1269300#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 1269298#L575-2 havoc eval_~tmp_ndt_5~0#1; 1269294#L572-1 assume !(0 == ~t5_st~0); 1269291#L586-1 [2023-11-26 11:51:50,575 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:50,575 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 5 times [2023-11-26 11:51:50,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:50,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120552457] [2023-11-26 11:51:50,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:50,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:50,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:50,585 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:50,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:50,605 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:50,605 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:50,605 INFO L85 PathProgramCache]: Analyzing trace with hash -175966429, now seen corresponding path program 1 times [2023-11-26 11:51:50,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:50,606 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567851561] [2023-11-26 11:51:50,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:50,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:50,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:50,611 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:51:50,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:51:50,616 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:51:50,617 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:51:50,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1014321193, now seen corresponding path program 1 times [2023-11-26 11:51:50,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:51:50,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562595657] [2023-11-26 11:51:50,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:51:50,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:51:50,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:51:50,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:51:50,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:51:50,656 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562595657] [2023-11-26 11:51:50,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1562595657] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:51:50,656 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:51:50,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:51:50,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703631293] [2023-11-26 11:51:50,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:51:50,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:51:50,753 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:51:50,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:51:50,753 INFO L87 Difference]: Start difference. First operand 141097 states and 179538 transitions. cyclomatic complexity: 38465 Second operand has 3 states, 2 states have (on average 48.5) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:51:52,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:51:52,212 INFO L93 Difference]: Finished difference Result 254991 states and 323524 transitions. [2023-11-26 11:51:52,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 254991 states and 323524 transitions.