./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:57:56,808 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:57:56,943 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:57:56,964 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:57:56,965 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:57:57,029 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:57:57,030 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:57:57,030 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:57:57,031 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:57:57,032 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:57:57,033 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:57:57,034 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:57:57,035 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:57:57,035 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:57:57,036 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:57:57,037 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:57:57,037 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:57:57,038 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:57:57,039 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:57:57,040 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:57:57,040 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:57:57,041 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:57:57,042 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:57:57,042 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:57:57,043 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:57:57,043 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:57:57,044 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:57:57,044 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:57:57,045 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:57:57,045 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:57:57,046 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:57:57,046 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:57:57,070 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:57:57,071 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:57:57,071 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:57:57,071 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:57:57,071 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:57:57,072 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:57:57,072 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2023-11-26 11:57:57,391 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:57:57,416 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:57:57,419 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:57:57,421 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:57:57,422 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:57:57,423 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2023-11-26 11:58:00,419 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:58:00,705 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:58:00,706 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/sv-benchmarks/c/systemc/transmitter.15.cil.c [2023-11-26 11:58:00,734 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/data/a7872b106/b783bbeed2814de398ea5b8d05d94f0d/FLAG4d1840fa6 [2023-11-26 11:58:00,750 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/data/a7872b106/b783bbeed2814de398ea5b8d05d94f0d [2023-11-26 11:58:00,753 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:58:00,755 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:58:00,757 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:58:00,757 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:58:00,763 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:58:00,764 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:58:00" (1/1) ... [2023-11-26 11:58:00,765 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5b99303 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:00, skipping insertion in model container [2023-11-26 11:58:00,765 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:58:00" (1/1) ... [2023-11-26 11:58:00,824 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:58:01,287 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:58:01,306 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:58:01,378 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:58:01,403 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:58:01,404 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01 WrapperNode [2023-11-26 11:58:01,404 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:58:01,405 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:58:01,406 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:58:01,406 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:58:01,414 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,440 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,572 INFO L138 Inliner]: procedures = 54, calls = 70, calls flagged for inlining = 65, calls inlined = 287, statements flattened = 4441 [2023-11-26 11:58:01,573 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:58:01,574 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:58:01,574 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:58:01,575 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:58:01,588 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,588 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,600 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,678 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 11:58:01,679 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,679 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,794 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,855 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,867 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,881 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,896 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:58:01,897 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:58:01,898 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:58:01,898 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:58:01,899 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (1/1) ... [2023-11-26 11:58:01,905 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:58:01,919 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:58:01,942 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:58:01,964 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91e815b5-d2de-4d80-ade3-290c1cbe3fd0/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:58:01,990 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:58:01,990 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:58:01,991 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:58:01,991 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:58:02,151 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:58:02,154 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:58:05,020 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:58:05,073 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:58:05,073 INFO L309 CfgBuilder]: Removed 17 assume(true) statements. [2023-11-26 11:58:05,076 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:58:05 BoogieIcfgContainer [2023-11-26 11:58:05,076 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:58:05,078 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:58:05,078 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:58:05,083 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:58:05,083 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:58:05,084 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:58:00" (1/3) ... [2023-11-26 11:58:05,085 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5b5a69a9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:58:05, skipping insertion in model container [2023-11-26 11:58:05,085 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:58:05,087 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:58:01" (2/3) ... [2023-11-26 11:58:05,089 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5b5a69a9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:58:05, skipping insertion in model container [2023-11-26 11:58:05,089 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:58:05,090 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:58:05" (3/3) ... [2023-11-26 11:58:05,091 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.15.cil.c [2023-11-26 11:58:05,207 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:58:05,207 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:58:05,208 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:58:05,208 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:58:05,208 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:58:05,208 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:58:05,208 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:58:05,209 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:58:05,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1935 states, 1934 states have (on average 1.4948293691830403) internal successors, (2891), 1934 states have internal predecessors, (2891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:05,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1758 [2023-11-26 11:58:05,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:05,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:05,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:05,363 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:05,363 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:58:05,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1935 states, 1934 states have (on average 1.4948293691830403) internal successors, (2891), 1934 states have internal predecessors, (2891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:05,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1758 [2023-11-26 11:58:05,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:05,398 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:05,405 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:05,405 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:05,424 INFO L748 eck$LassoCheckResult]: Stem: 145#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1846#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 683#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1842#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1769#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1059#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1402#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 260#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1395#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 537#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 435#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 792#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 292#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 544#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 675#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 801#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 827#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 906#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 301#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1825#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1392#L1258-2true assume !(0 == ~T1_E~0); 484#L1263-1true assume !(0 == ~T2_E~0); 708#L1268-1true assume !(0 == ~T3_E~0); 1358#L1273-1true assume !(0 == ~T4_E~0); 1758#L1278-1true assume !(0 == ~T5_E~0); 1140#L1283-1true assume !(0 == ~T6_E~0); 1792#L1288-1true assume !(0 == ~T7_E~0); 1562#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1531#L1298-1true assume !(0 == ~T9_E~0); 1378#L1303-1true assume !(0 == ~T10_E~0); 195#L1308-1true assume !(0 == ~T11_E~0); 164#L1313-1true assume !(0 == ~T12_E~0); 1850#L1318-1true assume !(0 == ~T13_E~0); 167#L1323-1true assume !(0 == ~E_1~0); 265#L1328-1true assume !(0 == ~E_2~0); 1802#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 960#L1338-1true assume !(0 == ~E_4~0); 1100#L1343-1true assume !(0 == ~E_5~0); 1654#L1348-1true assume !(0 == ~E_6~0); 1670#L1353-1true assume !(0 == ~E_7~0); 724#L1358-1true assume !(0 == ~E_8~0); 989#L1363-1true assume !(0 == ~E_9~0); 1050#L1368-1true assume !(0 == ~E_10~0); 91#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 483#L1378-1true assume !(0 == ~E_12~0); 235#L1383-1true assume !(0 == ~E_13~0); 1088#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 726#L607true assume 1 == ~m_pc~0; 997#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1095#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 581#is_master_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 657#L1560true assume !(0 != activate_threads_~tmp~1#1); 1736#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 175#L626true assume !(1 == ~t1_pc~0); 1259#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 324#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 970#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1922#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 128#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1328#L645true assume 1 == ~t2_pc~0; 184#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1292#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1914#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 642#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1717#L664true assume 1 == ~t3_pc~0; 1634#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 951#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 410#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1410#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1627#L683true assume !(1 == ~t4_pc~0); 972#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 779#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1703#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 917#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 598#L702true assume 1 == ~t5_pc~0; 1692#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 909#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1559#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1385#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1228#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74#L721true assume !(1 == ~t6_pc~0); 65#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 141#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 418#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1515#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 855#L740true assume 1 == ~t7_pc~0; 100#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1866#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 759#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 375#L759true assume !(1 == ~t8_pc~0); 1369#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1855#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1506#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1066#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1676#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1560#L778true assume 1 == ~t9_pc~0; 1333#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1265#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 246#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 730#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 182#L797true assume !(1 == ~t10_pc~0); 252#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1299#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1298#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 481#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 693#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1384#L816true assume 1 == ~t11_pc~0; 47#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 574#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1422#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 422#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1501#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 800#L835true assume 1 == ~t12_pc~0; 703#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 132#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1796#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 518#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1434#L854true assume !(1 == ~t13_pc~0); 293#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 321#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1354#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 140#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1220#L1664-2true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1803#L1401true assume !(1 == ~M_E~0); 414#L1401-2true assume !(1 == ~T1_E~0); 1231#L1406-1true assume !(1 == ~T2_E~0); 847#L1411-1true assume !(1 == ~T3_E~0); 1611#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 580#L1421-1true assume !(1 == ~T5_E~0); 291#L1426-1true assume !(1 == ~T6_E~0); 1003#L1431-1true assume !(1 == ~T7_E~0); 64#L1436-1true assume !(1 == ~T8_E~0); 744#L1441-1true assume !(1 == ~T9_E~0); 477#L1446-1true assume !(1 == ~T10_E~0); 1783#L1451-1true assume !(1 == ~T11_E~0); 1094#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 742#L1461-1true assume !(1 == ~T13_E~0); 432#L1466-1true assume !(1 == ~E_1~0); 1776#L1471-1true assume !(1 == ~E_2~0); 1065#L1476-1true assume !(1 == ~E_3~0); 1305#L1481-1true assume !(1 == ~E_4~0); 1590#L1486-1true assume !(1 == ~E_5~0); 203#L1491-1true assume !(1 == ~E_6~0); 35#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 755#L1501-1true assume !(1 == ~E_8~0); 474#L1506-1true assume !(1 == ~E_9~0); 1026#L1511-1true assume !(1 == ~E_10~0); 447#L1516-1true assume !(1 == ~E_11~0); 12#L1521-1true assume !(1 == ~E_12~0); 34#L1526-1true assume !(1 == ~E_13~0); 305#L1531-1true assume { :end_inline_reset_delta_events } true; 1160#L1892-2true [2023-11-26 11:58:05,428 INFO L750 eck$LassoCheckResult]: Loop: 1160#L1892-2true assume !false; 1878#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1766#L1233-1true assume !true; 536#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 330#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1630#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1913#L1258-5true assume !(0 == ~T1_E~0); 135#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1601#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1620#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1920#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1621#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 254#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1801#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1157#L1298-3true assume !(0 == ~T9_E~0); 1702#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1419#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1156#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 648#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 136#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1293#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1679#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 210#L1338-3true assume !(0 == ~E_4~0); 1044#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1532#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1302#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1342#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 610#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 325#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1897#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 872#L1378-3true assume !(0 == ~E_12~0); 1451#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1086#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1775#L607-42true assume 1 == ~m_pc~0; 712#L608-14true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 503#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 405#is_master_triggered_returnLabel#15true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 337#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 694#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1210#L626-42true assume 1 == ~t1_pc~0; 390#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1462#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1760#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1117#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 152#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1567#L645-42true assume 1 == ~t2_pc~0; 1406#L646-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1704#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 608#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 266#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1664#L664-42true assume 1 == ~t3_pc~0; 451#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1624#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 939#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 826#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1004#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1800#L683-42true assume 1 == ~t4_pc~0; 1709#L684-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 832#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1007#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1403#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1918#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1151#L702-42true assume 1 == ~t5_pc~0; 633#L703-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 576#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 654#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1279#L1600-42true assume !(0 != activate_threads_~tmp___4~0#1); 26#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98#L721-42true assume !(1 == ~t6_pc~0); 1575#L721-44true is_transmit6_triggered_~__retres1~6#1 := 0; 357#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1583#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 463#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 368#L740-42true assume 1 == ~t7_pc~0; 1309#L741-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 550#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 669#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 453#L1616-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 637#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1910#L759-42true assume !(1 == ~t8_pc~0); 1347#L759-44true is_transmit8_triggered_~__retres1~8#1 := 0; 487#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 796#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 538#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 600#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1163#L778-42true assume !(1 == ~t9_pc~0); 603#L778-44true is_transmit9_triggered_~__retres1~9#1 := 0; 803#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1780#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 729#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1612#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 774#L797-42true assume !(1 == ~t10_pc~0); 1033#L797-44true is_transmit10_triggered_~__retres1~10#1 := 0; 923#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 789#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1889#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 804#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1721#L816-42true assume 1 == ~t11_pc~0; 9#L817-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1864#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1481#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 479#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 314#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 573#L835-42true assume !(1 == ~t12_pc~0); 500#L835-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1234#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 640#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1849#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1227#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 937#L854-42true assume 1 == ~t13_pc~0; 1793#L855-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 475#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 364#is_transmit13_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 508#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 430#L1664-44true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1868#L1401-3true assume !(1 == ~M_E~0); 1078#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 183#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 119#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1685#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 457#L1421-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1040#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 207#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 281#L1436-3true assume !(1 == ~T8_E~0); 14#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1133#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1122#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 513#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 295#L1461-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1610#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1827#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 267#L1476-3true assume !(1 == ~E_3~0); 1694#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 507#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 280#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1470#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 535#L1501-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1592#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 868#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 860#L1516-3true assume !(1 == ~E_11~0); 1729#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 613#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 956#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1853#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1892#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 194#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 489#L1911true assume !(0 == start_simulation_~tmp~3#1); 1296#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 891#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1015#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 94#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 511#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1324#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1338#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1160#L1892-2true [2023-11-26 11:58:05,449 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:05,450 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2023-11-26 11:58:05,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:05,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508464145] [2023-11-26 11:58:05,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:05,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:05,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:06,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:06,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:06,048 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508464145] [2023-11-26 11:58:06,049 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508464145] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:06,049 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:06,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:06,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1541228844] [2023-11-26 11:58:06,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:06,058 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:06,059 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:06,060 INFO L85 PathProgramCache]: Analyzing trace with hash 472771742, now seen corresponding path program 1 times [2023-11-26 11:58:06,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:06,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040690856] [2023-11-26 11:58:06,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:06,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:06,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:06,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:06,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:06,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040690856] [2023-11-26 11:58:06,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040690856] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:06,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:06,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:58:06,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1329201751] [2023-11-26 11:58:06,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:06,161 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:06,162 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:06,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-26 11:58:06,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-26 11:58:06,211 INFO L87 Difference]: Start difference. First operand has 1935 states, 1934 states have (on average 1.4948293691830403) internal successors, (2891), 1934 states have internal predecessors, (2891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:06,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:06,326 INFO L93 Difference]: Finished difference Result 1933 states and 2854 transitions. [2023-11-26 11:58:06,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1933 states and 2854 transitions. [2023-11-26 11:58:06,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:06,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1933 states to 1928 states and 2849 transitions. [2023-11-26 11:58:06,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:06,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:06,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2849 transitions. [2023-11-26 11:58:06,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:06,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2849 transitions. [2023-11-26 11:58:06,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2849 transitions. [2023-11-26 11:58:06,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:06,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4776970954356847) internal successors, (2849), 1927 states have internal predecessors, (2849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:06,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2849 transitions. [2023-11-26 11:58:06,561 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2849 transitions. [2023-11-26 11:58:06,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-26 11:58:06,566 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2849 transitions. [2023-11-26 11:58:06,566 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:58:06,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2849 transitions. [2023-11-26 11:58:06,581 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:06,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:06,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:06,586 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:06,587 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:06,588 INFO L748 eck$LassoCheckResult]: Stem: 4168#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5068#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5069#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5794#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5465#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5466#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4389#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4390#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4867#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4704#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4705#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4453#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4454#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4875#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5059#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5227#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5260#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4469#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4470#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5685#L1258-2 assume !(0 == ~T1_E~0); 4787#L1263-1 assume !(0 == ~T2_E~0); 4788#L1268-1 assume !(0 == ~T3_E~0); 5105#L1273-1 assume !(0 == ~T4_E~0); 5664#L1278-1 assume !(0 == ~T5_E~0); 5522#L1283-1 assume !(0 == ~T6_E~0); 5523#L1288-1 assume !(0 == ~T7_E~0); 5760#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5749#L1298-1 assume !(0 == ~T9_E~0); 5680#L1303-1 assume !(0 == ~T10_E~0); 4267#L1308-1 assume !(0 == ~T11_E~0); 4207#L1313-1 assume !(0 == ~T12_E~0); 4208#L1318-1 assume !(0 == ~T13_E~0); 4213#L1323-1 assume !(0 == ~E_1~0); 4214#L1328-1 assume !(0 == ~E_2~0); 4399#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5393#L1338-1 assume !(0 == ~E_4~0); 5394#L1343-1 assume !(0 == ~E_5~0); 5499#L1348-1 assume !(0 == ~E_6~0); 5779#L1353-1 assume !(0 == ~E_7~0); 5128#L1358-1 assume !(0 == ~E_8~0); 5129#L1363-1 assume !(0 == ~E_9~0); 5415#L1368-1 assume !(0 == ~E_10~0); 4061#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4062#L1378-1 assume !(0 == ~E_12~0); 4342#L1383-1 assume !(0 == ~E_13~0); 4343#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5133#L607 assume 1 == ~m_pc~0; 5134#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4417#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4930#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4931#L1560 assume !(0 != activate_threads_~tmp~1#1); 5040#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4228#L626 assume !(1 == ~t1_pc~0); 4229#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4510#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4511#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5401#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4136#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4137#L645 assume 1 == ~t2_pc~0; 4244#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4201#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4310#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4311#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 5014#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5015#L664 assume 1 == ~t3_pc~0; 5777#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3995#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3996#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4659#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4660#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5693#L683 assume !(1 == ~t4_pc~0); 5244#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5198#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4019#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4020#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5351#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4954#L702 assume 1 == ~t5_pc~0; 4955#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4890#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5346#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5683#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5591#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4031#L721 assume !(1 == ~t6_pc~0); 4012#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4013#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4160#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4295#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4675#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5291#L740 assume 1 == ~t7_pc~0; 4077#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3912#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3913#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3902#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3903#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4599#L759 assume !(1 == ~t8_pc~0); 4600#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4631#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5737#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5476#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5477#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5759#L778 assume 1 == ~t9_pc~0; 5649#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4060#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4365#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3938#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3939#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4240#L797 assume !(1 == ~t10_pc~0); 4241#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4375#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5626#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4783#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4784#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5085#L816 assume 1 == ~t11_pc~0; 3973#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3974#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4919#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4681#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4682#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5226#L835 assume 1 == ~t12_pc~0; 5100#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4124#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3963#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3964#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4839#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4840#L854 assume !(1 == ~t13_pc~0); 4455#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4456#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4505#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4158#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4159#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5587#L1401 assume !(1 == ~M_E~0); 4668#L1401-2 assume !(1 == ~T1_E~0); 4669#L1406-1 assume !(1 == ~T2_E~0); 5280#L1411-1 assume !(1 == ~T3_E~0); 5281#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4929#L1421-1 assume !(1 == ~T5_E~0); 4451#L1426-1 assume !(1 == ~T6_E~0); 4452#L1431-1 assume !(1 == ~T7_E~0); 4010#L1436-1 assume !(1 == ~T8_E~0); 4011#L1441-1 assume !(1 == ~T9_E~0); 4776#L1446-1 assume !(1 == ~T10_E~0); 4777#L1451-1 assume !(1 == ~T11_E~0); 5495#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5153#L1461-1 assume !(1 == ~T13_E~0); 4697#L1466-1 assume !(1 == ~E_1~0); 4698#L1471-1 assume !(1 == ~E_2~0); 5474#L1476-1 assume !(1 == ~E_3~0); 5475#L1481-1 assume !(1 == ~E_4~0); 5632#L1486-1 assume !(1 == ~E_5~0); 4280#L1491-1 assume !(1 == ~E_6~0); 3948#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3949#L1501-1 assume !(1 == ~E_8~0); 4772#L1506-1 assume !(1 == ~E_9~0); 4773#L1511-1 assume !(1 == ~E_10~0); 4727#L1516-1 assume !(1 == ~E_11~0); 3900#L1521-1 assume !(1 == ~E_12~0); 3901#L1526-1 assume !(1 == ~E_13~0); 3947#L1531-1 assume { :end_inline_reset_delta_events } true; 4477#L1892-2 [2023-11-26 11:58:06,589 INFO L750 eck$LassoCheckResult]: Loop: 4477#L1892-2 assume !false; 5540#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5793#L1233-1 assume !false; 5720#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5041#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 5021#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5569#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3989#L1046 assume !(0 != eval_~tmp~0#1); 3991#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4522#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4523#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5776#L1258-5 assume !(0 == ~T1_E~0); 4148#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4149#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5768#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5772#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5773#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4380#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4381#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5537#L1298-3 assume !(0 == ~T9_E~0); 5538#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5700#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5536#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5025#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4150#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4151#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5624#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4291#L1338-3 assume !(0 == ~E_4~0); 4292#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5451#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5629#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5630#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4970#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4512#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4513#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5311#L1378-3 assume !(0 == ~E_12~0); 5312#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5492#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5493#L607-42 assume 1 == ~m_pc~0; 5110#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4820#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4652#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4532#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4533#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5086#L626-42 assume !(1 == ~t1_pc~0); 4625#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 4624#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5724#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5509#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4183#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4184#L645-42 assume !(1 == ~t2_pc~0); 5429#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5430#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4968#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4400#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3920#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3921#L664-42 assume !(1 == ~t3_pc~0); 4436#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4437#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5370#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5258#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5259#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5422#L683-42 assume !(1 == ~t4_pc~0); 5136#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 5137#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5265#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5425#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5690#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5531#L702-42 assume !(1 == ~t5_pc~0); 4613#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4614#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4922#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5035#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 3932#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3933#L721-42 assume 1 == ~t6_pc~0; 4072#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4093#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4271#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4272#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4753#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4587#L740-42 assume !(1 == ~t7_pc~0); 4306#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4307#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4883#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4736#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4737#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5008#L759-42 assume 1 == ~t8_pc~0; 4859#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4793#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4794#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4868#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4869#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4959#L778-42 assume 1 == ~t9_pc~0; 4805#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4807#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5230#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5138#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5139#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5193#L797-42 assume 1 == ~t10_pc~0; 4314#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4315#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5211#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5212#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5231#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5232#L816-42 assume 1 == ~t11_pc~0; 3892#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3893#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5730#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4780#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4491#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4492#L835-42 assume !(1 == ~t12_pc~0); 4816#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4817#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5011#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5012#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5590#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5368#L854-42 assume 1 == ~t13_pc~0; 5369#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4413#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4579#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4580#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4693#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4694#L1401-3 assume !(1 == ~M_E~0); 5485#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4243#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4119#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4120#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4743#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4744#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4285#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4286#L1436-3 assume !(1 == ~T8_E~0); 3904#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3905#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5513#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4831#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4459#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4460#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5770#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4401#L1476-3 assume !(1 == ~E_3~0); 4402#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4825#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4429#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4430#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4865#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4866#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5307#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5295#L1516-3 assume !(1 == ~E_11~0); 5296#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4973#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4974#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5389#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4218#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4265#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4266#L1911 assume !(0 == start_simulation_~tmp~3#1); 4797#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5328#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4357#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3942#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3943#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4066#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4829#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 5643#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4477#L1892-2 [2023-11-26 11:58:06,590 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:06,590 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2023-11-26 11:58:06,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:06,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895249888] [2023-11-26 11:58:06,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:06,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:06,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:06,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:06,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:06,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895249888] [2023-11-26 11:58:06,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895249888] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:06,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:06,808 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:06,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955409909] [2023-11-26 11:58:06,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:06,810 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:06,810 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:06,811 INFO L85 PathProgramCache]: Analyzing trace with hash 998494126, now seen corresponding path program 1 times [2023-11-26 11:58:06,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:06,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586689078] [2023-11-26 11:58:06,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:06,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:06,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:06,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:06,944 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:06,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [586689078] [2023-11-26 11:58:06,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [586689078] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:06,945 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:06,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:06,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245243286] [2023-11-26 11:58:06,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:06,947 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:06,947 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:06,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:06,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:06,949 INFO L87 Difference]: Start difference. First operand 1928 states and 2849 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:07,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:07,026 INFO L93 Difference]: Finished difference Result 1928 states and 2848 transitions. [2023-11-26 11:58:07,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2848 transitions. [2023-11-26 11:58:07,047 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:07,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2848 transitions. [2023-11-26 11:58:07,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:07,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:07,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2848 transitions. [2023-11-26 11:58:07,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:07,074 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2848 transitions. [2023-11-26 11:58:07,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2848 transitions. [2023-11-26 11:58:07,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:07,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4771784232365146) internal successors, (2848), 1927 states have internal predecessors, (2848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:07,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2848 transitions. [2023-11-26 11:58:07,134 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2848 transitions. [2023-11-26 11:58:07,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:07,136 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2848 transitions. [2023-11-26 11:58:07,136 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:58:07,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2848 transitions. [2023-11-26 11:58:07,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:07,155 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:07,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:07,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:07,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:07,168 INFO L748 eck$LassoCheckResult]: Stem: 8031#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8032#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8931#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8932#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9657#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9328#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9329#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8252#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8253#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8730#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8567#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8568#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8316#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8317#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8738#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8922#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9090#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9123#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8332#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8333#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9548#L1258-2 assume !(0 == ~T1_E~0); 8650#L1263-1 assume !(0 == ~T2_E~0); 8651#L1268-1 assume !(0 == ~T3_E~0); 8968#L1273-1 assume !(0 == ~T4_E~0); 9527#L1278-1 assume !(0 == ~T5_E~0); 9385#L1283-1 assume !(0 == ~T6_E~0); 9386#L1288-1 assume !(0 == ~T7_E~0); 9623#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9612#L1298-1 assume !(0 == ~T9_E~0); 9543#L1303-1 assume !(0 == ~T10_E~0); 8130#L1308-1 assume !(0 == ~T11_E~0); 8070#L1313-1 assume !(0 == ~T12_E~0); 8071#L1318-1 assume !(0 == ~T13_E~0); 8076#L1323-1 assume !(0 == ~E_1~0); 8077#L1328-1 assume !(0 == ~E_2~0); 8262#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9256#L1338-1 assume !(0 == ~E_4~0); 9257#L1343-1 assume !(0 == ~E_5~0); 9362#L1348-1 assume !(0 == ~E_6~0); 9642#L1353-1 assume !(0 == ~E_7~0); 8991#L1358-1 assume !(0 == ~E_8~0); 8992#L1363-1 assume !(0 == ~E_9~0); 9278#L1368-1 assume !(0 == ~E_10~0); 7924#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7925#L1378-1 assume !(0 == ~E_12~0); 8205#L1383-1 assume !(0 == ~E_13~0); 8206#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8996#L607 assume 1 == ~m_pc~0; 8997#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8280#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8793#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8794#L1560 assume !(0 != activate_threads_~tmp~1#1); 8903#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8091#L626 assume !(1 == ~t1_pc~0); 8092#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8373#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8374#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9264#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 7999#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8000#L645 assume 1 == ~t2_pc~0; 8107#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8064#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8173#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8174#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8877#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8878#L664 assume 1 == ~t3_pc~0; 9640#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7858#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7859#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8522#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8523#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9556#L683 assume !(1 == ~t4_pc~0); 9107#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9061#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7882#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7883#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9214#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8817#L702 assume 1 == ~t5_pc~0; 8818#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8753#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9209#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9546#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9454#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7894#L721 assume !(1 == ~t6_pc~0); 7875#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7876#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8023#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8158#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8538#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9154#L740 assume 1 == ~t7_pc~0; 7940#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7775#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7776#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7765#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7766#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8462#L759 assume !(1 == ~t8_pc~0); 8463#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8494#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9600#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9339#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9340#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9622#L778 assume 1 == ~t9_pc~0; 9512#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7923#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8228#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7801#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7802#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8103#L797 assume !(1 == ~t10_pc~0); 8104#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8238#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9489#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8646#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8647#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8948#L816 assume 1 == ~t11_pc~0; 7836#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7837#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8782#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8544#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8545#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9089#L835 assume 1 == ~t12_pc~0; 8963#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7987#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7826#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7827#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8702#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8703#L854 assume !(1 == ~t13_pc~0); 8318#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8319#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8368#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8021#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8022#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9450#L1401 assume !(1 == ~M_E~0); 8531#L1401-2 assume !(1 == ~T1_E~0); 8532#L1406-1 assume !(1 == ~T2_E~0); 9143#L1411-1 assume !(1 == ~T3_E~0); 9144#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8792#L1421-1 assume !(1 == ~T5_E~0); 8314#L1426-1 assume !(1 == ~T6_E~0); 8315#L1431-1 assume !(1 == ~T7_E~0); 7873#L1436-1 assume !(1 == ~T8_E~0); 7874#L1441-1 assume !(1 == ~T9_E~0); 8639#L1446-1 assume !(1 == ~T10_E~0); 8640#L1451-1 assume !(1 == ~T11_E~0); 9358#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9016#L1461-1 assume !(1 == ~T13_E~0); 8560#L1466-1 assume !(1 == ~E_1~0); 8561#L1471-1 assume !(1 == ~E_2~0); 9337#L1476-1 assume !(1 == ~E_3~0); 9338#L1481-1 assume !(1 == ~E_4~0); 9495#L1486-1 assume !(1 == ~E_5~0); 8143#L1491-1 assume !(1 == ~E_6~0); 7811#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7812#L1501-1 assume !(1 == ~E_8~0); 8635#L1506-1 assume !(1 == ~E_9~0); 8636#L1511-1 assume !(1 == ~E_10~0); 8590#L1516-1 assume !(1 == ~E_11~0); 7763#L1521-1 assume !(1 == ~E_12~0); 7764#L1526-1 assume !(1 == ~E_13~0); 7810#L1531-1 assume { :end_inline_reset_delta_events } true; 8340#L1892-2 [2023-11-26 11:58:07,169 INFO L750 eck$LassoCheckResult]: Loop: 8340#L1892-2 assume !false; 9403#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9656#L1233-1 assume !false; 9583#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8904#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8884#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9432#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7852#L1046 assume !(0 != eval_~tmp~0#1); 7854#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8385#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8386#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9639#L1258-5 assume !(0 == ~T1_E~0); 8011#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8012#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9631#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9635#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9636#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8243#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8244#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9400#L1298-3 assume !(0 == ~T9_E~0); 9401#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9563#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9399#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8888#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8013#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8014#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9487#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8154#L1338-3 assume !(0 == ~E_4~0); 8155#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9314#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9492#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9493#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8833#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8375#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8376#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9174#L1378-3 assume !(0 == ~E_12~0); 9175#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9355#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9356#L607-42 assume 1 == ~m_pc~0; 8973#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8683#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8515#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8395#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8396#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8949#L626-42 assume 1 == ~t1_pc~0; 8486#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8487#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9587#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9372#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8046#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8047#L645-42 assume 1 == ~t2_pc~0; 9555#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9293#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8831#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8263#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7783#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7784#L664-42 assume 1 == ~t3_pc~0; 8596#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8300#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9233#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9121#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9122#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9285#L683-42 assume 1 == ~t4_pc~0; 9648#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9000#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9128#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9288#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9553#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9394#L702-42 assume 1 == ~t5_pc~0; 8865#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8477#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8785#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8898#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 7795#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7796#L721-42 assume !(1 == ~t6_pc~0); 7936#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 7956#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8134#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8135#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8616#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8450#L740-42 assume 1 == ~t7_pc~0; 8451#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8170#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8746#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8599#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8600#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8871#L759-42 assume 1 == ~t8_pc~0; 8722#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8656#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8657#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8731#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8732#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8822#L778-42 assume 1 == ~t9_pc~0; 8668#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8670#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9093#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9001#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9002#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9056#L797-42 assume 1 == ~t10_pc~0; 8177#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8178#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9074#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9075#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9094#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9095#L816-42 assume 1 == ~t11_pc~0; 7755#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7756#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9593#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8643#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8354#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8355#L835-42 assume !(1 == ~t12_pc~0); 8679#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 8680#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8874#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8875#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9453#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9231#L854-42 assume 1 == ~t13_pc~0; 9232#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8276#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8442#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8443#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8556#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8557#L1401-3 assume !(1 == ~M_E~0); 9348#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8106#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7982#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7983#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8606#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8607#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8148#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8149#L1436-3 assume !(1 == ~T8_E~0); 7767#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7768#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9376#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8694#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8322#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8323#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9633#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8264#L1476-3 assume !(1 == ~E_3~0); 8265#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8688#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8292#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8293#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8728#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8729#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9170#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9158#L1516-3 assume !(1 == ~E_11~0); 9159#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8836#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8837#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9252#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8081#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8128#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8129#L1911 assume !(0 == start_simulation_~tmp~3#1); 8660#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9191#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8220#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 7805#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7806#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7929#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8692#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 9506#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8340#L1892-2 [2023-11-26 11:58:07,171 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:07,171 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2023-11-26 11:58:07,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:07,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816463419] [2023-11-26 11:58:07,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:07,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:07,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:07,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:07,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:07,285 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816463419] [2023-11-26 11:58:07,285 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816463419] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:07,286 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:07,286 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:07,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039226138] [2023-11-26 11:58:07,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:07,287 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:07,287 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:07,288 INFO L85 PathProgramCache]: Analyzing trace with hash 173917971, now seen corresponding path program 1 times [2023-11-26 11:58:07,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:07,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926661948] [2023-11-26 11:58:07,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:07,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:07,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:07,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:07,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:07,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926661948] [2023-11-26 11:58:07,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926661948] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:07,400 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:07,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:07,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223986164] [2023-11-26 11:58:07,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:07,402 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:07,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:07,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:07,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:07,403 INFO L87 Difference]: Start difference. First operand 1928 states and 2848 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:07,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:07,486 INFO L93 Difference]: Finished difference Result 1928 states and 2847 transitions. [2023-11-26 11:58:07,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2847 transitions. [2023-11-26 11:58:07,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:07,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2847 transitions. [2023-11-26 11:58:07,520 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:07,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:07,522 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2847 transitions. [2023-11-26 11:58:07,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:07,525 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2847 transitions. [2023-11-26 11:58:07,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2847 transitions. [2023-11-26 11:58:07,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:07,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4766597510373445) internal successors, (2847), 1927 states have internal predecessors, (2847), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:07,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2847 transitions. [2023-11-26 11:58:07,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2847 transitions. [2023-11-26 11:58:07,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:07,574 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2847 transitions. [2023-11-26 11:58:07,574 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:58:07,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2847 transitions. [2023-11-26 11:58:07,586 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:07,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:07,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:07,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:07,590 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:07,591 INFO L748 eck$LassoCheckResult]: Stem: 11894#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 11895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12794#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12795#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13520#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13191#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13192#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12115#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12116#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12593#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12430#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12431#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12179#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12180#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12601#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12785#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12953#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12986#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12195#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12196#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13411#L1258-2 assume !(0 == ~T1_E~0); 12513#L1263-1 assume !(0 == ~T2_E~0); 12514#L1268-1 assume !(0 == ~T3_E~0); 12831#L1273-1 assume !(0 == ~T4_E~0); 13390#L1278-1 assume !(0 == ~T5_E~0); 13248#L1283-1 assume !(0 == ~T6_E~0); 13249#L1288-1 assume !(0 == ~T7_E~0); 13486#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13475#L1298-1 assume !(0 == ~T9_E~0); 13406#L1303-1 assume !(0 == ~T10_E~0); 11993#L1308-1 assume !(0 == ~T11_E~0); 11933#L1313-1 assume !(0 == ~T12_E~0); 11934#L1318-1 assume !(0 == ~T13_E~0); 11939#L1323-1 assume !(0 == ~E_1~0); 11940#L1328-1 assume !(0 == ~E_2~0); 12125#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13119#L1338-1 assume !(0 == ~E_4~0); 13120#L1343-1 assume !(0 == ~E_5~0); 13225#L1348-1 assume !(0 == ~E_6~0); 13505#L1353-1 assume !(0 == ~E_7~0); 12854#L1358-1 assume !(0 == ~E_8~0); 12855#L1363-1 assume !(0 == ~E_9~0); 13141#L1368-1 assume !(0 == ~E_10~0); 11787#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11788#L1378-1 assume !(0 == ~E_12~0); 12068#L1383-1 assume !(0 == ~E_13~0); 12069#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12859#L607 assume 1 == ~m_pc~0; 12860#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12143#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12656#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12657#L1560 assume !(0 != activate_threads_~tmp~1#1); 12766#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11954#L626 assume !(1 == ~t1_pc~0); 11955#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12236#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12237#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13127#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11862#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11863#L645 assume 1 == ~t2_pc~0; 11970#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11927#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12036#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12037#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12740#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12741#L664 assume 1 == ~t3_pc~0; 13503#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11721#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11722#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12385#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12386#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13419#L683 assume !(1 == ~t4_pc~0); 12970#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12924#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11745#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11746#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13077#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12680#L702 assume 1 == ~t5_pc~0; 12681#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12616#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13072#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13409#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13317#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11757#L721 assume !(1 == ~t6_pc~0); 11738#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11739#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11886#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12021#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12401#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13017#L740 assume 1 == ~t7_pc~0; 11803#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11638#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11639#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11628#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11629#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12325#L759 assume !(1 == ~t8_pc~0); 12326#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12357#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13463#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13202#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13203#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13485#L778 assume 1 == ~t9_pc~0; 13375#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11786#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12091#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11664#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11665#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11966#L797 assume !(1 == ~t10_pc~0); 11967#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12101#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13352#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12509#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12510#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12811#L816 assume 1 == ~t11_pc~0; 11699#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11700#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12645#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12407#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12408#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12952#L835 assume 1 == ~t12_pc~0; 12826#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11850#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11689#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11690#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12565#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12566#L854 assume !(1 == ~t13_pc~0); 12181#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12182#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12231#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11884#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11885#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13313#L1401 assume !(1 == ~M_E~0); 12394#L1401-2 assume !(1 == ~T1_E~0); 12395#L1406-1 assume !(1 == ~T2_E~0); 13006#L1411-1 assume !(1 == ~T3_E~0); 13007#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12655#L1421-1 assume !(1 == ~T5_E~0); 12177#L1426-1 assume !(1 == ~T6_E~0); 12178#L1431-1 assume !(1 == ~T7_E~0); 11736#L1436-1 assume !(1 == ~T8_E~0); 11737#L1441-1 assume !(1 == ~T9_E~0); 12502#L1446-1 assume !(1 == ~T10_E~0); 12503#L1451-1 assume !(1 == ~T11_E~0); 13221#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12879#L1461-1 assume !(1 == ~T13_E~0); 12423#L1466-1 assume !(1 == ~E_1~0); 12424#L1471-1 assume !(1 == ~E_2~0); 13200#L1476-1 assume !(1 == ~E_3~0); 13201#L1481-1 assume !(1 == ~E_4~0); 13358#L1486-1 assume !(1 == ~E_5~0); 12006#L1491-1 assume !(1 == ~E_6~0); 11674#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11675#L1501-1 assume !(1 == ~E_8~0); 12498#L1506-1 assume !(1 == ~E_9~0); 12499#L1511-1 assume !(1 == ~E_10~0); 12453#L1516-1 assume !(1 == ~E_11~0); 11626#L1521-1 assume !(1 == ~E_12~0); 11627#L1526-1 assume !(1 == ~E_13~0); 11673#L1531-1 assume { :end_inline_reset_delta_events } true; 12203#L1892-2 [2023-11-26 11:58:07,592 INFO L750 eck$LassoCheckResult]: Loop: 12203#L1892-2 assume !false; 13266#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13519#L1233-1 assume !false; 13446#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12767#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12747#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13295#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11715#L1046 assume !(0 != eval_~tmp~0#1); 11717#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12248#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12249#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13502#L1258-5 assume !(0 == ~T1_E~0); 11874#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11875#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13494#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13498#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13499#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12106#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12107#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13263#L1298-3 assume !(0 == ~T9_E~0); 13264#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13426#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13262#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12751#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11876#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11877#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13350#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12017#L1338-3 assume !(0 == ~E_4~0); 12018#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13177#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13355#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13356#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12696#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12238#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12239#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13037#L1378-3 assume !(0 == ~E_12~0); 13038#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13218#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13219#L607-42 assume 1 == ~m_pc~0; 12836#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12546#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12378#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12258#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12259#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12812#L626-42 assume 1 == ~t1_pc~0; 12349#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12350#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13450#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13235#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11909#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11910#L645-42 assume !(1 == ~t2_pc~0); 13155#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 13156#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12694#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12126#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11646#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11647#L664-42 assume !(1 == ~t3_pc~0); 12162#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 12163#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13096#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12984#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12985#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13148#L683-42 assume 1 == ~t4_pc~0; 13511#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12863#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12991#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13151#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13416#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13257#L702-42 assume !(1 == ~t5_pc~0); 12339#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 12340#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12648#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12761#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 11658#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11659#L721-42 assume 1 == ~t6_pc~0; 11798#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11819#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11997#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11998#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12479#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12313#L740-42 assume !(1 == ~t7_pc~0); 12032#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 12033#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12609#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12462#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12463#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12734#L759-42 assume 1 == ~t8_pc~0; 12585#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12519#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12520#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12594#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12595#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12685#L778-42 assume 1 == ~t9_pc~0; 12531#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12533#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12956#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12864#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12865#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12919#L797-42 assume 1 == ~t10_pc~0; 12040#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12041#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12937#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12938#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12957#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12958#L816-42 assume 1 == ~t11_pc~0; 11618#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11619#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13456#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12506#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12217#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12218#L835-42 assume 1 == ~t12_pc~0; 12644#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12543#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12737#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12738#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13316#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13094#L854-42 assume 1 == ~t13_pc~0; 13095#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12139#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12305#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12306#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12419#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12420#L1401-3 assume !(1 == ~M_E~0); 13211#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11969#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11845#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11846#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12469#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12470#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12011#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12012#L1436-3 assume !(1 == ~T8_E~0); 11630#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11631#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13239#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12557#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12185#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12186#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13496#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12127#L1476-3 assume !(1 == ~E_3~0); 12128#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12551#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12155#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12156#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12591#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12592#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13033#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13021#L1516-3 assume !(1 == ~E_11~0); 13022#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12699#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12700#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13115#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11944#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11991#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11992#L1911 assume !(0 == start_simulation_~tmp~3#1); 12523#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13054#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12083#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11668#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11669#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11792#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12555#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 13369#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12203#L1892-2 [2023-11-26 11:58:07,593 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:07,593 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2023-11-26 11:58:07,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:07,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660423342] [2023-11-26 11:58:07,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:07,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:07,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:07,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:07,662 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:07,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1660423342] [2023-11-26 11:58:07,663 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1660423342] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:07,663 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:07,663 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:07,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571684199] [2023-11-26 11:58:07,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:07,668 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:07,669 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:07,669 INFO L85 PathProgramCache]: Analyzing trace with hash -714593263, now seen corresponding path program 1 times [2023-11-26 11:58:07,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:07,669 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [603945098] [2023-11-26 11:58:07,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:07,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:07,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:07,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:07,774 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:07,775 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [603945098] [2023-11-26 11:58:07,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [603945098] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:07,775 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:07,775 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:07,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197271896] [2023-11-26 11:58:07,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:07,776 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:07,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:07,777 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:07,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:07,777 INFO L87 Difference]: Start difference. First operand 1928 states and 2847 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:07,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:07,835 INFO L93 Difference]: Finished difference Result 1928 states and 2846 transitions. [2023-11-26 11:58:07,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2846 transitions. [2023-11-26 11:58:07,853 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:07,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2846 transitions. [2023-11-26 11:58:07,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:07,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:07,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2846 transitions. [2023-11-26 11:58:07,875 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:07,875 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2846 transitions. [2023-11-26 11:58:07,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2846 transitions. [2023-11-26 11:58:07,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:07,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4761410788381744) internal successors, (2846), 1927 states have internal predecessors, (2846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:07,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2846 transitions. [2023-11-26 11:58:07,926 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2846 transitions. [2023-11-26 11:58:07,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:07,928 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2846 transitions. [2023-11-26 11:58:07,928 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:58:07,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2846 transitions. [2023-11-26 11:58:07,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:07,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:07,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:07,946 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:07,946 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:07,946 INFO L748 eck$LassoCheckResult]: Stem: 15757#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 15758#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16657#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16658#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17383#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 17054#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17055#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15978#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15979#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16456#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16293#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16294#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16042#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16043#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16464#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16648#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16816#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16849#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 16058#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16059#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17274#L1258-2 assume !(0 == ~T1_E~0); 16376#L1263-1 assume !(0 == ~T2_E~0); 16377#L1268-1 assume !(0 == ~T3_E~0); 16694#L1273-1 assume !(0 == ~T4_E~0); 17253#L1278-1 assume !(0 == ~T5_E~0); 17111#L1283-1 assume !(0 == ~T6_E~0); 17112#L1288-1 assume !(0 == ~T7_E~0); 17349#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17338#L1298-1 assume !(0 == ~T9_E~0); 17269#L1303-1 assume !(0 == ~T10_E~0); 15856#L1308-1 assume !(0 == ~T11_E~0); 15796#L1313-1 assume !(0 == ~T12_E~0); 15797#L1318-1 assume !(0 == ~T13_E~0); 15802#L1323-1 assume !(0 == ~E_1~0); 15803#L1328-1 assume !(0 == ~E_2~0); 15988#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16982#L1338-1 assume !(0 == ~E_4~0); 16983#L1343-1 assume !(0 == ~E_5~0); 17088#L1348-1 assume !(0 == ~E_6~0); 17368#L1353-1 assume !(0 == ~E_7~0); 16717#L1358-1 assume !(0 == ~E_8~0); 16718#L1363-1 assume !(0 == ~E_9~0); 17004#L1368-1 assume !(0 == ~E_10~0); 15650#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15651#L1378-1 assume !(0 == ~E_12~0); 15931#L1383-1 assume !(0 == ~E_13~0); 15932#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16722#L607 assume 1 == ~m_pc~0; 16723#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16006#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16519#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16520#L1560 assume !(0 != activate_threads_~tmp~1#1); 16629#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15817#L626 assume !(1 == ~t1_pc~0); 15818#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16099#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16100#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16990#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15725#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15726#L645 assume 1 == ~t2_pc~0; 15833#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15790#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15899#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15900#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16603#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16604#L664 assume 1 == ~t3_pc~0; 17366#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15584#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15585#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16248#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16249#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17282#L683 assume !(1 == ~t4_pc~0); 16833#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16787#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15608#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15609#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16940#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16543#L702 assume 1 == ~t5_pc~0; 16544#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16479#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16935#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17272#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17180#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15620#L721 assume !(1 == ~t6_pc~0); 15601#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15602#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15749#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15884#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16264#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16880#L740 assume 1 == ~t7_pc~0; 15666#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15501#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15502#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15491#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15492#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16188#L759 assume !(1 == ~t8_pc~0); 16189#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16220#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17326#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17065#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 17066#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17348#L778 assume 1 == ~t9_pc~0; 17238#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15649#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15954#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15527#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15528#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15829#L797 assume !(1 == ~t10_pc~0); 15830#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15964#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17215#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16372#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16373#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16674#L816 assume 1 == ~t11_pc~0; 15562#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15563#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16508#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16270#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16271#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16815#L835 assume 1 == ~t12_pc~0; 16689#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15713#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15552#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15553#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16428#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16429#L854 assume !(1 == ~t13_pc~0); 16044#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 16045#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16094#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15747#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15748#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17176#L1401 assume !(1 == ~M_E~0); 16257#L1401-2 assume !(1 == ~T1_E~0); 16258#L1406-1 assume !(1 == ~T2_E~0); 16869#L1411-1 assume !(1 == ~T3_E~0); 16870#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16518#L1421-1 assume !(1 == ~T5_E~0); 16040#L1426-1 assume !(1 == ~T6_E~0); 16041#L1431-1 assume !(1 == ~T7_E~0); 15599#L1436-1 assume !(1 == ~T8_E~0); 15600#L1441-1 assume !(1 == ~T9_E~0); 16365#L1446-1 assume !(1 == ~T10_E~0); 16366#L1451-1 assume !(1 == ~T11_E~0); 17084#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16742#L1461-1 assume !(1 == ~T13_E~0); 16286#L1466-1 assume !(1 == ~E_1~0); 16287#L1471-1 assume !(1 == ~E_2~0); 17063#L1476-1 assume !(1 == ~E_3~0); 17064#L1481-1 assume !(1 == ~E_4~0); 17221#L1486-1 assume !(1 == ~E_5~0); 15869#L1491-1 assume !(1 == ~E_6~0); 15537#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15538#L1501-1 assume !(1 == ~E_8~0); 16361#L1506-1 assume !(1 == ~E_9~0); 16362#L1511-1 assume !(1 == ~E_10~0); 16316#L1516-1 assume !(1 == ~E_11~0); 15489#L1521-1 assume !(1 == ~E_12~0); 15490#L1526-1 assume !(1 == ~E_13~0); 15536#L1531-1 assume { :end_inline_reset_delta_events } true; 16066#L1892-2 [2023-11-26 11:58:07,947 INFO L750 eck$LassoCheckResult]: Loop: 16066#L1892-2 assume !false; 17129#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17382#L1233-1 assume !false; 17309#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16630#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16610#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17158#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15578#L1046 assume !(0 != eval_~tmp~0#1); 15580#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16111#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16112#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17365#L1258-5 assume !(0 == ~T1_E~0); 15737#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15738#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17357#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17361#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17362#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15969#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15970#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17126#L1298-3 assume !(0 == ~T9_E~0); 17127#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17289#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17125#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16614#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15739#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15740#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17213#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15880#L1338-3 assume !(0 == ~E_4~0); 15881#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17040#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17218#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17219#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16559#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16101#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16102#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16900#L1378-3 assume !(0 == ~E_12~0); 16901#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17081#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17082#L607-42 assume 1 == ~m_pc~0; 16699#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16409#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16241#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16121#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16122#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16675#L626-42 assume 1 == ~t1_pc~0; 16212#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16213#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17313#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17098#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15772#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15773#L645-42 assume 1 == ~t2_pc~0; 17281#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17019#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16557#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15989#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15509#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15510#L664-42 assume 1 == ~t3_pc~0; 16322#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16026#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16959#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16847#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16848#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17011#L683-42 assume !(1 == ~t4_pc~0); 16725#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 16726#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16854#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17014#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17279#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17120#L702-42 assume !(1 == ~t5_pc~0); 16202#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 16203#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16511#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16624#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 15521#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15522#L721-42 assume 1 == ~t6_pc~0; 15661#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15682#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15860#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15861#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16342#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16176#L740-42 assume 1 == ~t7_pc~0; 16177#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15896#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16472#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16325#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16326#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16597#L759-42 assume 1 == ~t8_pc~0; 16448#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16382#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16383#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16457#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16458#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16548#L778-42 assume 1 == ~t9_pc~0; 16394#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16396#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16819#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16727#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16728#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16782#L797-42 assume !(1 == ~t10_pc~0); 15905#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 15904#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16800#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16801#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16820#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16821#L816-42 assume 1 == ~t11_pc~0; 15481#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15482#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17319#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16369#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16080#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16081#L835-42 assume !(1 == ~t12_pc~0); 16405#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16406#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16600#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16601#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17179#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16957#L854-42 assume !(1 == ~t13_pc~0); 16001#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 16002#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16168#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16169#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16282#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16283#L1401-3 assume !(1 == ~M_E~0); 17074#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15832#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15708#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15709#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16332#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16333#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15874#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15875#L1436-3 assume !(1 == ~T8_E~0); 15493#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15494#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17102#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16420#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16048#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 16049#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17359#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15990#L1476-3 assume !(1 == ~E_3~0); 15991#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16414#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16018#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16019#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16454#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16455#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16896#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16884#L1516-3 assume !(1 == ~E_11~0); 16885#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16562#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16563#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16978#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15807#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 15854#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15855#L1911 assume !(0 == start_simulation_~tmp~3#1); 16386#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16917#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15946#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 15531#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15532#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15655#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16418#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 17232#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 16066#L1892-2 [2023-11-26 11:58:07,948 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:07,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2023-11-26 11:58:07,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:07,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49311723] [2023-11-26 11:58:07,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:07,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:07,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:08,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:08,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:08,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [49311723] [2023-11-26 11:58:08,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [49311723] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:08,055 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:08,055 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:08,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595940057] [2023-11-26 11:58:08,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:08,056 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:08,056 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:08,057 INFO L85 PathProgramCache]: Analyzing trace with hash 1933543408, now seen corresponding path program 1 times [2023-11-26 11:58:08,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:08,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741388788] [2023-11-26 11:58:08,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:08,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:08,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:08,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:08,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:08,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741388788] [2023-11-26 11:58:08,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741388788] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:08,157 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:08,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:08,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [63627585] [2023-11-26 11:58:08,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:08,159 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:08,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:08,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:08,159 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:08,160 INFO L87 Difference]: Start difference. First operand 1928 states and 2846 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:08,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:08,207 INFO L93 Difference]: Finished difference Result 1928 states and 2845 transitions. [2023-11-26 11:58:08,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2845 transitions. [2023-11-26 11:58:08,221 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:08,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2845 transitions. [2023-11-26 11:58:08,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:08,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:08,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2845 transitions. [2023-11-26 11:58:08,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:08,244 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2845 transitions. [2023-11-26 11:58:08,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2845 transitions. [2023-11-26 11:58:08,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:08,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4756224066390042) internal successors, (2845), 1927 states have internal predecessors, (2845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:08,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2845 transitions. [2023-11-26 11:58:08,290 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2845 transitions. [2023-11-26 11:58:08,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:08,293 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2845 transitions. [2023-11-26 11:58:08,294 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:58:08,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2845 transitions. [2023-11-26 11:58:08,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:08,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:08,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:08,309 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:08,309 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:08,310 INFO L748 eck$LassoCheckResult]: Stem: 19620#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 19621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20520#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20521#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21246#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20917#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20918#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19841#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19842#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20319#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20156#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20157#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19905#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19906#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20327#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20511#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20679#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20712#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19921#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19922#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 21137#L1258-2 assume !(0 == ~T1_E~0); 20239#L1263-1 assume !(0 == ~T2_E~0); 20240#L1268-1 assume !(0 == ~T3_E~0); 20557#L1273-1 assume !(0 == ~T4_E~0); 21116#L1278-1 assume !(0 == ~T5_E~0); 20974#L1283-1 assume !(0 == ~T6_E~0); 20975#L1288-1 assume !(0 == ~T7_E~0); 21212#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21201#L1298-1 assume !(0 == ~T9_E~0); 21132#L1303-1 assume !(0 == ~T10_E~0); 19719#L1308-1 assume !(0 == ~T11_E~0); 19659#L1313-1 assume !(0 == ~T12_E~0); 19660#L1318-1 assume !(0 == ~T13_E~0); 19665#L1323-1 assume !(0 == ~E_1~0); 19666#L1328-1 assume !(0 == ~E_2~0); 19851#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20845#L1338-1 assume !(0 == ~E_4~0); 20846#L1343-1 assume !(0 == ~E_5~0); 20951#L1348-1 assume !(0 == ~E_6~0); 21231#L1353-1 assume !(0 == ~E_7~0); 20580#L1358-1 assume !(0 == ~E_8~0); 20581#L1363-1 assume !(0 == ~E_9~0); 20867#L1368-1 assume !(0 == ~E_10~0); 19513#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19514#L1378-1 assume !(0 == ~E_12~0); 19794#L1383-1 assume !(0 == ~E_13~0); 19795#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20585#L607 assume 1 == ~m_pc~0; 20586#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19869#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20382#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20383#L1560 assume !(0 != activate_threads_~tmp~1#1); 20492#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19680#L626 assume !(1 == ~t1_pc~0); 19681#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19962#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19963#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20853#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19588#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19589#L645 assume 1 == ~t2_pc~0; 19696#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19653#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19762#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19763#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20466#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20467#L664 assume 1 == ~t3_pc~0; 21229#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19447#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19448#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20111#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 20112#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21145#L683 assume !(1 == ~t4_pc~0); 20696#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20650#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19471#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19472#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20803#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20406#L702 assume 1 == ~t5_pc~0; 20407#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20342#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20798#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21135#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 21043#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19483#L721 assume !(1 == ~t6_pc~0); 19464#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19465#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19612#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19747#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 20127#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20743#L740 assume 1 == ~t7_pc~0; 19529#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19364#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19365#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19354#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19355#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20051#L759 assume !(1 == ~t8_pc~0); 20052#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20083#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21189#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20928#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20929#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21211#L778 assume 1 == ~t9_pc~0; 21101#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19512#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19817#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19390#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19391#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19692#L797 assume !(1 == ~t10_pc~0); 19693#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19827#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21078#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20235#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20236#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20537#L816 assume 1 == ~t11_pc~0; 19425#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19426#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20371#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20133#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 20134#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20678#L835 assume 1 == ~t12_pc~0; 20552#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19576#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19415#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19416#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20291#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20292#L854 assume !(1 == ~t13_pc~0); 19907#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19908#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19957#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19610#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19611#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21039#L1401 assume !(1 == ~M_E~0); 20120#L1401-2 assume !(1 == ~T1_E~0); 20121#L1406-1 assume !(1 == ~T2_E~0); 20732#L1411-1 assume !(1 == ~T3_E~0); 20733#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20381#L1421-1 assume !(1 == ~T5_E~0); 19903#L1426-1 assume !(1 == ~T6_E~0); 19904#L1431-1 assume !(1 == ~T7_E~0); 19462#L1436-1 assume !(1 == ~T8_E~0); 19463#L1441-1 assume !(1 == ~T9_E~0); 20228#L1446-1 assume !(1 == ~T10_E~0); 20229#L1451-1 assume !(1 == ~T11_E~0); 20947#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20605#L1461-1 assume !(1 == ~T13_E~0); 20149#L1466-1 assume !(1 == ~E_1~0); 20150#L1471-1 assume !(1 == ~E_2~0); 20926#L1476-1 assume !(1 == ~E_3~0); 20927#L1481-1 assume !(1 == ~E_4~0); 21084#L1486-1 assume !(1 == ~E_5~0); 19732#L1491-1 assume !(1 == ~E_6~0); 19400#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19401#L1501-1 assume !(1 == ~E_8~0); 20224#L1506-1 assume !(1 == ~E_9~0); 20225#L1511-1 assume !(1 == ~E_10~0); 20179#L1516-1 assume !(1 == ~E_11~0); 19352#L1521-1 assume !(1 == ~E_12~0); 19353#L1526-1 assume !(1 == ~E_13~0); 19399#L1531-1 assume { :end_inline_reset_delta_events } true; 19929#L1892-2 [2023-11-26 11:58:08,311 INFO L750 eck$LassoCheckResult]: Loop: 19929#L1892-2 assume !false; 20992#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21245#L1233-1 assume !false; 21172#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20493#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20473#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21021#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19441#L1046 assume !(0 != eval_~tmp~0#1); 19443#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19974#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19975#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21228#L1258-5 assume !(0 == ~T1_E~0); 19600#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19601#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21220#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21224#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21225#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19832#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19833#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20989#L1298-3 assume !(0 == ~T9_E~0); 20990#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21152#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20988#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20477#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19602#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19603#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21076#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19743#L1338-3 assume !(0 == ~E_4~0); 19744#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20903#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21081#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21082#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20422#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19964#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19965#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20763#L1378-3 assume !(0 == ~E_12~0); 20764#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20944#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20945#L607-42 assume 1 == ~m_pc~0; 20562#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20272#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20104#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19984#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19985#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20538#L626-42 assume 1 == ~t1_pc~0; 20075#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20076#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21176#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20961#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19635#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19636#L645-42 assume !(1 == ~t2_pc~0); 20881#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20882#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20420#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19852#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19372#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19373#L664-42 assume !(1 == ~t3_pc~0); 19888#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19889#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20822#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20710#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20711#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20874#L683-42 assume 1 == ~t4_pc~0; 21237#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20589#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20717#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20877#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21142#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20983#L702-42 assume !(1 == ~t5_pc~0); 20065#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 20066#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20374#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20487#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 19384#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19385#L721-42 assume 1 == ~t6_pc~0; 19524#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19545#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19723#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19724#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20205#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20039#L740-42 assume 1 == ~t7_pc~0; 20040#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19759#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20335#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20188#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20189#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20460#L759-42 assume 1 == ~t8_pc~0; 20311#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20245#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20246#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20320#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20321#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20411#L778-42 assume 1 == ~t9_pc~0; 20257#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20259#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20682#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20590#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20591#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20645#L797-42 assume 1 == ~t10_pc~0; 19766#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19767#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20663#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20664#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20683#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20684#L816-42 assume 1 == ~t11_pc~0; 19344#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19345#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21182#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20232#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19943#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19944#L835-42 assume 1 == ~t12_pc~0; 20370#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20269#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20463#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20464#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21042#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20820#L854-42 assume 1 == ~t13_pc~0; 20821#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 19865#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20031#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20032#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20145#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20146#L1401-3 assume !(1 == ~M_E~0); 20937#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19695#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19571#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19572#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20195#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20196#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19737#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19738#L1436-3 assume !(1 == ~T8_E~0); 19356#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19357#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20965#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20283#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19911#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 19912#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21222#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19853#L1476-3 assume !(1 == ~E_3~0); 19854#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20277#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19881#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19882#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20317#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20318#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20759#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20747#L1516-3 assume !(1 == ~E_11~0); 20748#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20425#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20426#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20841#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19670#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 19717#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19718#L1911 assume !(0 == start_simulation_~tmp~3#1); 20249#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20780#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19809#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 19394#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19395#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19518#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20281#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 21095#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19929#L1892-2 [2023-11-26 11:58:08,312 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:08,312 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2023-11-26 11:58:08,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:08,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980252664] [2023-11-26 11:58:08,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:08,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:08,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:08,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:08,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:08,390 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [980252664] [2023-11-26 11:58:08,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [980252664] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:08,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:08,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:08,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428162660] [2023-11-26 11:58:08,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:08,397 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:08,398 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:08,398 INFO L85 PathProgramCache]: Analyzing trace with hash 1270235442, now seen corresponding path program 1 times [2023-11-26 11:58:08,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:08,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273294274] [2023-11-26 11:58:08,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:08,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:08,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:08,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:08,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:08,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1273294274] [2023-11-26 11:58:08,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1273294274] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:08,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:08,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:08,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2106729728] [2023-11-26 11:58:08,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:08,524 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:08,524 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:08,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:08,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:08,526 INFO L87 Difference]: Start difference. First operand 1928 states and 2845 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:08,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:08,573 INFO L93 Difference]: Finished difference Result 1928 states and 2844 transitions. [2023-11-26 11:58:08,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2844 transitions. [2023-11-26 11:58:08,585 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:08,600 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2844 transitions. [2023-11-26 11:58:08,601 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:08,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:08,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2844 transitions. [2023-11-26 11:58:08,608 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:08,608 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2844 transitions. [2023-11-26 11:58:08,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2844 transitions. [2023-11-26 11:58:08,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:08,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4751037344398341) internal successors, (2844), 1927 states have internal predecessors, (2844), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:08,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2844 transitions. [2023-11-26 11:58:08,693 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2844 transitions. [2023-11-26 11:58:08,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:08,694 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2844 transitions. [2023-11-26 11:58:08,694 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:58:08,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2844 transitions. [2023-11-26 11:58:08,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:08,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:08,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:08,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:08,705 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:08,705 INFO L748 eck$LassoCheckResult]: Stem: 23483#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23484#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 24383#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24384#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25109#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24780#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24781#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23704#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23705#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24182#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24019#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 24020#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23768#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23769#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24190#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24374#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24542#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24575#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23784#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23785#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 25000#L1258-2 assume !(0 == ~T1_E~0); 24102#L1263-1 assume !(0 == ~T2_E~0); 24103#L1268-1 assume !(0 == ~T3_E~0); 24420#L1273-1 assume !(0 == ~T4_E~0); 24979#L1278-1 assume !(0 == ~T5_E~0); 24837#L1283-1 assume !(0 == ~T6_E~0); 24838#L1288-1 assume !(0 == ~T7_E~0); 25075#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25064#L1298-1 assume !(0 == ~T9_E~0); 24995#L1303-1 assume !(0 == ~T10_E~0); 23582#L1308-1 assume !(0 == ~T11_E~0); 23522#L1313-1 assume !(0 == ~T12_E~0); 23523#L1318-1 assume !(0 == ~T13_E~0); 23528#L1323-1 assume !(0 == ~E_1~0); 23529#L1328-1 assume !(0 == ~E_2~0); 23714#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24708#L1338-1 assume !(0 == ~E_4~0); 24709#L1343-1 assume !(0 == ~E_5~0); 24814#L1348-1 assume !(0 == ~E_6~0); 25094#L1353-1 assume !(0 == ~E_7~0); 24443#L1358-1 assume !(0 == ~E_8~0); 24444#L1363-1 assume !(0 == ~E_9~0); 24730#L1368-1 assume !(0 == ~E_10~0); 23376#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23377#L1378-1 assume !(0 == ~E_12~0); 23657#L1383-1 assume !(0 == ~E_13~0); 23658#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24448#L607 assume 1 == ~m_pc~0; 24449#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23732#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24245#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24246#L1560 assume !(0 != activate_threads_~tmp~1#1); 24355#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23543#L626 assume !(1 == ~t1_pc~0); 23544#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23825#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23826#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24716#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23451#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23452#L645 assume 1 == ~t2_pc~0; 23559#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23516#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23625#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23626#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24329#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24330#L664 assume 1 == ~t3_pc~0; 25092#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23310#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23311#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23974#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23975#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25008#L683 assume !(1 == ~t4_pc~0); 24559#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24513#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23334#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23335#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24666#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24269#L702 assume 1 == ~t5_pc~0; 24270#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24205#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24661#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24998#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24906#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23346#L721 assume !(1 == ~t6_pc~0); 23327#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23328#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23475#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23610#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23990#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24606#L740 assume 1 == ~t7_pc~0; 23392#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23227#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23228#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23217#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23218#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23914#L759 assume !(1 == ~t8_pc~0); 23915#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23946#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25052#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24791#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24792#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25074#L778 assume 1 == ~t9_pc~0; 24964#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23375#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23680#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23253#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23254#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23555#L797 assume !(1 == ~t10_pc~0); 23556#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23690#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24941#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24098#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 24099#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24400#L816 assume 1 == ~t11_pc~0; 23288#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23289#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24234#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23996#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23997#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24541#L835 assume 1 == ~t12_pc~0; 24415#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23439#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23278#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23279#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 24154#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24155#L854 assume !(1 == ~t13_pc~0); 23770#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23771#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23820#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23473#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23474#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24902#L1401 assume !(1 == ~M_E~0); 23983#L1401-2 assume !(1 == ~T1_E~0); 23984#L1406-1 assume !(1 == ~T2_E~0); 24595#L1411-1 assume !(1 == ~T3_E~0); 24596#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24244#L1421-1 assume !(1 == ~T5_E~0); 23766#L1426-1 assume !(1 == ~T6_E~0); 23767#L1431-1 assume !(1 == ~T7_E~0); 23325#L1436-1 assume !(1 == ~T8_E~0); 23326#L1441-1 assume !(1 == ~T9_E~0); 24091#L1446-1 assume !(1 == ~T10_E~0); 24092#L1451-1 assume !(1 == ~T11_E~0); 24810#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24468#L1461-1 assume !(1 == ~T13_E~0); 24012#L1466-1 assume !(1 == ~E_1~0); 24013#L1471-1 assume !(1 == ~E_2~0); 24789#L1476-1 assume !(1 == ~E_3~0); 24790#L1481-1 assume !(1 == ~E_4~0); 24947#L1486-1 assume !(1 == ~E_5~0); 23595#L1491-1 assume !(1 == ~E_6~0); 23263#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23264#L1501-1 assume !(1 == ~E_8~0); 24087#L1506-1 assume !(1 == ~E_9~0); 24088#L1511-1 assume !(1 == ~E_10~0); 24042#L1516-1 assume !(1 == ~E_11~0); 23215#L1521-1 assume !(1 == ~E_12~0); 23216#L1526-1 assume !(1 == ~E_13~0); 23262#L1531-1 assume { :end_inline_reset_delta_events } true; 23792#L1892-2 [2023-11-26 11:58:08,706 INFO L750 eck$LassoCheckResult]: Loop: 23792#L1892-2 assume !false; 24855#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25108#L1233-1 assume !false; 25035#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24356#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24336#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24884#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23304#L1046 assume !(0 != eval_~tmp~0#1); 23306#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23837#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23838#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25091#L1258-5 assume !(0 == ~T1_E~0); 23463#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23464#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25083#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25087#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25088#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23695#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23696#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24852#L1298-3 assume !(0 == ~T9_E~0); 24853#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25015#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24851#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24340#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23465#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23466#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24939#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23606#L1338-3 assume !(0 == ~E_4~0); 23607#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24766#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24944#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24945#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24285#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23827#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23828#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24626#L1378-3 assume !(0 == ~E_12~0); 24627#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24807#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24808#L607-42 assume 1 == ~m_pc~0; 24425#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24135#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23967#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23847#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23848#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24401#L626-42 assume 1 == ~t1_pc~0; 23938#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23939#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25039#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24824#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23498#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23499#L645-42 assume !(1 == ~t2_pc~0); 24744#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 24745#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24283#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23715#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23235#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23236#L664-42 assume 1 == ~t3_pc~0; 24048#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23752#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24685#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24573#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24574#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24737#L683-42 assume !(1 == ~t4_pc~0); 24451#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24452#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24580#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24740#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25005#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24846#L702-42 assume !(1 == ~t5_pc~0); 23928#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 23929#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24237#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24350#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 23247#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23248#L721-42 assume 1 == ~t6_pc~0; 23387#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23408#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23586#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23587#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24068#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23902#L740-42 assume !(1 == ~t7_pc~0); 23621#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 23622#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24198#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24051#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24052#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24323#L759-42 assume 1 == ~t8_pc~0; 24174#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24108#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24109#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24183#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24184#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24274#L778-42 assume 1 == ~t9_pc~0; 24120#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24122#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24545#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24453#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24454#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24508#L797-42 assume 1 == ~t10_pc~0; 23629#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23630#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24526#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24527#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24546#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24547#L816-42 assume 1 == ~t11_pc~0; 23207#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23208#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25045#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24095#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23806#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23807#L835-42 assume !(1 == ~t12_pc~0); 24131#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 24132#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24326#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24327#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24905#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24683#L854-42 assume 1 == ~t13_pc~0; 24684#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 23728#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23894#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23895#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 24008#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24009#L1401-3 assume !(1 == ~M_E~0); 24800#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23558#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23434#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23435#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24058#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24059#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23600#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23601#L1436-3 assume !(1 == ~T8_E~0); 23219#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23220#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24828#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24146#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23774#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 23775#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25085#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23716#L1476-3 assume !(1 == ~E_3~0); 23717#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24140#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23744#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23745#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24180#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24181#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24622#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24610#L1516-3 assume !(1 == ~E_11~0); 24611#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24288#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24289#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24704#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23533#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 23580#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23581#L1911 assume !(0 == start_simulation_~tmp~3#1); 24112#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24643#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23672#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 23257#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23258#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23381#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24144#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24958#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23792#L1892-2 [2023-11-26 11:58:08,708 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:08,708 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2023-11-26 11:58:08,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:08,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616061299] [2023-11-26 11:58:08,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:08,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:08,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:08,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:08,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:08,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [616061299] [2023-11-26 11:58:08,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [616061299] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:08,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:08,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:08,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34833530] [2023-11-26 11:58:08,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:08,771 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:08,771 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:08,771 INFO L85 PathProgramCache]: Analyzing trace with hash 1554426480, now seen corresponding path program 1 times [2023-11-26 11:58:08,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:08,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392168809] [2023-11-26 11:58:08,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:08,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:08,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:08,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:08,851 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:08,851 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392168809] [2023-11-26 11:58:08,851 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392168809] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:08,851 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:08,852 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:08,852 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017191990] [2023-11-26 11:58:08,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:08,852 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:08,853 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:08,853 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:08,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:08,853 INFO L87 Difference]: Start difference. First operand 1928 states and 2844 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:08,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:08,900 INFO L93 Difference]: Finished difference Result 1928 states and 2843 transitions. [2023-11-26 11:58:08,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2843 transitions. [2023-11-26 11:58:08,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:08,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2843 transitions. [2023-11-26 11:58:08,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:08,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:08,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2843 transitions. [2023-11-26 11:58:08,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:08,934 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2843 transitions. [2023-11-26 11:58:08,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2843 transitions. [2023-11-26 11:58:08,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:08,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.474585062240664) internal successors, (2843), 1927 states have internal predecessors, (2843), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:08,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2843 transitions. [2023-11-26 11:58:08,980 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2843 transitions. [2023-11-26 11:58:08,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:08,981 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2843 transitions. [2023-11-26 11:58:08,981 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:58:08,981 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2843 transitions. [2023-11-26 11:58:08,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:08,990 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:08,990 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:08,993 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:08,993 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:08,993 INFO L748 eck$LassoCheckResult]: Stem: 27346#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27347#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28246#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28247#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28972#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28643#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28644#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27567#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27568#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28045#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27882#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27883#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27631#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27632#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28053#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28237#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28405#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28438#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27647#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27648#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28863#L1258-2 assume !(0 == ~T1_E~0); 27965#L1263-1 assume !(0 == ~T2_E~0); 27966#L1268-1 assume !(0 == ~T3_E~0); 28283#L1273-1 assume !(0 == ~T4_E~0); 28842#L1278-1 assume !(0 == ~T5_E~0); 28700#L1283-1 assume !(0 == ~T6_E~0); 28701#L1288-1 assume !(0 == ~T7_E~0); 28938#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28927#L1298-1 assume !(0 == ~T9_E~0); 28858#L1303-1 assume !(0 == ~T10_E~0); 27445#L1308-1 assume !(0 == ~T11_E~0); 27385#L1313-1 assume !(0 == ~T12_E~0); 27386#L1318-1 assume !(0 == ~T13_E~0); 27391#L1323-1 assume !(0 == ~E_1~0); 27392#L1328-1 assume !(0 == ~E_2~0); 27577#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28571#L1338-1 assume !(0 == ~E_4~0); 28572#L1343-1 assume !(0 == ~E_5~0); 28677#L1348-1 assume !(0 == ~E_6~0); 28957#L1353-1 assume !(0 == ~E_7~0); 28306#L1358-1 assume !(0 == ~E_8~0); 28307#L1363-1 assume !(0 == ~E_9~0); 28593#L1368-1 assume !(0 == ~E_10~0); 27239#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27240#L1378-1 assume !(0 == ~E_12~0); 27520#L1383-1 assume !(0 == ~E_13~0); 27521#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28311#L607 assume 1 == ~m_pc~0; 28312#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27595#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28108#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28109#L1560 assume !(0 != activate_threads_~tmp~1#1); 28218#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27406#L626 assume !(1 == ~t1_pc~0); 27407#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27688#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27689#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28579#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27314#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27315#L645 assume 1 == ~t2_pc~0; 27422#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27379#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27488#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27489#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 28192#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28193#L664 assume 1 == ~t3_pc~0; 28955#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27173#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27174#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27837#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27838#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28871#L683 assume !(1 == ~t4_pc~0); 28422#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28376#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27197#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27198#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28529#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28132#L702 assume 1 == ~t5_pc~0; 28133#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28068#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28524#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28861#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28769#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27209#L721 assume !(1 == ~t6_pc~0); 27190#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27191#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27338#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27473#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27853#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28469#L740 assume 1 == ~t7_pc~0; 27255#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27090#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27091#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27080#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 27081#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27777#L759 assume !(1 == ~t8_pc~0); 27778#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27809#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28915#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28654#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28655#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28937#L778 assume 1 == ~t9_pc~0; 28827#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27238#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27543#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27116#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 27117#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27418#L797 assume !(1 == ~t10_pc~0); 27419#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27553#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28804#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27961#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27962#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28263#L816 assume 1 == ~t11_pc~0; 27151#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 27152#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28097#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27859#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27860#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28404#L835 assume 1 == ~t12_pc~0; 28278#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27302#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27141#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27142#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 28017#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28018#L854 assume !(1 == ~t13_pc~0); 27633#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27634#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27683#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27336#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27337#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28765#L1401 assume !(1 == ~M_E~0); 27846#L1401-2 assume !(1 == ~T1_E~0); 27847#L1406-1 assume !(1 == ~T2_E~0); 28458#L1411-1 assume !(1 == ~T3_E~0); 28459#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28107#L1421-1 assume !(1 == ~T5_E~0); 27629#L1426-1 assume !(1 == ~T6_E~0); 27630#L1431-1 assume !(1 == ~T7_E~0); 27188#L1436-1 assume !(1 == ~T8_E~0); 27189#L1441-1 assume !(1 == ~T9_E~0); 27954#L1446-1 assume !(1 == ~T10_E~0); 27955#L1451-1 assume !(1 == ~T11_E~0); 28673#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28331#L1461-1 assume !(1 == ~T13_E~0); 27875#L1466-1 assume !(1 == ~E_1~0); 27876#L1471-1 assume !(1 == ~E_2~0); 28652#L1476-1 assume !(1 == ~E_3~0); 28653#L1481-1 assume !(1 == ~E_4~0); 28810#L1486-1 assume !(1 == ~E_5~0); 27458#L1491-1 assume !(1 == ~E_6~0); 27126#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27127#L1501-1 assume !(1 == ~E_8~0); 27950#L1506-1 assume !(1 == ~E_9~0); 27951#L1511-1 assume !(1 == ~E_10~0); 27905#L1516-1 assume !(1 == ~E_11~0); 27078#L1521-1 assume !(1 == ~E_12~0); 27079#L1526-1 assume !(1 == ~E_13~0); 27125#L1531-1 assume { :end_inline_reset_delta_events } true; 27655#L1892-2 [2023-11-26 11:58:08,994 INFO L750 eck$LassoCheckResult]: Loop: 27655#L1892-2 assume !false; 28718#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28971#L1233-1 assume !false; 28898#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28219#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28199#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28747#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27167#L1046 assume !(0 != eval_~tmp~0#1); 27169#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27700#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27701#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28954#L1258-5 assume !(0 == ~T1_E~0); 27326#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27327#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28946#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28950#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28951#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27558#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27559#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28715#L1298-3 assume !(0 == ~T9_E~0); 28716#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28878#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28714#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28203#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27328#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27329#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28802#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27469#L1338-3 assume !(0 == ~E_4~0); 27470#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28629#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28807#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28808#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28148#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27690#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27691#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28489#L1378-3 assume !(0 == ~E_12~0); 28490#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28670#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28671#L607-42 assume 1 == ~m_pc~0; 28288#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27998#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27830#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27710#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27711#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28264#L626-42 assume 1 == ~t1_pc~0; 27801#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27802#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28902#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28687#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27361#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27362#L645-42 assume 1 == ~t2_pc~0; 28870#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28608#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28146#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27578#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27098#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27099#L664-42 assume 1 == ~t3_pc~0; 27911#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27615#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28548#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28436#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28437#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28600#L683-42 assume 1 == ~t4_pc~0; 28963#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28315#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28443#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28603#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28868#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28709#L702-42 assume 1 == ~t5_pc~0; 28180#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27792#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28100#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28213#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 27110#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27111#L721-42 assume 1 == ~t6_pc~0; 27250#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27271#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27449#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27450#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27931#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27765#L740-42 assume 1 == ~t7_pc~0; 27766#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27485#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28061#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27914#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27915#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28186#L759-42 assume 1 == ~t8_pc~0; 28037#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27971#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27972#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28046#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28047#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28137#L778-42 assume !(1 == ~t9_pc~0); 27984#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 27985#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28408#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28316#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28317#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28371#L797-42 assume 1 == ~t10_pc~0; 27492#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27493#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28389#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28390#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28409#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28410#L816-42 assume !(1 == ~t11_pc~0); 27072#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 27071#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28908#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27958#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27669#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27670#L835-42 assume 1 == ~t12_pc~0; 28096#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27995#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28189#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28190#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28768#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28546#L854-42 assume 1 == ~t13_pc~0; 28547#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27591#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27757#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27758#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27871#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27872#L1401-3 assume !(1 == ~M_E~0); 28663#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27421#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27297#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27298#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27921#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27922#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27463#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27464#L1436-3 assume !(1 == ~T8_E~0); 27082#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27083#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28691#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28009#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27637#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 27638#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28948#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27579#L1476-3 assume !(1 == ~E_3~0); 27580#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28003#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27607#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27608#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28043#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28044#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28485#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28473#L1516-3 assume !(1 == ~E_11~0); 28474#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28151#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 28152#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28567#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27396#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 27443#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27444#L1911 assume !(0 == start_simulation_~tmp~3#1); 27975#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28506#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27535#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 27120#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27121#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27244#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28007#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28821#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27655#L1892-2 [2023-11-26 11:58:08,996 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:08,996 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2023-11-26 11:58:08,996 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:08,996 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [503731193] [2023-11-26 11:58:08,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:08,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:09,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:09,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:09,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:09,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [503731193] [2023-11-26 11:58:09,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [503731193] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:09,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:09,055 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:09,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996453437] [2023-11-26 11:58:09,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:09,055 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:09,056 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:09,056 INFO L85 PathProgramCache]: Analyzing trace with hash -561599085, now seen corresponding path program 1 times [2023-11-26 11:58:09,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:09,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201064260] [2023-11-26 11:58:09,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:09,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:09,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:09,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:09,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:09,134 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201064260] [2023-11-26 11:58:09,134 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201064260] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:09,134 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:09,134 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:09,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404825081] [2023-11-26 11:58:09,135 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:09,135 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:09,135 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:09,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:09,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:09,136 INFO L87 Difference]: Start difference. First operand 1928 states and 2843 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:09,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:09,184 INFO L93 Difference]: Finished difference Result 1928 states and 2842 transitions. [2023-11-26 11:58:09,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2842 transitions. [2023-11-26 11:58:09,238 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:09,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2842 transitions. [2023-11-26 11:58:09,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:09,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:09,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2842 transitions. [2023-11-26 11:58:09,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:09,262 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2842 transitions. [2023-11-26 11:58:09,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2842 transitions. [2023-11-26 11:58:09,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:09,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4740663900414939) internal successors, (2842), 1927 states have internal predecessors, (2842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:09,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2842 transitions. [2023-11-26 11:58:09,313 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2842 transitions. [2023-11-26 11:58:09,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:09,315 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2842 transitions. [2023-11-26 11:58:09,315 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 11:58:09,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2842 transitions. [2023-11-26 11:58:09,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:09,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:09,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:09,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:09,330 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:09,331 INFO L748 eck$LassoCheckResult]: Stem: 31209#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 31210#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 32109#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32110#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32835#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32506#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32507#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31430#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31431#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31908#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31745#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31746#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31494#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31495#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31916#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32100#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32268#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32301#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31510#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31511#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32726#L1258-2 assume !(0 == ~T1_E~0); 31828#L1263-1 assume !(0 == ~T2_E~0); 31829#L1268-1 assume !(0 == ~T3_E~0); 32146#L1273-1 assume !(0 == ~T4_E~0); 32705#L1278-1 assume !(0 == ~T5_E~0); 32563#L1283-1 assume !(0 == ~T6_E~0); 32564#L1288-1 assume !(0 == ~T7_E~0); 32801#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32790#L1298-1 assume !(0 == ~T9_E~0); 32721#L1303-1 assume !(0 == ~T10_E~0); 31308#L1308-1 assume !(0 == ~T11_E~0); 31248#L1313-1 assume !(0 == ~T12_E~0); 31249#L1318-1 assume !(0 == ~T13_E~0); 31254#L1323-1 assume !(0 == ~E_1~0); 31255#L1328-1 assume !(0 == ~E_2~0); 31440#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32434#L1338-1 assume !(0 == ~E_4~0); 32435#L1343-1 assume !(0 == ~E_5~0); 32540#L1348-1 assume !(0 == ~E_6~0); 32820#L1353-1 assume !(0 == ~E_7~0); 32169#L1358-1 assume !(0 == ~E_8~0); 32170#L1363-1 assume !(0 == ~E_9~0); 32456#L1368-1 assume !(0 == ~E_10~0); 31102#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 31103#L1378-1 assume !(0 == ~E_12~0); 31383#L1383-1 assume !(0 == ~E_13~0); 31384#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32174#L607 assume 1 == ~m_pc~0; 32175#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31458#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31971#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31972#L1560 assume !(0 != activate_threads_~tmp~1#1); 32081#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31269#L626 assume !(1 == ~t1_pc~0); 31270#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31551#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31552#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32442#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 31177#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31178#L645 assume 1 == ~t2_pc~0; 31285#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31242#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31351#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31352#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 32055#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32056#L664 assume 1 == ~t3_pc~0; 32818#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31036#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31037#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31700#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31701#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32734#L683 assume !(1 == ~t4_pc~0); 32285#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32239#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31060#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31061#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32392#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31995#L702 assume 1 == ~t5_pc~0; 31996#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31931#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32387#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32724#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32632#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31072#L721 assume !(1 == ~t6_pc~0); 31053#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31054#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31201#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31336#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31716#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32332#L740 assume 1 == ~t7_pc~0; 31118#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30953#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30954#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30943#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30944#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31640#L759 assume !(1 == ~t8_pc~0); 31641#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31672#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32778#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32517#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32518#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32800#L778 assume 1 == ~t9_pc~0; 32690#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31101#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31406#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30979#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30980#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31281#L797 assume !(1 == ~t10_pc~0); 31282#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31416#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32667#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31824#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31825#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32126#L816 assume 1 == ~t11_pc~0; 31014#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31015#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31960#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31722#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31723#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32267#L835 assume 1 == ~t12_pc~0; 32141#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31165#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31004#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31005#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31880#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31881#L854 assume !(1 == ~t13_pc~0); 31496#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31497#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31546#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31199#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31200#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32628#L1401 assume !(1 == ~M_E~0); 31709#L1401-2 assume !(1 == ~T1_E~0); 31710#L1406-1 assume !(1 == ~T2_E~0); 32321#L1411-1 assume !(1 == ~T3_E~0); 32322#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31970#L1421-1 assume !(1 == ~T5_E~0); 31492#L1426-1 assume !(1 == ~T6_E~0); 31493#L1431-1 assume !(1 == ~T7_E~0); 31051#L1436-1 assume !(1 == ~T8_E~0); 31052#L1441-1 assume !(1 == ~T9_E~0); 31817#L1446-1 assume !(1 == ~T10_E~0); 31818#L1451-1 assume !(1 == ~T11_E~0); 32536#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32194#L1461-1 assume !(1 == ~T13_E~0); 31738#L1466-1 assume !(1 == ~E_1~0); 31739#L1471-1 assume !(1 == ~E_2~0); 32515#L1476-1 assume !(1 == ~E_3~0); 32516#L1481-1 assume !(1 == ~E_4~0); 32673#L1486-1 assume !(1 == ~E_5~0); 31321#L1491-1 assume !(1 == ~E_6~0); 30989#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30990#L1501-1 assume !(1 == ~E_8~0); 31813#L1506-1 assume !(1 == ~E_9~0); 31814#L1511-1 assume !(1 == ~E_10~0); 31768#L1516-1 assume !(1 == ~E_11~0); 30941#L1521-1 assume !(1 == ~E_12~0); 30942#L1526-1 assume !(1 == ~E_13~0); 30988#L1531-1 assume { :end_inline_reset_delta_events } true; 31518#L1892-2 [2023-11-26 11:58:09,332 INFO L750 eck$LassoCheckResult]: Loop: 31518#L1892-2 assume !false; 32581#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32834#L1233-1 assume !false; 32761#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32082#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32062#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32610#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31030#L1046 assume !(0 != eval_~tmp~0#1); 31032#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31563#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31564#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32817#L1258-5 assume !(0 == ~T1_E~0); 31189#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31190#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32809#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32813#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32814#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31421#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31422#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32578#L1298-3 assume !(0 == ~T9_E~0); 32579#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32741#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32577#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32066#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 31191#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31192#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32665#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31332#L1338-3 assume !(0 == ~E_4~0); 31333#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32492#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32670#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32671#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32011#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31553#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31554#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32352#L1378-3 assume !(0 == ~E_12~0); 32353#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32533#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32534#L607-42 assume 1 == ~m_pc~0; 32151#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31861#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31693#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31573#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31574#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32127#L626-42 assume 1 == ~t1_pc~0; 31664#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31665#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32765#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32550#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31224#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31225#L645-42 assume !(1 == ~t2_pc~0); 32470#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32471#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32009#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31441#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30961#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30962#L664-42 assume !(1 == ~t3_pc~0); 31477#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 31478#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32411#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32299#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32300#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32463#L683-42 assume !(1 == ~t4_pc~0); 32177#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32178#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32306#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32466#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32731#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32572#L702-42 assume !(1 == ~t5_pc~0); 31654#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 31655#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31963#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32076#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 30973#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30974#L721-42 assume 1 == ~t6_pc~0; 31113#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31134#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31312#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31313#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31794#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31628#L740-42 assume !(1 == ~t7_pc~0); 31347#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31348#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31924#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31777#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31778#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32049#L759-42 assume 1 == ~t8_pc~0; 31900#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31834#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31835#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31909#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31910#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32000#L778-42 assume 1 == ~t9_pc~0; 31846#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31848#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32271#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32179#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32180#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32234#L797-42 assume 1 == ~t10_pc~0; 31355#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31356#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32252#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32253#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32272#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32273#L816-42 assume 1 == ~t11_pc~0; 30933#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30934#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32771#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31821#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31532#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31533#L835-42 assume !(1 == ~t12_pc~0); 31857#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 31858#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32052#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32053#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32631#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32409#L854-42 assume 1 == ~t13_pc~0; 32410#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 31454#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31620#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31621#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31734#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31735#L1401-3 assume !(1 == ~M_E~0); 32526#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31284#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31160#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31161#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31784#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31785#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31326#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31327#L1436-3 assume !(1 == ~T8_E~0); 30945#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30946#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32554#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31872#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31500#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 31501#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32811#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31442#L1476-3 assume !(1 == ~E_3~0); 31443#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31866#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31470#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31471#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31906#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31907#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32348#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32336#L1516-3 assume !(1 == ~E_11~0); 32337#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32014#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 32015#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32430#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31259#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31306#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31307#L1911 assume !(0 == start_simulation_~tmp~3#1); 31838#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32369#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31398#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30983#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30984#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31107#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31870#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32684#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31518#L1892-2 [2023-11-26 11:58:09,333 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:09,334 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2023-11-26 11:58:09,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:09,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797848984] [2023-11-26 11:58:09,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:09,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:09,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:09,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:09,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:09,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797848984] [2023-11-26 11:58:09,407 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797848984] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:09,407 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:09,407 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:09,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250639801] [2023-11-26 11:58:09,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:09,408 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:09,409 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:09,409 INFO L85 PathProgramCache]: Analyzing trace with hash 1875748943, now seen corresponding path program 1 times [2023-11-26 11:58:09,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:09,409 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874772006] [2023-11-26 11:58:09,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:09,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:09,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:09,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:09,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:09,503 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [874772006] [2023-11-26 11:58:09,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [874772006] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:09,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:09,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:09,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [761511793] [2023-11-26 11:58:09,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:09,504 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:09,504 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:09,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:09,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:09,505 INFO L87 Difference]: Start difference. First operand 1928 states and 2842 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:09,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:09,550 INFO L93 Difference]: Finished difference Result 1928 states and 2841 transitions. [2023-11-26 11:58:09,551 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2841 transitions. [2023-11-26 11:58:09,563 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:09,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2841 transitions. [2023-11-26 11:58:09,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:09,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:09,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2841 transitions. [2023-11-26 11:58:09,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:09,583 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2841 transitions. [2023-11-26 11:58:09,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2841 transitions. [2023-11-26 11:58:09,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:09,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4735477178423237) internal successors, (2841), 1927 states have internal predecessors, (2841), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:09,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2841 transitions. [2023-11-26 11:58:09,628 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2841 transitions. [2023-11-26 11:58:09,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:09,629 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2841 transitions. [2023-11-26 11:58:09,630 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 11:58:09,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2841 transitions. [2023-11-26 11:58:09,639 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:09,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:09,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:09,642 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:09,643 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:09,643 INFO L748 eck$LassoCheckResult]: Stem: 35072#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36698#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36369#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36370#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35293#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35294#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35771#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35608#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35609#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35357#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35358#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35779#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35963#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36131#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36164#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35373#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35374#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36589#L1258-2 assume !(0 == ~T1_E~0); 35691#L1263-1 assume !(0 == ~T2_E~0); 35692#L1268-1 assume !(0 == ~T3_E~0); 36009#L1273-1 assume !(0 == ~T4_E~0); 36568#L1278-1 assume !(0 == ~T5_E~0); 36426#L1283-1 assume !(0 == ~T6_E~0); 36427#L1288-1 assume !(0 == ~T7_E~0); 36664#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36653#L1298-1 assume !(0 == ~T9_E~0); 36584#L1303-1 assume !(0 == ~T10_E~0); 35171#L1308-1 assume !(0 == ~T11_E~0); 35111#L1313-1 assume !(0 == ~T12_E~0); 35112#L1318-1 assume !(0 == ~T13_E~0); 35117#L1323-1 assume !(0 == ~E_1~0); 35118#L1328-1 assume !(0 == ~E_2~0); 35303#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36297#L1338-1 assume !(0 == ~E_4~0); 36298#L1343-1 assume !(0 == ~E_5~0); 36403#L1348-1 assume !(0 == ~E_6~0); 36683#L1353-1 assume !(0 == ~E_7~0); 36032#L1358-1 assume !(0 == ~E_8~0); 36033#L1363-1 assume !(0 == ~E_9~0); 36319#L1368-1 assume !(0 == ~E_10~0); 34965#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34966#L1378-1 assume !(0 == ~E_12~0); 35246#L1383-1 assume !(0 == ~E_13~0); 35247#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36037#L607 assume 1 == ~m_pc~0; 36038#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35321#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35834#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35835#L1560 assume !(0 != activate_threads_~tmp~1#1); 35944#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35132#L626 assume !(1 == ~t1_pc~0); 35133#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35414#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35415#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36305#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 35040#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35041#L645 assume 1 == ~t2_pc~0; 35148#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35105#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35214#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35215#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35918#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35919#L664 assume 1 == ~t3_pc~0; 36681#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34899#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34900#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35563#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35564#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36597#L683 assume !(1 == ~t4_pc~0); 36148#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36102#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34923#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34924#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36255#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35858#L702 assume 1 == ~t5_pc~0; 35859#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35794#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36250#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36587#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36495#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34935#L721 assume !(1 == ~t6_pc~0); 34916#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34917#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35064#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35199#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35579#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36195#L740 assume 1 == ~t7_pc~0; 34981#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34816#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34817#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34806#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34807#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35503#L759 assume !(1 == ~t8_pc~0); 35504#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35535#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36641#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36380#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36381#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36663#L778 assume 1 == ~t9_pc~0; 36553#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34964#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35269#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34842#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34843#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35144#L797 assume !(1 == ~t10_pc~0); 35145#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35279#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36530#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35687#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35688#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35989#L816 assume 1 == ~t11_pc~0; 34877#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34878#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35823#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35585#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35586#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36130#L835 assume 1 == ~t12_pc~0; 36004#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35028#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34867#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34868#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35743#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35744#L854 assume !(1 == ~t13_pc~0); 35359#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35360#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35409#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35062#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35063#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36491#L1401 assume !(1 == ~M_E~0); 35572#L1401-2 assume !(1 == ~T1_E~0); 35573#L1406-1 assume !(1 == ~T2_E~0); 36184#L1411-1 assume !(1 == ~T3_E~0); 36185#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35833#L1421-1 assume !(1 == ~T5_E~0); 35355#L1426-1 assume !(1 == ~T6_E~0); 35356#L1431-1 assume !(1 == ~T7_E~0); 34914#L1436-1 assume !(1 == ~T8_E~0); 34915#L1441-1 assume !(1 == ~T9_E~0); 35680#L1446-1 assume !(1 == ~T10_E~0); 35681#L1451-1 assume !(1 == ~T11_E~0); 36399#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36057#L1461-1 assume !(1 == ~T13_E~0); 35601#L1466-1 assume !(1 == ~E_1~0); 35602#L1471-1 assume !(1 == ~E_2~0); 36378#L1476-1 assume !(1 == ~E_3~0); 36379#L1481-1 assume !(1 == ~E_4~0); 36536#L1486-1 assume !(1 == ~E_5~0); 35184#L1491-1 assume !(1 == ~E_6~0); 34852#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34853#L1501-1 assume !(1 == ~E_8~0); 35676#L1506-1 assume !(1 == ~E_9~0); 35677#L1511-1 assume !(1 == ~E_10~0); 35631#L1516-1 assume !(1 == ~E_11~0); 34804#L1521-1 assume !(1 == ~E_12~0); 34805#L1526-1 assume !(1 == ~E_13~0); 34851#L1531-1 assume { :end_inline_reset_delta_events } true; 35381#L1892-2 [2023-11-26 11:58:09,644 INFO L750 eck$LassoCheckResult]: Loop: 35381#L1892-2 assume !false; 36444#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36697#L1233-1 assume !false; 36624#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35945#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35925#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36473#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34893#L1046 assume !(0 != eval_~tmp~0#1); 34895#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35426#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35427#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36680#L1258-5 assume !(0 == ~T1_E~0); 35052#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35053#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36672#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36676#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36677#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35284#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35285#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36441#L1298-3 assume !(0 == ~T9_E~0); 36442#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36604#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36440#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35929#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 35054#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35055#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36528#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35195#L1338-3 assume !(0 == ~E_4~0); 35196#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36355#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36533#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36534#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35874#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35416#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35417#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36215#L1378-3 assume !(0 == ~E_12~0); 36216#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36396#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36397#L607-42 assume 1 == ~m_pc~0; 36014#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35724#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35556#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35436#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35437#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35990#L626-42 assume 1 == ~t1_pc~0; 35527#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35528#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36628#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36413#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35087#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35088#L645-42 assume 1 == ~t2_pc~0; 36596#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36334#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35872#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35304#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34824#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34825#L664-42 assume 1 == ~t3_pc~0; 35637#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35341#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36274#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36162#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36163#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36326#L683-42 assume 1 == ~t4_pc~0; 36689#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36041#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36169#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36329#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36594#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36435#L702-42 assume 1 == ~t5_pc~0; 35906#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35518#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35826#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35939#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 34836#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34837#L721-42 assume 1 == ~t6_pc~0; 34976#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34997#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35175#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35176#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35657#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35491#L740-42 assume 1 == ~t7_pc~0; 35492#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35211#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35787#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35640#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35641#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35912#L759-42 assume 1 == ~t8_pc~0; 35763#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35697#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35698#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35772#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35773#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35863#L778-42 assume 1 == ~t9_pc~0; 35709#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35711#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36134#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36042#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36043#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36097#L797-42 assume 1 == ~t10_pc~0; 35218#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35219#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36115#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36116#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36135#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36136#L816-42 assume 1 == ~t11_pc~0; 34796#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34797#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36634#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35684#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35395#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35396#L835-42 assume !(1 == ~t12_pc~0); 35720#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 35721#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35915#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35916#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36494#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36272#L854-42 assume 1 == ~t13_pc~0; 36273#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35317#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35483#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35484#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35597#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35598#L1401-3 assume !(1 == ~M_E~0); 36389#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35147#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35023#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35024#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35647#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35648#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35189#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35190#L1436-3 assume !(1 == ~T8_E~0); 34808#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34809#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36417#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35735#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35363#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 35364#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36674#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35305#L1476-3 assume !(1 == ~E_3~0); 35306#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35729#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35333#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35334#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35769#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35770#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36211#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36199#L1516-3 assume !(1 == ~E_11~0); 36200#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35877#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35878#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36293#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35122#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35169#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35170#L1911 assume !(0 == start_simulation_~tmp~3#1); 35701#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36232#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35261#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34846#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34847#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34970#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35733#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36547#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35381#L1892-2 [2023-11-26 11:58:09,646 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:09,646 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2023-11-26 11:58:09,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:09,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541465743] [2023-11-26 11:58:09,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:09,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:09,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:09,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:09,702 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:09,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [541465743] [2023-11-26 11:58:09,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [541465743] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:09,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:09,703 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:09,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114103133] [2023-11-26 11:58:09,703 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:09,704 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:09,704 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:09,704 INFO L85 PathProgramCache]: Analyzing trace with hash -1028276364, now seen corresponding path program 1 times [2023-11-26 11:58:09,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:09,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430624824] [2023-11-26 11:58:09,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:09,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:09,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:09,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:09,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:09,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430624824] [2023-11-26 11:58:09,777 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430624824] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:09,777 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:09,777 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:09,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995065967] [2023-11-26 11:58:09,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:09,778 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:09,778 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:09,779 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:09,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:09,779 INFO L87 Difference]: Start difference. First operand 1928 states and 2841 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:09,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:09,823 INFO L93 Difference]: Finished difference Result 1928 states and 2840 transitions. [2023-11-26 11:58:09,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2840 transitions. [2023-11-26 11:58:09,834 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:09,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2840 transitions. [2023-11-26 11:58:09,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:09,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:09,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2840 transitions. [2023-11-26 11:58:09,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:09,892 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2840 transitions. [2023-11-26 11:58:09,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2840 transitions. [2023-11-26 11:58:09,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:09,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4730290456431536) internal successors, (2840), 1927 states have internal predecessors, (2840), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:09,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2840 transitions. [2023-11-26 11:58:09,953 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2840 transitions. [2023-11-26 11:58:09,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:09,954 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2840 transitions. [2023-11-26 11:58:09,954 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 11:58:09,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2840 transitions. [2023-11-26 11:58:09,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:09,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:09,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:09,966 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:09,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:09,967 INFO L748 eck$LassoCheckResult]: Stem: 38935#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 38936#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39836#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39837#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40561#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 40232#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40233#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39156#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39157#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39636#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39471#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39472#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39220#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39221#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39642#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39826#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39994#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40028#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 39236#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39237#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40452#L1258-2 assume !(0 == ~T1_E~0); 39554#L1263-1 assume !(0 == ~T2_E~0); 39555#L1268-1 assume !(0 == ~T3_E~0); 39872#L1273-1 assume !(0 == ~T4_E~0); 40431#L1278-1 assume !(0 == ~T5_E~0); 40289#L1283-1 assume !(0 == ~T6_E~0); 40290#L1288-1 assume !(0 == ~T7_E~0); 40528#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40516#L1298-1 assume !(0 == ~T9_E~0); 40447#L1303-1 assume !(0 == ~T10_E~0); 39034#L1308-1 assume !(0 == ~T11_E~0); 38977#L1313-1 assume !(0 == ~T12_E~0); 38978#L1318-1 assume !(0 == ~T13_E~0); 38982#L1323-1 assume !(0 == ~E_1~0); 38983#L1328-1 assume !(0 == ~E_2~0); 39166#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 40160#L1338-1 assume !(0 == ~E_4~0); 40161#L1343-1 assume !(0 == ~E_5~0); 40266#L1348-1 assume !(0 == ~E_6~0); 40546#L1353-1 assume !(0 == ~E_7~0); 39895#L1358-1 assume !(0 == ~E_8~0); 39896#L1363-1 assume !(0 == ~E_9~0); 40182#L1368-1 assume !(0 == ~E_10~0); 38828#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38829#L1378-1 assume !(0 == ~E_12~0); 39111#L1383-1 assume !(0 == ~E_13~0); 39112#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39900#L607 assume 1 == ~m_pc~0; 39901#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39186#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39700#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39701#L1560 assume !(0 != activate_threads_~tmp~1#1); 39807#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38995#L626 assume !(1 == ~t1_pc~0); 38996#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39279#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39280#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40168#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38904#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38905#L645 assume 1 == ~t2_pc~0; 39013#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38968#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39079#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39080#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39781#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39782#L664 assume 1 == ~t3_pc~0; 40544#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38766#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38767#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39426#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39427#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40460#L683 assume !(1 == ~t4_pc~0); 40011#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39965#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38786#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38787#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40118#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39725#L702 assume 1 == ~t5_pc~0; 39726#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39658#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40113#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40450#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40359#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38802#L721 assume !(1 == ~t6_pc~0); 38779#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38780#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38927#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39062#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39442#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40058#L740 assume 1 == ~t7_pc~0; 38844#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38679#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38680#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38669#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38670#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39367#L759 assume !(1 == ~t8_pc~0); 39368#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39398#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40507#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40243#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 40244#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40526#L778 assume 1 == ~t9_pc~0; 40418#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38827#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39132#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38705#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38706#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39008#L797 assume !(1 == ~t10_pc~0); 39009#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39142#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40393#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39550#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39551#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39852#L816 assume 1 == ~t11_pc~0; 38742#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38743#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39688#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39448#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39449#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39993#L835 assume 1 == ~t12_pc~0; 39867#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38891#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38730#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38731#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39606#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39607#L854 assume !(1 == ~t13_pc~0); 39222#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 39223#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39274#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38925#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38926#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40354#L1401 assume !(1 == ~M_E~0); 39435#L1401-2 assume !(1 == ~T1_E~0); 39436#L1406-1 assume !(1 == ~T2_E~0); 40047#L1411-1 assume !(1 == ~T3_E~0); 40048#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39696#L1421-1 assume !(1 == ~T5_E~0); 39218#L1426-1 assume !(1 == ~T6_E~0); 39219#L1431-1 assume !(1 == ~T7_E~0); 38777#L1436-1 assume !(1 == ~T8_E~0); 38778#L1441-1 assume !(1 == ~T9_E~0); 39543#L1446-1 assume !(1 == ~T10_E~0); 39544#L1451-1 assume !(1 == ~T11_E~0); 40262#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39920#L1461-1 assume !(1 == ~T13_E~0); 39464#L1466-1 assume !(1 == ~E_1~0); 39465#L1471-1 assume !(1 == ~E_2~0); 40241#L1476-1 assume !(1 == ~E_3~0); 40242#L1481-1 assume !(1 == ~E_4~0); 40399#L1486-1 assume !(1 == ~E_5~0); 39047#L1491-1 assume !(1 == ~E_6~0); 38715#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38716#L1501-1 assume !(1 == ~E_8~0); 39539#L1506-1 assume !(1 == ~E_9~0); 39540#L1511-1 assume !(1 == ~E_10~0); 39494#L1516-1 assume !(1 == ~E_11~0); 38667#L1521-1 assume !(1 == ~E_12~0); 38668#L1526-1 assume !(1 == ~E_13~0); 38714#L1531-1 assume { :end_inline_reset_delta_events } true; 39244#L1892-2 [2023-11-26 11:58:09,968 INFO L750 eck$LassoCheckResult]: Loop: 39244#L1892-2 assume !false; 40307#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40560#L1233-1 assume !false; 40487#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39808#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39788#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40336#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38756#L1046 assume !(0 != eval_~tmp~0#1); 38758#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39289#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39290#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40543#L1258-5 assume !(0 == ~T1_E~0); 38915#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38916#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40535#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40539#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40540#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39147#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39148#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40304#L1298-3 assume !(0 == ~T9_E~0); 40305#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40467#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40303#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39792#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38917#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38918#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40391#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39058#L1338-3 assume !(0 == ~E_4~0); 39059#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40218#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40396#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40397#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39737#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39277#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39278#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40078#L1378-3 assume !(0 == ~E_12~0); 40079#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 40259#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40260#L607-42 assume 1 == ~m_pc~0; 39877#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39587#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39419#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39299#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39300#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39853#L626-42 assume !(1 == ~t1_pc~0); 39392#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 39391#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40491#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40276#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38950#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38951#L645-42 assume !(1 == ~t2_pc~0); 40196#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40197#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39735#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39167#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38687#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38688#L664-42 assume !(1 == ~t3_pc~0); 39203#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 39204#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40137#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40025#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40026#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40189#L683-42 assume 1 == ~t4_pc~0; 40552#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39904#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40032#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40192#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40457#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40298#L702-42 assume !(1 == ~t5_pc~0); 39380#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 39381#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39689#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39802#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 38699#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38700#L721-42 assume 1 == ~t6_pc~0; 38839#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38860#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39038#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39039#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39520#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39354#L740-42 assume !(1 == ~t7_pc~0); 39073#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 39074#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39650#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39503#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39504#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39775#L759-42 assume 1 == ~t8_pc~0; 39626#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39560#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39561#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39634#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39635#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39724#L778-42 assume 1 == ~t9_pc~0; 39572#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39574#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39997#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39905#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39906#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39960#L797-42 assume 1 == ~t10_pc~0; 39081#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39082#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39978#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39979#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39998#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39999#L816-42 assume 1 == ~t11_pc~0; 38659#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38660#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40497#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39547#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39258#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39259#L835-42 assume 1 == ~t12_pc~0; 39685#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 39584#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39778#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39779#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40357#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 40135#L854-42 assume 1 == ~t13_pc~0; 40136#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 39180#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39346#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39347#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39460#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39461#L1401-3 assume !(1 == ~M_E~0); 40252#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39007#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38886#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38887#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39510#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39511#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39052#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39053#L1436-3 assume !(1 == ~T8_E~0); 38671#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38672#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40280#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39598#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39226#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 39227#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40537#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39168#L1476-3 assume !(1 == ~E_3~0); 39169#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39592#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39196#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39197#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39632#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39633#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40074#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40062#L1516-3 assume !(1 == ~E_11~0); 40063#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39740#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39741#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40156#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38985#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39032#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39033#L1911 assume !(0 == start_simulation_~tmp~3#1); 39564#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40095#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39124#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38709#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38710#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38833#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39596#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40410#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 39244#L1892-2 [2023-11-26 11:58:09,969 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:09,969 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2023-11-26 11:58:09,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:09,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227136253] [2023-11-26 11:58:09,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:09,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:09,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:10,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:10,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:10,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227136253] [2023-11-26 11:58:10,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227136253] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:10,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:10,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:10,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435830525] [2023-11-26 11:58:10,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:10,029 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:10,030 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:10,030 INFO L85 PathProgramCache]: Analyzing trace with hash -1591848080, now seen corresponding path program 1 times [2023-11-26 11:58:10,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:10,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717558555] [2023-11-26 11:58:10,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:10,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:10,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:10,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:10,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:10,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717558555] [2023-11-26 11:58:10,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [717558555] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:10,105 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:10,105 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:10,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [672790190] [2023-11-26 11:58:10,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:10,106 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:10,106 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:10,107 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:10,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:10,108 INFO L87 Difference]: Start difference. First operand 1928 states and 2840 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:10,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:10,152 INFO L93 Difference]: Finished difference Result 1928 states and 2839 transitions. [2023-11-26 11:58:10,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2839 transitions. [2023-11-26 11:58:10,164 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:10,180 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2839 transitions. [2023-11-26 11:58:10,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:10,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:10,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2839 transitions. [2023-11-26 11:58:10,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:10,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2839 transitions. [2023-11-26 11:58:10,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2839 transitions. [2023-11-26 11:58:10,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:10,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4725103734439835) internal successors, (2839), 1927 states have internal predecessors, (2839), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:10,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2839 transitions. [2023-11-26 11:58:10,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2839 transitions. [2023-11-26 11:58:10,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:10,231 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2839 transitions. [2023-11-26 11:58:10,231 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 11:58:10,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2839 transitions. [2023-11-26 11:58:10,240 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:10,240 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:10,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:10,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:10,244 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:10,244 INFO L748 eck$LassoCheckResult]: Stem: 42798#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 42799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 43699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44424#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 44095#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44096#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43019#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43020#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43499#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43334#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43335#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43083#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43084#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43505#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43689#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43857#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43891#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 43099#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43100#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 44315#L1258-2 assume !(0 == ~T1_E~0); 43417#L1263-1 assume !(0 == ~T2_E~0); 43418#L1268-1 assume !(0 == ~T3_E~0); 43735#L1273-1 assume !(0 == ~T4_E~0); 44294#L1278-1 assume !(0 == ~T5_E~0); 44152#L1283-1 assume !(0 == ~T6_E~0); 44153#L1288-1 assume !(0 == ~T7_E~0); 44391#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44379#L1298-1 assume !(0 == ~T9_E~0); 44310#L1303-1 assume !(0 == ~T10_E~0); 42897#L1308-1 assume !(0 == ~T11_E~0); 42837#L1313-1 assume !(0 == ~T12_E~0); 42838#L1318-1 assume !(0 == ~T13_E~0); 42845#L1323-1 assume !(0 == ~E_1~0); 42846#L1328-1 assume !(0 == ~E_2~0); 43029#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 44023#L1338-1 assume !(0 == ~E_4~0); 44024#L1343-1 assume !(0 == ~E_5~0); 44129#L1348-1 assume !(0 == ~E_6~0); 44409#L1353-1 assume !(0 == ~E_7~0); 43758#L1358-1 assume !(0 == ~E_8~0); 43759#L1363-1 assume !(0 == ~E_9~0); 44045#L1368-1 assume !(0 == ~E_10~0); 42691#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42692#L1378-1 assume !(0 == ~E_12~0); 42974#L1383-1 assume !(0 == ~E_13~0); 42975#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43763#L607 assume 1 == ~m_pc~0; 43764#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43049#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43563#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43564#L1560 assume !(0 != activate_threads_~tmp~1#1); 43670#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42858#L626 assume !(1 == ~t1_pc~0); 42859#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43142#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44031#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42767#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42768#L645 assume 1 == ~t2_pc~0; 42876#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42831#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42942#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42943#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43644#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43645#L664 assume 1 == ~t3_pc~0; 44407#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42629#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42630#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43289#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 43290#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44323#L683 assume !(1 == ~t4_pc~0); 43874#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43828#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42649#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42650#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43981#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43588#L702 assume 1 == ~t5_pc~0; 43589#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43521#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43976#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44313#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 44222#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42665#L721 assume !(1 == ~t6_pc~0); 42642#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42643#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42790#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42925#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 43305#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43921#L740 assume 1 == ~t7_pc~0; 42707#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42542#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42543#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42532#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42533#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43230#L759 assume !(1 == ~t8_pc~0); 43231#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43261#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44369#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44106#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 44107#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44389#L778 assume 1 == ~t9_pc~0; 44281#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42690#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42995#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42568#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42569#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42871#L797 assume !(1 == ~t10_pc~0); 42872#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43005#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44256#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43413#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43414#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43715#L816 assume 1 == ~t11_pc~0; 42605#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42606#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43551#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43311#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 43312#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43856#L835 assume 1 == ~t12_pc~0; 43730#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42754#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42593#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42594#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43469#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43470#L854 assume !(1 == ~t13_pc~0); 43085#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 43086#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 43137#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42788#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42789#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44217#L1401 assume !(1 == ~M_E~0); 43298#L1401-2 assume !(1 == ~T1_E~0); 43299#L1406-1 assume !(1 == ~T2_E~0); 43910#L1411-1 assume !(1 == ~T3_E~0); 43911#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43559#L1421-1 assume !(1 == ~T5_E~0); 43081#L1426-1 assume !(1 == ~T6_E~0); 43082#L1431-1 assume !(1 == ~T7_E~0); 42640#L1436-1 assume !(1 == ~T8_E~0); 42641#L1441-1 assume !(1 == ~T9_E~0); 43408#L1446-1 assume !(1 == ~T10_E~0); 43409#L1451-1 assume !(1 == ~T11_E~0); 44125#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43783#L1461-1 assume !(1 == ~T13_E~0); 43327#L1466-1 assume !(1 == ~E_1~0); 43328#L1471-1 assume !(1 == ~E_2~0); 44104#L1476-1 assume !(1 == ~E_3~0); 44105#L1481-1 assume !(1 == ~E_4~0); 44262#L1486-1 assume !(1 == ~E_5~0); 42910#L1491-1 assume !(1 == ~E_6~0); 42578#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42579#L1501-1 assume !(1 == ~E_8~0); 43402#L1506-1 assume !(1 == ~E_9~0); 43403#L1511-1 assume !(1 == ~E_10~0); 43357#L1516-1 assume !(1 == ~E_11~0); 42530#L1521-1 assume !(1 == ~E_12~0); 42531#L1526-1 assume !(1 == ~E_13~0); 42577#L1531-1 assume { :end_inline_reset_delta_events } true; 43107#L1892-2 [2023-11-26 11:58:10,245 INFO L750 eck$LassoCheckResult]: Loop: 43107#L1892-2 assume !false; 44170#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44423#L1233-1 assume !false; 44350#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43671#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43651#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44199#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42619#L1046 assume !(0 != eval_~tmp~0#1); 42621#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43153#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43154#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44406#L1258-5 assume !(0 == ~T1_E~0); 42782#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42783#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44398#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44402#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44403#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43010#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43011#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44167#L1298-3 assume !(0 == ~T9_E~0); 44168#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44330#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44166#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43655#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42778#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42779#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44254#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42919#L1338-3 assume !(0 == ~E_4~0); 42920#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44081#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44259#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44260#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43600#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43140#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43141#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43941#L1378-3 assume !(0 == ~E_12~0); 43942#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 44122#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44123#L607-42 assume 1 == ~m_pc~0; 43740#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43450#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43282#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43162#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43163#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43716#L626-42 assume 1 == ~t1_pc~0; 43253#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43254#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44354#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44139#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42811#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42812#L645-42 assume 1 == ~t2_pc~0; 44322#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44060#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43598#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43030#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42550#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42551#L664-42 assume 1 == ~t3_pc~0; 43363#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43067#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44000#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43888#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43889#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44052#L683-42 assume !(1 == ~t4_pc~0); 43766#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43767#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43895#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44055#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44320#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44161#L702-42 assume 1 == ~t5_pc~0; 43632#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43244#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43552#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43665#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 42562#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42563#L721-42 assume 1 == ~t6_pc~0; 42702#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42723#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42901#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42902#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43383#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43217#L740-42 assume 1 == ~t7_pc~0; 43218#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42937#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43513#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43366#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43367#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43638#L759-42 assume 1 == ~t8_pc~0; 43489#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43423#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43424#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43497#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43498#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43587#L778-42 assume 1 == ~t9_pc~0; 43435#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43437#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43860#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43768#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43769#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43823#L797-42 assume 1 == ~t10_pc~0; 42944#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42945#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43841#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43842#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43861#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43862#L816-42 assume 1 == ~t11_pc~0; 42522#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42523#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44360#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43410#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43121#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43122#L835-42 assume !(1 == ~t12_pc~0); 43446#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 43447#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43640#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43641#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44220#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43998#L854-42 assume !(1 == ~t13_pc~0); 43040#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 43041#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 43209#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43210#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43323#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43324#L1401-3 assume !(1 == ~M_E~0); 44115#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42870#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42749#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42750#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43373#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43374#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42915#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42916#L1436-3 assume !(1 == ~T8_E~0); 42534#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42535#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44143#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43461#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43089#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 43090#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44400#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43031#L1476-3 assume !(1 == ~E_3~0); 43032#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43455#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43059#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43060#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43495#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43496#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43937#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43925#L1516-3 assume !(1 == ~E_11~0); 43926#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43603#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43604#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44019#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42848#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42895#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 42896#L1911 assume !(0 == start_simulation_~tmp~3#1); 43427#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43958#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42987#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42572#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42573#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42696#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43459#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 44273#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 43107#L1892-2 [2023-11-26 11:58:10,246 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:10,246 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2023-11-26 11:58:10,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:10,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757381744] [2023-11-26 11:58:10,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:10,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:10,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:10,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:10,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:10,332 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757381744] [2023-11-26 11:58:10,332 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757381744] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:10,332 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:10,332 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:10,333 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384767662] [2023-11-26 11:58:10,333 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:10,333 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:10,334 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:10,334 INFO L85 PathProgramCache]: Analyzing trace with hash 955629298, now seen corresponding path program 1 times [2023-11-26 11:58:10,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:10,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168198911] [2023-11-26 11:58:10,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:10,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:10,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:10,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:10,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:10,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168198911] [2023-11-26 11:58:10,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1168198911] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:10,406 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:10,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:10,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991167571] [2023-11-26 11:58:10,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:10,407 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:10,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:10,408 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:10,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:10,408 INFO L87 Difference]: Start difference. First operand 1928 states and 2839 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:10,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:10,451 INFO L93 Difference]: Finished difference Result 1928 states and 2838 transitions. [2023-11-26 11:58:10,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2838 transitions. [2023-11-26 11:58:10,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:10,473 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2838 transitions. [2023-11-26 11:58:10,473 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:10,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:10,475 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2838 transitions. [2023-11-26 11:58:10,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:10,479 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2838 transitions. [2023-11-26 11:58:10,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2838 transitions. [2023-11-26 11:58:10,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:10,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4719917012448134) internal successors, (2838), 1927 states have internal predecessors, (2838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:10,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2838 transitions. [2023-11-26 11:58:10,521 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2838 transitions. [2023-11-26 11:58:10,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:10,522 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2838 transitions. [2023-11-26 11:58:10,522 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 11:58:10,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2838 transitions. [2023-11-26 11:58:10,530 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:10,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:10,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:10,533 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:10,534 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:10,534 INFO L748 eck$LassoCheckResult]: Stem: 46661#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46662#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 47561#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47562#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48287#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47958#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47959#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46882#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46883#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47362#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47197#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47198#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46946#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46947#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47368#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47552#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47720#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47753#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46962#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46963#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 48178#L1258-2 assume !(0 == ~T1_E~0); 47280#L1263-1 assume !(0 == ~T2_E~0); 47281#L1268-1 assume !(0 == ~T3_E~0); 47598#L1273-1 assume !(0 == ~T4_E~0); 48157#L1278-1 assume !(0 == ~T5_E~0); 48015#L1283-1 assume !(0 == ~T6_E~0); 48016#L1288-1 assume !(0 == ~T7_E~0); 48254#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48242#L1298-1 assume !(0 == ~T9_E~0); 48173#L1303-1 assume !(0 == ~T10_E~0); 46760#L1308-1 assume !(0 == ~T11_E~0); 46700#L1313-1 assume !(0 == ~T12_E~0); 46701#L1318-1 assume !(0 == ~T13_E~0); 46708#L1323-1 assume !(0 == ~E_1~0); 46709#L1328-1 assume !(0 == ~E_2~0); 46892#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47886#L1338-1 assume !(0 == ~E_4~0); 47887#L1343-1 assume !(0 == ~E_5~0); 47992#L1348-1 assume !(0 == ~E_6~0); 48272#L1353-1 assume !(0 == ~E_7~0); 47621#L1358-1 assume !(0 == ~E_8~0); 47622#L1363-1 assume !(0 == ~E_9~0); 47908#L1368-1 assume !(0 == ~E_10~0); 46554#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46555#L1378-1 assume !(0 == ~E_12~0); 46837#L1383-1 assume !(0 == ~E_13~0); 46838#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47626#L607 assume 1 == ~m_pc~0; 47627#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46910#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47426#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47427#L1560 assume !(0 != activate_threads_~tmp~1#1); 47533#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46721#L626 assume !(1 == ~t1_pc~0); 46722#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47003#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47004#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47894#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46629#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46630#L645 assume 1 == ~t2_pc~0; 46739#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46694#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46805#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46806#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47507#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47508#L664 assume 1 == ~t3_pc~0; 48270#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46492#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46493#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47152#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 47153#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48186#L683 assume !(1 == ~t4_pc~0); 47737#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47691#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46512#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46513#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47844#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47451#L702 assume 1 == ~t5_pc~0; 47452#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47384#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48176#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 48085#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46528#L721 assume !(1 == ~t6_pc~0); 46505#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46506#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46653#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46788#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 47168#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47784#L740 assume 1 == ~t7_pc~0; 46570#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46405#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46406#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46395#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46396#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47093#L759 assume !(1 == ~t8_pc~0); 47094#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47124#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48232#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47969#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47970#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48252#L778 assume 1 == ~t9_pc~0; 48142#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46553#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46858#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46431#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46432#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46734#L797 assume !(1 == ~t10_pc~0); 46735#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46868#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48119#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47276#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 47277#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47578#L816 assume 1 == ~t11_pc~0; 46468#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46469#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47414#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47174#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 47175#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47719#L835 assume 1 == ~t12_pc~0; 47593#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46617#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46456#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46457#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 47332#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47333#L854 assume !(1 == ~t13_pc~0); 46948#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46949#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46998#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46651#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46652#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48080#L1401 assume !(1 == ~M_E~0); 47161#L1401-2 assume !(1 == ~T1_E~0); 47162#L1406-1 assume !(1 == ~T2_E~0); 47773#L1411-1 assume !(1 == ~T3_E~0); 47774#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47422#L1421-1 assume !(1 == ~T5_E~0); 46944#L1426-1 assume !(1 == ~T6_E~0); 46945#L1431-1 assume !(1 == ~T7_E~0); 46503#L1436-1 assume !(1 == ~T8_E~0); 46504#L1441-1 assume !(1 == ~T9_E~0); 47271#L1446-1 assume !(1 == ~T10_E~0); 47272#L1451-1 assume !(1 == ~T11_E~0); 47988#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47646#L1461-1 assume !(1 == ~T13_E~0); 47190#L1466-1 assume !(1 == ~E_1~0); 47191#L1471-1 assume !(1 == ~E_2~0); 47967#L1476-1 assume !(1 == ~E_3~0); 47968#L1481-1 assume !(1 == ~E_4~0); 48125#L1486-1 assume !(1 == ~E_5~0); 46773#L1491-1 assume !(1 == ~E_6~0); 46441#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46442#L1501-1 assume !(1 == ~E_8~0); 47265#L1506-1 assume !(1 == ~E_9~0); 47266#L1511-1 assume !(1 == ~E_10~0); 47220#L1516-1 assume !(1 == ~E_11~0); 46393#L1521-1 assume !(1 == ~E_12~0); 46394#L1526-1 assume !(1 == ~E_13~0); 46440#L1531-1 assume { :end_inline_reset_delta_events } true; 46970#L1892-2 [2023-11-26 11:58:10,535 INFO L750 eck$LassoCheckResult]: Loop: 46970#L1892-2 assume !false; 48033#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48286#L1233-1 assume !false; 48213#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47534#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47514#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48062#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46482#L1046 assume !(0 != eval_~tmp~0#1); 46484#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47016#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47017#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48269#L1258-5 assume !(0 == ~T1_E~0); 46643#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46644#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48261#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48265#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48266#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46873#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46874#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48030#L1298-3 assume !(0 == ~T9_E~0); 48031#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48193#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48029#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47518#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46645#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46646#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48117#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46784#L1338-3 assume !(0 == ~E_4~0); 46785#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47944#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48123#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48124#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47463#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47005#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47006#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47804#L1378-3 assume !(0 == ~E_12~0); 47805#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47985#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47986#L607-42 assume 1 == ~m_pc~0; 47603#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 47313#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47145#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47025#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47026#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47579#L626-42 assume 1 == ~t1_pc~0; 47116#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47117#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48217#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48002#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46674#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46675#L645-42 assume !(1 == ~t2_pc~0); 47922#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47923#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47461#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46893#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46413#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46414#L664-42 assume !(1 == ~t3_pc~0); 46929#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46930#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47863#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47751#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47752#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47915#L683-42 assume 1 == ~t4_pc~0; 48278#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47630#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47758#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47918#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48183#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48024#L702-42 assume !(1 == ~t5_pc~0); 47106#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 47107#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47415#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47528#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 46425#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46426#L721-42 assume 1 == ~t6_pc~0; 46565#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46586#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46764#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46765#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47246#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47080#L740-42 assume 1 == ~t7_pc~0; 47081#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46800#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47376#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47229#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47230#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47501#L759-42 assume 1 == ~t8_pc~0; 47352#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47286#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47287#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47360#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47361#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47450#L778-42 assume 1 == ~t9_pc~0; 47298#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47300#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47723#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47631#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47632#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47686#L797-42 assume 1 == ~t10_pc~0; 46807#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46808#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47704#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47705#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47724#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47725#L816-42 assume 1 == ~t11_pc~0; 46385#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46386#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48223#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47273#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46984#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46985#L835-42 assume 1 == ~t12_pc~0; 47411#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47309#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47503#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47504#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 48083#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47861#L854-42 assume 1 == ~t13_pc~0; 47862#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46904#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 47072#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47073#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 47186#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47187#L1401-3 assume !(1 == ~M_E~0); 47978#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46733#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46612#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46613#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47236#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47237#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46778#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46779#L1436-3 assume !(1 == ~T8_E~0); 46397#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46398#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48006#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47324#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46952#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46953#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48263#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46894#L1476-3 assume !(1 == ~E_3~0); 46895#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47318#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46922#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46923#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47357#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47358#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47800#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47788#L1516-3 assume !(1 == ~E_11~0); 47789#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47466#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47467#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47882#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46711#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46758#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46759#L1911 assume !(0 == start_simulation_~tmp~3#1); 47290#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47821#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46850#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46435#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46436#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46559#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47322#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 48136#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46970#L1892-2 [2023-11-26 11:58:10,536 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:10,536 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2023-11-26 11:58:10,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:10,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061422865] [2023-11-26 11:58:10,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:10,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:10,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:10,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:10,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:10,589 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1061422865] [2023-11-26 11:58:10,589 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1061422865] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:10,589 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:10,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:10,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402380384] [2023-11-26 11:58:10,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:10,591 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:10,591 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:10,591 INFO L85 PathProgramCache]: Analyzing trace with hash 1270235442, now seen corresponding path program 2 times [2023-11-26 11:58:10,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:10,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559590193] [2023-11-26 11:58:10,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:10,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:10,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:10,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:10,689 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:10,689 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [559590193] [2023-11-26 11:58:10,689 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [559590193] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:10,689 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:10,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:10,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869219038] [2023-11-26 11:58:10,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:10,690 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:10,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:10,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:10,691 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:10,691 INFO L87 Difference]: Start difference. First operand 1928 states and 2838 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:10,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:10,734 INFO L93 Difference]: Finished difference Result 1928 states and 2837 transitions. [2023-11-26 11:58:10,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2837 transitions. [2023-11-26 11:58:10,745 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:10,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2837 transitions. [2023-11-26 11:58:10,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2023-11-26 11:58:10,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2023-11-26 11:58:10,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2837 transitions. [2023-11-26 11:58:10,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:10,762 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2837 transitions. [2023-11-26 11:58:10,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2837 transitions. [2023-11-26 11:58:10,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2023-11-26 11:58:10,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4714730290456433) internal successors, (2837), 1927 states have internal predecessors, (2837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:10,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2837 transitions. [2023-11-26 11:58:10,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2837 transitions. [2023-11-26 11:58:10,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:10,808 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2837 transitions. [2023-11-26 11:58:10,808 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 11:58:10,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2837 transitions. [2023-11-26 11:58:10,817 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2023-11-26 11:58:10,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:10,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:10,821 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:10,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:10,822 INFO L748 eck$LassoCheckResult]: Stem: 50524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 51424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52150#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51821#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51822#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50745#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50746#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51225#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51060#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 51061#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50809#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50810#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 51231#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51415#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51583#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51616#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50825#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50826#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 52041#L1258-2 assume !(0 == ~T1_E~0); 51143#L1263-1 assume !(0 == ~T2_E~0); 51144#L1268-1 assume !(0 == ~T3_E~0); 51461#L1273-1 assume !(0 == ~T4_E~0); 52020#L1278-1 assume !(0 == ~T5_E~0); 51878#L1283-1 assume !(0 == ~T6_E~0); 51879#L1288-1 assume !(0 == ~T7_E~0); 52116#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52105#L1298-1 assume !(0 == ~T9_E~0); 52036#L1303-1 assume !(0 == ~T10_E~0); 50623#L1308-1 assume !(0 == ~T11_E~0); 50563#L1313-1 assume !(0 == ~T12_E~0); 50564#L1318-1 assume !(0 == ~T13_E~0); 50571#L1323-1 assume !(0 == ~E_1~0); 50572#L1328-1 assume !(0 == ~E_2~0); 50755#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51749#L1338-1 assume !(0 == ~E_4~0); 51750#L1343-1 assume !(0 == ~E_5~0); 51855#L1348-1 assume !(0 == ~E_6~0); 52135#L1353-1 assume !(0 == ~E_7~0); 51484#L1358-1 assume !(0 == ~E_8~0); 51485#L1363-1 assume !(0 == ~E_9~0); 51771#L1368-1 assume !(0 == ~E_10~0); 50417#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50418#L1378-1 assume !(0 == ~E_12~0); 50700#L1383-1 assume !(0 == ~E_13~0); 50701#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51489#L607 assume 1 == ~m_pc~0; 51490#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50773#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51289#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51290#L1560 assume !(0 != activate_threads_~tmp~1#1); 51396#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50584#L626 assume !(1 == ~t1_pc~0); 50585#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50866#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50867#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51757#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50492#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50493#L645 assume 1 == ~t2_pc~0; 50602#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50557#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50668#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50669#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 51370#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51371#L664 assume 1 == ~t3_pc~0; 52133#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50353#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50354#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51015#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 51016#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52049#L683 assume !(1 == ~t4_pc~0); 51600#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51554#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50375#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50376#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51707#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51314#L702 assume 1 == ~t5_pc~0; 51315#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51247#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51702#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52039#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51948#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50391#L721 assume !(1 == ~t6_pc~0); 50368#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50369#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50516#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50651#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 51031#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51647#L740 assume 1 == ~t7_pc~0; 50433#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50268#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50269#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50258#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 50259#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50956#L759 assume !(1 == ~t8_pc~0); 50957#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50987#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52095#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51832#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51833#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52115#L778 assume 1 == ~t9_pc~0; 52005#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50416#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50721#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50294#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 50295#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50597#L797 assume !(1 == ~t10_pc~0); 50598#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50731#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51982#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51139#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 51140#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51441#L816 assume 1 == ~t11_pc~0; 50331#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50332#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51275#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51037#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 51038#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51582#L835 assume 1 == ~t12_pc~0; 51456#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50480#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50319#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50320#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 51195#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51196#L854 assume !(1 == ~t13_pc~0); 50811#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50812#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50861#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50514#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50515#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51943#L1401 assume !(1 == ~M_E~0); 51024#L1401-2 assume !(1 == ~T1_E~0); 51025#L1406-1 assume !(1 == ~T2_E~0); 51636#L1411-1 assume !(1 == ~T3_E~0); 51637#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51285#L1421-1 assume !(1 == ~T5_E~0); 50807#L1426-1 assume !(1 == ~T6_E~0); 50808#L1431-1 assume !(1 == ~T7_E~0); 50366#L1436-1 assume !(1 == ~T8_E~0); 50367#L1441-1 assume !(1 == ~T9_E~0); 51134#L1446-1 assume !(1 == ~T10_E~0); 51135#L1451-1 assume !(1 == ~T11_E~0); 51851#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51509#L1461-1 assume !(1 == ~T13_E~0); 51053#L1466-1 assume !(1 == ~E_1~0); 51054#L1471-1 assume !(1 == ~E_2~0); 51830#L1476-1 assume !(1 == ~E_3~0); 51831#L1481-1 assume !(1 == ~E_4~0); 51988#L1486-1 assume !(1 == ~E_5~0); 50636#L1491-1 assume !(1 == ~E_6~0); 50304#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50305#L1501-1 assume !(1 == ~E_8~0); 51128#L1506-1 assume !(1 == ~E_9~0); 51129#L1511-1 assume !(1 == ~E_10~0); 51083#L1516-1 assume !(1 == ~E_11~0); 50256#L1521-1 assume !(1 == ~E_12~0); 50257#L1526-1 assume !(1 == ~E_13~0); 50303#L1531-1 assume { :end_inline_reset_delta_events } true; 50833#L1892-2 [2023-11-26 11:58:10,822 INFO L750 eck$LassoCheckResult]: Loop: 50833#L1892-2 assume !false; 51896#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52149#L1233-1 assume !false; 52076#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51397#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51377#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51925#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 50345#L1046 assume !(0 != eval_~tmp~0#1); 50347#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50879#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50880#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 52132#L1258-5 assume !(0 == ~T1_E~0); 50506#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50507#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52124#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52128#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52129#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50736#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50737#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51893#L1298-3 assume !(0 == ~T9_E~0); 51894#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 52056#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51892#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51381#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50508#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50509#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51980#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50647#L1338-3 assume !(0 == ~E_4~0); 50648#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51807#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51986#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51987#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51326#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50868#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50869#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51667#L1378-3 assume !(0 == ~E_12~0); 51668#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51848#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51849#L607-42 assume 1 == ~m_pc~0; 51469#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51176#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51010#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50888#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50889#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51445#L626-42 assume 1 == ~t1_pc~0; 50982#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50983#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52080#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51865#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50539#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50540#L645-42 assume 1 == ~t2_pc~0; 52048#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51785#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51324#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50756#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50276#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50277#L664-42 assume 1 == ~t3_pc~0; 51089#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50790#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51726#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51614#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51615#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51778#L683-42 assume !(1 == ~t4_pc~0); 51491#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 51492#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51620#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51781#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52046#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51887#L702-42 assume !(1 == ~t5_pc~0); 50969#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 50970#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51278#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51391#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 50288#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50289#L721-42 assume 1 == ~t6_pc~0; 50428#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50449#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50627#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50628#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51109#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50943#L740-42 assume 1 == ~t7_pc~0; 50944#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50663#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51239#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51092#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51093#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51364#L759-42 assume !(1 == ~t8_pc~0); 51216#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 51149#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51150#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51223#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51224#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51313#L778-42 assume 1 == ~t9_pc~0; 51161#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51163#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51586#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51493#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51494#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51549#L797-42 assume !(1 == ~t10_pc~0); 50672#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 50671#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51567#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51568#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51587#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51588#L816-42 assume 1 == ~t11_pc~0; 50248#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50249#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52086#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51136#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50847#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50848#L835-42 assume !(1 == ~t12_pc~0); 51169#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 51170#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51366#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51367#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51946#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51724#L854-42 assume 1 == ~t13_pc~0; 51725#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50767#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50935#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50936#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 51049#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51050#L1401-3 assume !(1 == ~M_E~0); 51841#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50596#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50475#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50476#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51099#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51100#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50641#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50642#L1436-3 assume !(1 == ~T8_E~0); 50260#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50261#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51869#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51187#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50815#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50816#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52126#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50757#L1476-3 assume !(1 == ~E_3~0); 50758#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51181#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50785#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50786#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51220#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51221#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51663#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51651#L1516-3 assume !(1 == ~E_11~0); 51652#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 51329#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 51330#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51745#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50574#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50621#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50622#L1911 assume !(0 == start_simulation_~tmp~3#1); 51153#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51684#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50713#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50298#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50299#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50422#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51185#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 51999#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50833#L1892-2 [2023-11-26 11:58:10,823 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:10,823 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2023-11-26 11:58:10,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:10,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059262248] [2023-11-26 11:58:10,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:10,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:10,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:10,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:10,898 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:10,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059262248] [2023-11-26 11:58:10,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059262248] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:10,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:10,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:58:10,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2001871146] [2023-11-26 11:58:10,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:10,900 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:10,900 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:10,900 INFO L85 PathProgramCache]: Analyzing trace with hash -974301264, now seen corresponding path program 1 times [2023-11-26 11:58:10,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:10,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485899096] [2023-11-26 11:58:10,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:10,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:10,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:10,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:10,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:10,971 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485899096] [2023-11-26 11:58:10,971 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485899096] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:10,971 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:10,971 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:10,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2093906058] [2023-11-26 11:58:10,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:10,973 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:10,973 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:10,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:10,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:10,974 INFO L87 Difference]: Start difference. First operand 1928 states and 2837 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:11,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:11,190 INFO L93 Difference]: Finished difference Result 3583 states and 5241 transitions. [2023-11-26 11:58:11,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3583 states and 5241 transitions. [2023-11-26 11:58:11,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3410 [2023-11-26 11:58:11,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3583 states to 3583 states and 5241 transitions. [2023-11-26 11:58:11,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3583 [2023-11-26 11:58:11,246 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3583 [2023-11-26 11:58:11,246 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3583 states and 5241 transitions. [2023-11-26 11:58:11,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:11,253 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3583 states and 5241 transitions. [2023-11-26 11:58:11,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3583 states and 5241 transitions. [2023-11-26 11:58:11,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3583 to 3583. [2023-11-26 11:58:11,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3583 states, 3583 states have (on average 1.462740720066983) internal successors, (5241), 3582 states have internal predecessors, (5241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:11,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3583 states to 3583 states and 5241 transitions. [2023-11-26 11:58:11,346 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3583 states and 5241 transitions. [2023-11-26 11:58:11,346 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:11,347 INFO L428 stractBuchiCegarLoop]: Abstraction has 3583 states and 5241 transitions. [2023-11-26 11:58:11,347 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 11:58:11,347 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3583 states and 5241 transitions. [2023-11-26 11:58:11,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3410 [2023-11-26 11:58:11,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:11,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:11,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:11,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:11,372 INFO L748 eck$LassoCheckResult]: Stem: 56042#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 56043#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56947#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56948#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57749#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 57358#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57359#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56264#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56265#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56743#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56579#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56580#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 56328#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 56329#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56751#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56937#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 57107#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 57144#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 56344#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56345#L1258 assume !(0 == ~M_E~0); 57596#L1258-2 assume !(0 == ~T1_E~0); 56662#L1263-1 assume !(0 == ~T2_E~0); 56663#L1268-1 assume !(0 == ~T3_E~0); 56984#L1273-1 assume !(0 == ~T4_E~0); 57572#L1278-1 assume !(0 == ~T5_E~0); 57418#L1283-1 assume !(0 == ~T6_E~0); 57419#L1288-1 assume !(0 == ~T7_E~0); 57696#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57679#L1298-1 assume !(0 == ~T9_E~0); 57589#L1303-1 assume !(0 == ~T10_E~0); 56141#L1308-1 assume !(0 == ~T11_E~0); 56081#L1313-1 assume !(0 == ~T12_E~0); 56082#L1318-1 assume !(0 == ~T13_E~0); 56087#L1323-1 assume !(0 == ~E_1~0); 56088#L1328-1 assume !(0 == ~E_2~0); 56274#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 57279#L1338-1 assume !(0 == ~E_4~0); 57280#L1343-1 assume !(0 == ~E_5~0); 57393#L1348-1 assume !(0 == ~E_6~0); 57730#L1353-1 assume !(0 == ~E_7~0); 57007#L1358-1 assume !(0 == ~E_8~0); 57008#L1363-1 assume !(0 == ~E_9~0); 57304#L1368-1 assume !(0 == ~E_10~0); 55935#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55936#L1378-1 assume !(0 == ~E_12~0); 56217#L1383-1 assume !(0 == ~E_13~0); 56218#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57011#L607 assume !(1 == ~m_pc~0); 56291#L607-2 is_master_triggered_~__retres1~0#1 := 0; 56292#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56807#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56808#L1560 assume !(0 != activate_threads_~tmp~1#1); 56918#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56102#L626 assume !(1 == ~t1_pc~0); 56103#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56385#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56386#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57289#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 56010#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56011#L645 assume 1 == ~t2_pc~0; 56118#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56075#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56184#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56185#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56891#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56892#L664 assume 1 == ~t3_pc~0; 57722#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55869#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55870#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56534#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56535#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57608#L683 assume !(1 == ~t4_pc~0); 57126#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 57077#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55893#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55894#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57236#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56831#L702 assume 1 == ~t5_pc~0; 56832#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56767#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57231#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57592#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57490#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55905#L721 assume !(1 == ~t6_pc~0); 55886#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55887#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56034#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56169#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56550#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57176#L740 assume 1 == ~t7_pc~0; 55951#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55786#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55787#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55776#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55777#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56474#L759 assume !(1 == ~t8_pc~0); 56475#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56506#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57662#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57369#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 57370#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57695#L778 assume 1 == ~t9_pc~0; 57557#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55934#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56240#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55812#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55813#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 56114#L797 assume !(1 == ~t10_pc~0); 56115#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 56250#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57529#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56658#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56659#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56964#L816 assume 1 == ~t11_pc~0; 55847#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55848#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56796#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56556#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56557#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57106#L835 assume 1 == ~t12_pc~0; 56979#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55998#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55837#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55838#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56714#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56715#L854 assume !(1 == ~t13_pc~0); 56330#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 56331#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56380#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 56032#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56033#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57485#L1401 assume !(1 == ~M_E~0); 56543#L1401-2 assume !(1 == ~T1_E~0); 56544#L1406-1 assume !(1 == ~T2_E~0); 57165#L1411-1 assume !(1 == ~T3_E~0); 57166#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56806#L1421-1 assume !(1 == ~T5_E~0); 56326#L1426-1 assume !(1 == ~T6_E~0); 56327#L1431-1 assume !(1 == ~T7_E~0); 55884#L1436-1 assume !(1 == ~T8_E~0); 55885#L1441-1 assume !(1 == ~T9_E~0); 56651#L1446-1 assume !(1 == ~T10_E~0); 56652#L1451-1 assume !(1 == ~T11_E~0); 57389#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 57032#L1461-1 assume !(1 == ~T13_E~0); 56572#L1466-1 assume !(1 == ~E_1~0); 56573#L1471-1 assume !(1 == ~E_2~0); 57367#L1476-1 assume !(1 == ~E_3~0); 57368#L1481-1 assume !(1 == ~E_4~0); 57536#L1486-1 assume !(1 == ~E_5~0); 56154#L1491-1 assume !(1 == ~E_6~0); 55822#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55823#L1501-1 assume !(1 == ~E_8~0); 56647#L1506-1 assume !(1 == ~E_9~0); 56648#L1511-1 assume !(1 == ~E_10~0); 56602#L1516-1 assume !(1 == ~E_11~0); 55774#L1521-1 assume !(1 == ~E_12~0); 55775#L1526-1 assume !(1 == ~E_13~0); 55821#L1531-1 assume { :end_inline_reset_delta_events } true; 56352#L1892-2 [2023-11-26 11:58:11,372 INFO L750 eck$LassoCheckResult]: Loop: 56352#L1892-2 assume !false; 57824#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57823#L1233-1 assume !false; 57643#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56919#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56898#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57467#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55863#L1046 assume !(0 != eval_~tmp~0#1); 55865#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59204#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59203#L1258-3 assume !(0 == ~M_E~0); 59202#L1258-5 assume !(0 == ~T1_E~0); 59201#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59200#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59199#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59198#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59197#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59196#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59195#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59194#L1298-3 assume !(0 == ~T9_E~0); 59193#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 59192#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59191#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59190#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 59189#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 59188#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59187#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 59186#L1338-3 assume !(0 == ~E_4~0); 59185#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 59184#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59183#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59182#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 59181#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59180#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59179#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59178#L1378-3 assume !(0 == ~E_12~0); 59177#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59176#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59175#L607-42 assume !(1 == ~m_pc~0); 59173#L607-44 is_master_triggered_~__retres1~0#1 := 0; 59172#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59171#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59170#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59169#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59168#L626-42 assume 1 == ~t1_pc~0; 59166#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59165#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59164#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59163#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 59162#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59161#L645-42 assume !(1 == ~t2_pc~0); 59159#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 59158#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59157#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59156#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59155#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59154#L664-42 assume 1 == ~t3_pc~0; 59152#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 59151#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59150#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59147#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59145#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59143#L683-42 assume !(1 == ~t4_pc~0); 59140#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 59138#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59136#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59134#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59131#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59129#L702-42 assume 1 == ~t5_pc~0; 59126#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59124#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59122#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59120#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 59117#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59115#L721-42 assume 1 == ~t6_pc~0; 59112#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59110#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59108#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59106#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59105#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59104#L740-42 assume 1 == ~t7_pc~0; 59101#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59099#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59097#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59095#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 59093#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59090#L759-42 assume !(1 == ~t8_pc~0); 59088#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 59085#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59083#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56744#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56745#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56836#L778-42 assume 1 == ~t9_pc~0; 56680#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56682#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57110#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57016#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 57017#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57072#L797-42 assume 1 == ~t10_pc~0; 56188#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56189#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57090#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57091#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 57111#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 57112#L816-42 assume 1 == ~t11_pc~0; 55766#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55767#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57653#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56655#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 56366#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56367#L835-42 assume !(1 == ~t12_pc~0); 56691#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 56692#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 56888#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 56889#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57489#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57254#L854-42 assume 1 == ~t13_pc~0; 57255#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 56288#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56454#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 56455#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56568#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56569#L1401-3 assume !(1 == ~M_E~0); 57378#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56117#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55993#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55994#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56618#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56619#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58204#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58197#L1436-3 assume !(1 == ~T8_E~0); 58196#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 58194#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 58192#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58190#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58188#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58186#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 58184#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58182#L1476-3 assume !(1 == ~E_3~0); 58180#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58178#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58176#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 58174#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58173#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58172#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 58171#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58170#L1516-3 assume !(1 == ~E_11~0); 58169#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58168#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58167#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57922#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57910#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57908#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 57907#L1911 assume !(0 == start_simulation_~tmp~3#1); 57905#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57898#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57889#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57886#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 57884#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57882#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57880#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57878#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 56352#L1892-2 [2023-11-26 11:58:11,373 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:11,373 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2023-11-26 11:58:11,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:11,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008853420] [2023-11-26 11:58:11,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:11,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:11,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:11,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:11,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:11,527 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008853420] [2023-11-26 11:58:11,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008853420] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:11,527 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:11,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:11,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289496469] [2023-11-26 11:58:11,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:11,528 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:11,529 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:11,529 INFO L85 PathProgramCache]: Analyzing trace with hash -1745056978, now seen corresponding path program 1 times [2023-11-26 11:58:11,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:11,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822332373] [2023-11-26 11:58:11,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:11,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:11,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:11,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:11,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:11,607 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822332373] [2023-11-26 11:58:11,607 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822332373] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:11,607 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:11,607 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:11,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1492237950] [2023-11-26 11:58:11,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:11,608 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:11,608 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:11,609 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:58:11,609 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:58:11,609 INFO L87 Difference]: Start difference. First operand 3583 states and 5241 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:11,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:11,863 INFO L93 Difference]: Finished difference Result 7018 states and 10255 transitions. [2023-11-26 11:58:11,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7018 states and 10255 transitions. [2023-11-26 11:58:11,906 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6820 [2023-11-26 11:58:11,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7018 states to 7018 states and 10255 transitions. [2023-11-26 11:58:11,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7018 [2023-11-26 11:58:11,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7018 [2023-11-26 11:58:11,947 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7018 states and 10255 transitions. [2023-11-26 11:58:11,958 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:11,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7018 states and 10255 transitions. [2023-11-26 11:58:11,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7018 states and 10255 transitions. [2023-11-26 11:58:12,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7018 to 7018. [2023-11-26 11:58:12,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7018 states, 7018 states have (on average 1.4612425192362497) internal successors, (10255), 7017 states have internal predecessors, (10255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:12,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7018 states to 7018 states and 10255 transitions. [2023-11-26 11:58:12,130 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7018 states and 10255 transitions. [2023-11-26 11:58:12,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:58:12,131 INFO L428 stractBuchiCegarLoop]: Abstraction has 7018 states and 10255 transitions. [2023-11-26 11:58:12,131 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 11:58:12,132 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7018 states and 10255 transitions. [2023-11-26 11:58:12,159 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6820 [2023-11-26 11:58:12,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:12,159 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:12,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:12,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:12,163 INFO L748 eck$LassoCheckResult]: Stem: 66652#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 67562#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67563#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68319#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 67962#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67963#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66875#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66876#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67361#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 67195#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 67196#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66940#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66941#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 67367#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67553#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67720#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 67753#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 66956#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66957#L1258 assume !(0 == ~M_E~0); 68193#L1258-2 assume !(0 == ~T1_E~0); 67279#L1263-1 assume !(0 == ~T2_E~0); 67280#L1268-1 assume !(0 == ~T3_E~0); 67599#L1273-1 assume !(0 == ~T4_E~0); 68171#L1278-1 assume !(0 == ~T5_E~0); 68022#L1283-1 assume !(0 == ~T6_E~0); 68023#L1288-1 assume !(0 == ~T7_E~0); 68277#L1293-1 assume !(0 == ~T8_E~0); 68265#L1298-1 assume !(0 == ~T9_E~0); 68188#L1303-1 assume !(0 == ~T10_E~0); 66752#L1308-1 assume !(0 == ~T11_E~0); 66691#L1313-1 assume !(0 == ~T12_E~0); 66692#L1318-1 assume !(0 == ~T13_E~0); 66697#L1323-1 assume !(0 == ~E_1~0); 66698#L1328-1 assume !(0 == ~E_2~0); 66885#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 67888#L1338-1 assume !(0 == ~E_4~0); 67889#L1343-1 assume !(0 == ~E_5~0); 67997#L1348-1 assume !(0 == ~E_6~0); 68300#L1353-1 assume !(0 == ~E_7~0); 67622#L1358-1 assume !(0 == ~E_8~0); 67623#L1363-1 assume !(0 == ~E_9~0); 67910#L1368-1 assume !(0 == ~E_10~0); 66545#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 66546#L1378-1 assume !(0 == ~E_12~0); 66828#L1383-1 assume !(0 == ~E_13~0); 66829#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67627#L607 assume !(1 == ~m_pc~0); 66902#L607-2 is_master_triggered_~__retres1~0#1 := 0; 66903#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67422#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67423#L1560 assume !(0 != activate_threads_~tmp~1#1); 67533#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66712#L626 assume !(1 == ~t1_pc~0); 66713#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67000#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67001#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67896#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 66620#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66621#L645 assume 1 == ~t2_pc~0; 66729#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66685#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66796#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66797#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 67507#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67508#L664 assume 1 == ~t3_pc~0; 68298#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66480#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66481#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67150#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 67151#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68201#L683 assume !(1 == ~t4_pc~0); 67737#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67691#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66504#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66505#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67846#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67447#L702 assume 1 == ~t5_pc~0; 67448#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67382#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67841#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68191#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 68095#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66517#L721 assume !(1 == ~t6_pc~0); 66497#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66498#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66644#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66781#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 67166#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67785#L740 assume 1 == ~t7_pc~0; 66561#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66397#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66398#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66387#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 66388#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67091#L759 assume !(1 == ~t8_pc~0); 67092#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 67122#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68250#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67973#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 67974#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68276#L778 assume 1 == ~t9_pc~0; 68155#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66544#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66851#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66423#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 66424#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66726#L797 assume !(1 == ~t10_pc~0); 66727#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66861#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68131#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67275#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 67276#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67579#L816 assume 1 == ~t11_pc~0; 66460#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 66461#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 67411#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 67172#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 67173#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67719#L835 assume 1 == ~t12_pc~0; 67594#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66608#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66448#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66449#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 67331#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 67332#L854 assume !(1 == ~t13_pc~0); 66942#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 66943#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66995#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66642#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66643#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68088#L1401 assume !(1 == ~M_E~0); 67159#L1401-2 assume !(1 == ~T1_E~0); 67160#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67774#L1411-1 assume !(1 == ~T3_E~0); 67775#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67421#L1421-1 assume !(1 == ~T5_E~0); 66938#L1426-1 assume !(1 == ~T6_E~0); 66939#L1431-1 assume !(1 == ~T7_E~0); 66495#L1436-1 assume !(1 == ~T8_E~0); 66496#L1441-1 assume !(1 == ~T9_E~0); 67268#L1446-1 assume !(1 == ~T10_E~0); 67269#L1451-1 assume !(1 == ~T11_E~0); 67993#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67646#L1461-1 assume !(1 == ~T13_E~0); 67188#L1466-1 assume !(1 == ~E_1~0); 67189#L1471-1 assume !(1 == ~E_2~0); 67971#L1476-1 assume !(1 == ~E_3~0); 67972#L1481-1 assume !(1 == ~E_4~0); 68137#L1486-1 assume !(1 == ~E_5~0); 66765#L1491-1 assume !(1 == ~E_6~0); 66433#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 66434#L1501-1 assume !(1 == ~E_8~0); 67264#L1506-1 assume !(1 == ~E_9~0); 67265#L1511-1 assume !(1 == ~E_10~0); 67218#L1516-1 assume !(1 == ~E_11~0); 66385#L1521-1 assume !(1 == ~E_12~0); 66386#L1526-1 assume !(1 == ~E_13~0); 66432#L1531-1 assume { :end_inline_reset_delta_events } true; 68387#L1892-2 [2023-11-26 11:58:12,164 INFO L750 eck$LassoCheckResult]: Loop: 68387#L1892-2 assume !false; 68382#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68381#L1233-1 assume !false; 68380#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68365#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68350#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68348#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 68345#L1046 assume !(0 != eval_~tmp~0#1); 68342#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68340#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68338#L1258-3 assume !(0 == ~M_E~0); 68335#L1258-5 assume !(0 == ~T1_E~0); 68334#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68285#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68286#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68291#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68292#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 66866#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 66867#L1293-3 assume !(0 == ~T8_E~0); 68037#L1298-3 assume !(0 == ~T9_E~0); 68038#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 68209#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68036#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 67518#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 66634#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66635#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68129#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66776#L1338-3 assume !(0 == ~E_4~0); 66777#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67948#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68135#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 68136#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67462#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 67002#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 67003#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67805#L1378-3 assume !(0 == ~E_12~0); 67806#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 67990#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67991#L607-42 assume !(1 == ~m_pc~0); 67605#L607-44 is_master_triggered_~__retres1~0#1 := 0; 67312#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67143#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67022#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67023#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67580#L626-42 assume 1 == ~t1_pc~0; 67114#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 67115#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68234#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68007#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66667#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66668#L645-42 assume !(1 == ~t2_pc~0); 67925#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 67926#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67460#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66886#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66405#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66406#L664-42 assume 1 == ~t3_pc~0; 67224#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66924#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67865#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67751#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67752#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67917#L683-42 assume !(1 == ~t4_pc~0); 67632#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 67633#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67758#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67921#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68198#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68033#L702-42 assume !(1 == ~t5_pc~0); 67104#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 67105#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67416#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67528#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 66417#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66418#L721-42 assume !(1 == ~t6_pc~0); 66557#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 66577#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66756#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66757#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 67245#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67078#L740-42 assume !(1 == ~t7_pc~0); 67079#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 71268#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71262#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 71256#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 71249#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 71242#L759-42 assume 1 == ~t8_pc~0; 71233#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 71227#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 71221#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 71215#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 71208#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 71201#L778-42 assume !(1 == ~t9_pc~0); 71191#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 71185#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 71179#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71173#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 71166#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 71159#L797-42 assume 1 == ~t10_pc~0; 71149#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 71144#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 71139#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 71134#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 71128#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 71122#L816-42 assume 1 == ~t11_pc~0; 71113#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 71106#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 71100#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 71094#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 71087#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 71080#L835-42 assume !(1 == ~t12_pc~0); 71072#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 71064#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 71058#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 71052#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 71046#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 71041#L854-42 assume !(1 == ~t13_pc~0); 71031#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 71024#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 71018#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 71012#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 71005#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70999#L1401-3 assume !(1 == ~M_E~0); 69218#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70984#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66725#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70973#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70966#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70960#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70952#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70944#L1436-3 assume !(1 == ~T8_E~0); 66917#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70933#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 70926#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 70920#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70912#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 70904#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70898#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70892#L1476-3 assume !(1 == ~E_3~0); 70885#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70879#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70871#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70863#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70857#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70852#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70847#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 70842#L1516-3 assume !(1 == ~E_11~0); 70835#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 70828#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 70823#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69272#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69261#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69260#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 69259#L1911 assume !(0 == start_simulation_~tmp~3#1); 68787#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68530#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68421#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68417#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 68415#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68413#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68410#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68397#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 68387#L1892-2 [2023-11-26 11:58:12,165 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:12,165 INFO L85 PathProgramCache]: Analyzing trace with hash -1259435077, now seen corresponding path program 1 times [2023-11-26 11:58:12,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:12,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350256160] [2023-11-26 11:58:12,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:12,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:12,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:12,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:12,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:12,262 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1350256160] [2023-11-26 11:58:12,262 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1350256160] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:12,262 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:12,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:12,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911817527] [2023-11-26 11:58:12,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:12,264 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:12,264 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:12,264 INFO L85 PathProgramCache]: Analyzing trace with hash 1898192744, now seen corresponding path program 1 times [2023-11-26 11:58:12,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:12,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397103098] [2023-11-26 11:58:12,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:12,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:12,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:12,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:12,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:12,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1397103098] [2023-11-26 11:58:12,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1397103098] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:12,383 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:12,383 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:12,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337261861] [2023-11-26 11:58:12,383 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:12,384 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:12,384 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:12,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:58:12,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:58:12,385 INFO L87 Difference]: Start difference. First operand 7018 states and 10255 transitions. cyclomatic complexity: 3239 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:12,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:12,764 INFO L93 Difference]: Finished difference Result 13472 states and 19680 transitions. [2023-11-26 11:58:12,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13472 states and 19680 transitions. [2023-11-26 11:58:12,850 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13240 [2023-11-26 11:58:12,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13472 states to 13472 states and 19680 transitions. [2023-11-26 11:58:12,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13472 [2023-11-26 11:58:12,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13472 [2023-11-26 11:58:12,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13472 states and 19680 transitions. [2023-11-26 11:58:12,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:12,953 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13472 states and 19680 transitions. [2023-11-26 11:58:12,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13472 states and 19680 transitions. [2023-11-26 11:58:13,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13472 to 13468. [2023-11-26 11:58:13,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13468 states, 13468 states have (on average 1.4609444609444608) internal successors, (19676), 13467 states have internal predecessors, (19676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:13,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13468 states to 13468 states and 19676 transitions. [2023-11-26 11:58:13,288 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13468 states and 19676 transitions. [2023-11-26 11:58:13,289 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:58:13,290 INFO L428 stractBuchiCegarLoop]: Abstraction has 13468 states and 19676 transitions. [2023-11-26 11:58:13,291 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 11:58:13,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13468 states and 19676 transitions. [2023-11-26 11:58:13,340 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13240 [2023-11-26 11:58:13,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:13,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:13,345 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:13,345 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:13,346 INFO L748 eck$LassoCheckResult]: Stem: 87153#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 87154#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 88076#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88077#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88921#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 88499#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88500#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87377#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87378#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87863#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87697#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87698#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 87443#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 87444#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87871#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 88067#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 88238#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 88274#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 87459#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87460#L1258 assume !(0 == ~M_E~0); 88762#L1258-2 assume !(0 == ~T1_E~0); 87781#L1263-1 assume !(0 == ~T2_E~0); 87782#L1268-1 assume !(0 == ~T3_E~0); 88114#L1273-1 assume !(0 == ~T4_E~0); 88735#L1278-1 assume !(0 == ~T5_E~0); 88572#L1283-1 assume !(0 == ~T6_E~0); 88573#L1288-1 assume !(0 == ~T7_E~0); 88853#L1293-1 assume !(0 == ~T8_E~0); 88839#L1298-1 assume !(0 == ~T9_E~0); 88755#L1303-1 assume !(0 == ~T10_E~0); 87253#L1308-1 assume !(0 == ~T11_E~0); 87192#L1313-1 assume !(0 == ~T12_E~0); 87193#L1318-1 assume !(0 == ~T13_E~0); 87198#L1323-1 assume !(0 == ~E_1~0); 87199#L1328-1 assume !(0 == ~E_2~0); 87387#L1333-1 assume !(0 == ~E_3~0); 88420#L1338-1 assume !(0 == ~E_4~0); 88421#L1343-1 assume !(0 == ~E_5~0); 88541#L1348-1 assume !(0 == ~E_6~0); 88885#L1353-1 assume !(0 == ~E_7~0); 88137#L1358-1 assume !(0 == ~E_8~0); 88138#L1363-1 assume !(0 == ~E_9~0); 88442#L1368-1 assume !(0 == ~E_10~0); 87046#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 87047#L1378-1 assume !(0 == ~E_12~0); 87330#L1383-1 assume !(0 == ~E_13~0); 87331#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88141#L607 assume !(1 == ~m_pc~0); 87404#L607-2 is_master_triggered_~__retres1~0#1 := 0; 87405#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87928#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87929#L1560 assume !(0 != activate_threads_~tmp~1#1); 88043#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87213#L626 assume !(1 == ~t1_pc~0); 87214#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 87500#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87501#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88428#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 87121#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87122#L645 assume 1 == ~t2_pc~0; 87230#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 87186#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87298#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87299#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 88016#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88017#L664 assume 1 == ~t3_pc~0; 88880#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86980#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86981#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87652#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 87653#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88770#L683 assume !(1 == ~t4_pc~0); 88258#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88206#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87005#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87006#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88376#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87952#L702 assume 1 == ~t5_pc~0; 87953#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87887#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88371#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88759#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 88646#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87016#L721 assume !(1 == ~t6_pc~0); 86998#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86999#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87145#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87283#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 87668#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88311#L740 assume 1 == ~t7_pc~0; 87062#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86897#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86898#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86887#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 86888#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87590#L759 assume !(1 == ~t8_pc~0); 87591#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 87624#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88826#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88511#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 88512#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88852#L778 assume 1 == ~t9_pc~0; 88715#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87045#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87353#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86923#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 86924#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87225#L797 assume !(1 == ~t10_pc~0); 87226#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 87363#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88690#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87777#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 87778#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 88093#L816 assume 1 == ~t11_pc~0; 86958#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86959#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87917#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87674#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 87675#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 88237#L835 assume 1 == ~t12_pc~0; 88109#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 87109#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86948#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86949#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 87834#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87835#L854 assume !(1 == ~t13_pc~0); 87445#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 87446#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 87495#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 87143#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 87144#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88641#L1401 assume !(1 == ~M_E~0); 87661#L1401-2 assume !(1 == ~T1_E~0); 87662#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88649#L1411-1 assume !(1 == ~T3_E~0); 97136#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97134#L1421-1 assume !(1 == ~T5_E~0); 97132#L1426-1 assume !(1 == ~T6_E~0); 97130#L1431-1 assume !(1 == ~T7_E~0); 97127#L1436-1 assume !(1 == ~T8_E~0); 97125#L1441-1 assume !(1 == ~T9_E~0); 97123#L1446-1 assume !(1 == ~T10_E~0); 97121#L1451-1 assume !(1 == ~T11_E~0); 97119#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 97117#L1461-1 assume !(1 == ~T13_E~0); 97114#L1466-1 assume !(1 == ~E_1~0); 97112#L1471-1 assume !(1 == ~E_2~0); 97110#L1476-1 assume !(1 == ~E_3~0); 88509#L1481-1 assume !(1 == ~E_4~0); 97107#L1486-1 assume !(1 == ~E_5~0); 97105#L1491-1 assume !(1 == ~E_6~0); 97102#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 97100#L1501-1 assume !(1 == ~E_8~0); 97098#L1506-1 assume !(1 == ~E_9~0); 97096#L1511-1 assume !(1 == ~E_10~0); 97094#L1516-1 assume !(1 == ~E_11~0); 97092#L1521-1 assume !(1 == ~E_12~0); 97089#L1526-1 assume !(1 == ~E_13~0); 97087#L1531-1 assume { :end_inline_reset_delta_events } true; 97085#L1892-2 [2023-11-26 11:58:13,346 INFO L750 eck$LassoCheckResult]: Loop: 97085#L1892-2 assume !false; 96022#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96021#L1233-1 assume !false; 96020#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 96006#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96005#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 96004#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 96002#L1046 assume !(0 != eval_~tmp~0#1); 96001#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87512#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87513#L1258-3 assume !(0 == ~M_E~0); 88879#L1258-5 assume !(0 == ~T1_E~0); 87133#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87134#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 95947#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 95946#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 95945#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 95944#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 95943#L1293-3 assume !(0 == ~T8_E~0); 95940#L1298-3 assume !(0 == ~T9_E~0); 95937#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 95934#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 95932#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 95930#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 95927#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 95924#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 95919#L1333-3 assume !(0 == ~E_3~0); 95915#L1338-3 assume !(0 == ~E_4~0); 95912#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 95910#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 95909#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 95908#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 95907#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 95906#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 95901#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 95898#L1378-3 assume !(0 == ~E_12~0); 95894#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 95891#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95887#L607-42 assume !(1 == ~m_pc~0); 95876#L607-44 is_master_triggered_~__retres1~0#1 := 0; 95873#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95871#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95868#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 95861#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88627#L626-42 assume !(1 == ~t1_pc~0); 88629#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 95850#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88918#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88919#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 87168#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87169#L645-42 assume 1 == ~t2_pc~0; 88769#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 88458#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88901#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87388#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86905#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86906#L664-42 assume !(1 == ~t3_pc~0); 87426#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 87427#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88395#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88396#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 92665#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92611#L683-42 assume 1 == ~t4_pc~0; 92609#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 92606#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92604#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 92570#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 92568#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92520#L702-42 assume !(1 == ~t5_pc~0); 92517#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 92514#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 92512#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 92510#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 92508#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 92506#L721-42 assume 1 == ~t6_pc~0; 92503#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 92501#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 92500#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 92444#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 92441#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 92439#L740-42 assume !(1 == ~t7_pc~0); 92437#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 92434#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 92432#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 92431#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 92428#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 92427#L759-42 assume 1 == ~t8_pc~0; 92425#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 92423#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 92421#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 92368#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 92278#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 92277#L778-42 assume !(1 == ~t9_pc~0); 92275#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 92272#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 92192#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 92190#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 92188#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 92186#L797-42 assume 1 == ~t10_pc~0; 92183#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 92115#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 92038#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 92036#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 92034#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 92032#L816-42 assume !(1 == ~t11_pc~0); 92029#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 92028#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 92027#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 91959#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 91957#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 91955#L835-42 assume !(1 == ~t12_pc~0); 91953#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 91951#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 91950#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 91948#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 91946#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 91941#L854-42 assume !(1 == ~t13_pc~0); 91933#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 91923#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 91917#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 91911#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 91905#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91898#L1401-3 assume !(1 == ~M_E~0); 91892#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 91889#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87229#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 91884#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 91881#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 91878#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 91875#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 91872#L1436-3 assume !(1 == ~T8_E~0); 87420#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 91867#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 91865#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 91863#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 91861#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 91859#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 91857#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 91855#L1476-3 assume !(1 == ~E_3~0); 91853#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 91851#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 91849#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 91847#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 91845#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 91843#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 91841#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 91839#L1516-3 assume !(1 == ~E_11~0); 91837#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 91835#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 91833#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 91828#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 91817#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 91816#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 91815#L1911 assume !(0 == start_simulation_~tmp~3#1); 88687#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 88352#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 87345#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86927#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 86928#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 87051#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 87823#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 88709#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 97085#L1892-2 [2023-11-26 11:58:13,347 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:13,348 INFO L85 PathProgramCache]: Analyzing trace with hash -312397191, now seen corresponding path program 1 times [2023-11-26 11:58:13,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:13,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719620] [2023-11-26 11:58:13,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:13,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:13,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:13,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:13,463 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:13,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1719620] [2023-11-26 11:58:13,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1719620] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:13,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:13,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:13,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1904322646] [2023-11-26 11:58:13,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:13,465 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:13,465 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:13,465 INFO L85 PathProgramCache]: Analyzing trace with hash -583261466, now seen corresponding path program 1 times [2023-11-26 11:58:13,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:13,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873879999] [2023-11-26 11:58:13,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:13,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:13,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:13,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:13,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:13,606 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873879999] [2023-11-26 11:58:13,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873879999] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:13,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:13,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:13,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [21990347] [2023-11-26 11:58:13,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:13,607 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:13,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:13,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:58:13,608 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:58:13,608 INFO L87 Difference]: Start difference. First operand 13468 states and 19676 transitions. cyclomatic complexity: 6212 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:13,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:13,985 INFO L93 Difference]: Finished difference Result 25936 states and 37873 transitions. [2023-11-26 11:58:13,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25936 states and 37873 transitions. [2023-11-26 11:58:14,117 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25680 [2023-11-26 11:58:14,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25936 states to 25936 states and 37873 transitions. [2023-11-26 11:58:14,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25936 [2023-11-26 11:58:14,269 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25936 [2023-11-26 11:58:14,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25936 states and 37873 transitions. [2023-11-26 11:58:14,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:14,297 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25936 states and 37873 transitions. [2023-11-26 11:58:14,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25936 states and 37873 transitions. [2023-11-26 11:58:14,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25936 to 25928. [2023-11-26 11:58:15,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25928 states, 25928 states have (on average 1.4603903116322123) internal successors, (37865), 25927 states have internal predecessors, (37865), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:15,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25928 states to 25928 states and 37865 transitions. [2023-11-26 11:58:15,117 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25928 states and 37865 transitions. [2023-11-26 11:58:15,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:58:15,118 INFO L428 stractBuchiCegarLoop]: Abstraction has 25928 states and 37865 transitions. [2023-11-26 11:58:15,119 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 11:58:15,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25928 states and 37865 transitions. [2023-11-26 11:58:15,283 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25680 [2023-11-26 11:58:15,283 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:15,283 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:15,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:15,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:15,288 INFO L748 eck$LassoCheckResult]: Stem: 126568#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 126569#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 127510#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 127511#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 128446#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 127958#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127959#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126794#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126795#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127291#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 127118#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 127119#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 126858#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 126859#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 127300#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 127501#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 127679#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 127714#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 126874#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126875#L1258 assume !(0 == ~M_E~0); 128248#L1258-2 assume !(0 == ~T1_E~0); 127208#L1263-1 assume !(0 == ~T2_E~0); 127209#L1268-1 assume !(0 == ~T3_E~0); 127549#L1273-1 assume !(0 == ~T4_E~0); 128220#L1278-1 assume !(0 == ~T5_E~0); 128031#L1283-1 assume !(0 == ~T6_E~0); 128032#L1288-1 assume !(0 == ~T7_E~0); 128366#L1293-1 assume !(0 == ~T8_E~0); 128348#L1298-1 assume !(0 == ~T9_E~0); 128240#L1303-1 assume !(0 == ~T10_E~0); 126669#L1308-1 assume !(0 == ~T11_E~0); 126608#L1313-1 assume !(0 == ~T12_E~0); 126609#L1318-1 assume !(0 == ~T13_E~0); 126614#L1323-1 assume !(0 == ~E_1~0); 126615#L1328-1 assume !(0 == ~E_2~0); 126804#L1333-1 assume !(0 == ~E_3~0); 127869#L1338-1 assume !(0 == ~E_4~0); 127870#L1343-1 assume !(0 == ~E_5~0); 128003#L1348-1 assume !(0 == ~E_6~0); 128412#L1353-1 assume !(0 == ~E_7~0); 127573#L1358-1 assume !(0 == ~E_8~0); 127574#L1363-1 assume !(0 == ~E_9~0); 127895#L1368-1 assume !(0 == ~E_10~0); 126460#L1373-1 assume !(0 == ~E_11~0); 126461#L1378-1 assume !(0 == ~E_12~0); 126747#L1383-1 assume !(0 == ~E_13~0); 126748#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 127577#L607 assume !(1 == ~m_pc~0); 126821#L607-2 is_master_triggered_~__retres1~0#1 := 0; 126822#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 127361#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 127362#L1560 assume !(0 != activate_threads_~tmp~1#1); 127478#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126629#L626 assume !(1 == ~t1_pc~0); 126630#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 126917#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126918#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 127877#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 126536#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126537#L645 assume 1 == ~t2_pc~0; 126646#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 126602#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126714#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126715#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 127451#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127452#L664 assume 1 == ~t3_pc~0; 128400#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 126395#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126396#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 127072#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 127073#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128261#L683 assume !(1 == ~t4_pc~0); 127697#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 127649#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126419#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126420#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 127821#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 127385#L702 assume 1 == ~t5_pc~0; 127386#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 127316#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127814#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 128243#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 128115#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 126430#L721 assume !(1 == ~t6_pc~0); 126412#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 126413#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 126560#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 126699#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 127088#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 127749#L740 assume 1 == ~t7_pc~0; 126476#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 126311#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 126312#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 126301#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 126302#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 127011#L759 assume !(1 == ~t8_pc~0); 127012#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 127043#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 128328#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 127970#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 127971#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 128365#L778 assume 1 == ~t9_pc~0; 128201#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 126459#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 126770#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 126337#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 126338#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 126641#L797 assume !(1 == ~t10_pc~0); 126642#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 126780#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 128170#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 127204#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 127205#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 127527#L816 assume 1 == ~t11_pc~0; 126373#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 126374#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 127350#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 127094#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 127095#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 127678#L835 assume 1 == ~t12_pc~0; 127544#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 126524#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 126363#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 126364#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 127263#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 127264#L854 assume !(1 == ~t13_pc~0); 126860#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 126861#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 126912#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 126558#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 126559#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128111#L1401 assume !(1 == ~M_E~0); 127081#L1401-2 assume !(1 == ~T1_E~0); 127082#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 127738#L1411-1 assume !(1 == ~T3_E~0); 127739#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 128388#L1421-1 assume !(1 == ~T5_E~0); 132453#L1426-1 assume !(1 == ~T6_E~0); 132451#L1431-1 assume !(1 == ~T7_E~0); 126410#L1436-1 assume !(1 == ~T8_E~0); 126411#L1441-1 assume !(1 == ~T9_E~0); 132452#L1446-1 assume !(1 == ~T10_E~0); 132450#L1451-1 assume !(1 == ~T11_E~0); 132449#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 132448#L1461-1 assume !(1 == ~T13_E~0); 127111#L1466-1 assume !(1 == ~E_1~0); 127112#L1471-1 assume !(1 == ~E_2~0); 130218#L1476-1 assume !(1 == ~E_3~0); 130216#L1481-1 assume !(1 == ~E_4~0); 130189#L1486-1 assume !(1 == ~E_5~0); 130163#L1491-1 assume !(1 == ~E_6~0); 130161#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 130132#L1501-1 assume !(1 == ~E_8~0); 130130#L1506-1 assume !(1 == ~E_9~0); 130097#L1511-1 assume !(1 == ~E_10~0); 130082#L1516-1 assume !(1 == ~E_11~0); 130070#L1521-1 assume !(1 == ~E_12~0); 130061#L1526-1 assume !(1 == ~E_13~0); 130053#L1531-1 assume { :end_inline_reset_delta_events } true; 130046#L1892-2 [2023-11-26 11:58:15,289 INFO L750 eck$LassoCheckResult]: Loop: 130046#L1892-2 assume !false; 130042#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 130041#L1233-1 assume !false; 130040#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 130026#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 130011#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 130009#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 130006#L1046 assume !(0 != eval_~tmp~0#1); 130003#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 130001#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 129999#L1258-3 assume !(0 == ~M_E~0); 129995#L1258-5 assume !(0 == ~T1_E~0); 129996#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 132880#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132878#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 132875#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 132873#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 132871#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 132869#L1293-3 assume !(0 == ~T8_E~0); 132867#L1298-3 assume !(0 == ~T9_E~0); 132865#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 132862#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 132860#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 132858#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 132856#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 132854#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 132852#L1333-3 assume !(0 == ~E_3~0); 132849#L1338-3 assume !(0 == ~E_4~0); 132847#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 132845#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 132843#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 132841#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 132839#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 132836#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 132834#L1373-3 assume !(0 == ~E_11~0); 132833#L1378-3 assume !(0 == ~E_12~0); 132832#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 132831#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132828#L607-42 assume !(1 == ~m_pc~0); 132825#L607-44 is_master_triggered_~__retres1~0#1 := 0; 132823#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132821#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 132819#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 132817#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132815#L626-42 assume 1 == ~t1_pc~0; 132811#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 132809#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132807#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132805#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 132803#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132801#L645-42 assume !(1 == ~t2_pc~0); 132062#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 132060#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132058#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 132055#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 132053#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132051#L664-42 assume 1 == ~t3_pc~0; 132048#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 132046#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132044#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132041#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 132039#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132037#L683-42 assume !(1 == ~t4_pc~0); 132034#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 132032#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132030#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132027#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132025#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132023#L702-42 assume 1 == ~t5_pc~0; 132020#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132018#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132017#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 132016#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 132015#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132014#L721-42 assume 1 == ~t6_pc~0; 132012#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 132011#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132010#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 132009#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 132008#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132007#L740-42 assume !(1 == ~t7_pc~0); 132006#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 132003#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 132001#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131999#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 131997#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 131995#L759-42 assume 1 == ~t8_pc~0; 131991#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 131989#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131987#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 131985#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 131983#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 131981#L778-42 assume 1 == ~t9_pc~0; 131978#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 131975#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 131973#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 131971#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 131969#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 131846#L797-42 assume 1 == ~t10_pc~0; 131842#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 131840#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 131838#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 131836#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 131834#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 131832#L816-42 assume !(1 == ~t11_pc~0); 131826#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 131824#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 131822#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 131820#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 131818#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 131815#L835-42 assume 1 == ~t12_pc~0; 131812#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 131810#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 131748#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 131745#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 131743#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 131740#L854-42 assume 1 == ~t13_pc~0; 131738#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 131735#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 131733#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 131731#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 131729#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131724#L1401-3 assume !(1 == ~M_E~0); 128900#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 131717#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 126645#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 131708#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 131704#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131699#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 131695#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 131691#L1436-3 assume !(1 == ~T8_E~0); 131073#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 131403#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 131401#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 131399#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 131397#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 131395#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 131393#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 131390#L1476-3 assume !(1 == ~E_3~0); 131304#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 131387#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 131385#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 131383#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 131382#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 131380#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 131378#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 131376#L1516-3 assume !(1 == ~E_11~0); 127756#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 131374#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 131373#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 131014#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 130249#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 130213#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 130181#L1911 assume !(0 == start_simulation_~tmp~3#1); 130148#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 130121#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 130112#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 130095#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 130079#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 130069#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 130060#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 130052#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 130046#L1892-2 [2023-11-26 11:58:15,290 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:15,290 INFO L85 PathProgramCache]: Analyzing trace with hash -645040329, now seen corresponding path program 1 times [2023-11-26 11:58:15,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:15,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485998956] [2023-11-26 11:58:15,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:15,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:15,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:15,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:15,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:15,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485998956] [2023-11-26 11:58:15,383 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485998956] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:15,383 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:15,383 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:58:15,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942640081] [2023-11-26 11:58:15,383 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:15,384 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:15,384 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:15,384 INFO L85 PathProgramCache]: Analyzing trace with hash 217289192, now seen corresponding path program 1 times [2023-11-26 11:58:15,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:15,385 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994297174] [2023-11-26 11:58:15,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:15,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:15,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:15,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:15,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:15,469 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994297174] [2023-11-26 11:58:15,469 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994297174] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:15,469 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:15,469 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:15,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319442675] [2023-11-26 11:58:15,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:15,471 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:15,471 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:15,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:15,471 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:15,472 INFO L87 Difference]: Start difference. First operand 25928 states and 37865 transitions. cyclomatic complexity: 11945 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:15,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:15,995 INFO L93 Difference]: Finished difference Result 50583 states and 73532 transitions. [2023-11-26 11:58:15,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50583 states and 73532 transitions. [2023-11-26 11:58:16,374 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 50304 [2023-11-26 11:58:16,600 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50583 states to 50583 states and 73532 transitions. [2023-11-26 11:58:16,600 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50583 [2023-11-26 11:58:16,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50583 [2023-11-26 11:58:16,626 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50583 states and 73532 transitions. [2023-11-26 11:58:16,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:16,664 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50583 states and 73532 transitions. [2023-11-26 11:58:16,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50583 states and 73532 transitions. [2023-11-26 11:58:17,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50583 to 50551. [2023-11-26 11:58:17,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50551 states, 50551 states have (on average 1.4539771715693062) internal successors, (73500), 50550 states have internal predecessors, (73500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:17,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50551 states to 50551 states and 73500 transitions. [2023-11-26 11:58:17,943 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50551 states and 73500 transitions. [2023-11-26 11:58:17,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:17,944 INFO L428 stractBuchiCegarLoop]: Abstraction has 50551 states and 73500 transitions. [2023-11-26 11:58:17,945 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 11:58:17,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50551 states and 73500 transitions. [2023-11-26 11:58:18,220 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 50272 [2023-11-26 11:58:18,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:18,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:18,224 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:18,224 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:18,224 INFO L748 eck$LassoCheckResult]: Stem: 203087#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 203088#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 204028#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 204029#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 205008#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 204495#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 204496#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 203311#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 203312#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 203804#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 203632#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 203633#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 203378#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 203379#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 203812#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 204018#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 204200#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 204237#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 203394#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 203395#L1258 assume !(0 == ~M_E~0); 204792#L1258-2 assume !(0 == ~T1_E~0); 203720#L1263-1 assume !(0 == ~T2_E~0); 203721#L1268-1 assume !(0 == ~T3_E~0); 204067#L1273-1 assume !(0 == ~T4_E~0); 204762#L1278-1 assume !(0 == ~T5_E~0); 204573#L1283-1 assume !(0 == ~T6_E~0); 204574#L1288-1 assume !(0 == ~T7_E~0); 204916#L1293-1 assume !(0 == ~T8_E~0); 204897#L1298-1 assume !(0 == ~T9_E~0); 204784#L1303-1 assume !(0 == ~T10_E~0); 203187#L1308-1 assume !(0 == ~T11_E~0); 203126#L1313-1 assume !(0 == ~T12_E~0); 203127#L1318-1 assume !(0 == ~T13_E~0); 203132#L1323-1 assume !(0 == ~E_1~0); 203133#L1328-1 assume !(0 == ~E_2~0); 203321#L1333-1 assume !(0 == ~E_3~0); 204398#L1338-1 assume !(0 == ~E_4~0); 204399#L1343-1 assume !(0 == ~E_5~0); 204539#L1348-1 assume !(0 == ~E_6~0); 204961#L1353-1 assume !(0 == ~E_7~0); 204090#L1358-1 assume !(0 == ~E_8~0); 204091#L1363-1 assume !(0 == ~E_9~0); 204424#L1368-1 assume !(0 == ~E_10~0); 202979#L1373-1 assume !(0 == ~E_11~0); 202980#L1378-1 assume !(0 == ~E_12~0); 203264#L1383-1 assume !(0 == ~E_13~0); 203265#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 204094#L607 assume !(1 == ~m_pc~0); 203339#L607-2 is_master_triggered_~__retres1~0#1 := 0; 203340#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 203874#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 203875#L1560 assume !(0 != activate_threads_~tmp~1#1); 203994#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 203147#L626 assume !(1 == ~t1_pc~0); 203148#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 203435#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 203436#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 204409#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 203055#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 203056#L645 assume !(1 == ~t2_pc~0); 203119#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 203120#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 203231#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 203232#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 203966#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203967#L664 assume 1 == ~t3_pc~0; 204954#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 202912#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 202913#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 203588#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 203589#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 204808#L683 assume !(1 == ~t4_pc~0); 204220#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 204169#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 202937#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 202938#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 204348#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 203900#L702 assume 1 == ~t5_pc~0; 203901#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 203829#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 204343#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 204787#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 204659#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 202948#L721 assume !(1 == ~t6_pc~0); 202930#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 202931#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 203079#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 203216#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 203604#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 204278#L740 assume 1 == ~t7_pc~0; 202996#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 202829#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 202830#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 202819#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 202820#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 203528#L759 assume !(1 == ~t8_pc~0); 203529#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 203560#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 204879#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 204505#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 204506#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 204915#L778 assume 1 == ~t9_pc~0; 204739#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 202978#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 203287#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 202855#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 202856#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 203159#L797 assume !(1 == ~t10_pc~0); 203160#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 203297#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 204711#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 203716#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 203717#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 204045#L816 assume 1 == ~t11_pc~0; 202890#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 202891#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 203863#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 203610#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 203611#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 204199#L835 assume 1 == ~t12_pc~0; 204061#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 203043#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 202880#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 202881#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 203775#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 203776#L854 assume !(1 == ~t13_pc~0); 203380#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 203381#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 203430#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 203077#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 203078#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 204651#L1401 assume !(1 == ~M_E~0); 203597#L1401-2 assume !(1 == ~T1_E~0); 203598#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 204662#L1411-1 assume !(1 == ~T3_E~0); 232979#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 232978#L1421-1 assume !(1 == ~T5_E~0); 232977#L1426-1 assume !(1 == ~T6_E~0); 232976#L1431-1 assume !(1 == ~T7_E~0); 232961#L1436-1 assume !(1 == ~T8_E~0); 232959#L1441-1 assume !(1 == ~T9_E~0); 232957#L1446-1 assume !(1 == ~T10_E~0); 232955#L1451-1 assume !(1 == ~T11_E~0); 232953#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 232951#L1461-1 assume !(1 == ~T13_E~0); 232949#L1466-1 assume !(1 == ~E_1~0); 205016#L1471-1 assume !(1 == ~E_2~0); 204503#L1476-1 assume !(1 == ~E_3~0); 204504#L1481-1 assume !(1 == ~E_4~0); 238386#L1486-1 assume !(1 == ~E_5~0); 238384#L1491-1 assume !(1 == ~E_6~0); 238382#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 238380#L1501-1 assume !(1 == ~E_8~0); 238377#L1506-1 assume !(1 == ~E_9~0); 238375#L1511-1 assume !(1 == ~E_10~0); 238373#L1516-1 assume !(1 == ~E_11~0); 225496#L1521-1 assume !(1 == ~E_12~0); 214543#L1526-1 assume !(1 == ~E_13~0); 213826#L1531-1 assume { :end_inline_reset_delta_events } true; 213177#L1892-2 [2023-11-26 11:58:18,225 INFO L750 eck$LassoCheckResult]: Loop: 213177#L1892-2 assume !false; 212514#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 212512#L1233-1 assume !false; 212511#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 212205#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 212204#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 212203#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 212201#L1046 assume !(0 != eval_~tmp~0#1); 212202#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 241215#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 241213#L1258-3 assume !(0 == ~M_E~0); 241211#L1258-5 assume !(0 == ~T1_E~0); 241209#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 241207#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 241205#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 241203#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 241201#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 241199#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 241197#L1293-3 assume !(0 == ~T8_E~0); 241195#L1298-3 assume !(0 == ~T9_E~0); 241193#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 241191#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 241189#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 241187#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 241185#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 241183#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 241181#L1333-3 assume !(0 == ~E_3~0); 241179#L1338-3 assume !(0 == ~E_4~0); 241177#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 241175#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 241173#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 241171#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 241169#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 241167#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 241165#L1373-3 assume !(0 == ~E_11~0); 241163#L1378-3 assume !(0 == ~E_12~0); 241161#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 241159#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 241157#L607-42 assume !(1 == ~m_pc~0); 241153#L607-44 is_master_triggered_~__retres1~0#1 := 0; 241151#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 241149#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 241147#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 241145#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 241143#L626-42 assume !(1 == ~t1_pc~0); 241141#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 241137#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 241135#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 241133#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 241131#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 241129#L645-42 assume !(1 == ~t2_pc~0); 241127#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 241125#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 241123#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 241121#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 241119#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 241117#L664-42 assume !(1 == ~t3_pc~0); 241115#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 241111#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 241109#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 241107#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 241105#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 241103#L683-42 assume 1 == ~t4_pc~0; 241101#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 241097#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 241095#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 241093#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 241091#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 241089#L702-42 assume !(1 == ~t5_pc~0); 241087#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 241083#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 241081#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 241079#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 241077#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 241075#L721-42 assume !(1 == ~t6_pc~0); 241073#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 241069#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 241067#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 241065#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 241063#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 241061#L740-42 assume !(1 == ~t7_pc~0); 241059#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 241055#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 241053#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 241051#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 241049#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 241047#L759-42 assume !(1 == ~t8_pc~0); 241045#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 241041#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 241039#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 241037#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 241035#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 241033#L778-42 assume 1 == ~t9_pc~0; 241031#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 241027#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 241025#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 241023#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 241021#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 241019#L797-42 assume !(1 == ~t10_pc~0); 241017#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 241013#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 241011#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 241009#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 241007#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 241005#L816-42 assume 1 == ~t11_pc~0; 241003#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 240999#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 240997#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 240995#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 240993#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 240991#L835-42 assume !(1 == ~t12_pc~0); 240989#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 240985#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 240983#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 240981#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 240979#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 240977#L854-42 assume 1 == ~t13_pc~0; 240975#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 240971#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 240969#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 240967#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 240965#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 240963#L1401-3 assume !(1 == ~M_E~0); 240543#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 240961#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 209557#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 240958#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 240956#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 240954#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 240952#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 240950#L1436-3 assume !(1 == ~T8_E~0); 203355#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 240948#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 240946#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 240944#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 240942#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 240940#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 240938#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 240934#L1476-3 assume !(1 == ~E_3~0); 240933#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 240932#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 240931#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 240930#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 240929#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 240928#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 240927#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 240926#L1516-3 assume !(1 == ~E_11~0); 226672#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 240925#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 240924#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 240920#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 240909#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 240908#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 240906#L1911 assume !(0 == start_simulation_~tmp~3#1); 240907#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 238364#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 238355#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 214542#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 214541#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 214539#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 214537#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 213825#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 213177#L1892-2 [2023-11-26 11:58:18,226 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:18,226 INFO L85 PathProgramCache]: Analyzing trace with hash -1648097194, now seen corresponding path program 1 times [2023-11-26 11:58:18,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:18,227 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053254801] [2023-11-26 11:58:18,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:18,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:18,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:18,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:18,315 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:18,315 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2053254801] [2023-11-26 11:58:18,315 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2053254801] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:18,315 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:18,316 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:58:18,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504589088] [2023-11-26 11:58:18,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:18,316 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:18,317 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:18,317 INFO L85 PathProgramCache]: Analyzing trace with hash -931248125, now seen corresponding path program 1 times [2023-11-26 11:58:18,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:18,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659293414] [2023-11-26 11:58:18,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:18,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:18,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:18,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:18,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:18,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659293414] [2023-11-26 11:58:18,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659293414] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:18,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:18,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:18,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [973600095] [2023-11-26 11:58:18,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:18,379 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:18,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:18,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:18,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:18,380 INFO L87 Difference]: Start difference. First operand 50551 states and 73500 transitions. cyclomatic complexity: 22965 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:19,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:19,088 INFO L93 Difference]: Finished difference Result 97214 states and 140809 transitions. [2023-11-26 11:58:19,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97214 states and 140809 transitions. [2023-11-26 11:58:19,515 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 96872 [2023-11-26 11:58:20,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97214 states to 97214 states and 140809 transitions. [2023-11-26 11:58:20,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97214 [2023-11-26 11:58:20,085 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97214 [2023-11-26 11:58:20,085 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97214 states and 140809 transitions. [2023-11-26 11:58:20,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:20,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97214 states and 140809 transitions. [2023-11-26 11:58:20,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97214 states and 140809 transitions. [2023-11-26 11:58:21,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97214 to 97150. [2023-11-26 11:58:21,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97150 states, 97150 states have (on average 1.4487390633041688) internal successors, (140745), 97149 states have internal predecessors, (140745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:21,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97150 states to 97150 states and 140745 transitions. [2023-11-26 11:58:21,921 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97150 states and 140745 transitions. [2023-11-26 11:58:21,921 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:21,922 INFO L428 stractBuchiCegarLoop]: Abstraction has 97150 states and 140745 transitions. [2023-11-26 11:58:21,922 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 11:58:21,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97150 states and 140745 transitions. [2023-11-26 11:58:22,207 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 96808 [2023-11-26 11:58:22,207 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:22,207 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:22,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:22,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:22,212 INFO L748 eck$LassoCheckResult]: Stem: 350857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 350858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 351772#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 351773#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 352631#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 352202#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 352203#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 351080#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 351081#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 351567#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 351397#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 351398#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 351145#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 351146#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 351573#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 351760#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 351936#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 351971#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 351161#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 351162#L1258 assume !(0 == ~M_E~0); 352469#L1258-2 assume !(0 == ~T1_E~0); 351482#L1263-1 assume !(0 == ~T2_E~0); 351483#L1268-1 assume !(0 == ~T3_E~0); 351809#L1273-1 assume !(0 == ~T4_E~0); 352446#L1278-1 assume !(0 == ~T5_E~0); 352270#L1283-1 assume !(0 == ~T6_E~0); 352271#L1288-1 assume !(0 == ~T7_E~0); 352562#L1293-1 assume !(0 == ~T8_E~0); 352548#L1298-1 assume !(0 == ~T9_E~0); 352463#L1303-1 assume !(0 == ~T10_E~0); 350956#L1308-1 assume !(0 == ~T11_E~0); 350899#L1313-1 assume !(0 == ~T12_E~0); 350900#L1318-1 assume !(0 == ~T13_E~0); 350904#L1323-1 assume !(0 == ~E_1~0); 350905#L1328-1 assume !(0 == ~E_2~0); 351090#L1333-1 assume !(0 == ~E_3~0); 352117#L1338-1 assume !(0 == ~E_4~0); 352118#L1343-1 assume !(0 == ~E_5~0); 352243#L1348-1 assume !(0 == ~E_6~0); 352600#L1353-1 assume !(0 == ~E_7~0); 351832#L1358-1 assume !(0 == ~E_8~0); 351833#L1363-1 assume !(0 == ~E_9~0); 352140#L1368-1 assume !(0 == ~E_10~0); 350750#L1373-1 assume !(0 == ~E_11~0); 350751#L1378-1 assume !(0 == ~E_12~0); 351034#L1383-1 assume !(0 == ~E_13~0); 351035#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 351836#L607 assume !(1 == ~m_pc~0); 351109#L607-2 is_master_triggered_~__retres1~0#1 := 0; 351110#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 351633#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 351634#L1560 assume !(0 != activate_threads_~tmp~1#1); 351741#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 350917#L626 assume !(1 == ~t1_pc~0); 350918#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 351204#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 351205#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 352126#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 350826#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 350827#L645 assume !(1 == ~t2_pc~0); 350889#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 350890#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 351002#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 351003#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 351715#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 351716#L664 assume !(1 == ~t3_pc~0); 352163#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 350688#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 350689#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 351353#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 351354#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 352481#L683 assume !(1 == ~t4_pc~0); 351954#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 351907#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350708#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350709#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 352070#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 351659#L702 assume 1 == ~t5_pc~0; 351660#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 351590#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 352065#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 352467#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 352347#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350724#L721 assume !(1 == ~t6_pc~0); 350701#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 350702#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 350849#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 350985#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 351369#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 352005#L740 assume 1 == ~t7_pc~0; 350766#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 350601#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350602#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 350591#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 350592#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 351294#L759 assume !(1 == ~t8_pc~0); 351295#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 351325#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 352536#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 352214#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 352215#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 352560#L778 assume 1 == ~t9_pc~0; 352425#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 350749#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 351056#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 350627#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 350628#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 350931#L797 assume !(1 == ~t10_pc~0); 350932#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 351066#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 352393#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 351478#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 351479#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 351788#L816 assume 1 == ~t11_pc~0; 350664#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 350665#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 351621#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 351375#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 351376#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 351935#L835 assume 1 == ~t12_pc~0; 351804#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 350813#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 350652#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 350653#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 351535#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 351536#L854 assume !(1 == ~t13_pc~0); 351147#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 351148#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 351199#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 350847#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 350848#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 352339#L1401 assume !(1 == ~M_E~0); 351362#L1401-2 assume !(1 == ~T1_E~0); 351363#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 352348#L1411-1 assume !(1 == ~T3_E~0); 357713#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 351629#L1421-1 assume !(1 == ~T5_E~0); 351143#L1426-1 assume !(1 == ~T6_E~0); 351144#L1431-1 assume !(1 == ~T7_E~0); 350699#L1436-1 assume !(1 == ~T8_E~0); 350700#L1441-1 assume !(1 == ~T9_E~0); 351473#L1446-1 assume !(1 == ~T10_E~0); 351474#L1451-1 assume !(1 == ~T11_E~0); 352239#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 351855#L1461-1 assume !(1 == ~T13_E~0); 351391#L1466-1 assume !(1 == ~E_1~0); 351392#L1471-1 assume !(1 == ~E_2~0); 352638#L1476-1 assume !(1 == ~E_3~0); 357778#L1481-1 assume !(1 == ~E_4~0); 357777#L1486-1 assume !(1 == ~E_5~0); 357141#L1491-1 assume !(1 == ~E_6~0); 357139#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 357138#L1501-1 assume !(1 == ~E_8~0); 357134#L1506-1 assume !(1 == ~E_9~0); 356451#L1511-1 assume !(1 == ~E_10~0); 356410#L1516-1 assume !(1 == ~E_11~0); 356398#L1521-1 assume !(1 == ~E_12~0); 356389#L1526-1 assume !(1 == ~E_13~0); 356381#L1531-1 assume { :end_inline_reset_delta_events } true; 356374#L1892-2 [2023-11-26 11:58:22,213 INFO L750 eck$LassoCheckResult]: Loop: 356374#L1892-2 assume !false; 356370#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 356369#L1233-1 assume !false; 356368#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 356354#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 356353#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 356352#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 356350#L1046 assume !(0 != eval_~tmp~0#1); 356349#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 356348#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 356347#L1258-3 assume !(0 == ~M_E~0); 356346#L1258-5 assume !(0 == ~T1_E~0); 356343#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 356341#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 356338#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 356339#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 376664#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 376662#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 356328#L1293-3 assume !(0 == ~T8_E~0); 356325#L1298-3 assume !(0 == ~T9_E~0); 356326#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 376629#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 356316#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 356317#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 356310#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 356311#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 356304#L1333-3 assume !(0 == ~E_3~0); 356305#L1338-3 assume !(0 == ~E_4~0); 371358#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 368229#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 368226#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 368224#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 368222#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 368220#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 368218#L1373-3 assume !(0 == ~E_11~0); 368216#L1378-3 assume !(0 == ~E_12~0); 368213#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 368211#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 368209#L607-42 assume !(1 == ~m_pc~0); 368206#L607-44 is_master_triggered_~__retres1~0#1 := 0; 368204#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 368202#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 368201#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 368200#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 368199#L626-42 assume !(1 == ~t1_pc~0); 367965#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 367962#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 367960#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 367959#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 367956#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 367954#L645-42 assume !(1 == ~t2_pc~0); 367952#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 367950#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 367948#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 367946#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 367943#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 367941#L664-42 assume !(1 == ~t3_pc~0); 367939#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 367937#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 367935#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 367933#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 367930#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 367928#L683-42 assume !(1 == ~t4_pc~0); 367925#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 367923#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 367921#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 367919#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 367916#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 367914#L702-42 assume !(1 == ~t5_pc~0); 367861#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 367858#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 367856#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 367854#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 367852#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 367850#L721-42 assume !(1 == ~t6_pc~0); 367847#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 367844#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 367842#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 367840#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 367838#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 367836#L740-42 assume !(1 == ~t7_pc~0); 367833#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 367830#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 367828#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 367826#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 367824#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 367822#L759-42 assume !(1 == ~t8_pc~0); 367819#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 367816#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 367814#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 367812#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 367810#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 367806#L778-42 assume 1 == ~t9_pc~0; 367789#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 367786#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 367784#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 367782#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 367780#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 367778#L797-42 assume !(1 == ~t10_pc~0); 367776#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 367774#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 367772#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 367770#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 367768#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 367766#L816-42 assume 1 == ~t11_pc~0; 367764#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 367761#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 367759#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 367757#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 367755#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 367753#L835-42 assume !(1 == ~t12_pc~0); 367751#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 367748#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 367746#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 367744#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 367039#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 366440#L854-42 assume 1 == ~t13_pc~0; 359299#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 359296#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 359294#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 359292#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 359290#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 359267#L1401-3 assume !(1 == ~M_E~0); 359265#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 359263#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 356115#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 359260#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 359258#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 359255#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 359253#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 359242#L1436-3 assume !(1 == ~T8_E~0); 359239#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 359237#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 359235#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 359233#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 359231#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 359229#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 359227#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 359223#L1476-3 assume !(1 == ~E_3~0); 359222#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 359220#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 359218#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 359216#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 359214#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 359212#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 359209#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 359207#L1516-3 assume !(1 == ~E_11~0); 358642#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 358871#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 358869#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 358459#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 358000#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 357998#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 357786#L1911 assume !(0 == start_simulation_~tmp~3#1); 357779#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 357645#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 357132#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 356449#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 356407#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 356397#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 356388#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 356380#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 356374#L1892-2 [2023-11-26 11:58:22,214 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:22,215 INFO L85 PathProgramCache]: Analyzing trace with hash -1375101771, now seen corresponding path program 1 times [2023-11-26 11:58:22,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:22,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339886119] [2023-11-26 11:58:22,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:22,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:22,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:22,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:22,344 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:22,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339886119] [2023-11-26 11:58:22,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339886119] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:22,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:22,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:58:22,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445388855] [2023-11-26 11:58:22,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:22,346 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:22,347 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:22,347 INFO L85 PathProgramCache]: Analyzing trace with hash -1934304990, now seen corresponding path program 1 times [2023-11-26 11:58:22,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:22,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958750148] [2023-11-26 11:58:22,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:22,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:22,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:22,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:22,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:22,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958750148] [2023-11-26 11:58:22,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [958750148] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:22,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:22,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:22,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623260634] [2023-11-26 11:58:22,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:22,424 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:22,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:22,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:58:22,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:58:22,426 INFO L87 Difference]: Start difference. First operand 97150 states and 140745 transitions. cyclomatic complexity: 43627 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:24,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:24,263 INFO L93 Difference]: Finished difference Result 244064 states and 350831 transitions. [2023-11-26 11:58:24,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244064 states and 350831 transitions. [2023-11-26 11:58:25,930 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 243392 [2023-11-26 11:58:27,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244064 states to 244064 states and 350831 transitions. [2023-11-26 11:58:27,206 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 244064 [2023-11-26 11:58:27,302 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 244064 [2023-11-26 11:58:27,302 INFO L73 IsDeterministic]: Start isDeterministic. Operand 244064 states and 350831 transitions. [2023-11-26 11:58:27,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:27,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 244064 states and 350831 transitions. [2023-11-26 11:58:27,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244064 states and 350831 transitions. [2023-11-26 11:58:29,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244064 to 99601. [2023-11-26 11:58:29,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99601 states, 99601 states have (on average 1.4376964086705957) internal successors, (143196), 99600 states have internal predecessors, (143196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:29,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99601 states to 99601 states and 143196 transitions. [2023-11-26 11:58:29,571 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99601 states and 143196 transitions. [2023-11-26 11:58:29,571 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:58:29,572 INFO L428 stractBuchiCegarLoop]: Abstraction has 99601 states and 143196 transitions. [2023-11-26 11:58:29,572 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 11:58:29,572 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99601 states and 143196 transitions. [2023-11-26 11:58:29,920 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99256 [2023-11-26 11:58:29,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:29,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:29,923 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:29,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:29,924 INFO L748 eck$LassoCheckResult]: Stem: 692083#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 692084#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 693008#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 693009#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 693935#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 693457#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 693458#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 692304#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 692305#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 692801#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 692625#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 692626#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 692368#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 692369#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 692807#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 692998#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 693177#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 693218#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 692384#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 692385#L1258 assume !(0 == ~M_E~0); 693738#L1258-2 assume !(0 == ~T1_E~0); 692714#L1263-1 assume !(0 == ~T2_E~0); 692715#L1268-1 assume !(0 == ~T3_E~0); 693050#L1273-1 assume !(0 == ~T4_E~0); 693711#L1278-1 assume !(0 == ~T5_E~0); 693523#L1283-1 assume !(0 == ~T6_E~0); 693524#L1288-1 assume !(0 == ~T7_E~0); 693855#L1293-1 assume !(0 == ~T8_E~0); 693838#L1298-1 assume !(0 == ~T9_E~0); 693731#L1303-1 assume !(0 == ~T10_E~0); 692182#L1308-1 assume !(0 == ~T11_E~0); 692125#L1313-1 assume !(0 == ~T12_E~0); 692126#L1318-1 assume !(0 == ~T13_E~0); 692131#L1323-1 assume !(0 == ~E_1~0); 692132#L1328-1 assume !(0 == ~E_2~0); 692314#L1333-1 assume !(0 == ~E_3~0); 693362#L1338-1 assume !(0 == ~E_4~0); 693363#L1343-1 assume !(0 == ~E_5~0); 693494#L1348-1 assume !(0 == ~E_6~0); 693892#L1353-1 assume !(0 == ~E_7~0); 693073#L1358-1 assume !(0 == ~E_8~0); 693074#L1363-1 assume !(0 == ~E_9~0); 693391#L1368-1 assume !(0 == ~E_10~0); 691976#L1373-1 assume !(0 == ~E_11~0); 691977#L1378-1 assume !(0 == ~E_12~0); 692259#L1383-1 assume !(0 == ~E_13~0); 692260#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 693077#L607 assume !(1 == ~m_pc~0); 692333#L607-2 is_master_triggered_~__retres1~0#1 := 0; 692334#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 692867#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 692868#L1560 assume !(0 != activate_threads_~tmp~1#1); 692978#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 692144#L626 assume !(1 == ~t1_pc~0); 692145#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 692428#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 692429#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 693370#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 692052#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 692053#L645 assume !(1 == ~t2_pc~0); 692115#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 692116#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 692226#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 692227#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 692952#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 692953#L664 assume !(1 == ~t3_pc~0); 693417#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 691914#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 691915#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 692580#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 692581#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 693747#L683 assume !(1 == ~t4_pc~0); 693198#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 693147#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 693148#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 693908#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 693313#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 692893#L702 assume 1 == ~t5_pc~0; 692894#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 692823#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 693308#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 693736#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 693612#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 691950#L721 assume !(1 == ~t6_pc~0); 691927#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 691928#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 692075#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 692210#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 692596#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 693252#L740 assume 1 == ~t7_pc~0; 691992#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 691828#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 691829#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 691818#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 691819#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 692518#L759 assume !(1 == ~t8_pc~0); 692519#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 692550#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 693826#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 693468#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 693469#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 693853#L778 assume 1 == ~t9_pc~0; 693691#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 691975#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 692280#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 691853#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 691854#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 692157#L797 assume !(1 == ~t10_pc~0); 692158#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 692290#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 693661#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 692710#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 692711#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 693025#L816 assume 1 == ~t11_pc~0; 691890#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 691891#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 692855#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 692602#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 692603#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 693176#L835 assume 1 == ~t12_pc~0; 693043#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 692039#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 691878#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 691879#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 692770#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 692771#L854 assume !(1 == ~t13_pc~0); 692370#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 692371#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 692423#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 692073#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 692074#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 693605#L1401 assume !(1 == ~M_E~0); 692589#L1401-2 assume !(1 == ~T1_E~0); 692590#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 693613#L1411-1 assume !(1 == ~T3_E~0); 699542#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 699541#L1421-1 assume !(1 == ~T5_E~0); 699540#L1426-1 assume !(1 == ~T6_E~0); 693399#L1431-1 assume !(1 == ~T7_E~0); 691925#L1436-1 assume !(1 == ~T8_E~0); 691926#L1441-1 assume !(1 == ~T9_E~0); 699600#L1446-1 assume !(1 == ~T10_E~0); 699598#L1451-1 assume !(1 == ~T11_E~0); 699596#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 699594#L1461-1 assume !(1 == ~T13_E~0); 699518#L1466-1 assume !(1 == ~E_1~0); 699516#L1471-1 assume !(1 == ~E_2~0); 699514#L1476-1 assume !(1 == ~E_3~0); 699512#L1481-1 assume !(1 == ~E_4~0); 699372#L1486-1 assume !(1 == ~E_5~0); 699370#L1491-1 assume !(1 == ~E_6~0); 699286#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 699284#L1501-1 assume !(1 == ~E_8~0); 699282#L1506-1 assume !(1 == ~E_9~0); 699278#L1511-1 assume !(1 == ~E_10~0); 699232#L1516-1 assume !(1 == ~E_11~0); 699228#L1521-1 assume !(1 == ~E_12~0); 699158#L1526-1 assume !(1 == ~E_13~0); 699113#L1531-1 assume { :end_inline_reset_delta_events } true; 699072#L1892-2 [2023-11-26 11:58:29,925 INFO L750 eck$LassoCheckResult]: Loop: 699072#L1892-2 assume !false; 699032#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 698997#L1233-1 assume !false; 698956#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 698922#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 698905#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 698890#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 698881#L1046 assume !(0 != eval_~tmp~0#1); 698882#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 723216#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 723215#L1258-3 assume !(0 == ~M_E~0); 723214#L1258-5 assume !(0 == ~T1_E~0); 723213#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 723212#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 723211#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 723210#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 723209#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 723208#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 723207#L1293-3 assume !(0 == ~T8_E~0); 723206#L1298-3 assume !(0 == ~T9_E~0); 723205#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 723204#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 723203#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 723202#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 723201#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 723200#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 723199#L1333-3 assume !(0 == ~E_3~0); 723198#L1338-3 assume !(0 == ~E_4~0); 723197#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 723196#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 723195#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 723194#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 723193#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 723192#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 723191#L1373-3 assume !(0 == ~E_11~0); 723190#L1378-3 assume !(0 == ~E_12~0); 723189#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 723188#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 723187#L607-42 assume !(1 == ~m_pc~0); 723185#L607-44 is_master_triggered_~__retres1~0#1 := 0; 723184#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 723183#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 723182#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 723181#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 723180#L626-42 assume !(1 == ~t1_pc~0); 723179#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 723177#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 723176#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 723175#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 723174#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 723173#L645-42 assume !(1 == ~t2_pc~0); 723172#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 723171#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 723170#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 723169#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 723168#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 723167#L664-42 assume !(1 == ~t3_pc~0); 723166#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 723165#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 723164#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 723163#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 723162#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 723161#L683-42 assume !(1 == ~t4_pc~0); 723160#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 723158#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 723156#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 723154#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 723151#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 723149#L702-42 assume !(1 == ~t5_pc~0); 723147#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 723144#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 723143#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 723142#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 723141#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 720822#L721-42 assume !(1 == ~t6_pc~0); 719042#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 719039#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 719037#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 719034#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 719032#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 719030#L740-42 assume 1 == ~t7_pc~0; 719027#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 719025#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 719023#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 719020#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 719018#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 719016#L759-42 assume !(1 == ~t8_pc~0); 719014#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 719012#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 719011#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 719010#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 719008#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 719006#L778-42 assume !(1 == ~t9_pc~0); 719002#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 719001#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 719000#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 718999#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 716777#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 716775#L797-42 assume 1 == ~t10_pc~0; 716772#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 716770#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 716768#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 716766#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 716763#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 716761#L816-42 assume !(1 == ~t11_pc~0); 716758#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 716756#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 716754#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 716752#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 716751#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 716748#L835-42 assume !(1 == ~t12_pc~0); 716746#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 716743#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 716741#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 716739#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 716737#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 716734#L854-42 assume 1 == ~t13_pc~0; 702654#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 702650#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 702648#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 702646#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 700175#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 700094#L1401-3 assume !(1 == ~M_E~0); 700092#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 700017#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 696588#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 700014#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 700011#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 700009#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 700005#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 699956#L1436-3 assume !(1 == ~T8_E~0); 699926#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 699924#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 699922#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 699909#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 699897#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 699876#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 699874#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 699857#L1476-3 assume !(1 == ~E_3~0); 699845#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 699827#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 699825#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 699775#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 699773#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 699709#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 699707#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 699703#L1516-3 assume !(1 == ~E_11~0); 699702#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 699701#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 699700#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 699623#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 699611#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 699609#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 699607#L1911 assume !(0 == start_simulation_~tmp~3#1); 699539#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 699399#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 699289#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 699235#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 699161#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 699159#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 699157#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 699112#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 699072#L1892-2 [2023-11-26 11:58:29,926 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:29,927 INFO L85 PathProgramCache]: Analyzing trace with hash 1040734579, now seen corresponding path program 1 times [2023-11-26 11:58:29,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:29,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506909524] [2023-11-26 11:58:29,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:29,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:29,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:30,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:30,037 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:30,037 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506909524] [2023-11-26 11:58:30,037 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [506909524] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:30,037 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:30,038 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:58:30,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1002038889] [2023-11-26 11:58:30,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:30,039 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:30,039 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:30,040 INFO L85 PathProgramCache]: Analyzing trace with hash -1946017120, now seen corresponding path program 1 times [2023-11-26 11:58:30,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:30,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439110885] [2023-11-26 11:58:30,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:30,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:30,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:30,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:30,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:30,180 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439110885] [2023-11-26 11:58:30,180 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1439110885] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:30,181 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:30,181 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:58:30,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887262929] [2023-11-26 11:58:30,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:30,182 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:30,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:30,183 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:58:30,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:58:30,184 INFO L87 Difference]: Start difference. First operand 99601 states and 143196 transitions. cyclomatic complexity: 43627 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:31,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:31,735 INFO L93 Difference]: Finished difference Result 191608 states and 274545 transitions. [2023-11-26 11:58:31,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191608 states and 274545 transitions. [2023-11-26 11:58:33,157 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 191040 [2023-11-26 11:58:33,613 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191608 states to 191608 states and 274545 transitions. [2023-11-26 11:58:33,613 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191608 [2023-11-26 11:58:33,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191608 [2023-11-26 11:58:33,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191608 states and 274545 transitions. [2023-11-26 11:58:33,754 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:58:33,754 INFO L218 hiAutomatonCegarLoop]: Abstraction has 191608 states and 274545 transitions. [2023-11-26 11:58:33,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191608 states and 274545 transitions. [2023-11-26 11:58:36,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191608 to 191480. [2023-11-26 11:58:36,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191480 states, 191480 states have (on average 1.433136620012534) internal successors, (274417), 191479 states have internal predecessors, (274417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:37,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191480 states to 191480 states and 274417 transitions. [2023-11-26 11:58:37,339 INFO L240 hiAutomatonCegarLoop]: Abstraction has 191480 states and 274417 transitions. [2023-11-26 11:58:37,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:58:37,340 INFO L428 stractBuchiCegarLoop]: Abstraction has 191480 states and 274417 transitions. [2023-11-26 11:58:37,340 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 11:58:37,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191480 states and 274417 transitions. [2023-11-26 11:58:37,965 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 190912 [2023-11-26 11:58:37,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:58:37,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:58:37,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:37,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:58:37,970 INFO L748 eck$LassoCheckResult]: Stem: 983299#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 983300#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 984236#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 984237#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 985196#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 984703#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 984704#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 983522#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 983523#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 984014#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 983843#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 983844#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 983588#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 983589#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 984022#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 984226#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 984408#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 984444#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 983604#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 983605#L1258 assume !(0 == ~M_E~0); 985000#L1258-2 assume !(0 == ~T1_E~0); 983927#L1263-1 assume !(0 == ~T2_E~0); 983928#L1268-1 assume !(0 == ~T3_E~0); 984276#L1273-1 assume !(0 == ~T4_E~0); 984976#L1278-1 assume !(0 == ~T5_E~0); 984781#L1283-1 assume !(0 == ~T6_E~0); 984782#L1288-1 assume !(0 == ~T7_E~0); 985119#L1293-1 assume !(0 == ~T8_E~0); 985104#L1298-1 assume !(0 == ~T9_E~0); 984993#L1303-1 assume !(0 == ~T10_E~0); 983397#L1308-1 assume !(0 == ~T11_E~0); 983339#L1313-1 assume !(0 == ~T12_E~0); 983340#L1318-1 assume !(0 == ~T13_E~0); 983345#L1323-1 assume !(0 == ~E_1~0); 983346#L1328-1 assume !(0 == ~E_2~0); 983532#L1333-1 assume !(0 == ~E_3~0); 984603#L1338-1 assume !(0 == ~E_4~0); 984604#L1343-1 assume !(0 == ~E_5~0); 984744#L1348-1 assume !(0 == ~E_6~0); 985161#L1353-1 assume !(0 == ~E_7~0); 984299#L1358-1 assume !(0 == ~E_8~0); 984300#L1363-1 assume !(0 == ~E_9~0); 984638#L1368-1 assume !(0 == ~E_10~0); 983193#L1373-1 assume !(0 == ~E_11~0); 983194#L1378-1 assume !(0 == ~E_12~0); 983474#L1383-1 assume !(0 == ~E_13~0); 983475#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 984303#L607 assume !(1 == ~m_pc~0); 983549#L607-2 is_master_triggered_~__retres1~0#1 := 0; 983550#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 984084#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 984085#L1560 assume !(0 != activate_threads_~tmp~1#1); 984204#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 983360#L626 assume !(1 == ~t1_pc~0); 983361#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 983647#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 983648#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 984613#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 983267#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 983268#L645 assume !(1 == ~t2_pc~0); 983332#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 983333#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 983442#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 983443#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 984177#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 984178#L664 assume !(1 == ~t3_pc~0); 984662#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 983127#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 983128#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 983799#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 983800#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 985011#L683 assume !(1 == ~t4_pc~0); 984426#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 984616#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 983151#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 983152#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 984554#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 984111#L702 assume !(1 == ~t5_pc~0); 984037#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 984038#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 984548#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 984997#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 984869#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 983163#L721 assume !(1 == ~t6_pc~0); 983144#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 983145#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 983291#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 983427#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 983815#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 984480#L740 assume 1 == ~t7_pc~0; 983208#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 983046#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 983047#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 983036#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 983037#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 983737#L759 assume !(1 == ~t8_pc~0); 983738#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 983771#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 985084#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 984715#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 984716#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 985118#L778 assume 1 == ~t9_pc~0; 984953#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 983192#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 983498#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 983069#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 983070#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 983372#L797 assume !(1 == ~t10_pc~0); 983373#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 983508#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 984922#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 983923#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 983924#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 984254#L816 assume 1 == ~t11_pc~0; 983105#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 983106#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 984072#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 983821#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 983822#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 984407#L835 assume 1 == ~t12_pc~0; 984271#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 983255#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 983095#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 983096#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 983985#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 983986#L854 assume !(1 == ~t13_pc~0); 983590#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 983591#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 983642#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 983289#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 983290#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 984864#L1401 assume !(1 == ~M_E~0); 983808#L1401-2 assume !(1 == ~T1_E~0); 983809#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 984871#L1411-1 assume !(1 == ~T3_E~0); 985141#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 985142#L1421-1 assume !(1 == ~T5_E~0); 983586#L1426-1 assume !(1 == ~T6_E~0); 983587#L1431-1 assume !(1 == ~T7_E~0); 983142#L1436-1 assume !(1 == ~T8_E~0); 983143#L1441-1 assume !(1 == ~T9_E~0); 1008780#L1446-1 assume !(1 == ~T10_E~0); 1008778#L1451-1 assume !(1 == ~T11_E~0); 1008776#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1008773#L1461-1 assume !(1 == ~T13_E~0); 1008771#L1466-1 assume !(1 == ~E_1~0); 985201#L1471-1 assume !(1 == ~E_2~0); 984713#L1476-1 assume !(1 == ~E_3~0); 984714#L1481-1 assume !(1 == ~E_4~0); 984929#L1486-1 assume !(1 == ~E_5~0); 983410#L1491-1 assume !(1 == ~E_6~0); 983080#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 983081#L1501-1 assume !(1 == ~E_8~0); 983912#L1506-1 assume !(1 == ~E_9~0); 983913#L1511-1 assume !(1 == ~E_10~0); 983866#L1516-1 assume !(1 == ~E_11~0); 983034#L1521-1 assume !(1 == ~E_12~0); 983035#L1526-1 assume !(1 == ~E_13~0); 983079#L1531-1 assume { :end_inline_reset_delta_events } true; 983612#L1892-2 [2023-11-26 11:58:37,971 INFO L750 eck$LassoCheckResult]: Loop: 983612#L1892-2 assume !false; 1029133#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1029131#L1233-1 assume !false; 1029129#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1029103#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1029101#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1029100#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1029098#L1046 assume !(0 != eval_~tmp~0#1); 1029097#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1029096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1029095#L1258-3 assume !(0 == ~M_E~0); 1029094#L1258-5 assume !(0 == ~T1_E~0); 1029093#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1029092#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1029091#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1029089#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1029086#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1029084#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1029082#L1293-3 assume !(0 == ~T8_E~0); 1029080#L1298-3 assume !(0 == ~T9_E~0); 1029078#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1029076#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1029073#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1029071#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1029069#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1029067#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1029065#L1333-3 assume !(0 == ~E_3~0); 1029063#L1338-3 assume !(0 == ~E_4~0); 1029061#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1029059#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1029057#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1029055#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1029053#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1029051#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1029049#L1373-3 assume !(0 == ~E_11~0); 1029047#L1378-3 assume !(0 == ~E_12~0); 1029045#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1029043#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1029041#L607-42 assume !(1 == ~m_pc~0); 1029038#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1029035#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1029032#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1029029#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1029026#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1029024#L626-42 assume !(1 == ~t1_pc~0); 1029022#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1029019#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1029017#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1029015#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1029013#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1029011#L645-42 assume !(1 == ~t2_pc~0); 1029009#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1029006#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1029004#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1029002#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1029000#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1028998#L664-42 assume !(1 == ~t3_pc~0); 1028996#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1028993#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1028991#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1028989#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1028987#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1028985#L683-42 assume !(1 == ~t4_pc~0); 1028983#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1028979#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1028976#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1028973#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 1028970#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1028968#L702-42 assume !(1 == ~t5_pc~0); 1028966#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1028963#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1028961#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1028959#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 1028957#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1028955#L721-42 assume !(1 == ~t6_pc~0); 1028953#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1028949#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1028947#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1028945#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1028943#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1028941#L740-42 assume !(1 == ~t7_pc~0); 1028939#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1028935#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1028933#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1028931#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1028929#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1028927#L759-42 assume !(1 == ~t8_pc~0); 1028925#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1028921#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1028919#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1028917#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1028915#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1028913#L778-42 assume 1 == ~t9_pc~0; 1028911#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1028907#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1028905#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1028903#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1028901#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1028899#L797-42 assume !(1 == ~t10_pc~0); 1028895#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1028892#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1028890#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1028887#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1028886#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1028885#L816-42 assume 1 == ~t11_pc~0; 1028883#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1028881#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1028879#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1028878#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1028877#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1028876#L835-42 assume !(1 == ~t12_pc~0); 1028875#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1028873#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1028872#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1028871#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1028870#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1028868#L854-42 assume 1 == ~t13_pc~0; 1028866#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1028863#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1028861#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1028859#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1028857#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1028855#L1401-3 assume !(1 == ~M_E~0); 1028568#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1028852#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1004315#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1028849#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1028847#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1028845#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1028843#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1028841#L1436-3 assume !(1 == ~T8_E~0); 1024193#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1028838#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1028836#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1028834#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1028832#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1028830#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1028828#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1028826#L1476-3 assume !(1 == ~E_3~0); 1022287#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1028823#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1028821#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1028819#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1028817#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1028815#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1028813#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1028810#L1516-3 assume !(1 == ~E_11~0); 1015438#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1028807#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1028805#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1028797#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1028785#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1028783#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1028780#L1911 assume !(0 == start_simulation_~tmp~3#1); 1028781#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1030332#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1030324#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1030323#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1030322#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1030320#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1030318#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1030316#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 983612#L1892-2 [2023-11-26 11:58:37,972 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:37,973 INFO L85 PathProgramCache]: Analyzing trace with hash -944094126, now seen corresponding path program 1 times [2023-11-26 11:58:37,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:37,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237466367] [2023-11-26 11:58:37,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:37,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:38,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:38,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:38,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:38,107 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1237466367] [2023-11-26 11:58:38,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1237466367] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:38,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:38,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:38,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264337621] [2023-11-26 11:58:38,108 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:38,108 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:58:38,109 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:58:38,109 INFO L85 PathProgramCache]: Analyzing trace with hash 1303931104, now seen corresponding path program 1 times [2023-11-26 11:58:38,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:58:38,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [945169964] [2023-11-26 11:58:38,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:58:38,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:58:38,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:58:38,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:58:38,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:58:38,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [945169964] [2023-11-26 11:58:38,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [945169964] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:58:38,199 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:58:38,199 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:58:38,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547226596] [2023-11-26 11:58:38,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:58:38,200 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:58:38,200 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:58:38,201 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:58:38,201 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:58:38,201 INFO L87 Difference]: Start difference. First operand 191480 states and 274417 transitions. cyclomatic complexity: 83001 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:58:40,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:58:40,832 INFO L93 Difference]: Finished difference Result 459055 states and 654742 transitions. [2023-11-26 11:58:40,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 459055 states and 654742 transitions. [2023-11-26 11:58:43,584 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 457592