./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-acceleration/array_3-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-acceleration/array_3-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9c5d8dd6c87f471ee77fd3b765c8ecabfaf01dd976e127275ea7c589f724f472 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:57:11,394 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:57:11,482 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:57:11,487 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:57:11,488 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:57:11,514 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:57:11,515 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:57:11,516 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:57:11,517 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:57:11,518 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:57:11,519 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:57:11,519 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:57:11,520 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:57:11,520 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:57:11,521 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:57:11,522 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:57:11,522 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:57:11,523 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:57:11,523 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:57:11,524 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:57:11,524 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:57:11,525 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:57:11,525 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:57:11,526 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:57:11,526 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:57:11,527 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:57:11,527 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:57:11,528 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:57:11,528 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:57:11,529 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:57:11,529 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:57:11,529 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:57:11,530 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:57:11,530 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:57:11,531 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:57:11,531 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:57:11,532 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:57:11,533 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:57:11,533 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9c5d8dd6c87f471ee77fd3b765c8ecabfaf01dd976e127275ea7c589f724f472 [2023-11-26 11:57:11,845 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:57:11,882 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:57:11,885 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:57:11,888 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:57:11,889 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:57:11,891 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/loop-acceleration/array_3-1.i [2023-11-26 11:57:15,160 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:57:15,390 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:57:15,390 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/sv-benchmarks/c/loop-acceleration/array_3-1.i [2023-11-26 11:57:15,398 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/data/15743dfa1/8fce3e4337984cdabc26b676d9f86a24/FLAGa020656f5 [2023-11-26 11:57:15,415 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/data/15743dfa1/8fce3e4337984cdabc26b676d9f86a24 [2023-11-26 11:57:15,418 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:57:15,420 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:57:15,422 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:57:15,422 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:57:15,431 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:57:15,432 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,433 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2f9135ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15, skipping insertion in model container [2023-11-26 11:57:15,433 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,456 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:57:15,661 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:57:15,675 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:57:15,699 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:57:15,718 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:57:15,718 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15 WrapperNode [2023-11-26 11:57:15,718 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:57:15,720 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:57:15,721 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:57:15,721 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:57:15,729 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,737 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,759 INFO L138 Inliner]: procedures = 16, calls = 12, calls flagged for inlining = 4, calls inlined = 4, statements flattened = 46 [2023-11-26 11:57:15,760 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:57:15,761 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:57:15,762 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:57:15,762 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:57:15,774 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,776 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,788 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,810 INFO L175 MemorySlicer]: Split 4 memory accesses to 2 slices as follows [2, 2]. 50 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 1 writes are split as follows [0, 1]. [2023-11-26 11:57:15,810 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,811 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,825 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,829 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,830 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,831 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,833 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:57:15,834 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:57:15,834 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:57:15,834 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:57:15,835 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (1/1) ... [2023-11-26 11:57:15,845 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:15,866 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:15,881 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:15,896 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:57:15,921 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:57:15,922 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:57:15,922 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2023-11-26 11:57:15,923 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2023-11-26 11:57:15,923 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2023-11-26 11:57:15,923 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2023-11-26 11:57:15,924 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:57:15,924 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:57:15,925 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2023-11-26 11:57:15,925 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2023-11-26 11:57:15,926 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2023-11-26 11:57:16,011 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:57:16,014 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:57:16,160 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:57:16,171 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:57:16,171 INFO L309 CfgBuilder]: Removed 2 assume(true) statements. [2023-11-26 11:57:16,173 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:57:16 BoogieIcfgContainer [2023-11-26 11:57:16,173 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:57:16,175 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:57:16,175 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:57:16,179 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:57:16,180 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:57:16,180 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:57:15" (1/3) ... [2023-11-26 11:57:16,182 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d64ad03 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:57:16, skipping insertion in model container [2023-11-26 11:57:16,182 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:57:16,182 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:57:15" (2/3) ... [2023-11-26 11:57:16,182 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d64ad03 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:57:16, skipping insertion in model container [2023-11-26 11:57:16,183 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:57:16,183 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:57:16" (3/3) ... [2023-11-26 11:57:16,184 INFO L332 chiAutomizerObserver]: Analyzing ICFG array_3-1.i [2023-11-26 11:57:16,246 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:57:16,246 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:57:16,246 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:57:16,246 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:57:16,246 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:57:16,247 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:57:16,247 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:57:16,247 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:57:16,253 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:16,273 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-26 11:57:16,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:57:16,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:57:16,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 11:57:16,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 11:57:16,278 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:57:16,292 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:16,295 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-26 11:57:16,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:57:16,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:57:16,296 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 11:57:16,296 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 11:57:16,303 INFO L748 eck$LassoCheckResult]: Stem: 12#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 8#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 14#L24-3true [2023-11-26 11:57:16,304 INFO L750 eck$LassoCheckResult]: Loop: 14#L24-3true assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5#L24-2true main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 14#L24-3true [2023-11-26 11:57:16,310 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:16,310 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2023-11-26 11:57:16,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:16,318 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435601473] [2023-11-26 11:57:16,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:16,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:16,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:16,428 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:57:16,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:16,459 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:57:16,462 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:16,462 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2023-11-26 11:57:16,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:16,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756618063] [2023-11-26 11:57:16,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:16,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:16,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:16,477 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:57:16,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:16,486 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:57:16,488 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:16,488 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2023-11-26 11:57:16,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:16,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023981186] [2023-11-26 11:57:16,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:16,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:16,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:16,516 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:57:16,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:16,536 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:57:16,946 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 11:57:16,946 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 11:57:16,947 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 11:57:16,947 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 11:57:16,947 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-26 11:57:16,947 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:16,947 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 11:57:16,948 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 11:57:16,948 INFO L133 ssoRankerPreferences]: Filename of dumped script: array_3-1.i_Iteration1_Lasso [2023-11-26 11:57:16,948 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 11:57:16,948 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 11:57:16,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:57:16,982 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:57:17,005 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:57:17,008 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:57:17,203 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:57:17,206 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:57:17,209 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 11:57:17,482 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 11:57:17,487 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-26 11:57:17,489 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:17,490 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:17,496 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:17,511 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:17,527 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-26 11:57:17,528 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:17,529 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:57:17,529 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:17,530 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:17,530 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:17,532 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:57:17,533 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:57:17,548 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:17,557 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:17,557 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:17,557 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:17,559 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:17,574 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:17,575 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-26 11:57:17,589 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:17,589 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:17,589 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:17,590 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:17,598 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 11:57:17,598 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 11:57:17,612 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:17,623 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:17,623 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:17,623 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:17,625 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:17,635 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:17,644 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-26 11:57:17,652 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:17,652 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:17,652 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:17,652 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:17,656 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 11:57:17,656 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 11:57:17,668 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:17,679 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:17,680 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:17,680 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:17,682 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:17,691 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:17,700 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-26 11:57:17,707 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:17,707 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 11:57:17,707 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:17,708 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:17,708 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:17,709 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 11:57:17,709 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 11:57:17,718 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:17,724 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:17,725 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:17,725 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:17,726 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:17,733 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-26 11:57:17,734 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:17,750 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:17,750 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:17,750 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:17,750 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:17,759 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 11:57:17,762 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 11:57:17,784 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:17,796 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:17,796 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:17,797 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:17,799 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:17,811 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:17,827 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-26 11:57:17,828 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:17,828 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:17,828 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:17,828 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:17,832 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 11:57:17,833 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 11:57:17,845 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:17,856 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:17,856 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:17,857 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:17,858 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:17,870 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:17,885 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-26 11:57:17,886 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:17,887 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:17,887 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:17,887 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:17,891 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 11:57:17,891 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 11:57:17,904 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:17,908 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:17,909 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:17,909 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:17,910 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:17,914 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-26 11:57:17,916 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:17,932 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:17,932 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:17,933 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:17,933 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:17,941 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 11:57:17,941 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 11:57:17,960 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:17,970 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:17,971 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:17,971 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:17,973 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:17,984 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:17,999 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-26 11:57:18,000 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:18,000 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:18,000 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:18,000 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:18,005 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 11:57:18,006 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 11:57:18,024 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:18,032 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:18,032 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:18,033 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:18,035 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:18,045 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-26 11:57:18,045 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:18,063 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:18,063 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:18,063 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:18,063 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:18,068 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 11:57:18,068 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 11:57:18,088 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:18,092 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:18,093 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:18,093 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:18,095 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:18,100 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-26 11:57:18,101 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:18,116 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:18,116 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:18,116 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:18,116 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:18,120 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 11:57:18,120 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 11:57:18,140 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 11:57:18,150 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:18,151 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:18,151 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:18,152 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:18,160 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-26 11:57:18,161 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 11:57:18,176 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 11:57:18,176 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 11:57:18,176 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 11:57:18,176 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 11:57:18,188 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 11:57:18,188 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 11:57:18,205 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-26 11:57:18,251 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2023-11-26 11:57:18,251 INFO L444 ModelExtractionUtils]: 1 out of 13 variables were initially zero. Simplification set additionally 9 variables to zero. [2023-11-26 11:57:18,253 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:57:18,254 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:18,293 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:57:18,297 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-26 11:57:18,297 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-26 11:57:18,321 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2023-11-26 11:57:18,321 INFO L513 LassoAnalysis]: Proved termination. [2023-11-26 11:57:18,322 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, v_rep(select #length ULTIMATE.start_main_~#A~0#1.base)_1) = -8*ULTIMATE.start_main_~i~0#1 + 2047*v_rep(select #length ULTIMATE.start_main_~#A~0#1.base)_1 Supporting invariants [] [2023-11-26 11:57:18,344 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:18,360 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2023-11-26 11:57:18,373 WARN L1572 BoogieBacktranslator]: Unfinished Backtranslation: ArrayAccessExpression #length[~#A~0!base] could not be translated [2023-11-26 11:57:18,399 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:18,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:57:18,425 INFO L262 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-26 11:57:18,427 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:57:18,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:57:18,446 INFO L262 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-26 11:57:18,447 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:57:18,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:18,551 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-26 11:57:18,557 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:18,639 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 49 transitions. Complement of second has 8 states. [2023-11-26 11:57:18,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2023-11-26 11:57:18,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:18,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 24 transitions. [2023-11-26 11:57:18,650 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 24 transitions. Stem has 2 letters. Loop has 2 letters. [2023-11-26 11:57:18,650 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:57:18,650 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 24 transitions. Stem has 4 letters. Loop has 2 letters. [2023-11-26 11:57:18,651 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:57:18,651 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 24 transitions. Stem has 2 letters. Loop has 4 letters. [2023-11-26 11:57:18,651 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 11:57:18,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 49 transitions. [2023-11-26 11:57:18,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:18,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 10 states and 12 transitions. [2023-11-26 11:57:18,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-26 11:57:18,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2023-11-26 11:57:18,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 12 transitions. [2023-11-26 11:57:18,662 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:57:18,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10 states and 12 transitions. [2023-11-26 11:57:18,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 12 transitions. [2023-11-26 11:57:18,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2023-11-26 11:57:18,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.2) internal successors, (12), 9 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:18,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 12 transitions. [2023-11-26 11:57:18,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10 states and 12 transitions. [2023-11-26 11:57:18,695 INFO L428 stractBuchiCegarLoop]: Abstraction has 10 states and 12 transitions. [2023-11-26 11:57:18,695 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:57:18,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 12 transitions. [2023-11-26 11:57:18,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:18,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:57:18,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:57:18,697 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2023-11-26 11:57:18,697 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2023-11-26 11:57:18,697 INFO L748 eck$LassoCheckResult]: Stem: 113#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 116#L24-3 assume !(main_~i~0#1 < 1024); 117#L24-4 main_~i~0#1 := 0; 115#L28-4 [2023-11-26 11:57:18,697 INFO L750 eck$LassoCheckResult]: Loop: 115#L28-4 call main_#t~mem4#1 := read~int#1(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 110#L28-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 111#L29 assume !(main_~i~0#1 >= 1023); 112#L28-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 115#L28-4 [2023-11-26 11:57:18,698 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:18,698 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2023-11-26 11:57:18,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:18,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934172464] [2023-11-26 11:57:18,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:18,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:18,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:57:18,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:18,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:57:18,773 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934172464] [2023-11-26 11:57:18,773 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1934172464] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:57:18,773 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:57:18,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:57:18,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443987752] [2023-11-26 11:57:18,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:57:18,777 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:57:18,777 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:18,778 INFO L85 PathProgramCache]: Analyzing trace with hash 1544328, now seen corresponding path program 1 times [2023-11-26 11:57:18,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:18,778 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684440853] [2023-11-26 11:57:18,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:18,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:18,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:18,786 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:57:18,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:18,794 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:57:18,850 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:57:18,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:57:18,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:57:18,854 INFO L87 Difference]: Start difference. First operand 10 states and 12 transitions. cyclomatic complexity: 4 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:18,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:57:18,878 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2023-11-26 11:57:18,878 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2023-11-26 11:57:18,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:18,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2023-11-26 11:57:18,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2023-11-26 11:57:18,880 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2023-11-26 11:57:18,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2023-11-26 11:57:18,881 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:57:18,881 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2023-11-26 11:57:18,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2023-11-26 11:57:18,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 10. [2023-11-26 11:57:18,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.1) internal successors, (11), 9 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:18,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 11 transitions. [2023-11-26 11:57:18,884 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10 states and 11 transitions. [2023-11-26 11:57:18,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:57:18,885 INFO L428 stractBuchiCegarLoop]: Abstraction has 10 states and 11 transitions. [2023-11-26 11:57:18,886 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:57:18,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 11 transitions. [2023-11-26 11:57:18,886 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:18,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:57:18,887 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:57:18,887 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2023-11-26 11:57:18,888 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2023-11-26 11:57:18,888 INFO L748 eck$LassoCheckResult]: Stem: 144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 147#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 139#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 140#L24-3 assume !(main_~i~0#1 < 1024); 148#L24-4 main_~i~0#1 := 0; 146#L28-4 [2023-11-26 11:57:18,888 INFO L750 eck$LassoCheckResult]: Loop: 146#L28-4 call main_#t~mem4#1 := read~int#1(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 141#L28-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 142#L29 assume !(main_~i~0#1 >= 1023); 143#L28-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 146#L28-4 [2023-11-26 11:57:18,889 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:18,889 INFO L85 PathProgramCache]: Analyzing trace with hash 889660429, now seen corresponding path program 1 times [2023-11-26 11:57:18,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:18,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249084857] [2023-11-26 11:57:18,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:18,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:18,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:57:18,957 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:18,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:57:18,958 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249084857] [2023-11-26 11:57:18,958 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249084857] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:57:18,958 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [455259141] [2023-11-26 11:57:18,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:18,959 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:57:18,959 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:18,960 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:57:18,972 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2023-11-26 11:57:19,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:57:19,024 INFO L262 TraceCheckSpWp]: Trace formula consists of 45 conjuncts, 3 conjunts are in the unsatisfiable core [2023-11-26 11:57:19,025 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:57:19,038 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:19,038 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 11:57:19,060 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:19,060 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [455259141] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 11:57:19,060 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 11:57:19,060 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2023-11-26 11:57:19,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687073046] [2023-11-26 11:57:19,061 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 11:57:19,061 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:57:19,062 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:19,062 INFO L85 PathProgramCache]: Analyzing trace with hash 1544328, now seen corresponding path program 2 times [2023-11-26 11:57:19,062 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:19,062 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336729506] [2023-11-26 11:57:19,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:19,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:19,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:19,069 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:57:19,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:19,075 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:57:19,135 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:57:19,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2023-11-26 11:57:19,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2023-11-26 11:57:19,138 INFO L87 Difference]: Start difference. First operand 10 states and 11 transitions. cyclomatic complexity: 3 Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:19,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:57:19,205 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2023-11-26 11:57:19,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2023-11-26 11:57:19,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:19,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2023-11-26 11:57:19,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2023-11-26 11:57:19,220 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2023-11-26 11:57:19,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2023-11-26 11:57:19,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:57:19,221 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2023-11-26 11:57:19,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2023-11-26 11:57:19,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 16. [2023-11-26 11:57:19,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.0625) internal successors, (17), 15 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:19,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 17 transitions. [2023-11-26 11:57:19,227 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 17 transitions. [2023-11-26 11:57:19,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-26 11:57:19,229 INFO L428 stractBuchiCegarLoop]: Abstraction has 16 states and 17 transitions. [2023-11-26 11:57:19,229 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:57:19,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 17 transitions. [2023-11-26 11:57:19,231 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:19,231 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:57:19,231 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:57:19,232 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1] [2023-11-26 11:57:19,232 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2023-11-26 11:57:19,233 INFO L748 eck$LassoCheckResult]: Stem: 221#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 222#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 224#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 216#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 217#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 225#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 231#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 230#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 229#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 228#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 227#L24-3 assume !(main_~i~0#1 < 1024); 226#L24-4 main_~i~0#1 := 0; 223#L28-4 [2023-11-26 11:57:19,233 INFO L750 eck$LassoCheckResult]: Loop: 223#L28-4 call main_#t~mem4#1 := read~int#1(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 218#L28-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 219#L29 assume !(main_~i~0#1 >= 1023); 220#L28-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 223#L28-4 [2023-11-26 11:57:19,234 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:19,234 INFO L85 PathProgramCache]: Analyzing trace with hash 833936659, now seen corresponding path program 2 times [2023-11-26 11:57:19,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:19,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131827996] [2023-11-26 11:57:19,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:19,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:19,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:57:19,477 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:19,478 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:57:19,478 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131827996] [2023-11-26 11:57:19,478 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131827996] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:57:19,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1791138343] [2023-11-26 11:57:19,479 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-26 11:57:19,479 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:57:19,480 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:19,483 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2023-11-26 11:57:19,483 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:57:19,521 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2023-11-26 11:57:19,565 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-26 11:57:19,566 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 11:57:19,567 INFO L262 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-26 11:57:19,568 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:57:19,601 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:19,601 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 11:57:19,697 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:19,699 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1791138343] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 11:57:19,699 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 11:57:19,699 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2023-11-26 11:57:19,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114435216] [2023-11-26 11:57:19,700 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 11:57:19,701 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:57:19,702 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:19,702 INFO L85 PathProgramCache]: Analyzing trace with hash 1544328, now seen corresponding path program 3 times [2023-11-26 11:57:19,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:19,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161044762] [2023-11-26 11:57:19,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:19,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:19,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:19,713 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:57:19,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:19,720 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:57:19,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:57:19,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2023-11-26 11:57:19,778 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2023-11-26 11:57:19,779 INFO L87 Difference]: Start difference. First operand 16 states and 17 transitions. cyclomatic complexity: 3 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 13 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:19,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:57:19,905 INFO L93 Difference]: Finished difference Result 63 states and 64 transitions. [2023-11-26 11:57:19,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 64 transitions. [2023-11-26 11:57:19,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:19,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 63 states and 64 transitions. [2023-11-26 11:57:19,912 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43 [2023-11-26 11:57:19,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43 [2023-11-26 11:57:19,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63 states and 64 transitions. [2023-11-26 11:57:19,914 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:57:19,914 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63 states and 64 transitions. [2023-11-26 11:57:19,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states and 64 transitions. [2023-11-26 11:57:19,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 28. [2023-11-26 11:57:19,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 27 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:19,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 29 transitions. [2023-11-26 11:57:19,922 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 29 transitions. [2023-11-26 11:57:19,922 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-26 11:57:19,923 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 29 transitions. [2023-11-26 11:57:19,924 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:57:19,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 29 transitions. [2023-11-26 11:57:19,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:19,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:57:19,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:57:19,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1] [2023-11-26 11:57:19,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2023-11-26 11:57:19,929 INFO L748 eck$LassoCheckResult]: Stem: 381#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 385#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 377#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 378#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 386#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 404#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 403#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 402#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 401#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 400#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 399#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 398#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 397#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 396#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 395#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 394#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 393#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 392#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 391#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 390#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 389#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 388#L24-3 assume !(main_~i~0#1 < 1024); 387#L24-4 main_~i~0#1 := 0; 384#L28-4 [2023-11-26 11:57:19,929 INFO L750 eck$LassoCheckResult]: Loop: 384#L28-4 call main_#t~mem4#1 := read~int#1(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 379#L28-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 380#L29 assume !(main_~i~0#1 >= 1023); 383#L28-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 384#L28-4 [2023-11-26 11:57:19,930 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:19,930 INFO L85 PathProgramCache]: Analyzing trace with hash 2127272351, now seen corresponding path program 3 times [2023-11-26 11:57:19,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:19,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343905951] [2023-11-26 11:57:19,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:19,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:19,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:57:20,366 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:20,367 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:57:20,367 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343905951] [2023-11-26 11:57:20,367 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343905951] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:57:20,367 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [648860636] [2023-11-26 11:57:20,368 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-26 11:57:20,368 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:57:20,368 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:20,369 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:57:20,396 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2023-11-26 11:57:20,554 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2023-11-26 11:57:20,554 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 11:57:20,556 INFO L262 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 12 conjunts are in the unsatisfiable core [2023-11-26 11:57:20,558 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:57:20,646 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:20,647 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 11:57:21,003 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:21,004 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [648860636] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 11:57:21,004 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 11:57:21,004 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 25 [2023-11-26 11:57:21,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124424422] [2023-11-26 11:57:21,005 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 11:57:21,005 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:57:21,006 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:21,006 INFO L85 PathProgramCache]: Analyzing trace with hash 1544328, now seen corresponding path program 4 times [2023-11-26 11:57:21,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:21,006 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550555015] [2023-11-26 11:57:21,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:21,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:21,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:21,016 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:57:21,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:21,023 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:57:21,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:57:21,081 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2023-11-26 11:57:21,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2023-11-26 11:57:21,083 INFO L87 Difference]: Start difference. First operand 28 states and 29 transitions. cyclomatic complexity: 3 Second operand has 25 states, 25 states have (on average 1.96) internal successors, (49), 25 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:21,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:57:21,506 INFO L93 Difference]: Finished difference Result 135 states and 136 transitions. [2023-11-26 11:57:21,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 135 states and 136 transitions. [2023-11-26 11:57:21,509 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:21,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 135 states to 135 states and 136 transitions. [2023-11-26 11:57:21,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91 [2023-11-26 11:57:21,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91 [2023-11-26 11:57:21,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135 states and 136 transitions. [2023-11-26 11:57:21,513 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:57:21,513 INFO L218 hiAutomatonCegarLoop]: Abstraction has 135 states and 136 transitions. [2023-11-26 11:57:21,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states and 136 transitions. [2023-11-26 11:57:21,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 52. [2023-11-26 11:57:21,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 51 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:21,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 53 transitions. [2023-11-26 11:57:21,519 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 53 transitions. [2023-11-26 11:57:21,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-26 11:57:21,520 INFO L428 stractBuchiCegarLoop]: Abstraction has 52 states and 53 transitions. [2023-11-26 11:57:21,520 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:57:21,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 53 transitions. [2023-11-26 11:57:21,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:21,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:57:21,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:57:21,523 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1] [2023-11-26 11:57:21,523 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2023-11-26 11:57:21,524 INFO L748 eck$LassoCheckResult]: Stem: 710#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 711#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 714#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 706#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 707#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 715#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 757#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 756#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 755#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 754#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 753#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 752#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 751#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 750#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 749#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 748#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 747#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 746#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 745#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 744#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 743#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 742#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 741#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 740#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 739#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 738#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 737#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 736#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 735#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 734#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 733#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 732#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 731#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 730#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 729#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 728#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 727#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 726#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 725#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 724#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 723#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 722#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 721#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 720#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 719#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 718#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 717#L24-3 assume !(main_~i~0#1 < 1024); 716#L24-4 main_~i~0#1 := 0; 713#L28-4 [2023-11-26 11:57:21,524 INFO L750 eck$LassoCheckResult]: Loop: 713#L28-4 call main_#t~mem4#1 := read~int#1(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 708#L28-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 709#L29 assume !(main_~i~0#1 >= 1023); 712#L28-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 713#L28-4 [2023-11-26 11:57:21,524 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:21,524 INFO L85 PathProgramCache]: Analyzing trace with hash 828161207, now seen corresponding path program 4 times [2023-11-26 11:57:21,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:21,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061835095] [2023-11-26 11:57:21,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:21,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:21,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:57:22,225 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:22,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:57:22,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1061835095] [2023-11-26 11:57:22,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1061835095] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:57:22,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [576858198] [2023-11-26 11:57:22,226 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-26 11:57:22,226 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:57:22,227 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:22,230 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:57:22,232 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2023-11-26 11:57:22,365 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-26 11:57:22,366 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 11:57:22,368 INFO L262 TraceCheckSpWp]: Trace formula consists of 276 conjuncts, 24 conjunts are in the unsatisfiable core [2023-11-26 11:57:22,371 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:57:22,458 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:22,459 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 11:57:23,417 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:23,417 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [576858198] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 11:57:23,417 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 11:57:23,417 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 49 [2023-11-26 11:57:23,417 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1882222302] [2023-11-26 11:57:23,418 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 11:57:23,418 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:57:23,418 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:23,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1544328, now seen corresponding path program 5 times [2023-11-26 11:57:23,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:23,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518293895] [2023-11-26 11:57:23,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:23,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:23,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:23,424 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:57:23,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:23,433 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:57:23,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:57:23,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2023-11-26 11:57:23,486 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2023-11-26 11:57:23,488 INFO L87 Difference]: Start difference. First operand 52 states and 53 transitions. cyclomatic complexity: 3 Second operand has 49 states, 49 states have (on average 1.9795918367346939) internal successors, (97), 49 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:24,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:57:24,176 INFO L93 Difference]: Finished difference Result 279 states and 280 transitions. [2023-11-26 11:57:24,176 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 279 states and 280 transitions. [2023-11-26 11:57:24,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:24,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 279 states to 279 states and 280 transitions. [2023-11-26 11:57:24,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 187 [2023-11-26 11:57:24,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 187 [2023-11-26 11:57:24,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 279 states and 280 transitions. [2023-11-26 11:57:24,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:57:24,199 INFO L218 hiAutomatonCegarLoop]: Abstraction has 279 states and 280 transitions. [2023-11-26 11:57:24,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279 states and 280 transitions. [2023-11-26 11:57:24,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279 to 100. [2023-11-26 11:57:24,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.01) internal successors, (101), 99 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:24,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 101 transitions. [2023-11-26 11:57:24,219 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 101 transitions. [2023-11-26 11:57:24,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2023-11-26 11:57:24,221 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 101 transitions. [2023-11-26 11:57:24,222 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:57:24,222 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 101 transitions. [2023-11-26 11:57:24,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:24,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:57:24,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:57:24,228 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1] [2023-11-26 11:57:24,229 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2023-11-26 11:57:24,230 INFO L748 eck$LassoCheckResult]: Stem: 1375#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 1376#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 1379#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1371#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1372#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1380#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1470#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1469#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1468#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1467#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1466#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1465#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1464#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1463#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1462#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1461#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1460#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1459#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1458#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1457#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1456#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1455#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1454#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1453#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1452#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1451#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1450#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1449#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1448#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1447#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1446#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1445#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1444#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1443#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1442#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1441#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1440#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1439#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1438#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1437#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1436#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1435#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1434#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1433#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1432#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1431#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1430#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1429#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1428#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1427#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1426#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1425#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1424#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1423#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1422#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1421#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1420#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1419#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1418#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1417#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1416#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1415#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1414#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1413#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1412#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1411#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1410#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1409#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1408#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1407#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1406#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1405#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1404#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1403#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1402#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1401#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1400#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1399#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1398#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1397#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1396#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1395#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1394#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1393#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1392#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1391#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1390#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1389#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1388#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1387#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1386#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1385#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1384#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1383#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1382#L24-3 assume !(main_~i~0#1 < 1024); 1381#L24-4 main_~i~0#1 := 0; 1378#L28-4 [2023-11-26 11:57:24,234 INFO L750 eck$LassoCheckResult]: Loop: 1378#L28-4 call main_#t~mem4#1 := read~int#1(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 1373#L28-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 1374#L29 assume !(main_~i~0#1 >= 1023); 1377#L28-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1378#L28-4 [2023-11-26 11:57:24,234 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:24,235 INFO L85 PathProgramCache]: Analyzing trace with hash 830581479, now seen corresponding path program 5 times [2023-11-26 11:57:24,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:24,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538574437] [2023-11-26 11:57:24,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:24,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:24,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:57:27,240 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:27,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:57:27,241 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538574437] [2023-11-26 11:57:27,241 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538574437] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:57:27,241 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [705093690] [2023-11-26 11:57:27,241 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-26 11:57:27,241 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:57:27,242 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:27,246 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:57:27,275 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2023-11-26 11:57:33,013 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2023-11-26 11:57:33,013 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 11:57:33,024 INFO L262 TraceCheckSpWp]: Trace formula consists of 540 conjuncts, 48 conjunts are in the unsatisfiable core [2023-11-26 11:57:33,031 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 11:57:33,239 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:33,240 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 11:57:37,175 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:37,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [705093690] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 11:57:37,175 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 11:57:37,176 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 97 [2023-11-26 11:57:37,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467429810] [2023-11-26 11:57:37,176 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 11:57:37,177 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:57:37,177 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:37,178 INFO L85 PathProgramCache]: Analyzing trace with hash 1544328, now seen corresponding path program 6 times [2023-11-26 11:57:37,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:37,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481601245] [2023-11-26 11:57:37,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:37,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:37,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:37,184 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:57:37,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:57:37,188 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:57:37,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:57:37,235 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2023-11-26 11:57:37,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2023-11-26 11:57:37,239 INFO L87 Difference]: Start difference. First operand 100 states and 101 transitions. cyclomatic complexity: 3 Second operand has 97 states, 97 states have (on average 1.9896907216494846) internal successors, (193), 97 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:40,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:57:40,346 INFO L93 Difference]: Finished difference Result 567 states and 568 transitions. [2023-11-26 11:57:40,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 567 states and 568 transitions. [2023-11-26 11:57:40,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:40,357 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 567 states to 567 states and 568 transitions. [2023-11-26 11:57:40,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 379 [2023-11-26 11:57:40,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 379 [2023-11-26 11:57:40,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 567 states and 568 transitions. [2023-11-26 11:57:40,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:57:40,359 INFO L218 hiAutomatonCegarLoop]: Abstraction has 567 states and 568 transitions. [2023-11-26 11:57:40,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states and 568 transitions. [2023-11-26 11:57:40,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 196. [2023-11-26 11:57:40,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 195 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:57:40,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 197 transitions. [2023-11-26 11:57:40,372 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196 states and 197 transitions. [2023-11-26 11:57:40,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2023-11-26 11:57:40,377 INFO L428 stractBuchiCegarLoop]: Abstraction has 196 states and 197 transitions. [2023-11-26 11:57:40,377 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:57:40,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 197 transitions. [2023-11-26 11:57:40,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2023-11-26 11:57:40,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:57:40,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:57:40,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 94, 1, 1, 1, 1] [2023-11-26 11:57:40,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2023-11-26 11:57:40,383 INFO L748 eck$LassoCheckResult]: Stem: 2712#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 2713#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 2716#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2708#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2709#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2717#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2903#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2902#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2901#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2900#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2899#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2898#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2897#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2896#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2895#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2894#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2893#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2892#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2891#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2890#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2889#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2888#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2887#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2886#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2885#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2884#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2883#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2882#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2881#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2880#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2879#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2878#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2877#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2876#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2875#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2874#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2873#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2872#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2871#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2870#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2869#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2868#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2867#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2866#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2865#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2864#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2863#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2862#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2861#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2860#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2859#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2858#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2857#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2856#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2855#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2854#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2853#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2852#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2851#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2850#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2849#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2848#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2847#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2846#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2845#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2844#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2843#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2842#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2841#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2840#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2839#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2838#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2837#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2836#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2835#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2834#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2833#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2832#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2831#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2830#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2829#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2828#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2827#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2826#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2825#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2824#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2823#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2822#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2821#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2820#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2819#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2818#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2817#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2816#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2815#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2814#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2813#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2812#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2811#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2810#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2809#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2808#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2807#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2806#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2805#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2804#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2803#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2802#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2801#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2800#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2799#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2798#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2797#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2796#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2795#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2794#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2793#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2792#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2791#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2790#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2789#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2788#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2787#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2786#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2785#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2784#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2783#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2782#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2781#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2780#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2779#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2778#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2777#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2776#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2775#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2774#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2773#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2772#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2771#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2770#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2769#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2768#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2767#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2766#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2765#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2764#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2763#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2762#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2761#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2760#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2759#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2758#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2757#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2756#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2755#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2754#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2753#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2752#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2751#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2750#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2749#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2748#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2747#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2746#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2745#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2744#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2743#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2742#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2741#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2740#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2739#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2738#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2737#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2736#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2735#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2734#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2733#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2732#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2731#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2730#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2729#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2728#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2727#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2726#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2725#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2724#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2723#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2722#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2721#L24-3 assume !!(main_~i~0#1 < 1024);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2720#L24-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2719#L24-3 assume !(main_~i~0#1 < 1024); 2718#L24-4 main_~i~0#1 := 0; 2715#L28-4 [2023-11-26 11:57:40,384 INFO L750 eck$LassoCheckResult]: Loop: 2715#L28-4 call main_#t~mem4#1 := read~int#1(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 2710#L28-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 2711#L29 assume !(main_~i~0#1 >= 1023); 2714#L28-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2715#L28-4 [2023-11-26 11:57:40,384 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:57:40,384 INFO L85 PathProgramCache]: Analyzing trace with hash 1165371207, now seen corresponding path program 6 times [2023-11-26 11:57:40,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:57:40,385 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [898251593] [2023-11-26 11:57:40,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:57:40,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:57:40,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:57:48,737 INFO L134 CoverageAnalysis]: Checked inductivity of 8836 backedges. 0 proven. 8836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:57:48,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:57:48,737 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [898251593] [2023-11-26 11:57:48,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [898251593] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 11:57:48,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2091184979] [2023-11-26 11:57:48,738 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-26 11:57:48,738 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 11:57:48,738 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:57:48,739 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 11:57:48,746 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_02149597-e6c0-486e-b989-80f235b9830e/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process