./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pipeline.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pipeline.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c42f0f019aa30bac52b753d657fd0a7a27ad0fcef5ea61d179259276789b8861 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 12:06:22,257 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 12:06:22,331 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 12:06:22,337 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 12:06:22,338 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 12:06:22,364 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 12:06:22,365 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 12:06:22,365 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 12:06:22,366 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 12:06:22,367 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 12:06:22,368 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 12:06:22,368 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 12:06:22,369 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 12:06:22,370 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 12:06:22,370 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 12:06:22,371 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 12:06:22,372 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 12:06:22,372 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 12:06:22,373 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 12:06:22,374 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 12:06:22,374 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 12:06:22,375 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 12:06:22,375 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 12:06:22,376 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 12:06:22,377 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 12:06:22,377 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 12:06:22,378 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 12:06:22,378 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 12:06:22,379 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 12:06:22,379 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 12:06:22,380 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 12:06:22,380 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 12:06:22,381 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 12:06:22,381 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 12:06:22,382 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 12:06:22,382 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 12:06:22,383 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 12:06:22,383 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 12:06:22,384 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c42f0f019aa30bac52b753d657fd0a7a27ad0fcef5ea61d179259276789b8861 [2023-11-26 12:06:22,619 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 12:06:22,656 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 12:06:22,659 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 12:06:22,660 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 12:06:22,661 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 12:06:22,663 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/pipeline.cil-2.c [2023-11-26 12:06:25,777 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 12:06:26,096 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 12:06:26,097 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/sv-benchmarks/c/systemc/pipeline.cil-2.c [2023-11-26 12:06:26,111 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/data/94ba9bd89/0aa3843555cf4e05924f7da99388b6d3/FLAG13b739310 [2023-11-26 12:06:26,127 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/data/94ba9bd89/0aa3843555cf4e05924f7da99388b6d3 [2023-11-26 12:06:26,130 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 12:06:26,132 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 12:06:26,134 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 12:06:26,134 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 12:06:26,147 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 12:06:26,147 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,149 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6be9afa8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26, skipping insertion in model container [2023-11-26 12:06:26,149 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,201 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 12:06:26,437 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:06:26,458 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 12:06:26,522 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:06:26,541 INFO L206 MainTranslator]: Completed translation [2023-11-26 12:06:26,542 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26 WrapperNode [2023-11-26 12:06:26,542 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 12:06:26,543 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 12:06:26,544 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 12:06:26,544 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 12:06:26,552 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,564 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,631 INFO L138 Inliner]: procedures = 20, calls = 18, calls flagged for inlining = 13, calls inlined = 25, statements flattened = 1052 [2023-11-26 12:06:26,631 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 12:06:26,633 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 12:06:26,633 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 12:06:26,634 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 12:06:26,647 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,651 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,659 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,690 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 12:06:26,690 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,690 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,711 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,730 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,734 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,739 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,747 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 12:06:26,748 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 12:06:26,748 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 12:06:26,749 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 12:06:26,750 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (1/1) ... [2023-11-26 12:06:26,756 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:06:26,769 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:06:26,782 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:06:26,819 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bdff0bfe-1406-4a44-867d-a50be8ddddbb/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 12:06:26,842 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 12:06:26,843 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 12:06:26,843 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 12:06:26,844 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 12:06:26,993 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 12:06:26,995 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 12:06:28,324 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 12:06:28,362 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 12:06:28,362 INFO L309 CfgBuilder]: Removed 7 assume(true) statements. [2023-11-26 12:06:28,364 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:06:28 BoogieIcfgContainer [2023-11-26 12:06:28,364 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 12:06:28,365 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 12:06:28,366 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 12:06:28,370 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 12:06:28,372 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:06:28,372 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 12:06:26" (1/3) ... [2023-11-26 12:06:28,374 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4fc051b3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:06:28, skipping insertion in model container [2023-11-26 12:06:28,374 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:06:28,374 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:06:26" (2/3) ... [2023-11-26 12:06:28,375 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4fc051b3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:06:28, skipping insertion in model container [2023-11-26 12:06:28,375 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:06:28,375 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:06:28" (3/3) ... [2023-11-26 12:06:28,377 INFO L332 chiAutomizerObserver]: Analyzing ICFG pipeline.cil-2.c [2023-11-26 12:06:28,478 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 12:06:28,479 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 12:06:28,479 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 12:06:28,479 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 12:06:28,479 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 12:06:28,480 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 12:06:28,480 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 12:06:28,480 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 12:06:28,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 423 states, 422 states have (on average 1.8127962085308056) internal successors, (765), 422 states have internal predecessors, (765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:28,556 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 361 [2023-11-26 12:06:28,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:28,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:28,569 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:28,569 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:28,569 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 12:06:28,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 423 states, 422 states have (on average 1.8127962085308056) internal successors, (765), 422 states have internal predecessors, (765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:28,588 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 361 [2023-11-26 12:06:28,589 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:28,589 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:28,593 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:28,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:28,605 INFO L748 eck$LassoCheckResult]: Stem: 127#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 358#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 32#L256true assume !(1 == ~main_in1_req_up~0); 9#L256-2true assume !(1 == ~main_in2_req_up~0); 26#L267-1true assume !(1 == ~main_sum_req_up~0); 304#L278-1true assume !(1 == ~main_diff_req_up~0); 2#L289-1true assume !(1 == ~main_pres_req_up~0); 255#L300-1true assume !(1 == ~main_dbl_req_up~0); 150#L311-1true assume !(1 == ~main_zero_req_up~0); 328#L322-1true assume !(1 == ~main_clk_req_up~0); 195#L333-1true assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 125#L351-1true assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 19#L356-1true assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0; 119#L361-1true assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 341#L366-1true assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 114#L371-1true assume !(0 == ~main_in1_ev~0); 44#L376-1true assume !(0 == ~main_in2_ev~0); 306#L381-1true assume !(0 == ~main_sum_ev~0); 134#L386-1true assume !(0 == ~main_diff_ev~0); 323#L391-1true assume !(0 == ~main_pres_ev~0); 232#L396-1true assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 82#L401-1true assume !(0 == ~main_zero_ev~0); 87#L406-1true assume !(0 == ~main_clk_ev~0); 353#L411-1true assume !(0 == ~main_clk_pos_edge~0); 338#L416-1true assume !(0 == ~main_clk_neg_edge~0); 395#L421-1true assume !(1 == ~main_clk_pos_edge~0); 291#L426-1true assume !(1 == ~main_clk_pos_edge~0); 107#L431-1true assume !(1 == ~main_clk_pos_edge~0); 236#L436-1true assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 95#L441-1true assume !(1 == ~main_clk_pos_edge~0); 386#L446-1true assume !(1 == ~main_in1_ev~0); 280#L451-1true assume !(1 == ~main_in2_ev~0); 396#L456-1true assume !(1 == ~main_sum_ev~0); 138#L461-1true assume !(1 == ~main_diff_ev~0); 380#L466-1true assume !(1 == ~main_pres_ev~0); 407#L471-1true assume !(1 == ~main_dbl_ev~0); 27#L476-1true assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 196#L481-1true assume !(1 == ~main_clk_ev~0); 92#L486-1true assume !(1 == ~main_clk_pos_edge~0); 29#L491-1true assume !(1 == ~main_clk_neg_edge~0); 250#L742-1true [2023-11-26 12:06:28,611 INFO L750 eck$LassoCheckResult]: Loop: 250#L742-1true assume !false; 376#L503true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 209#L229true assume false; 63#eval_returnLabel#1true havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 256#L509true assume !(1 == ~main_in1_req_up~0); 175#L509-2true assume !(1 == ~main_in2_req_up~0); 339#L520-1true assume !(1 == ~main_sum_req_up~0); 223#L531-1true assume !(1 == ~main_diff_req_up~0); 144#L542-1true assume !(1 == ~main_pres_req_up~0); 394#L553-1true assume !(1 == ~main_dbl_req_up~0); 161#L564-1true assume !(1 == ~main_zero_req_up~0); 245#L575-1true assume !(1 == ~main_clk_req_up~0); 343#L586-1true start_simulation_~kernel_st~0#1 := 3; 370#L605true assume !(0 == ~main_in1_ev~0); 287#L605-2true assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 17#L610-1true assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 194#L615-1true assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 191#L620-1true assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 188#L625-1true assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 271#L630-1true assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 329#L635-1true assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 327#L640-1true assume !(0 == ~main_clk_pos_edge~0); 85#L645-1true assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 113#L650-1true assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 132#L655-1true assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 207#L660-1true assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 241#L665-1true assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 290#L670-1true assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 184#L675-1true assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 239#L680-1true assume !(1 == ~main_in2_ev~0); 313#L685-1true assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 218#L690-1true assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 406#L695-1true assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 277#L700-1true assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 269#L705-1true assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 375#L710-1true assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 180#L715-1true assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 136#L720-1true assume !(1 == ~main_clk_neg_edge~0); 167#L725-1true assume 0 == ~N_generate_st~0; 250#L742-1true [2023-11-26 12:06:28,617 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:28,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 1 times [2023-11-26 12:06:28,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:28,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893238109] [2023-11-26 12:06:28,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:28,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:28,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:29,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:29,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:29,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893238109] [2023-11-26 12:06:29,066 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893238109] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:29,066 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:29,067 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:29,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [647280658] [2023-11-26 12:06:29,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:29,076 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:29,078 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:29,078 INFO L85 PathProgramCache]: Analyzing trace with hash -727719859, now seen corresponding path program 1 times [2023-11-26 12:06:29,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:29,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163633644] [2023-11-26 12:06:29,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:29,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:29,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:29,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:29,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:29,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163633644] [2023-11-26 12:06:29,137 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163633644] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:29,137 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:29,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:06:29,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198867976] [2023-11-26 12:06:29,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:29,140 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:29,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:29,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-26 12:06:29,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-26 12:06:29,199 INFO L87 Difference]: Start difference. First operand has 423 states, 422 states have (on average 1.8127962085308056) internal successors, (765), 422 states have internal predecessors, (765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 19.5) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:29,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:29,247 INFO L93 Difference]: Finished difference Result 417 states and 745 transitions. [2023-11-26 12:06:29,249 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417 states and 745 transitions. [2023-11-26 12:06:29,254 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2023-11-26 12:06:29,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417 states to 416 states and 744 transitions. [2023-11-26 12:06:29,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 416 [2023-11-26 12:06:29,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 416 [2023-11-26 12:06:29,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 416 states and 744 transitions. [2023-11-26 12:06:29,276 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:29,276 INFO L218 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2023-11-26 12:06:29,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states and 744 transitions. [2023-11-26 12:06:29,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 416. [2023-11-26 12:06:29,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 416 states, 416 states have (on average 1.7884615384615385) internal successors, (744), 415 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:29,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 416 states to 416 states and 744 transitions. [2023-11-26 12:06:29,371 INFO L240 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2023-11-26 12:06:29,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-26 12:06:29,379 INFO L428 stractBuchiCegarLoop]: Abstraction has 416 states and 744 transitions. [2023-11-26 12:06:29,380 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 12:06:29,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 416 states and 744 transitions. [2023-11-26 12:06:29,386 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2023-11-26 12:06:29,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:29,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:29,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:29,391 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:29,392 INFO L748 eck$LassoCheckResult]: Stem: 1071#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 912#L256 assume !(1 == ~main_in1_req_up~0); 867#L256-2 assume !(1 == ~main_in2_req_up~0); 869#L267-1 assume !(1 == ~main_sum_req_up~0); 900#L278-1 assume !(1 == ~main_diff_req_up~0); 850#L289-1 assume !(1 == ~main_pres_req_up~0); 851#L300-1 assume !(1 == ~main_dbl_req_up~0); 960#L311-1 assume !(1 == ~main_zero_req_up~0); 1103#L322-1 assume !(1 == ~main_clk_req_up~0); 1078#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1069#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 889#L356-1 assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0; 890#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1063#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 1058#L371-1 assume !(0 == ~main_in1_ev~0); 938#L376-1 assume !(0 == ~main_in2_ev~0); 939#L381-1 assume !(0 == ~main_sum_ev~0); 1080#L386-1 assume !(0 == ~main_diff_ev~0); 1081#L391-1 assume !(0 == ~main_pres_ev~0); 1190#L396-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 1008#L401-1 assume !(0 == ~main_zero_ev~0); 1009#L406-1 assume !(0 == ~main_clk_ev~0); 1016#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1249#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1250#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1236#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1047#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1048#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 1025#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1026#L446-1 assume !(1 == ~main_in1_ev~0); 1228#L451-1 assume !(1 == ~main_in2_ev~0); 1229#L456-1 assume !(1 == ~main_sum_ev~0); 1087#L461-1 assume !(1 == ~main_diff_ev~0); 1088#L466-1 assume !(1 == ~main_pres_ev~0); 1263#L471-1 assume !(1 == ~main_dbl_ev~0); 902#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 903#L481-1 assume !(1 == ~main_clk_ev~0); 1023#L486-1 assume !(1 == ~main_clk_pos_edge~0); 907#L491-1 assume !(1 == ~main_clk_neg_edge~0); 908#L742-1 [2023-11-26 12:06:29,393 INFO L750 eck$LassoCheckResult]: Loop: 908#L742-1 assume !false; 1206#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 942#L229 assume !false; 1168#L147 assume !(0 == ~N_generate_st~0); 973#L151 assume !(0 == ~S1_addsub_st~0); 974#L154 assume !(0 == ~S2_presdbl_st~0); 860#L157 assume !(0 == ~S3_zero_st~0); 862#L160 assume !(0 == ~D_print_st~0); 976#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 977#L509 assume !(1 == ~main_in1_req_up~0); 864#L509-2 assume !(1 == ~main_in2_req_up~0); 1133#L520-1 assume !(1 == ~main_sum_req_up~0); 1181#L531-1 assume !(1 == ~main_diff_req_up~0); 1095#L542-1 assume !(1 == ~main_pres_req_up~0); 871#L553-1 assume !(1 == ~main_dbl_req_up~0); 1107#L564-1 assume !(1 == ~main_zero_req_up~0); 1117#L575-1 assume !(1 == ~main_clk_req_up~0); 1201#L586-1 start_simulation_~kernel_st~0#1 := 3; 1251#L605 assume !(0 == ~main_in1_ev~0); 1235#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 886#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 887#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 1158#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 1153#L625-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 1154#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 1222#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 1246#L640-1 assume !(0 == ~main_clk_pos_edge~0); 1014#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 1015#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 1057#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 1079#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 1167#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 1198#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 1146#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 1147#L680-1 assume !(1 == ~main_in2_ev~0); 1196#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 1176#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 1177#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 1223#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 1220#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 1221#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 1140#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 1083#L720-1 assume !(1 == ~main_clk_neg_edge~0); 1084#L725-1 assume 0 == ~N_generate_st~0; 908#L742-1 [2023-11-26 12:06:29,393 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:29,393 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 2 times [2023-11-26 12:06:29,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:29,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990226047] [2023-11-26 12:06:29,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:29,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:29,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:29,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:29,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:29,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990226047] [2023-11-26 12:06:29,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [990226047] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:29,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:29,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:29,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778444997] [2023-11-26 12:06:29,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:29,532 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:29,533 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:29,533 INFO L85 PathProgramCache]: Analyzing trace with hash 1802774254, now seen corresponding path program 1 times [2023-11-26 12:06:29,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:29,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135597211] [2023-11-26 12:06:29,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:29,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:29,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:29,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:29,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:29,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135597211] [2023-11-26 12:06:29,570 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135597211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:29,570 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:29,570 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:29,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430270727] [2023-11-26 12:06:29,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:29,571 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:29,572 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:29,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:06:29,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:06:29,573 INFO L87 Difference]: Start difference. First operand 416 states and 744 transitions. cyclomatic complexity: 330 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:29,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:29,709 INFO L93 Difference]: Finished difference Result 760 states and 1352 transitions. [2023-11-26 12:06:29,709 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 760 states and 1352 transitions. [2023-11-26 12:06:29,718 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 703 [2023-11-26 12:06:29,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 760 states to 760 states and 1352 transitions. [2023-11-26 12:06:29,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 760 [2023-11-26 12:06:29,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 760 [2023-11-26 12:06:29,728 INFO L73 IsDeterministic]: Start isDeterministic. Operand 760 states and 1352 transitions. [2023-11-26 12:06:29,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:29,732 INFO L218 hiAutomatonCegarLoop]: Abstraction has 760 states and 1352 transitions. [2023-11-26 12:06:29,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 760 states and 1352 transitions. [2023-11-26 12:06:29,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 760 to 760. [2023-11-26 12:06:29,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 760 states, 760 states have (on average 1.7789473684210526) internal successors, (1352), 759 states have internal predecessors, (1352), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:29,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 760 states to 760 states and 1352 transitions. [2023-11-26 12:06:29,762 INFO L240 hiAutomatonCegarLoop]: Abstraction has 760 states and 1352 transitions. [2023-11-26 12:06:29,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:06:29,764 INFO L428 stractBuchiCegarLoop]: Abstraction has 760 states and 1352 transitions. [2023-11-26 12:06:29,764 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 12:06:29,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 760 states and 1352 transitions. [2023-11-26 12:06:29,770 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 703 [2023-11-26 12:06:29,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:29,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:29,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:29,772 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:29,772 INFO L748 eck$LassoCheckResult]: Stem: 2262#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2263#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2100#L256 assume !(1 == ~main_in1_req_up~0); 2054#L256-2 assume !(1 == ~main_in2_req_up~0); 2056#L267-1 assume !(1 == ~main_sum_req_up~0); 2088#L278-1 assume !(1 == ~main_diff_req_up~0); 2037#L289-1 assume !(1 == ~main_pres_req_up~0); 2038#L300-1 assume !(1 == ~main_dbl_req_up~0); 2146#L311-1 assume !(1 == ~main_zero_req_up~0); 2296#L322-1 assume !(1 == ~main_clk_req_up~0); 2270#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2259#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2076#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2077#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2253#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2248#L371-1 assume !(0 == ~main_in1_ev~0); 2124#L376-1 assume !(0 == ~main_in2_ev~0); 2125#L381-1 assume !(0 == ~main_sum_ev~0); 2272#L386-1 assume !(0 == ~main_diff_ev~0); 2273#L391-1 assume !(0 == ~main_pres_ev~0); 2391#L396-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 2196#L401-1 assume !(0 == ~main_zero_ev~0); 2197#L406-1 assume !(0 == ~main_clk_ev~0); 2205#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2472#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2473#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2442#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2236#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2237#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 2213#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2214#L446-1 assume !(1 == ~main_in1_ev~0); 2433#L451-1 assume !(1 == ~main_in2_ev~0); 2434#L456-1 assume !(1 == ~main_sum_ev~0); 2280#L461-1 assume !(1 == ~main_diff_ev~0); 2281#L466-1 assume !(1 == ~main_pres_ev~0); 2492#L471-1 assume !(1 == ~main_dbl_ev~0); 2090#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 2091#L481-1 assume !(1 == ~main_clk_ev~0); 2212#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2095#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2096#L742-1 [2023-11-26 12:06:29,773 INFO L750 eck$LassoCheckResult]: Loop: 2096#L742-1 assume !false; 2408#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2128#L229 assume !false; 2366#L147 assume !(0 == ~N_generate_st~0); 2160#L151 assume !(0 == ~S1_addsub_st~0); 2161#L154 assume !(0 == ~S2_presdbl_st~0); 2047#L157 assume !(0 == ~S3_zero_st~0); 2049#L160 assume !(0 == ~D_print_st~0); 2163#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2164#L509 assume !(1 == ~main_in1_req_up~0); 2328#L509-2 assume !(1 == ~main_in2_req_up~0); 2329#L520-1 assume !(1 == ~main_sum_req_up~0); 2379#L531-1 assume !(1 == ~main_diff_req_up~0); 2288#L542-1 assume !(1 == ~main_pres_req_up~0); 2058#L553-1 assume !(1 == ~main_dbl_req_up~0); 2300#L564-1 assume !(1 == ~main_zero_req_up~0); 2311#L575-1 assume !(1 == ~main_clk_req_up~0); 2403#L586-1 start_simulation_~kernel_st~0#1 := 3; 2474#L605 assume !(0 == ~main_in1_ev~0); 2440#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 2073#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2074#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2356#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2351#L625-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 2352#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 2426#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2467#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2202#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 2203#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 2247#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 2271#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 2365#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 2400#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 2344#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 2345#L680-1 assume !(1 == ~main_in2_ev~0); 2398#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2374#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2375#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2428#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 2424#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 2425#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2338#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 2275#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2276#L725-1 assume 0 == ~N_generate_st~0; 2096#L742-1 [2023-11-26 12:06:29,773 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:29,773 INFO L85 PathProgramCache]: Analyzing trace with hash 782320317, now seen corresponding path program 1 times [2023-11-26 12:06:29,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:29,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707580865] [2023-11-26 12:06:29,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:29,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:29,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:29,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:29,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:29,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707580865] [2023-11-26 12:06:29,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707580865] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:29,847 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:29,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:29,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [603865975] [2023-11-26 12:06:29,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:29,848 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:29,848 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:29,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1802774254, now seen corresponding path program 2 times [2023-11-26 12:06:29,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:29,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353504092] [2023-11-26 12:06:29,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:29,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:29,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:29,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:29,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:29,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353504092] [2023-11-26 12:06:29,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353504092] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:29,884 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:29,884 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:29,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717895107] [2023-11-26 12:06:29,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:29,885 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:29,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:29,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:06:29,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:06:29,886 INFO L87 Difference]: Start difference. First operand 760 states and 1352 transitions. cyclomatic complexity: 596 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:30,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:30,144 INFO L93 Difference]: Finished difference Result 1669 states and 2937 transitions. [2023-11-26 12:06:30,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1669 states and 2937 transitions. [2023-11-26 12:06:30,160 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1572 [2023-11-26 12:06:30,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1669 states to 1669 states and 2937 transitions. [2023-11-26 12:06:30,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1669 [2023-11-26 12:06:30,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1669 [2023-11-26 12:06:30,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1669 states and 2937 transitions. [2023-11-26 12:06:30,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:30,182 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2023-11-26 12:06:30,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1669 states and 2937 transitions. [2023-11-26 12:06:30,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1669 to 1669. [2023-11-26 12:06:30,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1669 states, 1669 states have (on average 1.7597363690832835) internal successors, (2937), 1668 states have internal predecessors, (2937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:30,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1669 states to 1669 states and 2937 transitions. [2023-11-26 12:06:30,229 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2023-11-26 12:06:30,229 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-26 12:06:30,230 INFO L428 stractBuchiCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2023-11-26 12:06:30,231 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 12:06:30,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1669 states and 2937 transitions. [2023-11-26 12:06:30,244 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1572 [2023-11-26 12:06:30,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:30,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:30,246 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:30,246 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:30,247 INFO L748 eck$LassoCheckResult]: Stem: 4704#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 4705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4538#L256 assume !(1 == ~main_in1_req_up~0); 4493#L256-2 assume !(1 == ~main_in2_req_up~0); 4495#L267-1 assume !(1 == ~main_sum_req_up~0); 4526#L278-1 assume !(1 == ~main_diff_req_up~0); 4476#L289-1 assume !(1 == ~main_pres_req_up~0); 4477#L300-1 assume !(1 == ~main_dbl_req_up~0); 4738#L311-1 assume !(1 == ~main_zero_req_up~0); 4737#L322-1 assume !(1 == ~main_clk_req_up~0); 4709#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4699#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4700#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4954#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4953#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4952#L371-1 assume !(0 == ~main_in1_ev~0); 4951#L376-1 assume !(0 == ~main_in2_ev~0); 4895#L381-1 assume !(0 == ~main_sum_ev~0); 4896#L386-1 assume !(0 == ~main_diff_ev~0); 4904#L391-1 assume !(0 == ~main_pres_ev~0); 4836#L396-1 assume !(0 == ~main_dbl_ev~0); 4837#L401-1 assume !(0 == ~main_zero_ev~0); 4644#L406-1 assume !(0 == ~main_clk_ev~0); 4645#L411-1 assume !(0 == ~main_clk_pos_edge~0); 4910#L416-1 assume !(0 == ~main_clk_neg_edge~0); 4911#L421-1 assume !(1 == ~main_clk_pos_edge~0); 4889#L426-1 assume !(1 == ~main_clk_pos_edge~0); 4677#L431-1 assume !(1 == ~main_clk_pos_edge~0); 4678#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 4654#L441-1 assume !(1 == ~main_clk_pos_edge~0); 4655#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 4934#L451-1 assume !(1 == ~main_in2_ev~0); 5227#L456-1 assume !(1 == ~main_sum_ev~0); 5226#L461-1 assume !(1 == ~main_diff_ev~0); 5225#L466-1 assume !(1 == ~main_pres_ev~0); 5224#L471-1 assume !(1 == ~main_dbl_ev~0); 4944#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 5223#L481-1 assume !(1 == ~main_clk_ev~0); 4653#L486-1 assume !(1 == ~main_clk_pos_edge~0); 4533#L491-1 assume !(1 == ~main_clk_neg_edge~0); 4534#L742-1 [2023-11-26 12:06:30,247 INFO L750 eck$LassoCheckResult]: Loop: 4534#L742-1 assume !false; 4854#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 5204#L229 assume !false; 5202#L147 assume !(0 == ~N_generate_st~0); 5198#L151 assume !(0 == ~S1_addsub_st~0); 5199#L154 assume !(0 == ~S2_presdbl_st~0); 5200#L157 assume !(0 == ~S3_zero_st~0); 5201#L160 assume !(0 == ~D_print_st~0); 4605#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 4606#L509 assume !(1 == ~main_in1_req_up~0); 4857#L509-2 assume !(1 == ~main_in2_req_up~0); 5269#L520-1 assume !(1 == ~main_sum_req_up~0); 5265#L531-1 assume !(1 == ~main_diff_req_up~0); 5263#L542-1 assume !(1 == ~main_pres_req_up~0); 4936#L553-1 assume !(1 == ~main_dbl_req_up~0); 4741#L564-1 assume !(1 == ~main_zero_req_up~0); 4753#L575-1 assume !(1 == ~main_clk_req_up~0); 4849#L586-1 start_simulation_~kernel_st~0#1 := 3; 4912#L605 assume !(0 == ~main_in1_ev~0); 4887#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 4512#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 4513#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 4798#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 4793#L625-1 assume !(0 == ~main_dbl_ev~0); 4794#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 4873#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 4905#L640-1 assume !(0 == ~main_clk_pos_edge~0); 4641#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 4642#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 4687#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 4710#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 4809#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 4845#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 4888#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 4786#L680-1 assume !(1 == ~main_in2_ev~0); 5236#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 5235#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 5234#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 4874#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 4871#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 4872#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 4778#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 4716#L720-1 assume !(1 == ~main_clk_neg_edge~0); 4717#L725-1 assume 0 == ~N_generate_st~0; 4534#L742-1 [2023-11-26 12:06:30,248 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:30,248 INFO L85 PathProgramCache]: Analyzing trace with hash 357698877, now seen corresponding path program 1 times [2023-11-26 12:06:30,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:30,249 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79453989] [2023-11-26 12:06:30,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:30,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:30,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:30,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:30,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:30,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [79453989] [2023-11-26 12:06:30,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [79453989] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:30,328 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:30,329 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:30,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597693734] [2023-11-26 12:06:30,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:30,331 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:30,332 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:30,333 INFO L85 PathProgramCache]: Analyzing trace with hash -2069491216, now seen corresponding path program 1 times [2023-11-26 12:06:30,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:30,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405029386] [2023-11-26 12:06:30,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:30,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:30,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:30,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:30,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:30,375 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405029386] [2023-11-26 12:06:30,376 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405029386] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:30,376 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:30,377 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:30,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163365443] [2023-11-26 12:06:30,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:30,378 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:30,378 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:30,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:06:30,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:06:30,379 INFO L87 Difference]: Start difference. First operand 1669 states and 2937 transitions. cyclomatic complexity: 1276 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:30,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:30,702 INFO L93 Difference]: Finished difference Result 1999 states and 3465 transitions. [2023-11-26 12:06:30,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1999 states and 3465 transitions. [2023-11-26 12:06:30,728 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1872 [2023-11-26 12:06:30,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1999 states to 1999 states and 3465 transitions. [2023-11-26 12:06:30,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1999 [2023-11-26 12:06:30,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1999 [2023-11-26 12:06:30,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1999 states and 3465 transitions. [2023-11-26 12:06:30,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:30,759 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2023-11-26 12:06:30,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1999 states and 3465 transitions. [2023-11-26 12:06:30,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1999 to 1999. [2023-11-26 12:06:30,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1999 states, 1999 states have (on average 1.7333666833416708) internal successors, (3465), 1998 states have internal predecessors, (3465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:30,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1999 states to 1999 states and 3465 transitions. [2023-11-26 12:06:30,820 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2023-11-26 12:06:30,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:06:30,824 INFO L428 stractBuchiCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2023-11-26 12:06:30,824 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 12:06:30,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1999 states and 3465 transitions. [2023-11-26 12:06:30,838 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1872 [2023-11-26 12:06:30,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:30,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:30,840 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:30,840 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:30,841 INFO L748 eck$LassoCheckResult]: Stem: 8385#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 8386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 8216#L256 assume !(1 == ~main_in1_req_up~0); 8168#L256-2 assume !(1 == ~main_in2_req_up~0); 8170#L267-1 assume !(1 == ~main_sum_req_up~0); 8203#L278-1 assume !(1 == ~main_diff_req_up~0); 8151#L289-1 assume !(1 == ~main_pres_req_up~0); 8152#L300-1 assume !(1 == ~main_dbl_req_up~0); 8422#L311-1 assume !(1 == ~main_zero_req_up~0); 8419#L322-1 assume !(1 == ~main_clk_req_up~0); 8643#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 8642#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 8190#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 8191#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 8375#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 8640#L371-1 assume !(0 == ~main_in1_ev~0); 8639#L376-1 assume !(0 == ~main_in2_ev~0); 8584#L381-1 assume !(0 == ~main_sum_ev~0); 8585#L386-1 assume !(0 == ~main_diff_ev~0); 8593#L391-1 assume !(0 == ~main_pres_ev~0); 8522#L396-1 assume !(0 == ~main_dbl_ev~0); 8523#L401-1 assume !(0 == ~main_zero_ev~0); 9930#L406-1 assume !(0 == ~main_clk_ev~0); 9927#L411-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 9928#L416-1 assume !(0 == ~main_clk_neg_edge~0); 9920#L421-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 9921#L426-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 9912#L431-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 9911#L436-1 assume !(1 == ~main_clk_pos_edge~0); 9909#L441-1 assume !(1 == ~main_clk_pos_edge~0); 9906#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 8568#L451-1 assume !(1 == ~main_in2_ev~0); 8569#L456-1 assume !(1 == ~main_sum_ev~0); 8402#L461-1 assume !(1 == ~main_diff_ev~0); 8403#L466-1 assume !(1 == ~main_pres_ev~0); 8623#L471-1 assume !(1 == ~main_dbl_ev~0); 8205#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 8206#L481-1 assume !(1 == ~main_clk_ev~0); 8332#L486-1 assume !(1 == ~main_clk_pos_edge~0); 8210#L491-1 assume !(1 == ~main_clk_neg_edge~0); 8211#L742-1 [2023-11-26 12:06:30,841 INFO L750 eck$LassoCheckResult]: Loop: 8211#L742-1 assume !false; 8621#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 8245#L229 assume !false; 9421#L147 assume !(0 == ~N_generate_st~0); 9419#L151 assume !(0 == ~S1_addsub_st~0); 9417#L154 assume !(0 == ~S2_presdbl_st~0); 9415#L157 assume !(0 == ~S3_zero_st~0); 9413#L160 assume !(0 == ~D_print_st~0); 9411#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 9409#L509 assume !(1 == ~main_in1_req_up~0); 9406#L509-2 assume !(1 == ~main_in2_req_up~0); 9402#L520-1 assume !(1 == ~main_sum_req_up~0); 9388#L531-1 assume !(1 == ~main_diff_req_up~0); 9385#L542-1 assume !(1 == ~main_pres_req_up~0); 9381#L553-1 assume !(1 == ~main_dbl_req_up~0); 9377#L564-1 assume !(1 == ~main_zero_req_up~0); 9373#L575-1 assume !(1 == ~main_clk_req_up~0); 9370#L586-1 start_simulation_~kernel_st~0#1 := 3; 9368#L605 assume !(0 == ~main_in1_ev~0); 9367#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 9366#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 9364#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 9362#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 9360#L625-1 assume !(0 == ~main_dbl_ev~0); 9358#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 9356#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 9355#L640-1 assume !(0 == ~main_clk_pos_edge~0); 8320#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 8321#L650-1 assume !(1 == ~main_clk_pos_edge~0); 9349#L655-1 assume !(1 == ~main_clk_pos_edge~0); 9346#L660-1 assume !(1 == ~main_clk_pos_edge~0); 9343#L665-1 assume !(1 == ~main_clk_pos_edge~0); 9333#L670-1 assume !(1 == ~main_clk_pos_edge~0); 9332#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 9329#L680-1 assume !(1 == ~main_in2_ev~0); 9327#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 9325#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 9323#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 9322#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 9319#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 9318#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 9317#L715-1 assume !(1 == ~main_clk_pos_edge~0); 9315#L720-1 assume !(1 == ~main_clk_neg_edge~0); 9314#L725-1 assume 0 == ~N_generate_st~0; 8211#L742-1 [2023-11-26 12:06:30,842 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:30,842 INFO L85 PathProgramCache]: Analyzing trace with hash 787031863, now seen corresponding path program 1 times [2023-11-26 12:06:30,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:30,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021394250] [2023-11-26 12:06:30,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:30,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:30,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:30,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:30,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:30,905 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021394250] [2023-11-26 12:06:30,905 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021394250] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:30,905 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:30,905 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:30,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681146784] [2023-11-26 12:06:30,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:30,906 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:30,907 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:30,907 INFO L85 PathProgramCache]: Analyzing trace with hash -1415211856, now seen corresponding path program 1 times [2023-11-26 12:06:30,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:30,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594739059] [2023-11-26 12:06:30,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:30,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:30,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:30,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:30,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:30,953 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1594739059] [2023-11-26 12:06:30,953 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1594739059] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:30,953 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:30,954 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:30,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [46521540] [2023-11-26 12:06:30,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:30,954 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:30,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:30,956 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:06:30,956 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:06:30,956 INFO L87 Difference]: Start difference. First operand 1999 states and 3465 transitions. cyclomatic complexity: 1474 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:31,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:31,342 INFO L93 Difference]: Finished difference Result 4015 states and 6814 transitions. [2023-11-26 12:06:31,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4015 states and 6814 transitions. [2023-11-26 12:06:31,381 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3762 [2023-11-26 12:06:31,414 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4015 states to 4015 states and 6814 transitions. [2023-11-26 12:06:31,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4015 [2023-11-26 12:06:31,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4015 [2023-11-26 12:06:31,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4015 states and 6814 transitions. [2023-11-26 12:06:31,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:31,456 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4015 states and 6814 transitions. [2023-11-26 12:06:31,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4015 states and 6814 transitions. [2023-11-26 12:06:31,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4015 to 3985. [2023-11-26 12:06:31,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3985 states, 3985 states have (on average 1.6948557089084064) internal successors, (6754), 3984 states have internal predecessors, (6754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:31,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3985 states to 3985 states and 6754 transitions. [2023-11-26 12:06:31,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3985 states and 6754 transitions. [2023-11-26 12:06:31,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-26 12:06:31,549 INFO L428 stractBuchiCegarLoop]: Abstraction has 3985 states and 6754 transitions. [2023-11-26 12:06:31,549 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 12:06:31,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3985 states and 6754 transitions. [2023-11-26 12:06:31,573 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3762 [2023-11-26 12:06:31,574 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:31,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:31,575 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:31,575 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:31,576 INFO L748 eck$LassoCheckResult]: Stem: 14409#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 14410#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 14238#L256 assume !(1 == ~main_in1_req_up~0); 14192#L256-2 assume !(1 == ~main_in2_req_up~0); 14194#L267-1 assume !(1 == ~main_sum_req_up~0); 14225#L278-1 assume !(1 == ~main_diff_req_up~0); 14175#L289-1 assume !(1 == ~main_pres_req_up~0); 14176#L300-1 assume !(1 == ~main_dbl_req_up~0); 14286#L311-1 assume !(1 == ~main_zero_req_up~0); 16526#L322-1 assume !(1 == ~main_clk_req_up~0); 16527#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 16821#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 16819#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 16817#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 16815#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 16813#L371-1 assume !(0 == ~main_in1_ev~0); 16811#L376-1 assume !(0 == ~main_in2_ev~0); 16809#L381-1 assume !(0 == ~main_sum_ev~0); 16805#L386-1 assume !(0 == ~main_diff_ev~0); 16800#L391-1 assume !(0 == ~main_pres_ev~0); 16795#L396-1 assume !(0 == ~main_dbl_ev~0); 16793#L401-1 assume !(0 == ~main_zero_ev~0); 16791#L406-1 assume !(0 == ~main_clk_ev~0); 16788#L411-1 assume !(0 == ~main_clk_pos_edge~0); 16785#L416-1 assume !(0 == ~main_clk_neg_edge~0); 16782#L421-1 assume !(1 == ~main_clk_pos_edge~0); 16780#L426-1 assume !(1 == ~main_clk_pos_edge~0); 16778#L431-1 assume !(1 == ~main_clk_pos_edge~0); 16775#L436-1 assume !(1 == ~main_clk_pos_edge~0); 16771#L441-1 assume !(1 == ~main_clk_pos_edge~0); 16767#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 14662#L451-1 assume !(1 == ~main_in2_ev~0); 16832#L456-1 assume !(1 == ~main_sum_ev~0); 14427#L461-1 assume !(1 == ~main_diff_ev~0); 14428#L466-1 assume !(1 == ~main_pres_ev~0); 14657#L471-1 assume !(1 == ~main_dbl_ev~0); 14227#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 14228#L481-1 assume !(1 == ~main_clk_ev~0); 14358#L486-1 assume !(1 == ~main_clk_pos_edge~0); 14232#L491-1 assume !(1 == ~main_clk_neg_edge~0); 14233#L742-1 [2023-11-26 12:06:31,576 INFO L750 eck$LassoCheckResult]: Loop: 14233#L742-1 assume !false; 14571#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 14267#L229 assume !false; 14522#L147 assume !(0 == ~N_generate_st~0); 14301#L151 assume !(0 == ~S1_addsub_st~0); 14302#L154 assume !(0 == ~S2_presdbl_st~0); 14185#L157 assume !(0 == ~S3_zero_st~0); 14187#L160 assume !(0 == ~D_print_st~0); 14305#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 14306#L509 assume !(1 == ~main_in1_req_up~0); 14574#L509-2 assume !(1 == ~main_in2_req_up~0); 16727#L520-1 assume !(1 == ~main_sum_req_up~0); 16723#L531-1 assume !(1 == ~main_diff_req_up~0); 16721#L542-1 assume !(1 == ~main_pres_req_up~0); 16717#L553-1 assume !(1 == ~main_dbl_req_up~0); 16718#L564-1 assume !(1 == ~main_zero_req_up~0); 16696#L575-1 assume !(1 == ~main_clk_req_up~0); 16694#L586-1 start_simulation_~kernel_st~0#1 := 3; 16692#L605 assume !(0 == ~main_in1_ev~0); 16691#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 16686#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 16684#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 16682#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 16680#L625-1 assume !(0 == ~main_dbl_ev~0); 16677#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 16675#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 16672#L640-1 assume !(0 == ~main_clk_pos_edge~0); 16596#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 16669#L650-1 assume !(1 == ~main_clk_pos_edge~0); 16591#L655-1 assume !(1 == ~main_clk_pos_edge~0); 16588#L660-1 assume !(1 == ~main_clk_pos_edge~0); 16585#L665-1 assume !(1 == ~main_clk_pos_edge~0); 16433#L670-1 assume !(1 == ~main_clk_pos_edge~0); 16428#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 16177#L680-1 assume !(1 == ~main_in2_ev~0); 16423#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 16421#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 16419#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 16417#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 16133#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 16413#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 16411#L715-1 assume !(1 == ~main_clk_pos_edge~0); 16409#L720-1 assume !(1 == ~main_clk_neg_edge~0); 16408#L725-1 assume 0 == ~N_generate_st~0; 14233#L742-1 [2023-11-26 12:06:31,577 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:31,577 INFO L85 PathProgramCache]: Analyzing trace with hash 615864315, now seen corresponding path program 1 times [2023-11-26 12:06:31,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:31,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426439492] [2023-11-26 12:06:31,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:31,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:31,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:31,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:31,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:31,637 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1426439492] [2023-11-26 12:06:31,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1426439492] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:31,638 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:31,638 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:31,638 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39691930] [2023-11-26 12:06:31,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:31,639 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:31,639 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:31,639 INFO L85 PathProgramCache]: Analyzing trace with hash -1415211856, now seen corresponding path program 2 times [2023-11-26 12:06:31,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:31,640 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008562258] [2023-11-26 12:06:31,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:31,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:31,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:31,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:31,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:31,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008562258] [2023-11-26 12:06:31,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008562258] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:31,677 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:31,677 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:31,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337127146] [2023-11-26 12:06:31,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:31,678 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:31,678 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:31,678 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:06:31,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:06:31,679 INFO L87 Difference]: Start difference. First operand 3985 states and 6754 transitions. cyclomatic complexity: 2785 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:32,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:32,026 INFO L93 Difference]: Finished difference Result 4445 states and 7522 transitions. [2023-11-26 12:06:32,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4445 states and 7522 transitions. [2023-11-26 12:06:32,058 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4162 [2023-11-26 12:06:32,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4445 states to 4445 states and 7522 transitions. [2023-11-26 12:06:32,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4445 [2023-11-26 12:06:32,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4445 [2023-11-26 12:06:32,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4445 states and 7522 transitions. [2023-11-26 12:06:32,109 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:32,109 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4445 states and 7522 transitions. [2023-11-26 12:06:32,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4445 states and 7522 transitions. [2023-11-26 12:06:32,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4445 to 4415. [2023-11-26 12:06:32,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4415 states, 4415 states have (on average 1.6901472253680634) internal successors, (7462), 4414 states have internal predecessors, (7462), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:32,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4415 states to 4415 states and 7462 transitions. [2023-11-26 12:06:32,277 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4415 states and 7462 transitions. [2023-11-26 12:06:32,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:06:32,281 INFO L428 stractBuchiCegarLoop]: Abstraction has 4415 states and 7462 transitions. [2023-11-26 12:06:32,283 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 12:06:32,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4415 states and 7462 transitions. [2023-11-26 12:06:32,316 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4162 [2023-11-26 12:06:32,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:32,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:32,318 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:32,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:32,319 INFO L748 eck$LassoCheckResult]: Stem: 22849#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 22850#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 22679#L256 assume !(1 == ~main_in1_req_up~0); 22633#L256-2 assume !(1 == ~main_in2_req_up~0); 22635#L267-1 assume !(1 == ~main_sum_req_up~0); 22666#L278-1 assume !(1 == ~main_diff_req_up~0); 22616#L289-1 assume !(1 == ~main_pres_req_up~0); 22617#L300-1 assume !(1 == ~main_dbl_req_up~0); 23011#L311-1 assume !(1 == ~main_zero_req_up~0); 25232#L322-1 assume !(1 == ~main_clk_req_up~0); 25233#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 26482#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 26479#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 26476#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 26472#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 26468#L371-1 assume !(0 == ~main_in1_ev~0); 26466#L376-1 assume !(0 == ~main_in2_ev~0); 26464#L381-1 assume !(0 == ~main_sum_ev~0); 26462#L386-1 assume !(0 == ~main_diff_ev~0); 26460#L391-1 assume !(0 == ~main_pres_ev~0); 26458#L396-1 assume !(0 == ~main_dbl_ev~0); 26456#L401-1 assume !(0 == ~main_zero_ev~0); 26454#L406-1 assume !(0 == ~main_clk_ev~0); 26452#L411-1 assume !(0 == ~main_clk_pos_edge~0); 26450#L416-1 assume !(0 == ~main_clk_neg_edge~0); 26448#L421-1 assume !(1 == ~main_clk_pos_edge~0); 26446#L426-1 assume !(1 == ~main_clk_pos_edge~0); 26444#L431-1 assume !(1 == ~main_clk_pos_edge~0); 26442#L436-1 assume !(1 == ~main_clk_pos_edge~0); 26440#L441-1 assume !(1 == ~main_clk_pos_edge~0); 26438#L446-1 assume !(1 == ~main_in1_ev~0); 26436#L451-1 assume !(1 == ~main_in2_ev~0); 26434#L456-1 assume !(1 == ~main_sum_ev~0); 26432#L461-1 assume !(1 == ~main_diff_ev~0); 26430#L466-1 assume !(1 == ~main_pres_ev~0); 26428#L471-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 22668#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 22669#L481-1 assume !(1 == ~main_clk_ev~0); 22797#L486-1 assume !(1 == ~main_clk_pos_edge~0); 22673#L491-1 assume !(1 == ~main_clk_neg_edge~0); 22674#L742-1 [2023-11-26 12:06:32,320 INFO L750 eck$LassoCheckResult]: Loop: 22674#L742-1 assume !false; 23008#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 22708#L229 assume !false; 22966#L147 assume !(0 == ~N_generate_st~0); 22742#L151 assume !(0 == ~S1_addsub_st~0); 22743#L154 assume !(0 == ~S2_presdbl_st~0); 22626#L157 assume !(0 == ~S3_zero_st~0); 22628#L160 assume !(0 == ~D_print_st~0); 23053#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 26770#L509 assume !(1 == ~main_in1_req_up~0); 26768#L509-2 assume !(1 == ~main_in2_req_up~0); 26765#L520-1 assume !(1 == ~main_sum_req_up~0); 26761#L531-1 assume !(1 == ~main_diff_req_up~0); 26759#L542-1 assume !(1 == ~main_pres_req_up~0); 23099#L553-1 assume !(1 == ~main_dbl_req_up~0); 23100#L564-1 assume !(1 == ~main_zero_req_up~0); 26962#L575-1 assume !(1 == ~main_clk_req_up~0); 26960#L586-1 start_simulation_~kernel_st~0#1 := 3; 26959#L605 assume !(0 == ~main_in1_ev~0); 26958#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 26955#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 26951#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 26949#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 26947#L625-1 assume !(0 == ~main_dbl_ev~0); 26944#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 26647#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 26646#L640-1 assume !(0 == ~main_clk_pos_edge~0); 26645#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 26644#L650-1 assume !(1 == ~main_clk_pos_edge~0); 26643#L655-1 assume !(1 == ~main_clk_pos_edge~0); 26642#L660-1 assume !(1 == ~main_clk_pos_edge~0); 26641#L665-1 assume !(1 == ~main_clk_pos_edge~0); 26640#L670-1 assume !(1 == ~main_clk_pos_edge~0); 26639#L675-1 assume !(1 == ~main_in1_ev~0); 26637#L680-1 assume !(1 == ~main_in2_ev~0); 26636#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 26635#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 26632#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 26628#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 26425#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 26621#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 26100#L715-1 assume !(1 == ~main_clk_pos_edge~0); 22864#L720-1 assume !(1 == ~main_clk_neg_edge~0); 22865#L725-1 assume 0 == ~N_generate_st~0; 22674#L742-1 [2023-11-26 12:06:32,321 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:32,322 INFO L85 PathProgramCache]: Analyzing trace with hash 220990263, now seen corresponding path program 1 times [2023-11-26 12:06:32,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:32,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881727791] [2023-11-26 12:06:32,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:32,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:32,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:32,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:32,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:32,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881727791] [2023-11-26 12:06:32,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881727791] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:32,405 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:32,405 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:32,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1913867319] [2023-11-26 12:06:32,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:32,406 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:32,406 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:32,407 INFO L85 PathProgramCache]: Analyzing trace with hash -714147278, now seen corresponding path program 1 times [2023-11-26 12:06:32,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:32,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779599701] [2023-11-26 12:06:32,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:32,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:32,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:32,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:32,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:32,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779599701] [2023-11-26 12:06:32,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779599701] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:32,436 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:32,437 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:32,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1151753530] [2023-11-26 12:06:32,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:32,438 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:32,438 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:32,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:06:32,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:06:32,439 INFO L87 Difference]: Start difference. First operand 4415 states and 7462 transitions. cyclomatic complexity: 3063 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:32,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:32,746 INFO L93 Difference]: Finished difference Result 5574 states and 9318 transitions. [2023-11-26 12:06:32,746 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5574 states and 9318 transitions. [2023-11-26 12:06:32,780 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 5240 [2023-11-26 12:06:32,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5574 states to 5574 states and 9318 transitions. [2023-11-26 12:06:32,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5574 [2023-11-26 12:06:32,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5574 [2023-11-26 12:06:32,834 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5574 states and 9318 transitions. [2023-11-26 12:06:32,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:32,843 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5574 states and 9318 transitions. [2023-11-26 12:06:32,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5574 states and 9318 transitions. [2023-11-26 12:06:33,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5574 to 5130. [2023-11-26 12:06:33,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5130 states, 5130 states have (on average 1.6754385964912282) internal successors, (8595), 5129 states have internal predecessors, (8595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:33,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5130 states to 5130 states and 8595 transitions. [2023-11-26 12:06:33,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5130 states and 8595 transitions. [2023-11-26 12:06:33,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:06:33,045 INFO L428 stractBuchiCegarLoop]: Abstraction has 5130 states and 8595 transitions. [2023-11-26 12:06:33,045 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 12:06:33,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5130 states and 8595 transitions. [2023-11-26 12:06:33,069 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4812 [2023-11-26 12:06:33,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:33,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:33,070 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:33,070 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:33,071 INFO L748 eck$LassoCheckResult]: Stem: 32846#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 32847#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 32679#L256 assume !(1 == ~main_in1_req_up~0); 32633#L256-2 assume !(1 == ~main_in2_req_up~0); 32635#L267-1 assume !(1 == ~main_sum_req_up~0); 32666#L278-1 assume !(1 == ~main_diff_req_up~0); 32616#L289-1 assume !(1 == ~main_pres_req_up~0); 32617#L300-1 assume !(1 == ~main_dbl_req_up~0); 32726#L311-1 assume !(1 == ~main_zero_req_up~0); 33068#L322-1 assume !(1 == ~main_clk_req_up~0); 32950#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 32842#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 32843#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 33273#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 33274#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 33269#L371-1 assume !(0 == ~main_in1_ev~0); 33270#L376-1 assume !(0 == ~main_in2_ev~0); 33053#L381-1 assume !(0 == ~main_sum_ev~0); 33054#L386-1 assume !(0 == ~main_diff_ev~0); 33065#L391-1 assume !(0 == ~main_pres_ev~0); 32987#L396-1 assume !(0 == ~main_dbl_ev~0); 32988#L401-1 assume !(0 == ~main_zero_ev~0); 33750#L406-1 assume !(0 == ~main_clk_ev~0); 33751#L411-1 assume !(0 == ~main_clk_pos_edge~0); 33741#L416-1 assume !(0 == ~main_clk_neg_edge~0); 33742#L421-1 assume !(1 == ~main_clk_pos_edge~0); 33730#L426-1 assume !(1 == ~main_clk_pos_edge~0); 33731#L431-1 assume !(1 == ~main_clk_pos_edge~0); 33720#L436-1 assume !(1 == ~main_clk_pos_edge~0); 33721#L441-1 assume !(1 == ~main_clk_pos_edge~0); 33703#L446-1 assume !(1 == ~main_in1_ev~0); 33704#L451-1 assume !(1 == ~main_in2_ev~0); 33112#L456-1 assume !(1 == ~main_sum_ev~0); 32866#L461-1 assume !(1 == ~main_diff_ev~0); 32867#L466-1 assume !(1 == ~main_pres_ev~0); 33657#L471-1 assume !(1 == ~main_dbl_ev~0); 33658#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 33612#L481-1 assume !(1 == ~main_clk_ev~0); 33613#L486-1 assume !(1 == ~main_clk_pos_edge~0); 33590#L491-1 assume !(1 == ~main_clk_neg_edge~0); 33591#L742-1 [2023-11-26 12:06:33,071 INFO L750 eck$LassoCheckResult]: Loop: 33591#L742-1 assume !false; 33577#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 33571#L229 assume !false; 33566#L147 assume !(0 == ~N_generate_st~0); 33559#L151 assume !(0 == ~S1_addsub_st~0); 33560#L154 assume !(0 == ~S2_presdbl_st~0); 33564#L157 assume !(0 == ~S3_zero_st~0); 33565#L160 assume !(0 == ~D_print_st~0); 33733#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 33734#L509 assume !(1 == ~main_in1_req_up~0); 33716#L509-2 assume !(1 == ~main_in2_req_up~0); 33708#L520-1 assume !(1 == ~main_sum_req_up~0); 33707#L531-1 assume !(1 == ~main_diff_req_up~0); 35147#L542-1 assume !(1 == ~main_pres_req_up~0); 33680#L553-1 assume !(1 == ~main_dbl_req_up~0); 33679#L564-1 assume !(1 == ~main_zero_req_up~0); 33661#L575-1 assume !(1 == ~main_clk_req_up~0); 33662#L586-1 start_simulation_~kernel_st~0#1 := 3; 33778#L605 assume !(0 == ~main_in1_ev~0); 33777#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 33776#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 33772#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 33768#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 33763#L625-1 assume !(0 == ~main_dbl_ev~0); 33759#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 33757#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 33752#L640-1 assume !(0 == ~main_clk_pos_edge~0); 33747#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 33743#L650-1 assume !(1 == ~main_clk_pos_edge~0); 33738#L655-1 assume !(1 == ~main_clk_pos_edge~0); 33732#L660-1 assume !(1 == ~main_clk_pos_edge~0); 33725#L665-1 assume !(1 == ~main_clk_pos_edge~0); 33722#L670-1 assume !(1 == ~main_clk_pos_edge~0); 33714#L675-1 assume !(1 == ~main_in1_ev~0); 33705#L680-1 assume !(1 == ~main_in2_ev~0); 33697#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 33685#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 33674#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 33675#L700-1 assume !(1 == ~main_dbl_ev~0); 33659#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 33660#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 33616#L715-1 assume !(1 == ~main_clk_pos_edge~0); 33617#L720-1 assume !(1 == ~main_clk_neg_edge~0); 33594#L725-1 assume 0 == ~N_generate_st~0; 33591#L742-1 [2023-11-26 12:06:33,072 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:33,072 INFO L85 PathProgramCache]: Analyzing trace with hash 222837305, now seen corresponding path program 1 times [2023-11-26 12:06:33,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:33,073 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885381993] [2023-11-26 12:06:33,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:33,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:33,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:33,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:33,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:33,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1885381993] [2023-11-26 12:06:33,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1885381993] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:33,173 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:33,173 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:33,173 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [728087035] [2023-11-26 12:06:33,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:33,174 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:33,174 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:33,174 INFO L85 PathProgramCache]: Analyzing trace with hash -656888976, now seen corresponding path program 1 times [2023-11-26 12:06:33,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:33,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064890091] [2023-11-26 12:06:33,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:33,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:33,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:33,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:33,208 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:33,208 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064890091] [2023-11-26 12:06:33,208 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1064890091] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:33,208 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:33,208 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:33,209 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097435218] [2023-11-26 12:06:33,209 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:33,209 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:33,209 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:33,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:06:33,210 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:06:33,210 INFO L87 Difference]: Start difference. First operand 5130 states and 8595 transitions. cyclomatic complexity: 3481 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:33,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:33,632 INFO L93 Difference]: Finished difference Result 9446 states and 15503 transitions. [2023-11-26 12:06:33,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9446 states and 15503 transitions. [2023-11-26 12:06:33,698 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 8840 [2023-11-26 12:06:33,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9446 states to 9446 states and 15503 transitions. [2023-11-26 12:06:33,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9446 [2023-11-26 12:06:33,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9446 [2023-11-26 12:06:33,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9446 states and 15503 transitions. [2023-11-26 12:06:33,782 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:33,782 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9446 states and 15503 transitions. [2023-11-26 12:06:33,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9446 states and 15503 transitions. [2023-11-26 12:06:33,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9446 to 6978. [2023-11-26 12:06:33,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6978 states, 6978 states have (on average 1.65262252794497) internal successors, (11532), 6977 states have internal predecessors, (11532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:33,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6978 states to 6978 states and 11532 transitions. [2023-11-26 12:06:33,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6978 states and 11532 transitions. [2023-11-26 12:06:33,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:06:33,973 INFO L428 stractBuchiCegarLoop]: Abstraction has 6978 states and 11532 transitions. [2023-11-26 12:06:33,973 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 12:06:33,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6978 states and 11532 transitions. [2023-11-26 12:06:34,013 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6492 [2023-11-26 12:06:34,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:34,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:34,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:34,019 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:34,019 INFO L748 eck$LassoCheckResult]: Stem: 47434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 47435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 47266#L256 assume !(1 == ~main_in1_req_up~0); 47220#L256-2 assume !(1 == ~main_in2_req_up~0); 47222#L267-1 assume !(1 == ~main_sum_req_up~0); 47253#L278-1 assume !(1 == ~main_diff_req_up~0); 47203#L289-1 assume !(1 == ~main_pres_req_up~0); 47204#L300-1 assume !(1 == ~main_dbl_req_up~0); 47313#L311-1 assume !(1 == ~main_zero_req_up~0); 47667#L322-1 assume !(1 == ~main_clk_req_up~0); 47444#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 47432#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 47242#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 47243#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 47426#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 47420#L371-1 assume !(0 == ~main_in1_ev~0); 47421#L376-1 assume !(0 == ~main_in2_ev~0); 47654#L381-1 assume !(0 == ~main_sum_ev~0); 47655#L386-1 assume !(0 == ~main_diff_ev~0); 47664#L391-1 assume !(0 == ~main_pres_ev~0); 47591#L396-1 assume !(0 == ~main_dbl_ev~0); 47363#L401-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 47364#L406-1 assume !(0 == ~main_clk_ev~0); 49731#L411-1 assume !(0 == ~main_clk_pos_edge~0); 49727#L416-1 assume !(0 == ~main_clk_neg_edge~0); 49728#L421-1 assume !(1 == ~main_clk_pos_edge~0); 49723#L426-1 assume !(1 == ~main_clk_pos_edge~0); 49724#L431-1 assume !(1 == ~main_clk_pos_edge~0); 49719#L436-1 assume !(1 == ~main_clk_pos_edge~0); 49720#L441-1 assume !(1 == ~main_clk_pos_edge~0); 49717#L446-1 assume !(1 == ~main_in1_ev~0); 49718#L451-1 assume !(1 == ~main_in2_ev~0); 49714#L456-1 assume !(1 == ~main_sum_ev~0); 49715#L461-1 assume !(1 == ~main_diff_ev~0); 49710#L466-1 assume !(1 == ~main_pres_ev~0); 49711#L471-1 assume !(1 == ~main_dbl_ev~0); 49708#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 47547#L481-1 assume !(1 == ~main_clk_ev~0); 47382#L486-1 assume !(1 == ~main_clk_pos_edge~0); 47383#L491-1 assume !(1 == ~main_clk_neg_edge~0); 49523#L742-1 [2023-11-26 12:06:34,019 INFO L750 eck$LassoCheckResult]: Loop: 49523#L742-1 assume !false; 49686#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 49680#L229 assume !false; 49668#L147 assume !(0 == ~N_generate_st~0); 49664#L151 assume !(0 == ~S1_addsub_st~0); 49665#L154 assume !(0 == ~S2_presdbl_st~0); 49666#L157 assume !(0 == ~S3_zero_st~0); 49667#L160 assume !(0 == ~D_print_st~0); 49669#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 49682#L509 assume !(1 == ~main_in1_req_up~0); 49678#L509-2 assume !(1 == ~main_in2_req_up~0); 49674#L520-1 assume !(1 == ~main_sum_req_up~0); 49661#L531-1 assume !(1 == ~main_diff_req_up~0); 49656#L542-1 assume !(1 == ~main_pres_req_up~0); 49648#L553-1 assume !(1 == ~main_dbl_req_up~0); 49640#L564-1 assume !(1 == ~main_zero_req_up~0); 49607#L575-1 assume !(1 == ~main_clk_req_up~0); 49608#L586-1 start_simulation_~kernel_st~0#1 := 3; 49676#L605 assume !(0 == ~main_in1_ev~0); 49672#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 49671#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 49660#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 49653#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 49645#L625-1 assume !(0 == ~main_dbl_ev~0); 49646#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 49634#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 49635#L640-1 assume !(0 == ~main_clk_pos_edge~0); 49631#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 49632#L650-1 assume !(1 == ~main_clk_pos_edge~0); 49628#L655-1 assume !(1 == ~main_clk_pos_edge~0); 49629#L660-1 assume !(1 == ~main_clk_pos_edge~0); 49626#L665-1 assume !(1 == ~main_clk_pos_edge~0); 49627#L670-1 assume !(1 == ~main_clk_pos_edge~0); 49624#L675-1 assume !(1 == ~main_in1_ev~0); 49625#L680-1 assume !(1 == ~main_in2_ev~0); 49620#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 49621#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 49616#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 49617#L700-1 assume !(1 == ~main_dbl_ev~0); 49612#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 49606#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 49546#L715-1 assume !(1 == ~main_clk_pos_edge~0); 49540#L720-1 assume !(1 == ~main_clk_neg_edge~0); 49535#L725-1 assume 0 == ~N_generate_st~0; 49523#L742-1 [2023-11-26 12:06:34,020 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:34,020 INFO L85 PathProgramCache]: Analyzing trace with hash 1911781047, now seen corresponding path program 1 times [2023-11-26 12:06:34,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:34,020 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596537785] [2023-11-26 12:06:34,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:34,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:34,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:34,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:34,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:34,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596537785] [2023-11-26 12:06:34,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [596537785] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:34,149 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:34,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:34,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214903277] [2023-11-26 12:06:34,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:34,150 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:34,150 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:34,151 INFO L85 PathProgramCache]: Analyzing trace with hash -656888976, now seen corresponding path program 2 times [2023-11-26 12:06:34,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:34,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071119750] [2023-11-26 12:06:34,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:34,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:34,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:34,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:34,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:34,175 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071119750] [2023-11-26 12:06:34,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1071119750] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:34,176 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:34,176 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:34,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592899517] [2023-11-26 12:06:34,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:34,177 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:34,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:34,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:06:34,177 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:06:34,178 INFO L87 Difference]: Start difference. First operand 6978 states and 11532 transitions. cyclomatic complexity: 4570 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:34,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:34,371 INFO L93 Difference]: Finished difference Result 12839 states and 21043 transitions. [2023-11-26 12:06:34,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12839 states and 21043 transitions. [2023-11-26 12:06:34,438 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 12108 [2023-11-26 12:06:34,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12839 states to 12839 states and 21043 transitions. [2023-11-26 12:06:34,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12839 [2023-11-26 12:06:34,501 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12839 [2023-11-26 12:06:34,501 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12839 states and 21043 transitions. [2023-11-26 12:06:34,516 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:34,517 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2023-11-26 12:06:34,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12839 states and 21043 transitions. [2023-11-26 12:06:34,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12839 to 12839. [2023-11-26 12:06:34,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12839 states, 12839 states have (on average 1.6389905755899992) internal successors, (21043), 12838 states have internal predecessors, (21043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:34,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12839 states to 12839 states and 21043 transitions. [2023-11-26 12:06:34,814 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2023-11-26 12:06:34,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-26 12:06:34,815 INFO L428 stractBuchiCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2023-11-26 12:06:34,815 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 12:06:34,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12839 states and 21043 transitions. [2023-11-26 12:06:34,863 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 12108 [2023-11-26 12:06:34,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:34,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:34,865 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:34,865 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:34,865 INFO L748 eck$LassoCheckResult]: Stem: 67266#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 67267#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 67094#L256 assume !(1 == ~main_in1_req_up~0); 67048#L256-2 assume !(1 == ~main_in2_req_up~0); 67050#L267-1 assume !(1 == ~main_sum_req_up~0); 67081#L278-1 assume !(1 == ~main_diff_req_up~0); 67030#L289-1 assume !(1 == ~main_pres_req_up~0); 67031#L300-1 assume !(1 == ~main_dbl_req_up~0); 67431#L311-1 assume !(1 == ~main_zero_req_up~0); 71691#L322-1 assume !(1 == ~main_clk_req_up~0); 71688#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 71686#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 71684#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 71682#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 71680#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 71678#L371-1 assume !(0 == ~main_in1_ev~0); 71676#L376-1 assume !(0 == ~main_in2_ev~0); 71674#L381-1 assume !(0 == ~main_sum_ev~0); 71672#L386-1 assume !(0 == ~main_diff_ev~0); 71670#L391-1 assume !(0 == ~main_pres_ev~0); 71668#L396-1 assume !(0 == ~main_dbl_ev~0); 71666#L401-1 assume !(0 == ~main_zero_ev~0); 71664#L406-1 assume !(0 == ~main_clk_ev~0); 71662#L411-1 assume !(0 == ~main_clk_pos_edge~0); 71660#L416-1 assume !(0 == ~main_clk_neg_edge~0); 71658#L421-1 assume !(1 == ~main_clk_pos_edge~0); 71657#L426-1 assume !(1 == ~main_clk_pos_edge~0); 71656#L431-1 assume !(1 == ~main_clk_pos_edge~0); 71655#L436-1 assume !(1 == ~main_clk_pos_edge~0); 71654#L441-1 assume !(1 == ~main_clk_pos_edge~0); 71653#L446-1 assume !(1 == ~main_in1_ev~0); 71652#L451-1 assume !(1 == ~main_in2_ev~0); 71651#L456-1 assume !(1 == ~main_sum_ev~0); 71650#L461-1 assume !(1 == ~main_diff_ev~0); 71649#L466-1 assume !(1 == ~main_pres_ev~0); 71648#L471-1 assume !(1 == ~main_dbl_ev~0); 71647#L476-1 assume !(1 == ~main_zero_ev~0); 71644#L481-1 assume !(1 == ~main_clk_ev~0); 71640#L486-1 assume !(1 == ~main_clk_pos_edge~0); 71636#L491-1 assume !(1 == ~main_clk_neg_edge~0); 71505#L742-1 [2023-11-26 12:06:34,866 INFO L750 eck$LassoCheckResult]: Loop: 71505#L742-1 assume !false; 71632#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 71624#L229 assume !false; 71622#L147 assume !(0 == ~N_generate_st~0); 71620#L151 assume !(0 == ~S1_addsub_st~0); 71618#L154 assume !(0 == ~S2_presdbl_st~0); 71616#L157 assume !(0 == ~S3_zero_st~0); 71613#L160 assume !(0 == ~D_print_st~0); 71610#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 71608#L509 assume !(1 == ~main_in1_req_up~0); 71605#L509-2 assume !(1 == ~main_in2_req_up~0); 71599#L520-1 assume !(1 == ~main_sum_req_up~0); 71595#L531-1 assume !(1 == ~main_diff_req_up~0); 71590#L542-1 assume !(1 == ~main_pres_req_up~0); 71584#L553-1 assume !(1 == ~main_dbl_req_up~0); 71578#L564-1 assume !(1 == ~main_zero_req_up~0); 71572#L575-1 assume !(1 == ~main_clk_req_up~0); 71567#L586-1 start_simulation_~kernel_st~0#1 := 3; 71563#L605 assume !(0 == ~main_in1_ev~0); 71561#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 71559#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 71557#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 71555#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 71553#L625-1 assume !(0 == ~main_dbl_ev~0); 71551#L630-1 assume !(0 == ~main_zero_ev~0); 71549#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 71547#L640-1 assume !(0 == ~main_clk_pos_edge~0); 71545#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 71543#L650-1 assume !(1 == ~main_clk_pos_edge~0); 71541#L655-1 assume !(1 == ~main_clk_pos_edge~0); 71539#L660-1 assume !(1 == ~main_clk_pos_edge~0); 71537#L665-1 assume !(1 == ~main_clk_pos_edge~0); 71535#L670-1 assume !(1 == ~main_clk_pos_edge~0); 71533#L675-1 assume !(1 == ~main_in1_ev~0); 71531#L680-1 assume !(1 == ~main_in2_ev~0); 71529#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 71527#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 71525#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 71523#L700-1 assume !(1 == ~main_dbl_ev~0); 71521#L705-1 assume !(1 == ~main_zero_ev~0); 71519#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 71517#L715-1 assume !(1 == ~main_clk_pos_edge~0); 71515#L720-1 assume !(1 == ~main_clk_neg_edge~0); 71513#L725-1 assume 0 == ~N_generate_st~0; 71505#L742-1 [2023-11-26 12:06:34,866 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:34,866 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 1 times [2023-11-26 12:06:34,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:34,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530940367] [2023-11-26 12:06:34,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:34,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:34,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:34,878 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:06:34,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:34,926 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:06:34,928 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:34,928 INFO L85 PathProgramCache]: Analyzing trace with hash -1472690384, now seen corresponding path program 1 times [2023-11-26 12:06:34,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:34,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414049924] [2023-11-26 12:06:34,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:34,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:34,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:35,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:35,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:35,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414049924] [2023-11-26 12:06:35,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1414049924] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:35,047 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:35,047 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:35,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [368888481] [2023-11-26 12:06:35,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:35,048 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:35,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:35,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:06:35,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:06:35,050 INFO L87 Difference]: Start difference. First operand 12839 states and 21043 transitions. cyclomatic complexity: 8236 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:35,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:35,162 INFO L93 Difference]: Finished difference Result 18429 states and 29722 transitions. [2023-11-26 12:06:35,162 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18429 states and 29722 transitions. [2023-11-26 12:06:35,374 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17278 [2023-11-26 12:06:35,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18429 states to 18429 states and 29722 transitions. [2023-11-26 12:06:35,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18429 [2023-11-26 12:06:35,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18429 [2023-11-26 12:06:35,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18429 states and 29722 transitions. [2023-11-26 12:06:35,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:35,576 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2023-11-26 12:06:35,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18429 states and 29722 transitions. [2023-11-26 12:06:36,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18429 to 18429. [2023-11-26 12:06:36,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18429 states, 18429 states have (on average 1.6127841988170817) internal successors, (29722), 18428 states have internal predecessors, (29722), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:36,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18429 states to 18429 states and 29722 transitions. [2023-11-26 12:06:36,119 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2023-11-26 12:06:36,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:06:36,120 INFO L428 stractBuchiCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2023-11-26 12:06:36,120 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 12:06:36,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18429 states and 29722 transitions. [2023-11-26 12:06:36,187 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17278 [2023-11-26 12:06:36,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:36,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:36,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:36,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:36,189 INFO L748 eck$LassoCheckResult]: Stem: 98540#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 98541#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 98369#L256 assume !(1 == ~main_in1_req_up~0); 98322#L256-2 assume !(1 == ~main_in2_req_up~0); 98324#L267-1 assume !(1 == ~main_sum_req_up~0); 98356#L278-1 assume !(1 == ~main_diff_req_up~0); 98304#L289-1 assume !(1 == ~main_pres_req_up~0); 98305#L300-1 assume !(1 == ~main_dbl_req_up~0); 98417#L311-1 assume !(1 == ~main_zero_req_up~0); 102522#L322-1 assume !(1 == ~main_clk_req_up~0); 102523#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 102635#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 102634#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 102633#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 102618#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 102617#L371-1 assume !(0 == ~main_in1_ev~0); 102615#L376-1 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 102607#L381-1 assume !(0 == ~main_sum_ev~0); 102604#L386-1 assume !(0 == ~main_diff_ev~0); 102601#L391-1 assume !(0 == ~main_pres_ev~0); 102598#L396-1 assume !(0 == ~main_dbl_ev~0); 102595#L401-1 assume !(0 == ~main_zero_ev~0); 102590#L406-1 assume !(0 == ~main_clk_ev~0); 102584#L411-1 assume !(0 == ~main_clk_pos_edge~0); 102579#L416-1 assume !(0 == ~main_clk_neg_edge~0); 102572#L421-1 assume !(1 == ~main_clk_pos_edge~0); 102565#L426-1 assume !(1 == ~main_clk_pos_edge~0); 102558#L431-1 assume !(1 == ~main_clk_pos_edge~0); 102551#L436-1 assume !(1 == ~main_clk_pos_edge~0); 102544#L441-1 assume !(1 == ~main_clk_pos_edge~0); 102539#L446-1 assume !(1 == ~main_in1_ev~0); 102233#L451-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 102232#L456-1 assume !(1 == ~main_sum_ev~0); 102230#L461-1 assume !(1 == ~main_diff_ev~0); 102228#L466-1 assume !(1 == ~main_pres_ev~0); 102227#L471-1 assume !(1 == ~main_dbl_ev~0); 102226#L476-1 assume !(1 == ~main_zero_ev~0); 102224#L481-1 assume !(1 == ~main_clk_ev~0); 102223#L486-1 assume !(1 == ~main_clk_pos_edge~0); 102219#L491-1 assume !(1 == ~main_clk_neg_edge~0); 102052#L742-1 [2023-11-26 12:06:36,190 INFO L750 eck$LassoCheckResult]: Loop: 102052#L742-1 assume !false; 102215#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 102211#L229 assume !false; 102210#L147 assume !(0 == ~N_generate_st~0); 102209#L151 assume !(0 == ~S1_addsub_st~0); 102208#L154 assume !(0 == ~S2_presdbl_st~0); 102207#L157 assume !(0 == ~S3_zero_st~0); 102205#L160 assume !(0 == ~D_print_st~0); 102204#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 102203#L509 assume !(1 == ~main_in1_req_up~0); 102201#L509-2 assume !(1 == ~main_in2_req_up~0); 102198#L520-1 assume !(1 == ~main_sum_req_up~0); 102194#L531-1 assume !(1 == ~main_diff_req_up~0); 102192#L542-1 assume !(1 == ~main_pres_req_up~0); 102136#L553-1 assume !(1 == ~main_dbl_req_up~0); 102131#L564-1 assume !(1 == ~main_zero_req_up~0); 102127#L575-1 assume !(1 == ~main_clk_req_up~0); 102124#L586-1 start_simulation_~kernel_st~0#1 := 3; 102121#L605 assume !(0 == ~main_in1_ev~0); 102118#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 102116#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 102114#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 102112#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 102110#L625-1 assume !(0 == ~main_dbl_ev~0); 102108#L630-1 assume !(0 == ~main_zero_ev~0); 102106#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 102104#L640-1 assume !(0 == ~main_clk_pos_edge~0); 102102#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 102100#L650-1 assume !(1 == ~main_clk_pos_edge~0); 102098#L655-1 assume !(1 == ~main_clk_pos_edge~0); 102096#L660-1 assume !(1 == ~main_clk_pos_edge~0); 102094#L665-1 assume !(1 == ~main_clk_pos_edge~0); 102092#L670-1 assume !(1 == ~main_clk_pos_edge~0); 102091#L675-1 assume !(1 == ~main_in1_ev~0); 102088#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 102085#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 102083#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 102081#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 102079#L700-1 assume !(1 == ~main_dbl_ev~0); 102077#L705-1 assume !(1 == ~main_zero_ev~0); 102074#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 102069#L715-1 assume !(1 == ~main_clk_pos_edge~0); 102064#L720-1 assume !(1 == ~main_clk_neg_edge~0); 102062#L725-1 assume 0 == ~N_generate_st~0; 102052#L742-1 [2023-11-26 12:06:36,190 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:36,191 INFO L85 PathProgramCache]: Analyzing trace with hash -323147977, now seen corresponding path program 1 times [2023-11-26 12:06:36,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:36,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56281511] [2023-11-26 12:06:36,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:36,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:36,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:36,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:36,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:36,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56281511] [2023-11-26 12:06:36,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56281511] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:36,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:36,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:36,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355216198] [2023-11-26 12:06:36,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:36,264 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:36,265 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:36,265 INFO L85 PathProgramCache]: Analyzing trace with hash -1079663374, now seen corresponding path program 1 times [2023-11-26 12:06:36,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:36,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436758682] [2023-11-26 12:06:36,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:36,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:36,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:36,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:36,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:36,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436758682] [2023-11-26 12:06:36,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1436758682] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:36,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:36,297 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:36,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898841869] [2023-11-26 12:06:36,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:36,297 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:36,298 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:36,299 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:06:36,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:06:36,299 INFO L87 Difference]: Start difference. First operand 18429 states and 29722 transitions. cyclomatic complexity: 11325 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:36,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:36,768 INFO L93 Difference]: Finished difference Result 33519 states and 53550 transitions. [2023-11-26 12:06:36,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33519 states and 53550 transitions. [2023-11-26 12:06:36,947 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2023-11-26 12:06:37,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33519 states to 33519 states and 53550 transitions. [2023-11-26 12:06:37,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33519 [2023-11-26 12:06:37,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33519 [2023-11-26 12:06:37,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33519 states and 53550 transitions. [2023-11-26 12:06:37,293 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:37,293 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2023-11-26 12:06:37,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33519 states and 53550 transitions. [2023-11-26 12:06:37,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33519 to 33519. [2023-11-26 12:06:37,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33519 states, 33519 states have (on average 1.597601360422447) internal successors, (53550), 33518 states have internal predecessors, (53550), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:37,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33519 states to 33519 states and 53550 transitions. [2023-11-26 12:06:37,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2023-11-26 12:06:37,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-26 12:06:37,900 INFO L428 stractBuchiCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2023-11-26 12:06:37,900 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 12:06:37,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33519 states and 53550 transitions. [2023-11-26 12:06:38,158 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2023-11-26 12:06:38,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:38,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:38,159 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:38,159 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:38,159 INFO L748 eck$LassoCheckResult]: Stem: 150510#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 150511#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 150328#L256 assume !(1 == ~main_in1_req_up~0); 150281#L256-2 assume !(1 == ~main_in2_req_up~0); 150283#L267-1 assume !(1 == ~main_sum_req_up~0); 150730#L278-1 assume !(1 == ~main_diff_req_up~0); 150424#L289-1 assume !(1 == ~main_pres_req_up~0); 158294#L300-1 assume !(1 == ~main_dbl_req_up~0); 157317#L311-1 assume !(1 == ~main_zero_req_up~0); 157318#L322-1 assume !(1 == ~main_clk_req_up~0); 158702#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 158695#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 158687#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 158679#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 158672#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 158665#L371-1 assume !(0 == ~main_in1_ev~0); 158659#L376-1 assume !(0 == ~main_in2_ev~0); 158652#L381-1 assume !(0 == ~main_sum_ev~0); 158645#L386-1 assume !(0 == ~main_diff_ev~0); 158638#L391-1 assume !(0 == ~main_pres_ev~0); 158631#L396-1 assume !(0 == ~main_dbl_ev~0); 158623#L401-1 assume !(0 == ~main_zero_ev~0); 158619#L406-1 assume !(0 == ~main_clk_ev~0); 158616#L411-1 assume !(0 == ~main_clk_pos_edge~0); 158613#L416-1 assume !(0 == ~main_clk_neg_edge~0); 158491#L421-1 assume !(1 == ~main_clk_pos_edge~0); 158490#L426-1 assume !(1 == ~main_clk_pos_edge~0); 158489#L431-1 assume !(1 == ~main_clk_pos_edge~0); 158488#L436-1 assume !(1 == ~main_clk_pos_edge~0); 158487#L441-1 assume !(1 == ~main_clk_pos_edge~0); 158486#L446-1 assume !(1 == ~main_in1_ev~0); 158484#L451-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 158485#L456-1 assume !(1 == ~main_sum_ev~0); 163786#L461-1 assume !(1 == ~main_diff_ev~0); 163785#L466-1 assume !(1 == ~main_pres_ev~0); 163784#L471-1 assume !(1 == ~main_dbl_ev~0); 163783#L476-1 assume !(1 == ~main_zero_ev~0); 163782#L481-1 assume !(1 == ~main_clk_ev~0); 163781#L486-1 assume !(1 == ~main_clk_pos_edge~0); 163744#L491-1 assume !(1 == ~main_clk_neg_edge~0); 163740#L742-1 [2023-11-26 12:06:38,160 INFO L750 eck$LassoCheckResult]: Loop: 163740#L742-1 assume !false; 163739#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 163735#L229 assume !false; 163733#L147 assume !(0 == ~N_generate_st~0); 163729#L151 assume !(0 == ~S1_addsub_st~0); 163730#L154 assume !(0 == ~S2_presdbl_st~0); 163731#L157 assume !(0 == ~S3_zero_st~0); 163732#L160 assume !(0 == ~D_print_st~0); 163734#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 165929#L509 assume !(1 == ~main_in1_req_up~0); 165927#L509-2 assume !(1 == ~main_in2_req_up~0); 165923#L520-1 assume !(1 == ~main_sum_req_up~0); 165919#L531-1 assume !(1 == ~main_diff_req_up~0); 165917#L542-1 assume !(1 == ~main_pres_req_up~0); 165914#L553-1 assume !(1 == ~main_dbl_req_up~0); 165911#L564-1 assume !(1 == ~main_zero_req_up~0); 165907#L575-1 assume !(1 == ~main_clk_req_up~0); 165905#L586-1 start_simulation_~kernel_st~0#1 := 3; 165903#L605 assume !(0 == ~main_in1_ev~0); 165899#L605-2 assume !(0 == ~main_in2_ev~0); 165889#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 165894#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 165892#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 165890#L625-1 assume !(0 == ~main_dbl_ev~0); 165887#L630-1 assume !(0 == ~main_zero_ev~0); 165885#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 165883#L640-1 assume !(0 == ~main_clk_pos_edge~0); 165881#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 165879#L650-1 assume !(1 == ~main_clk_pos_edge~0); 165877#L655-1 assume !(1 == ~main_clk_pos_edge~0); 165875#L660-1 assume !(1 == ~main_clk_pos_edge~0); 165873#L665-1 assume !(1 == ~main_clk_pos_edge~0); 165871#L670-1 assume !(1 == ~main_clk_pos_edge~0); 165869#L675-1 assume !(1 == ~main_in1_ev~0); 165859#L680-1 assume !(1 == ~main_in2_ev~0); 161666#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 165856#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 165854#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 165852#L700-1 assume !(1 == ~main_dbl_ev~0); 165850#L705-1 assume !(1 == ~main_zero_ev~0); 165848#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 165846#L715-1 assume !(1 == ~main_clk_pos_edge~0); 165845#L720-1 assume !(1 == ~main_clk_neg_edge~0); 163747#L725-1 assume 0 == ~N_generate_st~0; 163740#L742-1 [2023-11-26 12:06:38,160 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:38,160 INFO L85 PathProgramCache]: Analyzing trace with hash -457161483, now seen corresponding path program 1 times [2023-11-26 12:06:38,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:38,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796030446] [2023-11-26 12:06:38,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:38,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:38,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:38,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:38,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:38,266 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796030446] [2023-11-26 12:06:38,266 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1796030446] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:38,267 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:38,267 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:38,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [146461772] [2023-11-26 12:06:38,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:38,272 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:38,272 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:38,272 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141774, now seen corresponding path program 1 times [2023-11-26 12:06:38,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:38,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106008877] [2023-11-26 12:06:38,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:38,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:38,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:38,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:38,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:38,309 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106008877] [2023-11-26 12:06:38,309 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1106008877] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:38,309 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:38,310 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:38,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1733666840] [2023-11-26 12:06:38,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:38,310 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:38,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:38,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:06:38,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:06:38,311 INFO L87 Difference]: Start difference. First operand 33519 states and 53550 transitions. cyclomatic complexity: 20095 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:38,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:38,778 INFO L93 Difference]: Finished difference Result 34717 states and 54842 transitions. [2023-11-26 12:06:38,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34717 states and 54842 transitions. [2023-11-26 12:06:38,951 INFO L131 ngComponentsAnalysis]: Automaton has 66 accepting balls. 32815 [2023-11-26 12:06:39,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34717 states to 34717 states and 54842 transitions. [2023-11-26 12:06:39,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34717 [2023-11-26 12:06:39,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34717 [2023-11-26 12:06:39,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34717 states and 54842 transitions. [2023-11-26 12:06:39,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:39,321 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34717 states and 54842 transitions. [2023-11-26 12:06:39,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34717 states and 54842 transitions. [2023-11-26 12:06:39,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34717 to 33519. [2023-11-26 12:06:40,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33519 states, 33519 states have (on average 1.5798800680211222) internal successors, (52956), 33518 states have internal predecessors, (52956), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:40,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33519 states to 33519 states and 52956 transitions. [2023-11-26 12:06:40,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33519 states and 52956 transitions. [2023-11-26 12:06:40,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:06:40,097 INFO L428 stractBuchiCegarLoop]: Abstraction has 33519 states and 52956 transitions. [2023-11-26 12:06:40,098 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 12:06:40,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33519 states and 52956 transitions. [2023-11-26 12:06:40,367 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2023-11-26 12:06:40,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:40,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:40,368 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:40,369 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:40,369 INFO L748 eck$LassoCheckResult]: Stem: 218752#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 218753#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 218574#L256 assume !(1 == ~main_in1_req_up~0); 218528#L256-2 assume !(1 == ~main_in2_req_up~0); 218530#L267-1 assume !(1 == ~main_sum_req_up~0); 218561#L278-1 assume !(1 == ~main_diff_req_up~0); 218509#L289-1 assume !(1 == ~main_pres_req_up~0); 218510#L300-1 assume !(1 == ~main_dbl_req_up~0); 218626#L311-1 assume !(1 == ~main_zero_req_up~0); 218997#L322-1 assume !(1 == ~main_clk_req_up~0); 218999#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 237321#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 237320#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 237319#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 237318#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 237317#L371-1 assume !(0 == ~main_in1_ev~0); 237316#L376-1 assume !(0 == ~main_in2_ev~0); 237315#L381-1 assume !(0 == ~main_sum_ev~0); 237314#L386-1 assume !(0 == ~main_diff_ev~0); 237313#L391-1 assume !(0 == ~main_pres_ev~0); 237312#L396-1 assume !(0 == ~main_dbl_ev~0); 237311#L401-1 assume !(0 == ~main_zero_ev~0); 237310#L406-1 assume !(0 == ~main_clk_ev~0); 237309#L411-1 assume !(0 == ~main_clk_pos_edge~0); 237308#L416-1 assume !(0 == ~main_clk_neg_edge~0); 237307#L421-1 assume !(1 == ~main_clk_pos_edge~0); 237306#L426-1 assume !(1 == ~main_clk_pos_edge~0); 237305#L431-1 assume !(1 == ~main_clk_pos_edge~0); 237304#L436-1 assume !(1 == ~main_clk_pos_edge~0); 237303#L441-1 assume !(1 == ~main_clk_pos_edge~0); 237302#L446-1 assume !(1 == ~main_in1_ev~0); 237301#L451-1 assume !(1 == ~main_in2_ev~0); 237300#L456-1 assume !(1 == ~main_sum_ev~0); 226375#L461-1 assume !(1 == ~main_diff_ev~0); 226374#L466-1 assume !(1 == ~main_pres_ev~0); 226373#L471-1 assume !(1 == ~main_dbl_ev~0); 226372#L476-1 assume !(1 == ~main_zero_ev~0); 226371#L481-1 assume !(1 == ~main_clk_ev~0); 226346#L486-1 assume !(1 == ~main_clk_pos_edge~0); 226347#L491-1 assume !(1 == ~main_clk_neg_edge~0); 225232#L742-1 [2023-11-26 12:06:40,369 INFO L750 eck$LassoCheckResult]: Loop: 225232#L742-1 assume !false; 225233#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 237252#L229 assume !false; 237251#L147 assume !(0 == ~N_generate_st~0); 237250#L151 assume !(0 == ~S1_addsub_st~0); 237249#L154 assume !(0 == ~S2_presdbl_st~0); 237248#L157 assume !(0 == ~S3_zero_st~0); 237247#L160 assume !(0 == ~D_print_st~0); 237246#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 237245#L509 assume !(1 == ~main_in1_req_up~0); 237244#L509-2 assume !(1 == ~main_in2_req_up~0); 237243#L520-1 assume !(1 == ~main_sum_req_up~0); 237242#L531-1 assume !(1 == ~main_diff_req_up~0); 237241#L542-1 assume !(1 == ~main_pres_req_up~0); 225190#L553-1 assume !(1 == ~main_dbl_req_up~0); 225192#L564-1 assume !(1 == ~main_zero_req_up~0); 225299#L575-1 assume !(1 == ~main_clk_req_up~0); 225300#L586-1 start_simulation_~kernel_st~0#1 := 3; 226464#L605 assume !(0 == ~main_in1_ev~0); 226460#L605-2 assume !(0 == ~main_in2_ev~0); 226456#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 226452#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 226450#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 226446#L625-1 assume !(0 == ~main_dbl_ev~0); 226403#L630-1 assume !(0 == ~main_zero_ev~0); 226402#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 226400#L640-1 assume !(0 == ~main_clk_pos_edge~0); 226399#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 226398#L650-1 assume !(1 == ~main_clk_pos_edge~0); 226397#L655-1 assume !(1 == ~main_clk_pos_edge~0); 226395#L660-1 assume !(1 == ~main_clk_pos_edge~0); 226393#L665-1 assume !(1 == ~main_clk_pos_edge~0); 226391#L670-1 assume !(1 == ~main_clk_pos_edge~0); 226389#L675-1 assume !(1 == ~main_in1_ev~0); 226387#L680-1 assume !(1 == ~main_in2_ev~0); 226385#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 226384#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 226382#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 226381#L700-1 assume !(1 == ~main_dbl_ev~0); 226380#L705-1 assume !(1 == ~main_zero_ev~0); 226379#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 225259#L715-1 assume !(1 == ~main_clk_pos_edge~0); 225255#L720-1 assume !(1 == ~main_clk_neg_edge~0); 225256#L725-1 assume 0 == ~N_generate_st~0; 225232#L742-1 [2023-11-26 12:06:40,369 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:40,370 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 2 times [2023-11-26 12:06:40,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:40,370 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724821880] [2023-11-26 12:06:40,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:40,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:40,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:40,398 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:06:40,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:40,430 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:06:40,431 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:40,432 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141774, now seen corresponding path program 2 times [2023-11-26 12:06:40,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:40,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308149041] [2023-11-26 12:06:40,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:40,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:40,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:40,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:40,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:40,454 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308149041] [2023-11-26 12:06:40,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308149041] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:40,455 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:40,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:06:40,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228006794] [2023-11-26 12:06:40,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:40,456 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:40,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:40,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:06:40,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:06:40,457 INFO L87 Difference]: Start difference. First operand 33519 states and 52956 transitions. cyclomatic complexity: 19501 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:40,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:40,659 INFO L93 Difference]: Finished difference Result 44288 states and 68290 transitions. [2023-11-26 12:06:40,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44288 states and 68290 transitions. [2023-11-26 12:06:41,021 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41518 [2023-11-26 12:06:41,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44288 states to 44288 states and 68290 transitions. [2023-11-26 12:06:41,148 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44288 [2023-11-26 12:06:41,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44288 [2023-11-26 12:06:41,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44288 states and 68290 transitions. [2023-11-26 12:06:41,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:41,227 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2023-11-26 12:06:41,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44288 states and 68290 transitions. [2023-11-26 12:06:41,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44288 to 44288. [2023-11-26 12:06:41,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44288 states, 44288 states have (on average 1.5419526734104045) internal successors, (68290), 44287 states have internal predecessors, (68290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:42,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44288 states to 44288 states and 68290 transitions. [2023-11-26 12:06:42,014 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2023-11-26 12:06:42,015 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:06:42,015 INFO L428 stractBuchiCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2023-11-26 12:06:42,016 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 12:06:42,016 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44288 states and 68290 transitions. [2023-11-26 12:06:42,202 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41518 [2023-11-26 12:06:42,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:42,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:42,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:42,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:42,204 INFO L748 eck$LassoCheckResult]: Stem: 296572#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 296573#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 296388#L256 assume !(1 == ~main_in1_req_up~0); 296341#L256-2 assume !(1 == ~main_in2_req_up~0); 296343#L267-1 assume !(1 == ~main_sum_req_up~0); 296375#L278-1 assume !(1 == ~main_diff_req_up~0); 296322#L289-1 assume !(1 == ~main_pres_req_up~0); 296323#L300-1 assume !(1 == ~main_dbl_req_up~0); 299668#L311-1 assume !(1 == ~main_zero_req_up~0); 299669#L322-1 assume !(1 == ~main_clk_req_up~0); 299782#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 299926#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 299924#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 299922#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 299878#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 299877#L371-1 assume !(0 == ~main_in1_ev~0); 299876#L376-1 assume !(0 == ~main_in2_ev~0); 299874#L381-1 assume !(0 == ~main_sum_ev~0); 299872#L386-1 assume !(0 == ~main_diff_ev~0); 299871#L391-1 assume !(0 == ~main_pres_ev~0); 299870#L396-1 assume !(0 == ~main_dbl_ev~0); 299869#L401-1 assume !(0 == ~main_zero_ev~0); 299867#L406-1 assume !(0 == ~main_clk_ev~0); 299865#L411-1 assume !(0 == ~main_clk_pos_edge~0); 299862#L416-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 299860#L421-1 assume !(1 == ~main_clk_pos_edge~0); 299858#L426-1 assume !(1 == ~main_clk_pos_edge~0); 299853#L431-1 assume !(1 == ~main_clk_pos_edge~0); 299848#L436-1 assume !(1 == ~main_clk_pos_edge~0); 299843#L441-1 assume !(1 == ~main_clk_pos_edge~0); 299838#L446-1 assume !(1 == ~main_in1_ev~0); 299832#L451-1 assume !(1 == ~main_in2_ev~0); 299828#L456-1 assume !(1 == ~main_sum_ev~0); 299825#L461-1 assume !(1 == ~main_diff_ev~0); 299822#L466-1 assume !(1 == ~main_pres_ev~0); 299818#L471-1 assume !(1 == ~main_dbl_ev~0); 299814#L476-1 assume !(1 == ~main_zero_ev~0); 299790#L481-1 assume !(1 == ~main_clk_ev~0); 299741#L486-1 assume !(1 == ~main_clk_pos_edge~0); 299730#L491-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 299454#L742-1 [2023-11-26 12:06:42,205 INFO L750 eck$LassoCheckResult]: Loop: 299454#L742-1 assume !false; 299721#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 310987#L229 assume !false; 310985#L147 assume !(0 == ~N_generate_st~0); 310981#L151 assume !(0 == ~S1_addsub_st~0); 310982#L154 assume !(0 == ~S2_presdbl_st~0); 310983#L157 assume !(0 == ~S3_zero_st~0); 310984#L160 assume !(0 == ~D_print_st~0); 310986#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 311155#L509 assume !(1 == ~main_in1_req_up~0); 311153#L509-2 assume !(1 == ~main_in2_req_up~0); 311150#L520-1 assume !(1 == ~main_sum_req_up~0); 311148#L531-1 assume !(1 == ~main_diff_req_up~0); 311146#L542-1 assume !(1 == ~main_pres_req_up~0); 299509#L553-1 assume !(1 == ~main_dbl_req_up~0); 299507#L564-1 assume !(1 == ~main_zero_req_up~0); 299505#L575-1 assume !(1 == ~main_clk_req_up~0); 299506#L586-1 start_simulation_~kernel_st~0#1 := 3; 299868#L605 assume !(0 == ~main_in1_ev~0); 299866#L605-2 assume !(0 == ~main_in2_ev~0); 299864#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 299861#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 299859#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 299857#L625-1 assume !(0 == ~main_dbl_ev~0); 299852#L630-1 assume !(0 == ~main_zero_ev~0); 299847#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 299842#L640-1 assume !(0 == ~main_clk_pos_edge~0); 299836#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 299831#L650-1 assume !(1 == ~main_clk_pos_edge~0); 299827#L655-1 assume !(1 == ~main_clk_pos_edge~0); 299824#L660-1 assume !(1 == ~main_clk_pos_edge~0); 299821#L665-1 assume !(1 == ~main_clk_pos_edge~0); 299817#L670-1 assume !(1 == ~main_clk_pos_edge~0); 299813#L675-1 assume !(1 == ~main_in1_ev~0); 299784#L680-1 assume !(1 == ~main_in2_ev~0); 299735#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 299725#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 299717#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 299709#L700-1 assume !(1 == ~main_dbl_ev~0); 299704#L705-1 assume !(1 == ~main_zero_ev~0); 299678#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 299468#L715-1 assume !(1 == ~main_clk_pos_edge~0); 299463#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 299461#L725-1 assume 0 == ~N_generate_st~0; 299454#L742-1 [2023-11-26 12:06:42,205 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:42,205 INFO L85 PathProgramCache]: Analyzing trace with hash 1243965239, now seen corresponding path program 1 times [2023-11-26 12:06:42,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:42,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312062053] [2023-11-26 12:06:42,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:42,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:42,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:42,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:42,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:42,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312062053] [2023-11-26 12:06:42,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312062053] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:42,270 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:42,270 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:06:42,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561245951] [2023-11-26 12:06:42,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:42,271 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:06:42,271 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:42,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141836, now seen corresponding path program 1 times [2023-11-26 12:06:42,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:42,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779763524] [2023-11-26 12:06:42,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:42,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:42,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:42,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:42,300 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:42,301 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779763524] [2023-11-26 12:06:42,301 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1779763524] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:42,301 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:42,301 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:06:42,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317873887] [2023-11-26 12:06:42,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:42,302 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:42,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:42,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:06:42,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:06:42,303 INFO L87 Difference]: Start difference. First operand 44288 states and 68290 transitions. cyclomatic complexity: 24066 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:42,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:42,732 INFO L93 Difference]: Finished difference Result 53275 states and 81140 transitions. [2023-11-26 12:06:42,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53275 states and 81140 transitions. [2023-11-26 12:06:43,282 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 50818 [2023-11-26 12:06:43,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53275 states to 53275 states and 81140 transitions. [2023-11-26 12:06:43,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53275 [2023-11-26 12:06:43,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53275 [2023-11-26 12:06:43,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53275 states and 81140 transitions. [2023-11-26 12:06:43,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:43,532 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53275 states and 81140 transitions. [2023-11-26 12:06:43,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53275 states and 81140 transitions. [2023-11-26 12:06:43,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53275 to 41741. [2023-11-26 12:06:43,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41741 states, 41741 states have (on average 1.5255504180541912) internal successors, (63678), 41740 states have internal predecessors, (63678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:43,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41741 states to 41741 states and 63678 transitions. [2023-11-26 12:06:43,989 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41741 states and 63678 transitions. [2023-11-26 12:06:43,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-26 12:06:43,989 INFO L428 stractBuchiCegarLoop]: Abstraction has 41741 states and 63678 transitions. [2023-11-26 12:06:43,990 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 12:06:43,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41741 states and 63678 transitions. [2023-11-26 12:06:44,415 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 39570 [2023-11-26 12:06:44,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:44,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:44,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:44,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:44,419 INFO L748 eck$LassoCheckResult]: Stem: 394150#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 394151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 393960#L256 assume !(1 == ~main_in1_req_up~0); 393914#L256-2 assume !(1 == ~main_in2_req_up~0); 393916#L267-1 assume !(1 == ~main_sum_req_up~0); 393947#L278-1 assume !(1 == ~main_diff_req_up~0); 393895#L289-1 assume !(1 == ~main_pres_req_up~0); 393896#L300-1 assume !(1 == ~main_dbl_req_up~0); 394008#L311-1 assume !(1 == ~main_zero_req_up~0); 394443#L322-1 assume !(1 == ~main_clk_req_up~0); 394445#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 395260#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 393936#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 393937#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 394453#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 394454#L371-1 assume !(0 == ~main_in1_ev~0); 393986#L376-1 assume !(0 == ~main_in2_ev~0); 393987#L381-1 assume !(0 == ~main_sum_ev~0); 394159#L386-1 assume !(0 == ~main_diff_ev~0); 394160#L391-1 assume !(0 == ~main_pres_ev~0); 394315#L396-1 assume !(0 == ~main_dbl_ev~0); 394316#L401-1 assume !(0 == ~main_zero_ev~0); 401260#L406-1 assume !(0 == ~main_clk_ev~0); 401258#L411-1 assume !(0 == ~main_clk_pos_edge~0); 401259#L416-1 assume !(0 == ~main_clk_neg_edge~0); 401256#L421-1 assume !(1 == ~main_clk_pos_edge~0); 401257#L426-1 assume !(1 == ~main_clk_pos_edge~0); 401254#L431-1 assume !(1 == ~main_clk_pos_edge~0); 401255#L436-1 assume !(1 == ~main_clk_pos_edge~0); 401252#L441-1 assume !(1 == ~main_clk_pos_edge~0); 401253#L446-1 assume !(1 == ~main_in1_ev~0); 401249#L451-1 assume !(1 == ~main_in2_ev~0); 401250#L456-1 assume !(1 == ~main_sum_ev~0); 401245#L461-1 assume !(1 == ~main_diff_ev~0); 401246#L466-1 assume !(1 == ~main_pres_ev~0); 401241#L471-1 assume !(1 == ~main_dbl_ev~0); 401242#L476-1 assume !(1 == ~main_zero_ev~0); 401237#L481-1 assume !(1 == ~main_clk_ev~0); 401238#L486-1 assume !(1 == ~main_clk_pos_edge~0); 401185#L491-1 assume !(1 == ~main_clk_neg_edge~0); 401181#L742-1 [2023-11-26 12:06:44,419 INFO L750 eck$LassoCheckResult]: Loop: 401181#L742-1 assume !false; 401177#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 401068#L229 assume !false; 401064#L147 assume !(0 == ~N_generate_st~0); 401059#L151 assume !(0 == ~S1_addsub_st~0); 401057#L154 assume !(0 == ~S2_presdbl_st~0); 401055#L157 assume !(0 == ~S3_zero_st~0); 401052#L160 assume !(0 == ~D_print_st~0); 401050#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 401048#L509 assume !(1 == ~main_in1_req_up~0); 401044#L509-2 assume !(1 == ~main_in2_req_up~0); 401045#L520-1 assume !(1 == ~main_sum_req_up~0); 401357#L531-1 assume !(1 == ~main_diff_req_up~0); 401354#L542-1 assume !(1 == ~main_pres_req_up~0); 401349#L553-1 assume !(1 == ~main_dbl_req_up~0); 401340#L564-1 assume !(1 == ~main_zero_req_up~0); 401333#L575-1 assume !(1 == ~main_clk_req_up~0); 401334#L586-1 start_simulation_~kernel_st~0#1 := 3; 401405#L605 assume !(0 == ~main_in1_ev~0); 401398#L605-2 assume !(0 == ~main_in2_ev~0); 401396#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 401393#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 401390#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 401386#L625-1 assume !(0 == ~main_dbl_ev~0); 401382#L630-1 assume !(0 == ~main_zero_ev~0); 401381#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 401379#L640-1 assume !(0 == ~main_clk_pos_edge~0); 401377#L645-1 assume !(0 == ~main_clk_neg_edge~0); 401375#L650-1 assume !(1 == ~main_clk_pos_edge~0); 401373#L655-1 assume !(1 == ~main_clk_pos_edge~0); 401371#L660-1 assume !(1 == ~main_clk_pos_edge~0); 401369#L665-1 assume !(1 == ~main_clk_pos_edge~0); 401367#L670-1 assume !(1 == ~main_clk_pos_edge~0); 401365#L675-1 assume !(1 == ~main_in1_ev~0); 401364#L680-1 assume !(1 == ~main_in2_ev~0); 401363#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 401360#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 401356#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 401351#L700-1 assume !(1 == ~main_dbl_ev~0); 401346#L705-1 assume !(1 == ~main_zero_ev~0); 401338#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 401302#L715-1 assume !(1 == ~main_clk_pos_edge~0); 401266#L720-1 assume !(1 == ~main_clk_neg_edge~0); 401190#L725-1 assume 0 == ~N_generate_st~0; 401181#L742-1 [2023-11-26 12:06:44,420 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:44,420 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 3 times [2023-11-26 12:06:44,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:44,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019421019] [2023-11-26 12:06:44,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:44,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:44,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:44,435 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:06:44,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:44,453 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:06:44,454 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:44,454 INFO L85 PathProgramCache]: Analyzing trace with hash 1374477620, now seen corresponding path program 1 times [2023-11-26 12:06:44,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:44,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046589344] [2023-11-26 12:06:44,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:44,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:44,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:44,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:44,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:44,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046589344] [2023-11-26 12:06:44,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046589344] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:44,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:44,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:06:44,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675006243] [2023-11-26 12:06:44,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:44,481 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:44,481 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:44,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:06:44,482 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:06:44,482 INFO L87 Difference]: Start difference. First operand 41741 states and 63678 transitions. cyclomatic complexity: 22001 Second operand has 3 states, 2 states have (on average 22.0) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:44,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:44,713 INFO L93 Difference]: Finished difference Result 57643 states and 86947 transitions. [2023-11-26 12:06:44,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57643 states and 86947 transitions. [2023-11-26 12:06:44,932 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 53732 [2023-11-26 12:06:45,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57643 states to 57643 states and 86947 transitions. [2023-11-26 12:06:45,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57643 [2023-11-26 12:06:45,103 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57643 [2023-11-26 12:06:45,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57643 states and 86947 transitions. [2023-11-26 12:06:45,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:45,134 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2023-11-26 12:06:45,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57643 states and 86947 transitions. [2023-11-26 12:06:46,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57643 to 57643. [2023-11-26 12:06:46,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57643 states, 57643 states have (on average 1.5083704873098207) internal successors, (86947), 57642 states have internal predecessors, (86947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:46,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57643 states to 57643 states and 86947 transitions. [2023-11-26 12:06:46,209 INFO L240 hiAutomatonCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2023-11-26 12:06:46,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:06:46,210 INFO L428 stractBuchiCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2023-11-26 12:06:46,210 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 12:06:46,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57643 states and 86947 transitions. [2023-11-26 12:06:46,369 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 53732 [2023-11-26 12:06:46,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:46,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:46,370 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:46,370 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:46,370 INFO L748 eck$LassoCheckResult]: Stem: 493538#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 493539#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 493352#L256 assume !(1 == ~main_in1_req_up~0); 493304#L256-2 assume !(1 == ~main_in2_req_up~0); 493306#L267-1 assume !(1 == ~main_sum_req_up~0); 493339#L278-1 assume !(1 == ~main_diff_req_up~0); 496626#L289-1 assume !(1 == ~main_pres_req_up~0); 493741#L300-1 assume !(1 == ~main_dbl_req_up~0); 493742#L311-1 assume !(1 == ~main_zero_req_up~0); 497327#L322-1 assume !(1 == ~main_clk_req_up~0); 497328#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 497401#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 497400#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 497399#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 497398#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 497397#L371-1 assume !(0 == ~main_in1_ev~0); 497396#L376-1 assume !(0 == ~main_in2_ev~0); 497395#L381-1 assume !(0 == ~main_sum_ev~0); 497394#L386-1 assume !(0 == ~main_diff_ev~0); 497393#L391-1 assume !(0 == ~main_pres_ev~0); 497392#L396-1 assume !(0 == ~main_dbl_ev~0); 497391#L401-1 assume !(0 == ~main_zero_ev~0); 497390#L406-1 assume !(0 == ~main_clk_ev~0); 497388#L411-1 assume !(0 == ~main_clk_pos_edge~0); 497389#L416-1 assume !(0 == ~main_clk_neg_edge~0); 502737#L421-1 assume !(1 == ~main_clk_pos_edge~0); 502736#L426-1 assume !(1 == ~main_clk_pos_edge~0); 502735#L431-1 assume !(1 == ~main_clk_pos_edge~0); 502734#L436-1 assume !(1 == ~main_clk_pos_edge~0); 502733#L441-1 assume !(1 == ~main_clk_pos_edge~0); 502732#L446-1 assume !(1 == ~main_in1_ev~0); 502731#L451-1 assume !(1 == ~main_in2_ev~0); 502730#L456-1 assume !(1 == ~main_sum_ev~0); 502729#L461-1 assume !(1 == ~main_diff_ev~0); 502728#L466-1 assume !(1 == ~main_pres_ev~0); 502727#L471-1 assume !(1 == ~main_dbl_ev~0); 502724#L476-1 assume !(1 == ~main_zero_ev~0); 502722#L481-1 assume !(1 == ~main_clk_ev~0); 502720#L486-1 assume !(1 == ~main_clk_pos_edge~0); 497233#L491-1 assume !(1 == ~main_clk_neg_edge~0); 497234#L742-1 [2023-11-26 12:06:46,370 INFO L750 eck$LassoCheckResult]: Loop: 497234#L742-1 assume !false; 497225#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 497222#L229 assume !false; 497216#L147 assume !(0 == ~N_generate_st~0); 496376#L151 assume !(0 == ~S1_addsub_st~0); 497210#L154 assume !(0 == ~S2_presdbl_st~0); 497211#L157 assume !(0 == ~S3_zero_st~0); 497202#L160 assume !(0 == ~D_print_st~0); 497203#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 497197#L509 assume !(1 == ~main_in1_req_up~0); 497198#L509-2 assume !(1 == ~main_in2_req_up~0); 497189#L520-1 assume !(1 == ~main_sum_req_up~0); 497188#L531-1 assume !(1 == ~main_diff_req_up~0); 497174#L542-1 assume !(1 == ~main_pres_req_up~0); 497173#L553-1 assume !(1 == ~main_dbl_req_up~0); 497164#L564-1 assume !(1 == ~main_zero_req_up~0); 497159#L575-1 assume !(1 == ~main_clk_req_up~0); 497160#L586-1 start_simulation_~kernel_st~0#1 := 3; 497351#L605 assume !(0 == ~main_in1_ev~0); 497349#L605-2 assume !(0 == ~main_in2_ev~0); 497347#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 497345#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 497343#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 497341#L625-1 assume !(0 == ~main_dbl_ev~0); 497339#L630-1 assume !(0 == ~main_zero_ev~0); 497337#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 497335#L640-1 assume !(0 == ~main_clk_pos_edge~0); 497333#L645-1 assume !(0 == ~main_clk_neg_edge~0); 497302#L650-1 assume !(1 == ~main_clk_pos_edge~0); 497300#L655-1 assume !(1 == ~main_clk_pos_edge~0); 497298#L660-1 assume !(1 == ~main_clk_pos_edge~0); 497296#L665-1 assume !(1 == ~main_clk_pos_edge~0); 497294#L670-1 assume !(1 == ~main_clk_pos_edge~0); 497291#L675-1 assume !(1 == ~main_in1_ev~0); 497292#L680-1 assume !(1 == ~main_in2_ev~0); 497285#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 497286#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 502746#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 502745#L700-1 assume !(1 == ~main_dbl_ev~0); 502744#L705-1 assume !(1 == ~main_zero_ev~0); 502743#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 502742#L715-1 assume !(1 == ~main_clk_pos_edge~0); 502741#L720-1 assume !(1 == ~main_clk_neg_edge~0); 502740#L725-1 assume !(0 == ~N_generate_st~0); 497238#L733 assume 0 == ~S1_addsub_st~0; 497234#L742-1 [2023-11-26 12:06:46,371 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:46,371 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 4 times [2023-11-26 12:06:46,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:46,371 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896879018] [2023-11-26 12:06:46,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:46,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:46,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:46,388 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:06:46,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:46,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:06:46,425 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:46,425 INFO L85 PathProgramCache]: Analyzing trace with hash -340865996, now seen corresponding path program 1 times [2023-11-26 12:06:46,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:46,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199124866] [2023-11-26 12:06:46,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:46,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:46,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:46,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:46,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:46,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199124866] [2023-11-26 12:06:46,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199124866] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:46,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:46,452 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:06:46,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1820494384] [2023-11-26 12:06:46,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:46,453 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:46,453 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:46,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:06:46,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:06:46,454 INFO L87 Difference]: Start difference. First operand 57643 states and 86947 transitions. cyclomatic complexity: 29376 Second operand has 3 states, 2 states have (on average 22.5) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:47,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:47,247 INFO L93 Difference]: Finished difference Result 86850 states and 129727 transitions. [2023-11-26 12:06:47,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86850 states and 129727 transitions. [2023-11-26 12:06:47,589 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 79456 [2023-11-26 12:06:47,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86850 states to 86850 states and 129727 transitions. [2023-11-26 12:06:47,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86850 [2023-11-26 12:06:47,834 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86850 [2023-11-26 12:06:47,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86850 states and 129727 transitions. [2023-11-26 12:06:47,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:47,877 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2023-11-26 12:06:47,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86850 states and 129727 transitions. [2023-11-26 12:06:48,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86850 to 86850. [2023-11-26 12:06:49,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86850 states, 86850 states have (on average 1.4936902705814623) internal successors, (129727), 86849 states have internal predecessors, (129727), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:49,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86850 states to 86850 states and 129727 transitions. [2023-11-26 12:06:49,198 INFO L240 hiAutomatonCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2023-11-26 12:06:49,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:06:49,199 INFO L428 stractBuchiCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2023-11-26 12:06:49,200 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 12:06:49,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86850 states and 129727 transitions. [2023-11-26 12:06:49,413 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 79456 [2023-11-26 12:06:49,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:49,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:49,414 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:49,414 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:49,414 INFO L748 eck$LassoCheckResult]: Stem: 638035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 638036#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 637852#L256 assume !(1 == ~main_in1_req_up~0); 637803#L256-2 assume !(1 == ~main_in2_req_up~0); 637805#L267-1 assume !(1 == ~main_sum_req_up~0); 638292#L278-1 assume !(1 == ~main_diff_req_up~0); 637951#L289-1 assume !(1 == ~main_pres_req_up~0); 638231#L300-1 assume !(1 == ~main_dbl_req_up~0); 638232#L311-1 assume !(1 == ~main_zero_req_up~0); 648287#L322-1 assume !(1 == ~main_clk_req_up~0); 648283#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 648284#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 648400#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 648398#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 648396#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 648394#L371-1 assume !(0 == ~main_in1_ev~0); 648392#L376-1 assume !(0 == ~main_in2_ev~0); 648390#L381-1 assume !(0 == ~main_sum_ev~0); 648388#L386-1 assume !(0 == ~main_diff_ev~0); 648386#L391-1 assume !(0 == ~main_pres_ev~0); 648384#L396-1 assume !(0 == ~main_dbl_ev~0); 648382#L401-1 assume !(0 == ~main_zero_ev~0); 648380#L406-1 assume !(0 == ~main_clk_ev~0); 648378#L411-1 assume !(0 == ~main_clk_pos_edge~0); 648376#L416-1 assume !(0 == ~main_clk_neg_edge~0); 648374#L421-1 assume !(1 == ~main_clk_pos_edge~0); 648372#L426-1 assume !(1 == ~main_clk_pos_edge~0); 648370#L431-1 assume !(1 == ~main_clk_pos_edge~0); 648368#L436-1 assume !(1 == ~main_clk_pos_edge~0); 648366#L441-1 assume !(1 == ~main_clk_pos_edge~0); 648364#L446-1 assume !(1 == ~main_in1_ev~0); 648362#L451-1 assume !(1 == ~main_in2_ev~0); 648360#L456-1 assume !(1 == ~main_sum_ev~0); 648358#L461-1 assume !(1 == ~main_diff_ev~0); 648354#L466-1 assume !(1 == ~main_pres_ev~0); 648352#L471-1 assume !(1 == ~main_dbl_ev~0); 648349#L476-1 assume !(1 == ~main_zero_ev~0); 648346#L481-1 assume !(1 == ~main_clk_ev~0); 648333#L486-1 assume !(1 == ~main_clk_pos_edge~0); 648334#L491-1 assume !(1 == ~main_clk_neg_edge~0); 645702#L742-1 [2023-11-26 12:06:49,415 INFO L750 eck$LassoCheckResult]: Loop: 645702#L742-1 assume !false; 648321#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 648299#L229 assume !false; 648300#L147 assume !(0 == ~N_generate_st~0); 646253#L151 assume !(0 == ~S1_addsub_st~0); 646252#L154 assume !(0 == ~S2_presdbl_st~0); 646251#L157 assume !(0 == ~S3_zero_st~0); 646249#L160 assume !(0 == ~D_print_st~0); 646248#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 646247#L509 assume !(1 == ~main_in1_req_up~0); 646245#L509-2 assume !(1 == ~main_in2_req_up~0); 646143#L520-1 assume !(1 == ~main_sum_req_up~0); 646131#L531-1 assume !(1 == ~main_diff_req_up~0); 645979#L542-1 assume !(1 == ~main_pres_req_up~0); 645975#L553-1 assume !(1 == ~main_dbl_req_up~0); 645972#L564-1 assume !(1 == ~main_zero_req_up~0); 645821#L575-1 assume !(1 == ~main_clk_req_up~0); 645818#L586-1 start_simulation_~kernel_st~0#1 := 3; 645816#L605 assume !(0 == ~main_in1_ev~0); 645814#L605-2 assume !(0 == ~main_in2_ev~0); 645812#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 645810#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 645808#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 645806#L625-1 assume !(0 == ~main_dbl_ev~0); 645804#L630-1 assume !(0 == ~main_zero_ev~0); 645802#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 645800#L640-1 assume !(0 == ~main_clk_pos_edge~0); 645798#L645-1 assume !(0 == ~main_clk_neg_edge~0); 645796#L650-1 assume !(1 == ~main_clk_pos_edge~0); 645794#L655-1 assume !(1 == ~main_clk_pos_edge~0); 645792#L660-1 assume !(1 == ~main_clk_pos_edge~0); 645790#L665-1 assume !(1 == ~main_clk_pos_edge~0); 645788#L670-1 assume !(1 == ~main_clk_pos_edge~0); 645786#L675-1 assume !(1 == ~main_in1_ev~0); 645784#L680-1 assume !(1 == ~main_in2_ev~0); 645782#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 645779#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 645777#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 645775#L700-1 assume !(1 == ~main_dbl_ev~0); 645773#L705-1 assume !(1 == ~main_zero_ev~0); 645771#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 645769#L715-1 assume !(1 == ~main_clk_pos_edge~0); 645767#L720-1 assume !(1 == ~main_clk_neg_edge~0); 645765#L725-1 assume !(0 == ~N_generate_st~0); 645763#L733 assume !(0 == ~S1_addsub_st~0); 645761#L736 assume 0 == ~S2_presdbl_st~0; 645702#L742-1 [2023-11-26 12:06:49,415 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:49,415 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 5 times [2023-11-26 12:06:49,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:49,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713019827] [2023-11-26 12:06:49,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:49,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:49,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:49,427 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:06:49,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:49,441 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:06:49,442 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:49,442 INFO L85 PathProgramCache]: Analyzing trace with hash -1976910535, now seen corresponding path program 1 times [2023-11-26 12:06:49,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:49,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905538892] [2023-11-26 12:06:49,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:49,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:49,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:49,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:49,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:49,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1905538892] [2023-11-26 12:06:49,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1905538892] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:49,466 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:49,466 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:06:49,466 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984906717] [2023-11-26 12:06:49,466 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:49,466 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:49,467 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:49,467 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:06:49,467 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:06:49,467 INFO L87 Difference]: Start difference. First operand 86850 states and 129727 transitions. cyclomatic complexity: 42973 Second operand has 3 states, 2 states have (on average 23.0) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:50,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:50,307 INFO L93 Difference]: Finished difference Result 91777 states and 136566 transitions. [2023-11-26 12:06:50,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91777 states and 136566 transitions. [2023-11-26 12:06:50,657 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 84178 [2023-11-26 12:06:50,813 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91777 states to 91777 states and 136566 transitions. [2023-11-26 12:06:50,813 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91777 [2023-11-26 12:06:50,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91777 [2023-11-26 12:06:50,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91777 states and 136566 transitions. [2023-11-26 12:06:50,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:50,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2023-11-26 12:06:50,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91777 states and 136566 transitions. [2023-11-26 12:06:51,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91777 to 91777. [2023-11-26 12:06:51,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91777 states, 91777 states have (on average 1.4880198742604356) internal successors, (136566), 91776 states have internal predecessors, (136566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:52,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91777 states to 91777 states and 136566 transitions. [2023-11-26 12:06:52,121 INFO L240 hiAutomatonCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2023-11-26 12:06:52,121 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:06:52,122 INFO L428 stractBuchiCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2023-11-26 12:06:52,122 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 12:06:52,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91777 states and 136566 transitions. [2023-11-26 12:06:52,354 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 84178 [2023-11-26 12:06:52,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:52,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:52,355 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:52,355 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:52,356 INFO L748 eck$LassoCheckResult]: Stem: 816675#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 816676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 816484#L256 assume !(1 == ~main_in1_req_up~0); 816436#L256-2 assume !(1 == ~main_in2_req_up~0); 816438#L267-1 assume !(1 == ~main_sum_req_up~0); 816471#L278-1 assume !(1 == ~main_diff_req_up~0); 816417#L289-1 assume !(1 == ~main_pres_req_up~0); 816418#L300-1 assume !(1 == ~main_dbl_req_up~0); 819934#L311-1 assume !(1 == ~main_zero_req_up~0); 819929#L322-1 assume !(1 == ~main_clk_req_up~0); 819925#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 819926#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 826652#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 826677#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 826676#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 826675#L371-1 assume !(0 == ~main_in1_ev~0); 826674#L376-1 assume !(0 == ~main_in2_ev~0); 826673#L381-1 assume !(0 == ~main_sum_ev~0); 826672#L386-1 assume !(0 == ~main_diff_ev~0); 826671#L391-1 assume !(0 == ~main_pres_ev~0); 826670#L396-1 assume !(0 == ~main_dbl_ev~0); 826669#L401-1 assume !(0 == ~main_zero_ev~0); 826668#L406-1 assume !(0 == ~main_clk_ev~0); 826667#L411-1 assume !(0 == ~main_clk_pos_edge~0); 826666#L416-1 assume !(0 == ~main_clk_neg_edge~0); 826665#L421-1 assume !(1 == ~main_clk_pos_edge~0); 826664#L426-1 assume !(1 == ~main_clk_pos_edge~0); 826663#L431-1 assume !(1 == ~main_clk_pos_edge~0); 826662#L436-1 assume !(1 == ~main_clk_pos_edge~0); 826661#L441-1 assume !(1 == ~main_clk_pos_edge~0); 826660#L446-1 assume !(1 == ~main_in1_ev~0); 826659#L451-1 assume !(1 == ~main_in2_ev~0); 826658#L456-1 assume !(1 == ~main_sum_ev~0); 826657#L461-1 assume !(1 == ~main_diff_ev~0); 826656#L466-1 assume !(1 == ~main_pres_ev~0); 826653#L471-1 assume !(1 == ~main_dbl_ev~0); 826648#L476-1 assume !(1 == ~main_zero_ev~0); 826642#L481-1 assume !(1 == ~main_clk_ev~0); 826637#L486-1 assume !(1 == ~main_clk_pos_edge~0); 826565#L491-1 assume !(1 == ~main_clk_neg_edge~0); 826555#L742-1 [2023-11-26 12:06:52,356 INFO L750 eck$LassoCheckResult]: Loop: 826555#L742-1 assume !false; 826556#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 826269#L229 assume !false; 826270#L147 assume !(0 == ~N_generate_st~0); 819809#L151 assume !(0 == ~S1_addsub_st~0); 825299#L154 assume !(0 == ~S2_presdbl_st~0); 825298#L157 assume !(0 == ~S3_zero_st~0); 825296#L160 assume !(0 == ~D_print_st~0); 825295#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 825294#L509 assume !(1 == ~main_in1_req_up~0); 825292#L509-2 assume !(1 == ~main_in2_req_up~0); 825293#L520-1 assume !(1 == ~main_sum_req_up~0); 826649#L531-1 assume !(1 == ~main_diff_req_up~0); 826645#L542-1 assume !(1 == ~main_pres_req_up~0); 826639#L553-1 assume !(1 == ~main_dbl_req_up~0); 826633#L564-1 assume !(1 == ~main_zero_req_up~0); 826629#L575-1 assume !(1 == ~main_clk_req_up~0); 826626#L586-1 start_simulation_~kernel_st~0#1 := 3; 826624#L605 assume !(0 == ~main_in1_ev~0); 826622#L605-2 assume !(0 == ~main_in2_ev~0); 826620#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 826618#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 826616#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 826614#L625-1 assume !(0 == ~main_dbl_ev~0); 826612#L630-1 assume !(0 == ~main_zero_ev~0); 826610#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 826608#L640-1 assume !(0 == ~main_clk_pos_edge~0); 826606#L645-1 assume !(0 == ~main_clk_neg_edge~0); 826604#L650-1 assume !(1 == ~main_clk_pos_edge~0); 826602#L655-1 assume !(1 == ~main_clk_pos_edge~0); 826600#L660-1 assume !(1 == ~main_clk_pos_edge~0); 826598#L665-1 assume !(1 == ~main_clk_pos_edge~0); 826596#L670-1 assume !(1 == ~main_clk_pos_edge~0); 826594#L675-1 assume !(1 == ~main_in1_ev~0); 826592#L680-1 assume !(1 == ~main_in2_ev~0); 826590#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 826588#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 826586#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 826584#L700-1 assume !(1 == ~main_dbl_ev~0); 826582#L705-1 assume !(1 == ~main_zero_ev~0); 826580#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 826576#L715-1 assume !(1 == ~main_clk_pos_edge~0); 826573#L720-1 assume !(1 == ~main_clk_neg_edge~0); 826572#L725-1 assume !(0 == ~N_generate_st~0); 826571#L733 assume !(0 == ~S1_addsub_st~0); 826570#L736 assume !(0 == ~S2_presdbl_st~0); 826566#L739 assume 0 == ~S3_zero_st~0; 826555#L742-1 [2023-11-26 12:06:52,356 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:52,357 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 6 times [2023-11-26 12:06:52,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:52,357 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928167745] [2023-11-26 12:06:52,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:52,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:52,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:52,369 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:06:52,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:52,384 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:06:52,384 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:52,385 INFO L85 PathProgramCache]: Analyzing trace with hash -1154683687, now seen corresponding path program 1 times [2023-11-26 12:06:52,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:52,385 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403634205] [2023-11-26 12:06:52,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:52,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:52,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:52,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:52,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:52,411 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1403634205] [2023-11-26 12:06:52,411 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1403634205] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:52,411 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:52,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:06:52,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337820146] [2023-11-26 12:06:52,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:52,412 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:52,413 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:52,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:06:52,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:06:52,413 INFO L87 Difference]: Start difference. First operand 91777 states and 136566 transitions. cyclomatic complexity: 44885 Second operand has 3 states, 2 states have (on average 23.5) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:53,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:53,481 INFO L93 Difference]: Finished difference Result 147978 states and 218783 transitions. [2023-11-26 12:06:53,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147978 states and 218783 transitions. [2023-11-26 12:06:54,114 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 133258 [2023-11-26 12:06:54,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147978 states to 147978 states and 218783 transitions. [2023-11-26 12:06:54,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147978 [2023-11-26 12:06:54,573 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147978 [2023-11-26 12:06:54,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147978 states and 218783 transitions. [2023-11-26 12:06:54,667 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:06:54,668 INFO L218 hiAutomatonCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2023-11-26 12:06:54,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147978 states and 218783 transitions. [2023-11-26 12:06:57,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147978 to 147978. [2023-11-26 12:06:57,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147978 states, 147978 states have (on average 1.4784832880563328) internal successors, (218783), 147977 states have internal predecessors, (218783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:57,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147978 states to 147978 states and 218783 transitions. [2023-11-26 12:06:57,563 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2023-11-26 12:06:57,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:06:57,563 INFO L428 stractBuchiCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2023-11-26 12:06:57,564 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 12:06:57,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147978 states and 218783 transitions. [2023-11-26 12:06:57,937 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 133258 [2023-11-26 12:06:57,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:06:57,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:06:57,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:57,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:06:57,938 INFO L748 eck$LassoCheckResult]: Stem: 1056434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1056435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1056243#L256 assume !(1 == ~main_in1_req_up~0); 1056196#L256-2 assume !(1 == ~main_in2_req_up~0); 1056198#L267-1 assume !(1 == ~main_sum_req_up~0); 1056230#L278-1 assume !(1 == ~main_diff_req_up~0); 1056178#L289-1 assume !(1 == ~main_pres_req_up~0); 1056179#L300-1 assume !(1 == ~main_dbl_req_up~0); 1069168#L311-1 assume !(1 == ~main_zero_req_up~0); 1069169#L322-1 assume !(1 == ~main_clk_req_up~0); 1070094#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1070348#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 1071478#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1071476#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1071477#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 1071746#L371-1 assume !(0 == ~main_in1_ev~0); 1071745#L376-1 assume !(0 == ~main_in2_ev~0); 1071744#L381-1 assume !(0 == ~main_sum_ev~0); 1071743#L386-1 assume !(0 == ~main_diff_ev~0); 1071742#L391-1 assume !(0 == ~main_pres_ev~0); 1071741#L396-1 assume !(0 == ~main_dbl_ev~0); 1071740#L401-1 assume !(0 == ~main_zero_ev~0); 1071739#L406-1 assume !(0 == ~main_clk_ev~0); 1071738#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1071737#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1071736#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1071735#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1071733#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1071731#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1071729#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1071727#L446-1 assume !(1 == ~main_in1_ev~0); 1071725#L451-1 assume !(1 == ~main_in2_ev~0); 1071723#L456-1 assume !(1 == ~main_sum_ev~0); 1071721#L461-1 assume !(1 == ~main_diff_ev~0); 1071719#L466-1 assume !(1 == ~main_pres_ev~0); 1071717#L471-1 assume !(1 == ~main_dbl_ev~0); 1071715#L476-1 assume !(1 == ~main_zero_ev~0); 1071713#L481-1 assume !(1 == ~main_clk_ev~0); 1071695#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1071696#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1071708#L742-1 [2023-11-26 12:06:57,938 INFO L750 eck$LassoCheckResult]: Loop: 1071708#L742-1 assume !false; 1071707#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1070729#L229 assume !false; 1070730#L147 assume !(0 == ~N_generate_st~0); 1069172#L151 assume !(0 == ~S1_addsub_st~0); 1069173#L154 assume !(0 == ~S2_presdbl_st~0); 1069090#L157 assume !(0 == ~S3_zero_st~0); 1069091#L160 assume !(0 == ~D_print_st~0); 1069084#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 1069085#L509 assume !(1 == ~main_in1_req_up~0); 1069075#L509-2 assume !(1 == ~main_in2_req_up~0); 1069074#L520-1 assume !(1 == ~main_sum_req_up~0); 1073602#L531-1 assume !(1 == ~main_diff_req_up~0); 1069050#L542-1 assume !(1 == ~main_pres_req_up~0); 1069039#L553-1 assume !(1 == ~main_dbl_req_up~0); 1069038#L564-1 assume !(1 == ~main_zero_req_up~0); 1070024#L575-1 assume !(1 == ~main_clk_req_up~0); 1070025#L586-1 start_simulation_~kernel_st~0#1 := 3; 1071683#L605 assume !(0 == ~main_in1_ev~0); 1071684#L605-2 assume !(0 == ~main_in2_ev~0); 1071679#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 1071680#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 1071675#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 1071676#L625-1 assume !(0 == ~main_dbl_ev~0); 1071668#L630-1 assume !(0 == ~main_zero_ev~0); 1071669#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 1071660#L640-1 assume !(0 == ~main_clk_pos_edge~0); 1071661#L645-1 assume !(0 == ~main_clk_neg_edge~0); 1071654#L650-1 assume !(1 == ~main_clk_pos_edge~0); 1071655#L655-1 assume !(1 == ~main_clk_pos_edge~0); 1071647#L660-1 assume !(1 == ~main_clk_pos_edge~0); 1071648#L665-1 assume !(1 == ~main_clk_pos_edge~0); 1071639#L670-1 assume !(1 == ~main_clk_pos_edge~0); 1071640#L675-1 assume !(1 == ~main_in1_ev~0); 1071630#L680-1 assume !(1 == ~main_in2_ev~0); 1071631#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 1071622#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 1071623#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 1071614#L700-1 assume !(1 == ~main_dbl_ev~0); 1071615#L705-1 assume !(1 == ~main_zero_ev~0); 1071606#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 1071607#L715-1 assume !(1 == ~main_clk_pos_edge~0); 1071571#L720-1 assume !(1 == ~main_clk_neg_edge~0); 1071572#L725-1 assume !(0 == ~N_generate_st~0); 1071549#L733 assume !(0 == ~S1_addsub_st~0); 1071550#L736 assume !(0 == ~S2_presdbl_st~0); 1071538#L739 assume !(0 == ~S3_zero_st~0); 1071539#L742 assume 0 == ~D_print_st~0; 1071708#L742-1 [2023-11-26 12:06:57,939 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:57,939 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 7 times [2023-11-26 12:06:57,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:57,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065664042] [2023-11-26 12:06:57,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:57,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:57,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:57,950 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:06:57,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:06:57,964 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:06:57,965 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:06:57,965 INFO L85 PathProgramCache]: Analyzing trace with hash -1435455170, now seen corresponding path program 1 times [2023-11-26 12:06:57,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:06:57,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360958890] [2023-11-26 12:06:57,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:06:57,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:06:57,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:06:57,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:06:57,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:06:57,988 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360958890] [2023-11-26 12:06:57,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1360958890] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:06:57,989 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:06:57,989 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:06:57,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429700906] [2023-11-26 12:06:57,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:06:57,990 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:06:57,990 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:06:57,990 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:06:57,990 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:06:57,991 INFO L87 Difference]: Start difference. First operand 147978 states and 218783 transitions. cyclomatic complexity: 70949 Second operand has 3 states, 2 states have (on average 24.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:06:59,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:06:59,912 INFO L93 Difference]: Finished difference Result 253411 states and 370695 transitions. [2023-11-26 12:06:59,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 253411 states and 370695 transitions. [2023-11-26 12:07:00,823 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 219346 [2023-11-26 12:07:02,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 253411 states to 253411 states and 370695 transitions. [2023-11-26 12:07:02,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 253411 [2023-11-26 12:07:02,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 253411 [2023-11-26 12:07:02,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 253411 states and 370695 transitions. [2023-11-26 12:07:02,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:07:02,494 INFO L218 hiAutomatonCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2023-11-26 12:07:02,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253411 states and 370695 transitions. [2023-11-26 12:07:05,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253411 to 253411. [2023-11-26 12:07:05,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 253411 states, 253411 states have (on average 1.4628212666379912) internal successors, (370695), 253410 states have internal predecessors, (370695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:07:06,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 253411 states to 253411 states and 370695 transitions. [2023-11-26 12:07:06,374 INFO L240 hiAutomatonCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2023-11-26 12:07:06,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:07:06,375 INFO L428 stractBuchiCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2023-11-26 12:07:06,375 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 12:07:06,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 253411 states and 370695 transitions. [2023-11-26 12:07:06,998 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 219346 [2023-11-26 12:07:06,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:07:06,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:07:06,999 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:07:06,999 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:07:07,000 INFO L748 eck$LassoCheckResult]: Stem: 1457826#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1457827#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1457639#L256 assume !(1 == ~main_in1_req_up~0); 1457591#L256-2 assume !(1 == ~main_in2_req_up~0); 1457593#L267-1 assume !(1 == ~main_sum_req_up~0); 1458130#L278-1 assume !(1 == ~main_diff_req_up~0); 1457573#L289-1 assume !(1 == ~main_pres_req_up~0); 1457574#L300-1 assume !(1 == ~main_dbl_req_up~0); 1474789#L311-1 assume !(1 == ~main_zero_req_up~0); 1474631#L322-1 assume !(1 == ~main_clk_req_up~0); 1474627#L333-1 assume 1 == ~N_generate_i~0;~N_generate_st~0 := 0; 1474624#L351-1 assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0; 1474622#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1474621#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 1474617#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1474615#L371-1 assume !(0 == ~main_in1_ev~0); 1474613#L376-1 assume !(0 == ~main_in2_ev~0); 1474611#L381-1 assume !(0 == ~main_sum_ev~0); 1474609#L386-1 assume !(0 == ~main_diff_ev~0); 1474607#L391-1 assume !(0 == ~main_pres_ev~0); 1474605#L396-1 assume !(0 == ~main_dbl_ev~0); 1474603#L401-1 assume !(0 == ~main_zero_ev~0); 1474601#L406-1 assume !(0 == ~main_clk_ev~0); 1474599#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1474597#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1474595#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1474593#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1474591#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1474589#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1474587#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1474585#L446-1 assume !(1 == ~main_in1_ev~0); 1474583#L451-1 assume !(1 == ~main_in2_ev~0); 1474581#L456-1 assume !(1 == ~main_sum_ev~0); 1474579#L461-1 assume !(1 == ~main_diff_ev~0); 1474577#L466-1 assume !(1 == ~main_pres_ev~0); 1474575#L471-1 assume !(1 == ~main_dbl_ev~0); 1474573#L476-1 assume !(1 == ~main_zero_ev~0); 1474571#L481-1 assume !(1 == ~main_clk_ev~0); 1474569#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1474567#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1474565#L742-1 assume !false; 1474563#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1474560#L229 [2023-11-26 12:07:07,000 INFO L750 eck$LassoCheckResult]: Loop: 1474560#L229 assume !false; 1474556#L147 assume 0 == ~N_generate_st~0; 1474552#L160-1 assume 0 == ~N_generate_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1; 1474548#L173 assume !(0 != eval_~tmp~0#1); 1474549#L169 assume 0 == ~S1_addsub_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1474636#L188 assume !(0 != eval_~tmp___0~0#1); 1474633#L184 assume !(0 == ~S2_presdbl_st~0); 1474629#L199 assume 0 == ~S3_zero_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1474626#L218 assume !(0 != eval_~tmp___2~0#1); 1474623#L214 assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1474561#L233 assume !(0 != eval_~tmp___3~0#1); 1474560#L229 [2023-11-26 12:07:07,000 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:07:07,000 INFO L85 PathProgramCache]: Analyzing trace with hash 1897430713, now seen corresponding path program 1 times [2023-11-26 12:07:07,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:07:07,000 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895854549] [2023-11-26 12:07:07,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:07:07,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:07:07,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:07:07,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:07:07,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:07:07,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1895854549] [2023-11-26 12:07:07,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1895854549] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:07:07,045 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:07:07,045 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:07:07,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1631894484] [2023-11-26 12:07:07,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:07:07,046 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:07:07,046 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:07:07,046 INFO L85 PathProgramCache]: Analyzing trace with hash 263530038, now seen corresponding path program 1 times [2023-11-26 12:07:07,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:07:07,047 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797687169] [2023-11-26 12:07:07,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:07:07,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:07:07,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:07:07,050 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:07:07,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:07:07,054 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:07:07,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:07:07,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:07:07,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:07:07,121 INFO L87 Difference]: Start difference. First operand 253411 states and 370695 transitions. cyclomatic complexity: 117508 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:07:08,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:07:08,416 INFO L93 Difference]: Finished difference Result 152871 states and 223090 transitions. [2023-11-26 12:07:08,417 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152871 states and 223090 transitions. [2023-11-26 12:07:08,995 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 131250 [2023-11-26 12:07:09,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152871 states to 152871 states and 223090 transitions. [2023-11-26 12:07:09,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 152871 [2023-11-26 12:07:09,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 152871 [2023-11-26 12:07:09,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 152871 states and 223090 transitions. [2023-11-26 12:07:09,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:07:09,431 INFO L218 hiAutomatonCegarLoop]: Abstraction has 152871 states and 223090 transitions. [2023-11-26 12:07:09,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152871 states and 223090 transitions.