./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 10:45:13,323 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 10:45:13,442 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 10:45:13,452 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 10:45:13,453 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 10:45:13,493 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 10:45:13,495 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 10:45:13,495 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 10:45:13,496 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 10:45:13,501 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 10:45:13,503 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 10:45:13,503 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 10:45:13,504 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 10:45:13,506 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 10:45:13,506 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 10:45:13,507 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 10:45:13,507 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 10:45:13,508 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 10:45:13,508 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 10:45:13,509 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 10:45:13,509 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 10:45:13,510 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 10:45:13,510 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 10:45:13,511 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 10:45:13,511 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 10:45:13,512 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 10:45:13,512 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 10:45:13,512 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 10:45:13,513 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 10:45:13,513 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 10:45:13,515 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 10:45:13,515 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 10:45:13,516 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 10:45:13,516 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 10:45:13,516 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 10:45:13,517 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 10:45:13,517 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 10:45:13,517 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 10:45:13,518 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 [2023-11-26 10:45:13,810 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 10:45:13,836 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 10:45:13,839 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 10:45:13,841 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 10:45:13,842 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 10:45:13,843 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2023-11-26 10:45:17,124 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 10:45:17,410 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 10:45:17,413 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2023-11-26 10:45:17,435 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/data/c27cce118/06e119a697a3402192511afdebc1c1ae/FLAGc329906b2 [2023-11-26 10:45:17,455 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/data/c27cce118/06e119a697a3402192511afdebc1c1ae [2023-11-26 10:45:17,460 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 10:45:17,463 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 10:45:17,467 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 10:45:17,467 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 10:45:17,473 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 10:45:17,474 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:45:17" (1/1) ... [2023-11-26 10:45:17,475 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@463ee98 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:17, skipping insertion in model container [2023-11-26 10:45:17,475 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:45:17" (1/1) ... [2023-11-26 10:45:17,551 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 10:45:17,859 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:45:17,879 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 10:45:18,006 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:45:18,046 INFO L206 MainTranslator]: Completed translation [2023-11-26 10:45:18,047 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18 WrapperNode [2023-11-26 10:45:18,047 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 10:45:18,049 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 10:45:18,049 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 10:45:18,049 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 10:45:18,057 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,081 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,187 INFO L138 Inliner]: procedures = 46, calls = 60, calls flagged for inlining = 55, calls inlined = 185, statements flattened = 2792 [2023-11-26 10:45:18,189 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 10:45:18,190 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 10:45:18,190 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 10:45:18,190 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 10:45:18,214 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,215 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,225 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,287 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 10:45:18,287 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,288 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,347 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,398 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,409 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,425 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,446 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 10:45:18,448 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 10:45:18,448 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 10:45:18,449 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 10:45:18,450 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (1/1) ... [2023-11-26 10:45:18,456 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:45:18,468 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:45:18,497 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:45:18,520 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f79001c-b35c-4a7a-b03c-60f536422260/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 10:45:18,543 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 10:45:18,543 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 10:45:18,544 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 10:45:18,544 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 10:45:18,703 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 10:45:18,706 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 10:45:20,727 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 10:45:20,768 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 10:45:20,768 INFO L309 CfgBuilder]: Removed 12 assume(true) statements. [2023-11-26 10:45:20,771 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:45:20 BoogieIcfgContainer [2023-11-26 10:45:20,771 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 10:45:20,772 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 10:45:20,772 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 10:45:20,776 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 10:45:20,777 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:45:20,778 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 10:45:17" (1/3) ... [2023-11-26 10:45:20,779 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@a3d7b09 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:45:20, skipping insertion in model container [2023-11-26 10:45:20,779 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:45:20,781 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:45:18" (2/3) ... [2023-11-26 10:45:20,783 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@a3d7b09 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:45:20, skipping insertion in model container [2023-11-26 10:45:20,783 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:45:20,783 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:45:20" (3/3) ... [2023-11-26 10:45:20,785 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-2.c [2023-11-26 10:45:20,888 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 10:45:20,888 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 10:45:20,888 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 10:45:20,888 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 10:45:20,889 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 10:45:20,889 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 10:45:20,889 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 10:45:20,889 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 10:45:20,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1195 states, 1194 states have (on average 1.5058626465661642) internal successors, (1798), 1194 states have internal predecessors, (1798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:20,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1064 [2023-11-26 10:45:20,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:20,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:21,002 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:21,002 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:21,003 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 10:45:21,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1195 states, 1194 states have (on average 1.5058626465661642) internal successors, (1798), 1194 states have internal predecessors, (1798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:21,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1064 [2023-11-26 10:45:21,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:21,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:21,030 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:21,030 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:21,041 INFO L748 eck$LassoCheckResult]: Stem: 181#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1095#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 882#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1093#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 521#L670true assume !(1 == ~m_i~0);~m_st~0 := 2; 305#L670-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 841#L675-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 926#L680-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1032#L685-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 906#L690-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1182#L695-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 397#L700-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L705-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 538#L710-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 255#L715-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 779#L951true assume !(0 == ~M_E~0); 112#L951-2true assume !(0 == ~T1_E~0); 194#L956-1true assume !(0 == ~T2_E~0); 1151#L961-1true assume !(0 == ~T3_E~0); 537#L966-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 657#L971-1true assume !(0 == ~T5_E~0); 1084#L976-1true assume !(0 == ~T6_E~0); 632#L981-1true assume !(0 == ~T7_E~0); 422#L986-1true assume !(0 == ~T8_E~0); 224#L991-1true assume !(0 == ~T9_E~0); 1125#L996-1true assume !(0 == ~E_M~0); 1004#L1001-1true assume !(0 == ~E_1~0); 585#L1006-1true assume 0 == ~E_2~0;~E_2~0 := 1; 927#L1011-1true assume !(0 == ~E_3~0); 962#L1016-1true assume !(0 == ~E_4~0); 1097#L1021-1true assume !(0 == ~E_5~0); 17#L1026-1true assume !(0 == ~E_6~0); 1161#L1031-1true assume !(0 == ~E_7~0); 545#L1036-1true assume !(0 == ~E_8~0); 542#L1041-1true assume !(0 == ~E_9~0); 853#L1046-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1086#L472true assume 1 == ~m_pc~0; 1041#L473true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 568#L483true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 754#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 578#L1179true assume !(0 != activate_threads_~tmp~1#1); 21#L1179-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 898#L491true assume 1 == ~t1_pc~0; 584#L492true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 644#L502true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9#L1187true assume !(0 != activate_threads_~tmp___0~0#1); 18#L1187-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 835#L510true assume !(1 == ~t2_pc~0); 4#L510-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1001#L521true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 298#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1160#L1195true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 137#L1195-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 428#L529true assume 1 == ~t3_pc~0; 361#L530true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 769#L540true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1075#L1203true assume !(0 != activate_threads_~tmp___2~0#1); 100#L1203-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1126#L548true assume !(1 == ~t4_pc~0); 315#L548-2true is_transmit4_triggered_~__retres1~4#1 := 0; 201#L559true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67#L1211true assume !(0 != activate_threads_~tmp___3~0#1); 642#L1211-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45#L567true assume 1 == ~t5_pc~0; 894#L568true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1100#L578true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 756#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1030#L1219true assume !(0 != activate_threads_~tmp___4~0#1); 831#L1219-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 105#L586true assume !(1 == ~t6_pc~0); 139#L586-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1027#L597true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 289#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1186#L1227true assume !(0 != activate_threads_~tmp___5~0#1); 824#L1227-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1123#L605true assume 1 == ~t7_pc~0; 761#L606true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 570#L616true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1116#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1107#L1235true assume !(0 != activate_threads_~tmp___6~0#1); 1096#L1235-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 514#L624true assume !(1 == ~t8_pc~0); 1060#L624-2true is_transmit8_triggered_~__retres1~8#1 := 0; 619#L635true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 684#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 790#L1243true assume !(0 != activate_threads_~tmp___7~0#1); 1169#L1243-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29#L643true assume 1 == ~t9_pc~0; 861#L644true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 716#L654true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 336#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 227#L1251true assume !(0 != activate_threads_~tmp___8~0#1); 1122#L1251-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127#L1059true assume !(1 == ~M_E~0); 1189#L1059-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 212#L1064-1true assume !(1 == ~T2_E~0); 725#L1069-1true assume !(1 == ~T3_E~0); 1083#L1074-1true assume !(1 == ~T4_E~0); 786#L1079-1true assume !(1 == ~T5_E~0); 760#L1084-1true assume !(1 == ~T6_E~0); 935#L1089-1true assume !(1 == ~T7_E~0); 815#L1094-1true assume !(1 == ~T8_E~0); 450#L1099-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 951#L1104-1true assume !(1 == ~E_M~0); 623#L1109-1true assume !(1 == ~E_1~0); 299#L1114-1true assume !(1 == ~E_2~0); 1130#L1119-1true assume !(1 == ~E_3~0); 344#L1124-1true assume !(1 == ~E_4~0); 27#L1129-1true assume !(1 == ~E_5~0); 524#L1134-1true assume !(1 == ~E_6~0); 192#L1139-1true assume 1 == ~E_7~0;~E_7~0 := 2; 311#L1144-1true assume !(1 == ~E_8~0); 1173#L1149-1true assume !(1 == ~E_9~0); 108#L1154-1true assume { :end_inline_reset_delta_events } true; 174#L1440-2true [2023-11-26 10:45:21,044 INFO L750 eck$LassoCheckResult]: Loop: 174#L1440-2true assume !false; 987#L1441true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 876#L926-1true assume false; 690#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 457#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 246#L951-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1162#L951-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 673#L956-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 516#L961-3true assume !(0 == ~T3_E~0); 332#L966-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 946#L971-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 562#L976-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 39#L981-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 237#L986-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 28#L991-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 651#L996-3true assume 0 == ~E_M~0;~E_M~0 := 1; 783#L1001-3true assume !(0 == ~E_1~0); 310#L1006-3true assume 0 == ~E_2~0;~E_2~0 := 1; 681#L1011-3true assume 0 == ~E_3~0;~E_3~0 := 1; 923#L1016-3true assume 0 == ~E_4~0;~E_4~0 := 1; 734#L1021-3true assume 0 == ~E_5~0;~E_5~0 := 1; 462#L1026-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1078#L1031-3true assume 0 == ~E_7~0;~E_7~0 := 1; 648#L1036-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1137#L1041-3true assume !(0 == ~E_9~0); 720#L1046-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 671#L472-33true assume !(1 == ~m_pc~0); 79#L472-35true is_master_triggered_~__retres1~0#1 := 0; 932#L483-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 705#is_master_triggered_returnLabel#12true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 678#L1179-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 339#L1179-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1063#L491-33true assume 1 == ~t1_pc~0; 579#L492-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 982#L502-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1079#is_transmit1_triggered_returnLabel#12true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1020#L1187-33true assume !(0 != activate_threads_~tmp___0~0#1); 1082#L1187-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 627#L510-33true assume 1 == ~t2_pc~0; 682#L511-11true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1006#L521-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 660#is_transmit2_triggered_returnLabel#12true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 740#L1195-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2#L1195-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152#L529-33true assume !(1 == ~t3_pc~0); 208#L529-35true is_transmit3_triggered_~__retres1~3#1 := 0; 143#L540-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86#is_transmit3_triggered_returnLabel#12true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1028#L1203-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59#L1203-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183#L548-33true assume !(1 == ~t4_pc~0); 1181#L548-35true is_transmit4_triggered_~__retres1~4#1 := 0; 592#L559-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 940#is_transmit4_triggered_returnLabel#12true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 281#L1211-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148#L1211-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 937#L567-33true assume 1 == ~t5_pc~0; 435#L568-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 367#L578-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1026#is_transmit5_triggered_returnLabel#12true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1048#L1219-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1138#L1219-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 536#L586-33true assume 1 == ~t6_pc~0; 503#L587-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 572#L597-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 379#is_transmit6_triggered_returnLabel#12true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1157#L1227-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 158#L1227-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 261#L605-33true assume !(1 == ~t7_pc~0); 555#L605-35true is_transmit7_triggered_~__retres1~7#1 := 0; 123#L616-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 775#is_transmit7_triggered_returnLabel#12true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1127#L1235-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64#L1235-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 142#L624-33true assume !(1 == ~t8_pc~0); 146#L624-35true is_transmit8_triggered_~__retres1~8#1 := 0; 1057#L635-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 515#is_transmit8_triggered_returnLabel#12true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 270#L1243-33true assume !(0 != activate_threads_~tmp___7~0#1); 1174#L1243-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124#L643-33true assume !(1 == ~t9_pc~0); 165#L643-35true is_transmit9_triggered_~__retres1~9#1 := 0; 484#L654-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 664#is_transmit9_triggered_returnLabel#12true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 448#L1251-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 809#L1251-35true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60#L1059-3true assume !(1 == ~M_E~0); 352#L1059-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1184#L1064-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 394#L1069-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 633#L1074-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 886#L1079-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 546#L1084-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 483#L1089-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 595#L1094-3true assume !(1 == ~T8_E~0); 415#L1099-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 653#L1104-3true assume 1 == ~E_M~0;~E_M~0 := 2; 958#L1109-3true assume 1 == ~E_1~0;~E_1~0 := 2; 641#L1114-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1049#L1119-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1183#L1124-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1080#L1129-3true assume 1 == ~E_5~0;~E_5~0 := 2; 216#L1134-3true assume !(1 == ~E_6~0); 500#L1139-3true assume 1 == ~E_7~0;~E_7~0 := 2; 328#L1144-3true assume 1 == ~E_8~0;~E_8~0 := 2; 451#L1149-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1177#L1154-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1114#L728-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 751#L780-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 268#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12#L1459true assume !(0 == start_simulation_~tmp~3#1); 736#L1459-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 919#L728-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 552#L780-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 243#L1414true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 355#L1421true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 473#stop_simulation_returnLabel#1true start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 732#L1472true assume !(0 != start_simulation_~tmp___0~1#1); 174#L1440-2true [2023-11-26 10:45:21,051 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:21,052 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2023-11-26 10:45:21,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:21,062 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187285759] [2023-11-26 10:45:21,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:21,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:21,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:21,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:21,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:21,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187285759] [2023-11-26 10:45:21,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1187285759] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:21,408 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:21,409 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:21,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101283475] [2023-11-26 10:45:21,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:21,419 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:21,421 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:21,421 INFO L85 PathProgramCache]: Analyzing trace with hash 1748189105, now seen corresponding path program 1 times [2023-11-26 10:45:21,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:21,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836282496] [2023-11-26 10:45:21,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:21,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:21,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:21,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:21,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:21,546 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1836282496] [2023-11-26 10:45:21,547 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1836282496] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:21,547 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:21,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:45:21,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816865925] [2023-11-26 10:45:21,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:21,549 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:21,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:21,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:21,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:21,588 INFO L87 Difference]: Start difference. First operand has 1195 states, 1194 states have (on average 1.5058626465661642) internal successors, (1798), 1194 states have internal predecessors, (1798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:21,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:21,711 INFO L93 Difference]: Finished difference Result 1191 states and 1767 transitions. [2023-11-26 10:45:21,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1191 states and 1767 transitions. [2023-11-26 10:45:21,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:21,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1191 states to 1185 states and 1761 transitions. [2023-11-26 10:45:21,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-26 10:45:21,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-26 10:45:21,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1761 transitions. [2023-11-26 10:45:21,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:21,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1761 transitions. [2023-11-26 10:45:21,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1761 transitions. [2023-11-26 10:45:21,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-26 10:45:21,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4860759493670885) internal successors, (1761), 1184 states have internal predecessors, (1761), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:21,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1761 transitions. [2023-11-26 10:45:21,875 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1761 transitions. [2023-11-26 10:45:21,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:21,884 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1761 transitions. [2023-11-26 10:45:21,885 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 10:45:21,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1761 transitions. [2023-11-26 10:45:21,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:21,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:21,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:21,905 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:21,906 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:21,906 INFO L748 eck$LassoCheckResult]: Stem: 2773#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3517#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3518#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3241#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2967#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2968#L675-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3496#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3530#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3523#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3524#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3095#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3082#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3083#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2892#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2893#L951 assume !(0 == ~M_E~0); 2637#L951-2 assume !(0 == ~T1_E~0); 2638#L956-1 assume !(0 == ~T2_E~0); 2792#L961-1 assume !(0 == ~T3_E~0); 3260#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3261#L971-1 assume !(0 == ~T5_E~0); 3384#L976-1 assume !(0 == ~T6_E~0); 3359#L981-1 assume !(0 == ~T7_E~0); 3131#L986-1 assume !(0 == ~T8_E~0); 2842#L991-1 assume !(0 == ~T9_E~0); 2843#L996-1 assume !(0 == ~E_M~0); 3553#L1001-1 assume !(0 == ~E_1~0); 3311#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3312#L1011-1 assume !(0 == ~E_3~0); 3531#L1016-1 assume !(0 == ~E_4~0); 3540#L1021-1 assume !(0 == ~E_5~0); 2431#L1026-1 assume !(0 == ~E_6~0); 2432#L1031-1 assume !(0 == ~E_7~0); 3267#L1036-1 assume !(0 == ~E_8~0); 3263#L1041-1 assume !(0 == ~E_9~0); 3264#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3503#L472 assume 1 == ~m_pc~0; 3569#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3292#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3293#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3301#L1179 assume !(0 != activate_threads_~tmp~1#1); 2439#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2440#L491 assume 1 == ~t1_pc~0; 3310#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2937#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2464#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2411#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2412#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2435#L510 assume !(1 == ~t2_pc~0); 2400#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2401#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2959#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2960#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2692#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2693#L529 assume 1 == ~t3_pc~0; 3044#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3045#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2409#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2410#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2612#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2613#L548 assume !(1 == ~t4_pc~0); 2506#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2505#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2577#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2548#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2549#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2493#L567 assume 1 == ~t5_pc~0; 2494#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2550#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3451#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3452#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 3491#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2623#L586 assume !(1 == ~t6_pc~0); 2624#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2696#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2942#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2943#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 3485#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3486#L605 assume 1 == ~t7_pc~0; 3459#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3118#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3294#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3578#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 3577#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3235#L624 assume !(1 == ~t8_pc~0); 2687#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2686#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3344#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3403#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 3469#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2456#L643 assume 1 == ~t9_pc~0; 2457#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3423#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3009#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2849#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2850#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2669#L1059 assume !(1 == ~M_E~0); 2670#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2820#L1064-1 assume !(1 == ~T2_E~0); 2821#L1069-1 assume !(1 == ~T3_E~0); 3430#L1074-1 assume !(1 == ~T4_E~0); 3467#L1079-1 assume !(1 == ~T5_E~0); 3457#L1084-1 assume !(1 == ~T6_E~0); 3458#L1089-1 assume !(1 == ~T7_E~0); 3481#L1094-1 assume !(1 == ~T8_E~0); 3169#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3170#L1104-1 assume !(1 == ~E_M~0); 3346#L1109-1 assume !(1 == ~E_1~0); 2961#L1114-1 assume !(1 == ~E_2~0); 2962#L1119-1 assume !(1 == ~E_3~0); 3019#L1124-1 assume !(1 == ~E_4~0); 2452#L1129-1 assume !(1 == ~E_5~0); 2453#L1134-1 assume !(1 == ~E_6~0); 2788#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2789#L1144-1 assume !(1 == ~E_8~0); 2977#L1149-1 assume !(1 == ~E_9~0); 2629#L1154-1 assume { :end_inline_reset_delta_events } true; 2630#L1440-2 [2023-11-26 10:45:21,907 INFO L750 eck$LassoCheckResult]: Loop: 2630#L1440-2 assume !false; 2758#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3333#L926-1 assume !false; 3021#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3022#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2717#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2718#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2725#L795 assume !(0 != eval_~tmp~0#1); 2726#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2876#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2877#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3394#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3237#L961-3 assume !(0 == ~T3_E~0); 3004#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3005#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3286#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2479#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2480#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2454#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2455#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3381#L1001-3 assume !(0 == ~E_1~0); 2973#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2974#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3402#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3437#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3182#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3183#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3375#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3376#L1041-3 assume !(0 == ~E_9~0); 3428#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3392#L472-33 assume 1 == ~m_pc~0; 3393#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2575#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3419#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3399#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3012#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3013#L491-33 assume !(1 == ~t1_pc~0); 2513#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2514#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3546#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3561#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 3562#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3353#L510-33 assume !(1 == ~t2_pc~0); 3347#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3348#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3386#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3387#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2395#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2396#L529-33 assume 1 == ~t3_pc~0; 2420#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2422#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2587#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2588#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2527#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2528#L548-33 assume 1 == ~t4_pc~0; 2776#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2894#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3318#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2931#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2712#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2713#L567-33 assume !(1 == ~t5_pc~0); 2815#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2816#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3055#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3566#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3571#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3259#L586-33 assume !(1 == ~t6_pc~0); 2832#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2833#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3071#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3072#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2729#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2730#L605-33 assume 1 == ~t7_pc~0; 2898#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2654#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2655#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3462#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2539#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2540#L624-33 assume !(1 == ~t8_pc~0); 2701#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2709#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3236#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2913#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 2914#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2656#L643-33 assume 1 == ~t9_pc~0; 2657#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2743#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3209#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3165#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3166#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2529#L1059-3 assume !(1 == ~M_E~0); 2530#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3033#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3091#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3092#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3360#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3268#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3207#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3208#L1094-3 assume !(1 == ~T8_E~0); 3124#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3125#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3382#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3366#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3367#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3572#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3576#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2827#L1134-3 assume !(1 == ~E_6~0); 2828#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2990#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2991#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3171#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3579#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2532#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2909#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2417#L1459 assume !(0 == start_simulation_~tmp~3#1); 2418#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3438#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2715#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2459#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2460#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2873#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3034#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3194#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2630#L1440-2 [2023-11-26 10:45:21,908 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:21,908 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2023-11-26 10:45:21,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:21,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814022840] [2023-11-26 10:45:21,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:21,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:21,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:22,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:22,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:22,063 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814022840] [2023-11-26 10:45:22,064 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814022840] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:22,064 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:22,064 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:22,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1128834107] [2023-11-26 10:45:22,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:22,065 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:22,065 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:22,066 INFO L85 PathProgramCache]: Analyzing trace with hash 1812965149, now seen corresponding path program 1 times [2023-11-26 10:45:22,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:22,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740825736] [2023-11-26 10:45:22,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:22,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:22,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:22,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:22,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:22,229 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740825736] [2023-11-26 10:45:22,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740825736] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:22,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:22,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:22,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734215756] [2023-11-26 10:45:22,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:22,230 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:22,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:22,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:22,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:22,231 INFO L87 Difference]: Start difference. First operand 1185 states and 1761 transitions. cyclomatic complexity: 577 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:22,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:22,273 INFO L93 Difference]: Finished difference Result 1185 states and 1760 transitions. [2023-11-26 10:45:22,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1760 transitions. [2023-11-26 10:45:22,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:22,296 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1760 transitions. [2023-11-26 10:45:22,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-26 10:45:22,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-26 10:45:22,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1760 transitions. [2023-11-26 10:45:22,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:22,302 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1760 transitions. [2023-11-26 10:45:22,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1760 transitions. [2023-11-26 10:45:22,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-26 10:45:22,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4852320675105486) internal successors, (1760), 1184 states have internal predecessors, (1760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:22,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1760 transitions. [2023-11-26 10:45:22,344 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1760 transitions. [2023-11-26 10:45:22,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:22,346 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1760 transitions. [2023-11-26 10:45:22,346 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 10:45:22,347 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1760 transitions. [2023-11-26 10:45:22,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:22,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:22,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:22,368 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:22,369 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:22,372 INFO L748 eck$LassoCheckResult]: Stem: 5153#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5154#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5894#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5895#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5618#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 5344#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5345#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5873#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5907#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5900#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5901#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5472#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5459#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5460#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5270#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5271#L951 assume !(0 == ~M_E~0); 5014#L951-2 assume !(0 == ~T1_E~0); 5015#L956-1 assume !(0 == ~T2_E~0); 5169#L961-1 assume !(0 == ~T3_E~0); 5637#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5638#L971-1 assume !(0 == ~T5_E~0); 5761#L976-1 assume !(0 == ~T6_E~0); 5736#L981-1 assume !(0 == ~T7_E~0); 5511#L986-1 assume !(0 == ~T8_E~0); 5219#L991-1 assume !(0 == ~T9_E~0); 5220#L996-1 assume !(0 == ~E_M~0); 5930#L1001-1 assume !(0 == ~E_1~0); 5688#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5689#L1011-1 assume !(0 == ~E_3~0); 5908#L1016-1 assume !(0 == ~E_4~0); 5917#L1021-1 assume !(0 == ~E_5~0); 4808#L1026-1 assume !(0 == ~E_6~0); 4809#L1031-1 assume !(0 == ~E_7~0); 5644#L1036-1 assume !(0 == ~E_8~0); 5642#L1041-1 assume !(0 == ~E_9~0); 5643#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5880#L472 assume 1 == ~m_pc~0; 5946#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5669#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5670#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5678#L1179 assume !(0 != activate_threads_~tmp~1#1); 4816#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4817#L491 assume 1 == ~t1_pc~0; 5687#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5316#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4841#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4788#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 4789#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4812#L510 assume !(1 == ~t2_pc~0); 4777#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4778#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5337#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5069#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5070#L529 assume 1 == ~t3_pc~0; 5421#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5422#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4786#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4787#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 4989#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4990#L548 assume !(1 == ~t4_pc~0); 4883#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4882#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4954#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4925#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 4926#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4875#L567 assume 1 == ~t5_pc~0; 4876#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4927#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5829#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 5868#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5000#L586 assume !(1 == ~t6_pc~0); 5001#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5075#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5322#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5323#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 5862#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5863#L605 assume 1 == ~t7_pc~0; 5836#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5496#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5672#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5955#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 5954#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5612#L624 assume !(1 == ~t8_pc~0); 5064#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5063#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5721#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5780#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 5846#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4833#L643 assume 1 == ~t9_pc~0; 4834#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5800#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5386#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5226#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 5227#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5046#L1059 assume !(1 == ~M_E~0); 5047#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5197#L1064-1 assume !(1 == ~T2_E~0); 5198#L1069-1 assume !(1 == ~T3_E~0); 5807#L1074-1 assume !(1 == ~T4_E~0); 5845#L1079-1 assume !(1 == ~T5_E~0); 5834#L1084-1 assume !(1 == ~T6_E~0); 5835#L1089-1 assume !(1 == ~T7_E~0); 5858#L1094-1 assume !(1 == ~T8_E~0); 5546#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5547#L1104-1 assume !(1 == ~E_M~0); 5725#L1109-1 assume !(1 == ~E_1~0); 5338#L1114-1 assume !(1 == ~E_2~0); 5339#L1119-1 assume !(1 == ~E_3~0); 5396#L1124-1 assume !(1 == ~E_4~0); 4829#L1129-1 assume !(1 == ~E_5~0); 4830#L1134-1 assume !(1 == ~E_6~0); 5165#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5166#L1144-1 assume !(1 == ~E_8~0); 5354#L1149-1 assume !(1 == ~E_9~0); 5006#L1154-1 assume { :end_inline_reset_delta_events } true; 5007#L1440-2 [2023-11-26 10:45:22,373 INFO L750 eck$LassoCheckResult]: Loop: 5007#L1440-2 assume !false; 5137#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5710#L926-1 assume !false; 5398#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5399#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5094#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5095#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5102#L795 assume !(0 != eval_~tmp~0#1); 5103#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5255#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5256#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5771#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5614#L961-3 assume !(0 == ~T3_E~0); 5382#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5383#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5663#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4856#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4857#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4831#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4832#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5758#L1001-3 assume !(0 == ~E_1~0); 5350#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5351#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5779#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5814#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5560#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5561#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5752#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5753#L1041-3 assume !(0 == ~E_9~0); 5805#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5769#L472-33 assume !(1 == ~m_pc~0); 4951#L472-35 is_master_triggered_~__retres1~0#1 := 0; 4952#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5796#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5776#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5389#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5390#L491-33 assume !(1 == ~t1_pc~0); 4887#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 4888#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5923#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5938#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 5939#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5726#L510-33 assume !(1 == ~t2_pc~0); 5723#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5724#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5763#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5764#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4772#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4773#L529-33 assume 1 == ~t3_pc~0; 4797#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4799#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4962#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4963#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4904#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4905#L548-33 assume 1 == ~t4_pc~0; 5149#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5269#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5695#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5308#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5089#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5090#L567-33 assume 1 == ~t5_pc~0; 5527#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5193#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5431#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5943#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5948#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5636#L586-33 assume 1 == ~t6_pc~0; 5602#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5211#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5448#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5449#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5108#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5109#L605-33 assume 1 == ~t7_pc~0; 5278#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5031#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5032#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5839#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4916#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4917#L624-33 assume !(1 == ~t8_pc~0); 5078#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 5086#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5613#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5290#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 5291#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5033#L643-33 assume 1 == ~t9_pc~0; 5034#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5120#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5586#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5542#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5543#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4906#L1059-3 assume !(1 == ~M_E~0); 4907#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5410#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5468#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5469#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5737#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5645#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5584#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5585#L1094-3 assume !(1 == ~T8_E~0); 5501#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5502#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5759#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5743#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5744#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5949#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5953#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5204#L1134-3 assume !(1 == ~E_6~0); 5205#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5370#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5371#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5548#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5956#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4909#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5288#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 4794#L1459 assume !(0 == start_simulation_~tmp~3#1); 4795#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5815#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5092#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4836#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 4837#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5250#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5412#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5571#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 5007#L1440-2 [2023-11-26 10:45:22,374 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:22,374 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2023-11-26 10:45:22,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:22,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842022460] [2023-11-26 10:45:22,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:22,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:22,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:22,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:22,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:22,482 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842022460] [2023-11-26 10:45:22,482 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842022460] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:22,482 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:22,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:22,483 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [576865112] [2023-11-26 10:45:22,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:22,483 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:22,484 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:22,484 INFO L85 PathProgramCache]: Analyzing trace with hash 2112954140, now seen corresponding path program 1 times [2023-11-26 10:45:22,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:22,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146816299] [2023-11-26 10:45:22,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:22,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:22,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:22,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:22,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:22,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146816299] [2023-11-26 10:45:22,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [146816299] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:22,594 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:22,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:22,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275132264] [2023-11-26 10:45:22,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:22,596 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:22,596 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:22,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:22,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:22,597 INFO L87 Difference]: Start difference. First operand 1185 states and 1760 transitions. cyclomatic complexity: 576 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:22,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:22,633 INFO L93 Difference]: Finished difference Result 1185 states and 1759 transitions. [2023-11-26 10:45:22,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1759 transitions. [2023-11-26 10:45:22,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:22,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1759 transitions. [2023-11-26 10:45:22,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-26 10:45:22,657 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-26 10:45:22,657 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1759 transitions. [2023-11-26 10:45:22,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:22,660 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1759 transitions. [2023-11-26 10:45:22,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1759 transitions. [2023-11-26 10:45:22,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-26 10:45:22,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4843881856540084) internal successors, (1759), 1184 states have internal predecessors, (1759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:22,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1759 transitions. [2023-11-26 10:45:22,690 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1759 transitions. [2023-11-26 10:45:22,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:22,692 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1759 transitions. [2023-11-26 10:45:22,693 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 10:45:22,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1759 transitions. [2023-11-26 10:45:22,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:22,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:22,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:22,707 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:22,707 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:22,708 INFO L748 eck$LassoCheckResult]: Stem: 7530#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7531#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7995#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 7723#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7724#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8250#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8284#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8277#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8278#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7849#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7836#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7837#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7647#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7648#L951 assume !(0 == ~M_E~0); 7393#L951-2 assume !(0 == ~T1_E~0); 7394#L956-1 assume !(0 == ~T2_E~0); 7546#L961-1 assume !(0 == ~T3_E~0); 8014#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8015#L971-1 assume !(0 == ~T5_E~0); 8138#L976-1 assume !(0 == ~T6_E~0); 8113#L981-1 assume !(0 == ~T7_E~0); 7888#L986-1 assume !(0 == ~T8_E~0); 7596#L991-1 assume !(0 == ~T9_E~0); 7597#L996-1 assume !(0 == ~E_M~0); 8307#L1001-1 assume !(0 == ~E_1~0); 8065#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 8066#L1011-1 assume !(0 == ~E_3~0); 8286#L1016-1 assume !(0 == ~E_4~0); 8294#L1021-1 assume !(0 == ~E_5~0); 7185#L1026-1 assume !(0 == ~E_6~0); 7186#L1031-1 assume !(0 == ~E_7~0); 8021#L1036-1 assume !(0 == ~E_8~0); 8019#L1041-1 assume !(0 == ~E_9~0); 8020#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8257#L472 assume 1 == ~m_pc~0; 8323#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8046#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8047#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8055#L1179 assume !(0 != activate_threads_~tmp~1#1); 7193#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7194#L491 assume 1 == ~t1_pc~0; 8064#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7693#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7218#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7165#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 7166#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7189#L510 assume !(1 == ~t2_pc~0); 7154#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7155#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7713#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7714#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7446#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7447#L529 assume 1 == ~t3_pc~0; 7798#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7799#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7163#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7164#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 7366#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7367#L548 assume !(1 == ~t4_pc~0); 7261#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7260#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7331#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7302#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 7303#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7252#L567 assume 1 == ~t5_pc~0; 7253#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7304#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8205#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8206#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 8245#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7377#L586 assume !(1 == ~t6_pc~0); 7378#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7452#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7699#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7700#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 8239#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8240#L605 assume 1 == ~t7_pc~0; 8213#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7876#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8049#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8332#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 8331#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7989#L624 assume !(1 == ~t8_pc~0); 7441#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7440#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8098#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8158#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 8223#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7210#L643 assume 1 == ~t9_pc~0; 7211#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8177#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7763#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7603#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 7604#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7423#L1059 assume !(1 == ~M_E~0); 7424#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7574#L1064-1 assume !(1 == ~T2_E~0); 7575#L1069-1 assume !(1 == ~T3_E~0); 8184#L1074-1 assume !(1 == ~T4_E~0); 8222#L1079-1 assume !(1 == ~T5_E~0); 8211#L1084-1 assume !(1 == ~T6_E~0); 8212#L1089-1 assume !(1 == ~T7_E~0); 8235#L1094-1 assume !(1 == ~T8_E~0); 7923#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7924#L1104-1 assume !(1 == ~E_M~0); 8102#L1109-1 assume !(1 == ~E_1~0); 7715#L1114-1 assume !(1 == ~E_2~0); 7716#L1119-1 assume !(1 == ~E_3~0); 7774#L1124-1 assume !(1 == ~E_4~0); 7208#L1129-1 assume !(1 == ~E_5~0); 7209#L1134-1 assume !(1 == ~E_6~0); 7544#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7545#L1144-1 assume !(1 == ~E_8~0); 7731#L1149-1 assume !(1 == ~E_9~0); 7383#L1154-1 assume { :end_inline_reset_delta_events } true; 7384#L1440-2 [2023-11-26 10:45:22,708 INFO L750 eck$LassoCheckResult]: Loop: 7384#L1440-2 assume !false; 7514#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8087#L926-1 assume !false; 7775#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7776#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7471#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7472#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7479#L795 assume !(0 != eval_~tmp~0#1); 7480#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7932#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7632#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7633#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8149#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7992#L961-3 assume !(0 == ~T3_E~0); 7755#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7756#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8040#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7230#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7231#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7206#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7207#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8135#L1001-3 assume !(0 == ~E_1~0); 7727#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7728#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8156#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8191#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7936#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7937#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8129#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8130#L1041-3 assume !(0 == ~E_9~0); 8182#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8146#L472-33 assume !(1 == ~m_pc~0); 7328#L472-35 is_master_triggered_~__retres1~0#1 := 0; 7329#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8173#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8153#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7766#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7767#L491-33 assume !(1 == ~t1_pc~0); 7267#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7268#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8300#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8315#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 8316#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8106#L510-33 assume !(1 == ~t2_pc~0); 8100#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 8101#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8140#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8141#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7149#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7150#L529-33 assume 1 == ~t3_pc~0; 7174#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7176#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7341#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7342#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7281#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7282#L548-33 assume 1 == ~t4_pc~0; 7526#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7646#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8072#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7685#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7466#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7467#L567-33 assume !(1 == ~t5_pc~0); 7569#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7570#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7808#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8320#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8325#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8013#L586-33 assume !(1 == ~t6_pc~0); 7587#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 7588#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7826#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7827#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7485#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7486#L605-33 assume 1 == ~t7_pc~0; 7655#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7415#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7416#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8216#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7293#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7294#L624-33 assume 1 == ~t8_pc~0; 7456#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7463#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7990#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7667#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 7668#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7417#L643-33 assume 1 == ~t9_pc~0; 7418#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7497#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7963#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7919#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7920#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7283#L1059-3 assume !(1 == ~M_E~0); 7284#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7787#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7846#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7847#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8114#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8022#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7961#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7962#L1094-3 assume !(1 == ~T8_E~0); 7878#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7879#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8136#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8122#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8123#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8326#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8330#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7581#L1134-3 assume !(1 == ~E_6~0); 7582#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7749#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7750#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7925#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8333#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7288#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7665#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7171#L1459 assume !(0 == start_simulation_~tmp~3#1); 7172#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8192#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7469#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7213#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 7214#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 7627#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7789#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 7948#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 7384#L1440-2 [2023-11-26 10:45:22,709 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:22,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2023-11-26 10:45:22,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:22,711 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880471002] [2023-11-26 10:45:22,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:22,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:22,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:22,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:22,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:22,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [880471002] [2023-11-26 10:45:22,791 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [880471002] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:22,791 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:22,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:22,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [909290025] [2023-11-26 10:45:22,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:22,832 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:22,832 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:22,833 INFO L85 PathProgramCache]: Analyzing trace with hash -491339491, now seen corresponding path program 1 times [2023-11-26 10:45:22,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:22,833 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274996283] [2023-11-26 10:45:22,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:22,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:22,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:22,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:22,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:22,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274996283] [2023-11-26 10:45:22,946 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274996283] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:22,946 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:22,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:22,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459177966] [2023-11-26 10:45:22,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:22,947 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:22,947 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:22,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:22,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:22,948 INFO L87 Difference]: Start difference. First operand 1185 states and 1759 transitions. cyclomatic complexity: 575 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:22,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:22,984 INFO L93 Difference]: Finished difference Result 1185 states and 1758 transitions. [2023-11-26 10:45:22,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1758 transitions. [2023-11-26 10:45:22,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:23,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1758 transitions. [2023-11-26 10:45:23,006 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-26 10:45:23,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-26 10:45:23,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1758 transitions. [2023-11-26 10:45:23,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:23,010 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1758 transitions. [2023-11-26 10:45:23,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1758 transitions. [2023-11-26 10:45:23,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-26 10:45:23,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4835443037974683) internal successors, (1758), 1184 states have internal predecessors, (1758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:23,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1758 transitions. [2023-11-26 10:45:23,044 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1758 transitions. [2023-11-26 10:45:23,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:23,047 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1758 transitions. [2023-11-26 10:45:23,047 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 10:45:23,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1758 transitions. [2023-11-26 10:45:23,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:23,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:23,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:23,061 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:23,062 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:23,062 INFO L748 eck$LassoCheckResult]: Stem: 9902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 9903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10646#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10647#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10372#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 10098#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10099#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10627#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10661#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10654#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10655#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10226#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10213#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10214#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10023#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10024#L951 assume !(0 == ~M_E~0); 9768#L951-2 assume !(0 == ~T1_E~0); 9769#L956-1 assume !(0 == ~T2_E~0); 9923#L961-1 assume !(0 == ~T3_E~0); 10391#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10392#L971-1 assume !(0 == ~T5_E~0); 10515#L976-1 assume !(0 == ~T6_E~0); 10490#L981-1 assume !(0 == ~T7_E~0); 10262#L986-1 assume !(0 == ~T8_E~0); 9973#L991-1 assume !(0 == ~T9_E~0); 9974#L996-1 assume !(0 == ~E_M~0); 10683#L1001-1 assume !(0 == ~E_1~0); 10442#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10443#L1011-1 assume !(0 == ~E_3~0); 10662#L1016-1 assume !(0 == ~E_4~0); 10671#L1021-1 assume !(0 == ~E_5~0); 9562#L1026-1 assume !(0 == ~E_6~0); 9563#L1031-1 assume !(0 == ~E_7~0); 10398#L1036-1 assume !(0 == ~E_8~0); 10394#L1041-1 assume !(0 == ~E_9~0); 10395#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10634#L472 assume 1 == ~m_pc~0; 10700#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10423#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10424#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10432#L1179 assume !(0 != activate_threads_~tmp~1#1); 9570#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9571#L491 assume 1 == ~t1_pc~0; 10441#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10068#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9595#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9542#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 9543#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9564#L510 assume !(1 == ~t2_pc~0); 9531#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9532#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10090#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10091#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9823#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9824#L529 assume 1 == ~t3_pc~0; 10175#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10176#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9540#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9541#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 9743#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9744#L548 assume !(1 == ~t4_pc~0); 9637#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9636#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9708#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9677#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 9678#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9624#L567 assume 1 == ~t5_pc~0; 9625#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9679#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10582#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10583#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 10622#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9754#L586 assume !(1 == ~t6_pc~0); 9755#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9827#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10073#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10074#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 10616#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10617#L605 assume 1 == ~t7_pc~0; 10590#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10246#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10425#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10709#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 10708#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10366#L624 assume !(1 == ~t8_pc~0); 9818#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9817#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10475#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10534#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 10600#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9587#L643 assume 1 == ~t9_pc~0; 9588#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10554#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10138#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9978#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 9979#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9800#L1059 assume !(1 == ~M_E~0); 9801#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9951#L1064-1 assume !(1 == ~T2_E~0); 9952#L1069-1 assume !(1 == ~T3_E~0); 10561#L1074-1 assume !(1 == ~T4_E~0); 10598#L1079-1 assume !(1 == ~T5_E~0); 10588#L1084-1 assume !(1 == ~T6_E~0); 10589#L1089-1 assume !(1 == ~T7_E~0); 10612#L1094-1 assume !(1 == ~T8_E~0); 10300#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10301#L1104-1 assume !(1 == ~E_M~0); 10477#L1109-1 assume !(1 == ~E_1~0); 10092#L1114-1 assume !(1 == ~E_2~0); 10093#L1119-1 assume !(1 == ~E_3~0); 10150#L1124-1 assume !(1 == ~E_4~0); 9583#L1129-1 assume !(1 == ~E_5~0); 9584#L1134-1 assume !(1 == ~E_6~0); 9919#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9920#L1144-1 assume !(1 == ~E_8~0); 10106#L1149-1 assume !(1 == ~E_9~0); 9760#L1154-1 assume { :end_inline_reset_delta_events } true; 9761#L1440-2 [2023-11-26 10:45:23,062 INFO L750 eck$LassoCheckResult]: Loop: 9761#L1440-2 assume !false; 9889#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10464#L926-1 assume !false; 10152#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10153#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9845#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9846#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9855#L795 assume !(0 != eval_~tmp~0#1); 9856#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10309#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10007#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10008#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10525#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10368#L961-3 assume !(0 == ~T3_E~0); 10132#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10133#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10417#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9607#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9608#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9585#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9586#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10512#L1001-3 assume !(0 == ~E_1~0); 10104#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10105#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10533#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10568#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10313#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10314#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10506#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10507#L1041-3 assume !(0 == ~E_9~0); 10559#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10523#L472-33 assume !(1 == ~m_pc~0); 9705#L472-35 is_master_triggered_~__retres1~0#1 := 0; 9706#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10550#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10530#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10143#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10144#L491-33 assume 1 == ~t1_pc~0; 10433#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9645#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10677#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10692#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 10693#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10483#L510-33 assume 1 == ~t2_pc~0; 10484#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10479#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10517#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10518#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9526#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9527#L529-33 assume !(1 == ~t3_pc~0); 9552#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 9553#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9718#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9719#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9658#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9659#L548-33 assume 1 == ~t4_pc~0; 9905#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10025#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10449#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10062#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9843#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9844#L567-33 assume !(1 == ~t5_pc~0); 9946#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 9947#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10185#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10697#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10702#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10390#L586-33 assume 1 == ~t6_pc~0; 10356#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9965#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10203#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10204#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9862#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9863#L605-33 assume 1 == ~t7_pc~0; 10032#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9792#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9793#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10593#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9670#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9671#L624-33 assume !(1 == ~t8_pc~0); 9832#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 9840#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10367#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10044#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 10045#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9794#L643-33 assume 1 == ~t9_pc~0; 9795#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9874#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10340#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10296#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10297#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9660#L1059-3 assume !(1 == ~M_E~0); 9661#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10164#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10223#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10224#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10491#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10399#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10338#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10339#L1094-3 assume !(1 == ~T8_E~0); 10255#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10256#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10513#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10499#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10500#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10703#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10707#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9958#L1134-3 assume !(1 == ~E_6~0); 9959#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10126#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10127#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10302#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10710#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9665#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10042#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 9548#L1459 assume !(0 == start_simulation_~tmp~3#1); 9549#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10569#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9848#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9590#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 9591#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 10004#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10168#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10328#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 9761#L1440-2 [2023-11-26 10:45:23,063 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:23,063 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2023-11-26 10:45:23,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:23,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793120811] [2023-11-26 10:45:23,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:23,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:23,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:23,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:23,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:23,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793120811] [2023-11-26 10:45:23,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793120811] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:23,137 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:23,137 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:23,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1322501145] [2023-11-26 10:45:23,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:23,138 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:23,138 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:23,138 INFO L85 PathProgramCache]: Analyzing trace with hash -1438738724, now seen corresponding path program 1 times [2023-11-26 10:45:23,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:23,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647236922] [2023-11-26 10:45:23,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:23,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:23,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:23,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:23,208 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:23,208 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647236922] [2023-11-26 10:45:23,209 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [647236922] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:23,209 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:23,209 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:23,209 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873511008] [2023-11-26 10:45:23,209 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:23,210 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:23,210 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:23,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:23,210 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:23,211 INFO L87 Difference]: Start difference. First operand 1185 states and 1758 transitions. cyclomatic complexity: 574 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:23,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:23,246 INFO L93 Difference]: Finished difference Result 1185 states and 1757 transitions. [2023-11-26 10:45:23,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1757 transitions. [2023-11-26 10:45:23,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:23,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1757 transitions. [2023-11-26 10:45:23,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-26 10:45:23,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-26 10:45:23,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1757 transitions. [2023-11-26 10:45:23,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:23,271 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1757 transitions. [2023-11-26 10:45:23,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1757 transitions. [2023-11-26 10:45:23,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-26 10:45:23,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4827004219409283) internal successors, (1757), 1184 states have internal predecessors, (1757), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:23,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1757 transitions. [2023-11-26 10:45:23,299 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1757 transitions. [2023-11-26 10:45:23,299 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:23,301 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1757 transitions. [2023-11-26 10:45:23,302 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 10:45:23,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1757 transitions. [2023-11-26 10:45:23,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:23,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:23,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:23,312 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:23,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:23,312 INFO L748 eck$LassoCheckResult]: Stem: 12279#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12280#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 13023#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12749#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 12475#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12476#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13004#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13038#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13031#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13032#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12603#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12590#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12591#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12400#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12401#L951 assume !(0 == ~M_E~0); 12145#L951-2 assume !(0 == ~T1_E~0); 12146#L956-1 assume !(0 == ~T2_E~0); 12300#L961-1 assume !(0 == ~T3_E~0); 12768#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12769#L971-1 assume !(0 == ~T5_E~0); 12892#L976-1 assume !(0 == ~T6_E~0); 12867#L981-1 assume !(0 == ~T7_E~0); 12639#L986-1 assume !(0 == ~T8_E~0); 12350#L991-1 assume !(0 == ~T9_E~0); 12351#L996-1 assume !(0 == ~E_M~0); 13060#L1001-1 assume !(0 == ~E_1~0); 12819#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12820#L1011-1 assume !(0 == ~E_3~0); 13039#L1016-1 assume !(0 == ~E_4~0); 13048#L1021-1 assume !(0 == ~E_5~0); 11939#L1026-1 assume !(0 == ~E_6~0); 11940#L1031-1 assume !(0 == ~E_7~0); 12775#L1036-1 assume !(0 == ~E_8~0); 12771#L1041-1 assume !(0 == ~E_9~0); 12772#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13011#L472 assume 1 == ~m_pc~0; 13077#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12800#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12801#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12809#L1179 assume !(0 != activate_threads_~tmp~1#1); 11947#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11948#L491 assume 1 == ~t1_pc~0; 12818#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12445#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11972#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11919#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 11920#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11941#L510 assume !(1 == ~t2_pc~0); 11908#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11909#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12467#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12468#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12200#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12201#L529 assume 1 == ~t3_pc~0; 12552#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12553#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11917#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11918#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 12120#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12121#L548 assume !(1 == ~t4_pc~0); 12014#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12013#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12085#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12054#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 12055#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12001#L567 assume 1 == ~t5_pc~0; 12002#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12056#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12959#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12960#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 12999#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12131#L586 assume !(1 == ~t6_pc~0); 12132#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12204#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12450#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12451#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 12993#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12994#L605 assume 1 == ~t7_pc~0; 12967#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12623#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12802#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13086#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 13085#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12743#L624 assume !(1 == ~t8_pc~0); 12195#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12194#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12852#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12911#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 12977#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11964#L643 assume 1 == ~t9_pc~0; 11965#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12931#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12515#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12355#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 12356#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12177#L1059 assume !(1 == ~M_E~0); 12178#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12328#L1064-1 assume !(1 == ~T2_E~0); 12329#L1069-1 assume !(1 == ~T3_E~0); 12938#L1074-1 assume !(1 == ~T4_E~0); 12975#L1079-1 assume !(1 == ~T5_E~0); 12965#L1084-1 assume !(1 == ~T6_E~0); 12966#L1089-1 assume !(1 == ~T7_E~0); 12989#L1094-1 assume !(1 == ~T8_E~0); 12677#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12678#L1104-1 assume !(1 == ~E_M~0); 12854#L1109-1 assume !(1 == ~E_1~0); 12469#L1114-1 assume !(1 == ~E_2~0); 12470#L1119-1 assume !(1 == ~E_3~0); 12527#L1124-1 assume !(1 == ~E_4~0); 11960#L1129-1 assume !(1 == ~E_5~0); 11961#L1134-1 assume !(1 == ~E_6~0); 12296#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12297#L1144-1 assume !(1 == ~E_8~0); 12483#L1149-1 assume !(1 == ~E_9~0); 12137#L1154-1 assume { :end_inline_reset_delta_events } true; 12138#L1440-2 [2023-11-26 10:45:23,313 INFO L750 eck$LassoCheckResult]: Loop: 12138#L1440-2 assume !false; 12266#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12841#L926-1 assume !false; 12529#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12530#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12222#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12223#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12232#L795 assume !(0 != eval_~tmp~0#1); 12233#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12686#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12384#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12385#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12902#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12745#L961-3 assume !(0 == ~T3_E~0); 12509#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12510#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12794#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11984#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11985#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11962#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11963#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12889#L1001-3 assume !(0 == ~E_1~0); 12481#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12482#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12910#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12945#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12690#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12691#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12883#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12884#L1041-3 assume !(0 == ~E_9~0); 12936#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12900#L472-33 assume !(1 == ~m_pc~0); 12082#L472-35 is_master_triggered_~__retres1~0#1 := 0; 12083#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12927#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12907#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12520#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12521#L491-33 assume !(1 == ~t1_pc~0); 12021#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12022#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13054#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13069#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 13070#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12860#L510-33 assume !(1 == ~t2_pc~0); 12855#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 12856#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12894#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12895#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11903#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11904#L529-33 assume 1 == ~t3_pc~0; 11928#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11930#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12095#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12096#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12035#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12036#L548-33 assume 1 == ~t4_pc~0; 12282#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12402#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12826#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12439#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12220#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12221#L567-33 assume !(1 == ~t5_pc~0); 12323#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 12324#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12562#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13074#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13079#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12767#L586-33 assume !(1 == ~t6_pc~0); 12341#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 12342#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12580#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12581#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12239#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12240#L605-33 assume 1 == ~t7_pc~0; 12409#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12169#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12170#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12970#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12047#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12048#L624-33 assume !(1 == ~t8_pc~0); 12209#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 12217#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12744#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12421#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 12422#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12171#L643-33 assume 1 == ~t9_pc~0; 12172#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12251#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12717#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12673#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12674#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12037#L1059-3 assume !(1 == ~M_E~0); 12038#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12541#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12600#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12601#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12868#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12776#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12715#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12716#L1094-3 assume !(1 == ~T8_E~0); 12632#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12633#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12890#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12876#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12877#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13080#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13084#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12335#L1134-3 assume !(1 == ~E_6~0); 12336#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12503#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12504#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12679#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 13087#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12042#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12419#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 11925#L1459 assume !(0 == start_simulation_~tmp~3#1); 11926#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12946#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12225#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11967#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 11968#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 12381#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12545#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 12705#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 12138#L1440-2 [2023-11-26 10:45:23,314 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:23,314 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2023-11-26 10:45:23,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:23,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472679719] [2023-11-26 10:45:23,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:23,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:23,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:23,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:23,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:23,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472679719] [2023-11-26 10:45:23,375 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472679719] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:23,375 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:23,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:23,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721879982] [2023-11-26 10:45:23,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:23,376 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:23,376 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:23,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1364817186, now seen corresponding path program 1 times [2023-11-26 10:45:23,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:23,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715976957] [2023-11-26 10:45:23,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:23,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:23,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:23,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:23,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:23,469 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715976957] [2023-11-26 10:45:23,470 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [715976957] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:23,470 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:23,470 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:23,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1945869779] [2023-11-26 10:45:23,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:23,472 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:23,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:23,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:23,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:23,473 INFO L87 Difference]: Start difference. First operand 1185 states and 1757 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:23,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:23,517 INFO L93 Difference]: Finished difference Result 1185 states and 1756 transitions. [2023-11-26 10:45:23,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1756 transitions. [2023-11-26 10:45:23,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:23,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1756 transitions. [2023-11-26 10:45:23,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-26 10:45:23,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-26 10:45:23,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1756 transitions. [2023-11-26 10:45:23,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:23,545 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1756 transitions. [2023-11-26 10:45:23,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1756 transitions. [2023-11-26 10:45:23,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-26 10:45:23,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.4818565400843882) internal successors, (1756), 1184 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:23,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1756 transitions. [2023-11-26 10:45:23,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1756 transitions. [2023-11-26 10:45:23,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:23,583 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1756 transitions. [2023-11-26 10:45:23,583 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 10:45:23,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1756 transitions. [2023-11-26 10:45:23,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:23,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:23,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:23,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:23,596 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:23,597 INFO L748 eck$LassoCheckResult]: Stem: 14656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15400#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15401#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15126#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 14852#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14853#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15381#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15415#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15408#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15409#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14980#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14967#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14968#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14777#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14778#L951 assume !(0 == ~M_E~0); 14522#L951-2 assume !(0 == ~T1_E~0); 14523#L956-1 assume !(0 == ~T2_E~0); 14677#L961-1 assume !(0 == ~T3_E~0); 15145#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15146#L971-1 assume !(0 == ~T5_E~0); 15269#L976-1 assume !(0 == ~T6_E~0); 15244#L981-1 assume !(0 == ~T7_E~0); 15016#L986-1 assume !(0 == ~T8_E~0); 14727#L991-1 assume !(0 == ~T9_E~0); 14728#L996-1 assume !(0 == ~E_M~0); 15437#L1001-1 assume !(0 == ~E_1~0); 15196#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 15197#L1011-1 assume !(0 == ~E_3~0); 15416#L1016-1 assume !(0 == ~E_4~0); 15425#L1021-1 assume !(0 == ~E_5~0); 14316#L1026-1 assume !(0 == ~E_6~0); 14317#L1031-1 assume !(0 == ~E_7~0); 15152#L1036-1 assume !(0 == ~E_8~0); 15148#L1041-1 assume !(0 == ~E_9~0); 15149#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15388#L472 assume 1 == ~m_pc~0; 15454#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15177#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15178#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15186#L1179 assume !(0 != activate_threads_~tmp~1#1); 14324#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14325#L491 assume 1 == ~t1_pc~0; 15195#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14822#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14349#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14296#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 14297#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14318#L510 assume !(1 == ~t2_pc~0); 14285#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14286#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14844#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14845#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14577#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14578#L529 assume 1 == ~t3_pc~0; 14929#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14930#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14294#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14295#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 14497#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14498#L548 assume !(1 == ~t4_pc~0); 14391#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14390#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14462#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14431#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 14432#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14378#L567 assume 1 == ~t5_pc~0; 14379#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14433#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15336#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15337#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 15376#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14508#L586 assume !(1 == ~t6_pc~0); 14509#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14581#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14827#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14828#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 15370#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15371#L605 assume 1 == ~t7_pc~0; 15344#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15000#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15179#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15463#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 15462#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15120#L624 assume !(1 == ~t8_pc~0); 14572#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14571#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15229#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15288#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 15354#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14341#L643 assume 1 == ~t9_pc~0; 14342#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15308#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14892#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14732#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 14733#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14554#L1059 assume !(1 == ~M_E~0); 14555#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14705#L1064-1 assume !(1 == ~T2_E~0); 14706#L1069-1 assume !(1 == ~T3_E~0); 15315#L1074-1 assume !(1 == ~T4_E~0); 15352#L1079-1 assume !(1 == ~T5_E~0); 15342#L1084-1 assume !(1 == ~T6_E~0); 15343#L1089-1 assume !(1 == ~T7_E~0); 15366#L1094-1 assume !(1 == ~T8_E~0); 15054#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15055#L1104-1 assume !(1 == ~E_M~0); 15231#L1109-1 assume !(1 == ~E_1~0); 14846#L1114-1 assume !(1 == ~E_2~0); 14847#L1119-1 assume !(1 == ~E_3~0); 14904#L1124-1 assume !(1 == ~E_4~0); 14337#L1129-1 assume !(1 == ~E_5~0); 14338#L1134-1 assume !(1 == ~E_6~0); 14673#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14674#L1144-1 assume !(1 == ~E_8~0); 14860#L1149-1 assume !(1 == ~E_9~0); 14514#L1154-1 assume { :end_inline_reset_delta_events } true; 14515#L1440-2 [2023-11-26 10:45:23,598 INFO L750 eck$LassoCheckResult]: Loop: 14515#L1440-2 assume !false; 14643#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15218#L926-1 assume !false; 14906#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14907#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14599#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14600#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14609#L795 assume !(0 != eval_~tmp~0#1); 14610#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14761#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14762#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15279#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15122#L961-3 assume !(0 == ~T3_E~0); 14886#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14887#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15171#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14361#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14362#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14339#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14340#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15266#L1001-3 assume !(0 == ~E_1~0); 14858#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14859#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15287#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15322#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15067#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15068#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15260#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15261#L1041-3 assume !(0 == ~E_9~0); 15313#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15277#L472-33 assume !(1 == ~m_pc~0); 14459#L472-35 is_master_triggered_~__retres1~0#1 := 0; 14460#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15304#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15284#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14897#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14898#L491-33 assume 1 == ~t1_pc~0; 15187#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14399#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15431#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15446#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 15447#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15237#L510-33 assume !(1 == ~t2_pc~0); 15232#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 15233#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15271#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15272#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14280#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14281#L529-33 assume 1 == ~t3_pc~0; 14305#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14307#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14472#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14473#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14412#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14413#L548-33 assume 1 == ~t4_pc~0; 14659#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14779#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15203#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14816#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14597#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14598#L567-33 assume !(1 == ~t5_pc~0); 14700#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 14701#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14939#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15451#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15456#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15144#L586-33 assume 1 == ~t6_pc~0; 15110#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14719#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14957#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14958#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14616#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14617#L605-33 assume 1 == ~t7_pc~0; 14786#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14546#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14547#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15347#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14424#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14425#L624-33 assume !(1 == ~t8_pc~0); 14586#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 14594#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15121#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14798#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 14799#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14548#L643-33 assume 1 == ~t9_pc~0; 14549#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14628#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15094#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15050#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15051#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14414#L1059-3 assume !(1 == ~M_E~0); 14415#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14918#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14977#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14978#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15245#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15153#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15092#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15093#L1094-3 assume !(1 == ~T8_E~0); 15009#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15010#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15267#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15253#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15254#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15457#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15461#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14712#L1134-3 assume !(1 == ~E_6~0); 14713#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14880#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14881#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15056#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15464#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14419#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14796#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14302#L1459 assume !(0 == start_simulation_~tmp~3#1); 14303#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15323#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14602#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14344#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 14345#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 14758#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14922#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 15082#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 14515#L1440-2 [2023-11-26 10:45:23,599 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:23,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2023-11-26 10:45:23,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:23,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574410853] [2023-11-26 10:45:23,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:23,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:23,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:23,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:23,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:23,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574410853] [2023-11-26 10:45:23,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574410853] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:23,658 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:23,659 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:23,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141353707] [2023-11-26 10:45:23,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:23,660 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:23,660 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:23,660 INFO L85 PathProgramCache]: Analyzing trace with hash -119844324, now seen corresponding path program 1 times [2023-11-26 10:45:23,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:23,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085729753] [2023-11-26 10:45:23,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:23,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:23,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:23,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:23,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:23,726 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085729753] [2023-11-26 10:45:23,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085729753] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:23,726 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:23,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:23,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1817674683] [2023-11-26 10:45:23,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:23,727 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:23,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:23,728 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:23,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:23,728 INFO L87 Difference]: Start difference. First operand 1185 states and 1756 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:23,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:23,764 INFO L93 Difference]: Finished difference Result 1185 states and 1755 transitions. [2023-11-26 10:45:23,765 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1755 transitions. [2023-11-26 10:45:23,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:23,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1755 transitions. [2023-11-26 10:45:23,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-26 10:45:23,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-26 10:45:23,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1755 transitions. [2023-11-26 10:45:23,790 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:23,790 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1755 transitions. [2023-11-26 10:45:23,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1755 transitions. [2023-11-26 10:45:23,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-26 10:45:23,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.481012658227848) internal successors, (1755), 1184 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:23,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1755 transitions. [2023-11-26 10:45:23,820 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1755 transitions. [2023-11-26 10:45:23,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:23,821 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1755 transitions. [2023-11-26 10:45:23,821 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 10:45:23,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1755 transitions. [2023-11-26 10:45:23,829 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:23,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:23,830 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:23,832 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:23,832 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:23,832 INFO L748 eck$LassoCheckResult]: Stem: 17035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17036#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17779#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17780#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17503#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 17229#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17230#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17758#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17792#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17785#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17786#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17357#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17344#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17345#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17154#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17155#L951 assume !(0 == ~M_E~0); 16899#L951-2 assume !(0 == ~T1_E~0); 16900#L956-1 assume !(0 == ~T2_E~0); 17054#L961-1 assume !(0 == ~T3_E~0); 17522#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17523#L971-1 assume !(0 == ~T5_E~0); 17646#L976-1 assume !(0 == ~T6_E~0); 17621#L981-1 assume !(0 == ~T7_E~0); 17393#L986-1 assume !(0 == ~T8_E~0); 17104#L991-1 assume !(0 == ~T9_E~0); 17105#L996-1 assume !(0 == ~E_M~0); 17814#L1001-1 assume !(0 == ~E_1~0); 17573#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17574#L1011-1 assume !(0 == ~E_3~0); 17793#L1016-1 assume !(0 == ~E_4~0); 17802#L1021-1 assume !(0 == ~E_5~0); 16693#L1026-1 assume !(0 == ~E_6~0); 16694#L1031-1 assume !(0 == ~E_7~0); 17529#L1036-1 assume !(0 == ~E_8~0); 17525#L1041-1 assume !(0 == ~E_9~0); 17526#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17765#L472 assume 1 == ~m_pc~0; 17831#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17554#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17555#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17563#L1179 assume !(0 != activate_threads_~tmp~1#1); 16701#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16702#L491 assume 1 == ~t1_pc~0; 17572#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17199#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16726#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16673#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 16674#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16697#L510 assume !(1 == ~t2_pc~0); 16662#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16663#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17221#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17222#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16954#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16955#L529 assume 1 == ~t3_pc~0; 17306#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17307#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16671#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16672#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 16874#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16875#L548 assume !(1 == ~t4_pc~0); 16768#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16767#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16839#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16810#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 16811#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16755#L567 assume 1 == ~t5_pc~0; 16756#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16812#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17713#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17714#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 17753#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16885#L586 assume !(1 == ~t6_pc~0); 16886#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16958#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17204#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17205#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 17747#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17748#L605 assume 1 == ~t7_pc~0; 17721#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17379#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17556#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17840#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 17839#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17497#L624 assume !(1 == ~t8_pc~0); 16949#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16948#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17606#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17665#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 17731#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16718#L643 assume 1 == ~t9_pc~0; 16719#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17685#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17271#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17111#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 17112#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16931#L1059 assume !(1 == ~M_E~0); 16932#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17082#L1064-1 assume !(1 == ~T2_E~0); 17083#L1069-1 assume !(1 == ~T3_E~0); 17692#L1074-1 assume !(1 == ~T4_E~0); 17729#L1079-1 assume !(1 == ~T5_E~0); 17719#L1084-1 assume !(1 == ~T6_E~0); 17720#L1089-1 assume !(1 == ~T7_E~0); 17743#L1094-1 assume !(1 == ~T8_E~0); 17431#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17432#L1104-1 assume !(1 == ~E_M~0); 17608#L1109-1 assume !(1 == ~E_1~0); 17223#L1114-1 assume !(1 == ~E_2~0); 17224#L1119-1 assume !(1 == ~E_3~0); 17281#L1124-1 assume !(1 == ~E_4~0); 16714#L1129-1 assume !(1 == ~E_5~0); 16715#L1134-1 assume !(1 == ~E_6~0); 17050#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17051#L1144-1 assume !(1 == ~E_8~0); 17239#L1149-1 assume !(1 == ~E_9~0); 16891#L1154-1 assume { :end_inline_reset_delta_events } true; 16892#L1440-2 [2023-11-26 10:45:23,833 INFO L750 eck$LassoCheckResult]: Loop: 16892#L1440-2 assume !false; 17020#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17595#L926-1 assume !false; 17283#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17284#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16979#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16980#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16987#L795 assume !(0 != eval_~tmp~0#1); 16988#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17440#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17138#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17139#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17656#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17499#L961-3 assume !(0 == ~T3_E~0); 17264#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17265#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17548#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16741#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16742#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16716#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16717#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17643#L1001-3 assume !(0 == ~E_1~0); 17235#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17236#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17664#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17699#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17444#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17445#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17637#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17638#L1041-3 assume !(0 == ~E_9~0); 17690#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17654#L472-33 assume !(1 == ~m_pc~0); 16836#L472-35 is_master_triggered_~__retres1~0#1 := 0; 16837#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17681#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17661#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17274#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17275#L491-33 assume !(1 == ~t1_pc~0); 16775#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16776#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17808#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17823#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 17824#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17614#L510-33 assume !(1 == ~t2_pc~0); 17609#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 17610#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17648#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17649#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16657#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16658#L529-33 assume 1 == ~t3_pc~0; 16682#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16684#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16849#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16850#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16789#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16790#L548-33 assume 1 == ~t4_pc~0; 17038#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17156#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17580#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17193#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16974#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16975#L567-33 assume !(1 == ~t5_pc~0); 17077#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 17078#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17317#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17828#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17834#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17521#L586-33 assume !(1 == ~t6_pc~0); 17095#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 17096#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17333#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17334#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16991#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16992#L605-33 assume 1 == ~t7_pc~0; 17160#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16916#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16917#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17724#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16801#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16802#L624-33 assume !(1 == ~t8_pc~0); 16961#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 16968#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17498#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17175#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 17176#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16918#L643-33 assume 1 == ~t9_pc~0; 16919#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17005#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17471#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17427#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17428#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16791#L1059-3 assume !(1 == ~M_E~0); 16792#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17295#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17353#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17354#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17622#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17530#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17469#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17470#L1094-3 assume !(1 == ~T8_E~0); 17386#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17387#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17644#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17628#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17629#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17833#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17838#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17089#L1134-3 assume !(1 == ~E_6~0); 17090#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17252#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17253#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17433#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17841#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16794#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17171#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16679#L1459 assume !(0 == start_simulation_~tmp~3#1); 16680#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17700#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16977#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16721#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 16722#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17135#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17296#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17456#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 16892#L1440-2 [2023-11-26 10:45:23,834 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:23,834 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2023-11-26 10:45:23,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:23,834 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164342772] [2023-11-26 10:45:23,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:23,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:23,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:23,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:23,880 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:23,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1164342772] [2023-11-26 10:45:23,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1164342772] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:23,881 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:23,881 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:23,881 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411844563] [2023-11-26 10:45:23,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:23,882 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:23,882 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:23,882 INFO L85 PathProgramCache]: Analyzing trace with hash -1364817186, now seen corresponding path program 2 times [2023-11-26 10:45:23,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:23,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881008952] [2023-11-26 10:45:23,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:23,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:23,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:23,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:23,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:23,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881008952] [2023-11-26 10:45:23,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881008952] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:23,941 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:23,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:23,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039655721] [2023-11-26 10:45:23,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:23,942 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:23,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:23,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:23,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:23,943 INFO L87 Difference]: Start difference. First operand 1185 states and 1755 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:23,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:23,978 INFO L93 Difference]: Finished difference Result 1185 states and 1754 transitions. [2023-11-26 10:45:23,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1754 transitions. [2023-11-26 10:45:24,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:24,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1185 states and 1754 transitions. [2023-11-26 10:45:24,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1185 [2023-11-26 10:45:24,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1185 [2023-11-26 10:45:24,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1185 states and 1754 transitions. [2023-11-26 10:45:24,026 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:24,026 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1754 transitions. [2023-11-26 10:45:24,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states and 1754 transitions. [2023-11-26 10:45:24,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1185. [2023-11-26 10:45:24,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.480168776371308) internal successors, (1754), 1184 states have internal predecessors, (1754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:24,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1754 transitions. [2023-11-26 10:45:24,057 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1754 transitions. [2023-11-26 10:45:24,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:24,060 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1754 transitions. [2023-11-26 10:45:24,060 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 10:45:24,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1754 transitions. [2023-11-26 10:45:24,067 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1058 [2023-11-26 10:45:24,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:24,067 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:24,069 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:24,070 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:24,070 INFO L748 eck$LassoCheckResult]: Stem: 19414#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 20156#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20157#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19880#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 19606#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19607#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20135#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20169#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20162#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20163#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19734#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19721#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19722#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19532#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19533#L951 assume !(0 == ~M_E~0); 19276#L951-2 assume !(0 == ~T1_E~0); 19277#L956-1 assume !(0 == ~T2_E~0); 19431#L961-1 assume !(0 == ~T3_E~0); 19899#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19900#L971-1 assume !(0 == ~T5_E~0); 20023#L976-1 assume !(0 == ~T6_E~0); 19998#L981-1 assume !(0 == ~T7_E~0); 19773#L986-1 assume !(0 == ~T8_E~0); 19481#L991-1 assume !(0 == ~T9_E~0); 19482#L996-1 assume !(0 == ~E_M~0); 20192#L1001-1 assume !(0 == ~E_1~0); 19950#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19951#L1011-1 assume !(0 == ~E_3~0); 20170#L1016-1 assume !(0 == ~E_4~0); 20179#L1021-1 assume !(0 == ~E_5~0); 19070#L1026-1 assume !(0 == ~E_6~0); 19071#L1031-1 assume !(0 == ~E_7~0); 19906#L1036-1 assume !(0 == ~E_8~0); 19904#L1041-1 assume !(0 == ~E_9~0); 19905#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20142#L472 assume 1 == ~m_pc~0; 20208#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19931#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19932#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19940#L1179 assume !(0 != activate_threads_~tmp~1#1); 19078#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19079#L491 assume 1 == ~t1_pc~0; 19949#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19576#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19103#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19050#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 19051#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19074#L510 assume !(1 == ~t2_pc~0); 19039#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19040#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19598#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19599#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19331#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19332#L529 assume 1 == ~t3_pc~0; 19683#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19684#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19049#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 19251#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19252#L548 assume !(1 == ~t4_pc~0); 19145#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19144#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19216#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19187#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 19188#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19132#L567 assume 1 == ~t5_pc~0; 19133#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19189#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20090#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20091#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 20130#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19262#L586 assume !(1 == ~t6_pc~0); 19263#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19337#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19584#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19585#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 20124#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20125#L605 assume 1 == ~t7_pc~0; 20098#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19757#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19934#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20217#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 20216#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19874#L624 assume !(1 == ~t8_pc~0); 19326#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19325#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19983#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20042#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 20108#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19095#L643 assume 1 == ~t9_pc~0; 19096#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20062#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19648#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19488#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 19489#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19308#L1059 assume !(1 == ~M_E~0); 19309#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19459#L1064-1 assume !(1 == ~T2_E~0); 19460#L1069-1 assume !(1 == ~T3_E~0); 20069#L1074-1 assume !(1 == ~T4_E~0); 20107#L1079-1 assume !(1 == ~T5_E~0); 20096#L1084-1 assume !(1 == ~T6_E~0); 20097#L1089-1 assume !(1 == ~T7_E~0); 20120#L1094-1 assume !(1 == ~T8_E~0); 19808#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19809#L1104-1 assume !(1 == ~E_M~0); 19987#L1109-1 assume !(1 == ~E_1~0); 19600#L1114-1 assume !(1 == ~E_2~0); 19601#L1119-1 assume !(1 == ~E_3~0); 19658#L1124-1 assume !(1 == ~E_4~0); 19091#L1129-1 assume !(1 == ~E_5~0); 19092#L1134-1 assume !(1 == ~E_6~0); 19427#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19428#L1144-1 assume !(1 == ~E_8~0); 19616#L1149-1 assume !(1 == ~E_9~0); 19268#L1154-1 assume { :end_inline_reset_delta_events } true; 19269#L1440-2 [2023-11-26 10:45:24,071 INFO L750 eck$LassoCheckResult]: Loop: 19269#L1440-2 assume !false; 19399#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19972#L926-1 assume !false; 19660#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19661#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19356#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19357#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19364#L795 assume !(0 != eval_~tmp~0#1); 19365#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19817#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19515#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19516#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20033#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19876#L961-3 assume !(0 == ~T3_E~0); 19644#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19645#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19925#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19118#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19119#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19093#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19094#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20020#L1001-3 assume !(0 == ~E_1~0); 19612#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19613#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20041#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20076#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19822#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19823#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20014#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20015#L1041-3 assume !(0 == ~E_9~0); 20067#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20031#L472-33 assume 1 == ~m_pc~0; 20032#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19214#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20058#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20038#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19651#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19652#L491-33 assume !(1 == ~t1_pc~0); 19152#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 19153#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20185#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20200#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 20201#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19992#L510-33 assume !(1 == ~t2_pc~0); 19985#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 19986#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20025#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20026#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19034#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19035#L529-33 assume 1 == ~t3_pc~0; 19059#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19061#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19224#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19225#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19166#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19167#L548-33 assume 1 == ~t4_pc~0; 19410#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19531#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19957#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19568#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19351#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19352#L567-33 assume 1 == ~t5_pc~0; 19789#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19455#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19693#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20205#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20210#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19898#L586-33 assume !(1 == ~t6_pc~0); 19472#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 19473#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19710#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19711#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19370#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19371#L605-33 assume 1 == ~t7_pc~0; 19540#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19293#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19294#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20101#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19178#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19179#L624-33 assume !(1 == ~t8_pc~0); 19340#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 19348#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19875#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19552#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 19553#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19295#L643-33 assume 1 == ~t9_pc~0; 19296#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19382#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19848#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19804#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19805#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19168#L1059-3 assume !(1 == ~M_E~0); 19169#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19672#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19730#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19731#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19999#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19907#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19846#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19847#L1094-3 assume !(1 == ~T8_E~0); 19763#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19764#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20021#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20005#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20006#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20211#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20215#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19466#L1134-3 assume !(1 == ~E_6~0); 19467#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19632#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19633#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19810#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20218#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19171#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19550#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 19056#L1459 assume !(0 == start_simulation_~tmp~3#1); 19057#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20077#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19354#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 19099#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 19512#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19674#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19833#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 19269#L1440-2 [2023-11-26 10:45:24,071 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:24,072 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2023-11-26 10:45:24,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:24,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265978458] [2023-11-26 10:45:24,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:24,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:24,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:24,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:24,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:24,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265978458] [2023-11-26 10:45:24,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265978458] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:24,173 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:24,173 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:24,173 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914419348] [2023-11-26 10:45:24,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:24,174 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:24,174 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:24,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1236036508, now seen corresponding path program 1 times [2023-11-26 10:45:24,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:24,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524918879] [2023-11-26 10:45:24,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:24,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:24,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:24,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:24,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:24,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524918879] [2023-11-26 10:45:24,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524918879] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:24,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:24,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:24,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327929851] [2023-11-26 10:45:24,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:24,240 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:24,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:24,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:45:24,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:45:24,241 INFO L87 Difference]: Start difference. First operand 1185 states and 1754 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:24,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:24,445 INFO L93 Difference]: Finished difference Result 2171 states and 3201 transitions. [2023-11-26 10:45:24,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2171 states and 3201 transitions. [2023-11-26 10:45:24,462 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2023-11-26 10:45:24,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2171 states to 2171 states and 3201 transitions. [2023-11-26 10:45:24,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2171 [2023-11-26 10:45:24,482 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2171 [2023-11-26 10:45:24,483 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2171 states and 3201 transitions. [2023-11-26 10:45:24,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:24,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3201 transitions. [2023-11-26 10:45:24,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2171 states and 3201 transitions. [2023-11-26 10:45:24,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2171 to 2171. [2023-11-26 10:45:24,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2171 states, 2171 states have (on average 1.4744357438968216) internal successors, (3201), 2170 states have internal predecessors, (3201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:24,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2171 states to 2171 states and 3201 transitions. [2023-11-26 10:45:24,551 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3201 transitions. [2023-11-26 10:45:24,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:45:24,553 INFO L428 stractBuchiCegarLoop]: Abstraction has 2171 states and 3201 transitions. [2023-11-26 10:45:24,554 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 10:45:24,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2171 states and 3201 transitions. [2023-11-26 10:45:24,565 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2023-11-26 10:45:24,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:24,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:24,567 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:24,567 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:24,568 INFO L748 eck$LassoCheckResult]: Stem: 22784#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 22785#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 23574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23575#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23263#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 22979#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22980#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23552#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23587#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23580#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23581#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23107#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23094#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 23095#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22902#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22903#L951 assume !(0 == ~M_E~0); 22645#L951-2 assume !(0 == ~T1_E~0); 22646#L956-1 assume !(0 == ~T2_E~0); 22800#L961-1 assume !(0 == ~T3_E~0); 23284#L966-1 assume !(0 == ~T4_E~0); 23285#L971-1 assume !(0 == ~T5_E~0); 23417#L976-1 assume !(0 == ~T6_E~0); 23391#L981-1 assume !(0 == ~T7_E~0); 23148#L986-1 assume !(0 == ~T8_E~0); 22851#L991-1 assume !(0 == ~T9_E~0); 22852#L996-1 assume !(0 == ~E_M~0); 23617#L1001-1 assume !(0 == ~E_1~0); 23338#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 23339#L1011-1 assume !(0 == ~E_3~0); 23589#L1016-1 assume !(0 == ~E_4~0); 23598#L1021-1 assume !(0 == ~E_5~0); 22436#L1026-1 assume !(0 == ~E_6~0); 22437#L1031-1 assume !(0 == ~E_7~0); 23291#L1036-1 assume !(0 == ~E_8~0); 23289#L1041-1 assume !(0 == ~E_9~0); 23290#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23559#L472 assume 1 == ~m_pc~0; 23634#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23319#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23320#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23328#L1179 assume !(0 != activate_threads_~tmp~1#1); 22444#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22445#L491 assume 1 == ~t1_pc~0; 23337#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22949#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22469#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22416#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 22417#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22440#L510 assume !(1 == ~t2_pc~0); 22405#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22406#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22969#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22970#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22699#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22700#L529 assume 1 == ~t3_pc~0; 23056#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23057#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22414#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22415#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 22618#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22619#L548 assume !(1 == ~t4_pc~0); 22512#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22511#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22583#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22554#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 22555#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22503#L567 assume 1 == ~t5_pc~0; 22504#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22556#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23496#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23497#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 23546#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22629#L586 assume !(1 == ~t6_pc~0); 22630#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22705#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22955#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22956#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 23538#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23539#L605 assume 1 == ~t7_pc~0; 23504#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23135#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23322#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23648#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 23647#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23257#L624 assume !(1 == ~t8_pc~0); 22694#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22693#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23375#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23441#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 23516#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22461#L643 assume 1 == ~t9_pc~0; 22462#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23463#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23021#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22858#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 22859#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22675#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 22676#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23657#L1064-1 assume !(1 == ~T2_E~0); 23690#L1069-1 assume !(1 == ~T3_E~0); 23689#L1074-1 assume !(1 == ~T4_E~0); 23643#L1079-1 assume !(1 == ~T5_E~0); 23688#L1084-1 assume !(1 == ~T6_E~0); 23687#L1089-1 assume !(1 == ~T7_E~0); 23686#L1094-1 assume !(1 == ~T8_E~0); 23685#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23684#L1104-1 assume !(1 == ~E_M~0); 23683#L1109-1 assume !(1 == ~E_1~0); 23682#L1114-1 assume !(1 == ~E_2~0); 23681#L1119-1 assume !(1 == ~E_3~0); 23680#L1124-1 assume !(1 == ~E_4~0); 23679#L1129-1 assume !(1 == ~E_5~0); 23678#L1134-1 assume !(1 == ~E_6~0); 23677#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23676#L1144-1 assume !(1 == ~E_8~0); 23675#L1149-1 assume !(1 == ~E_9~0); 23674#L1154-1 assume { :end_inline_reset_delta_events } true; 23672#L1440-2 [2023-11-26 10:45:24,569 INFO L750 eck$LassoCheckResult]: Loop: 23672#L1440-2 assume !false; 23671#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23670#L926-1 assume !false; 23669#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23667#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22724#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22725#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22732#L795 assume !(0 != eval_~tmp~0#1); 22733#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23195#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23196#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23655#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23431#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23260#L961-3 assume !(0 == ~T3_E~0); 23013#L966-3 assume !(0 == ~T4_E~0); 23014#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23311#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22481#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22482#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22457#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22458#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23414#L1001-3 assume !(0 == ~E_1~0); 22983#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22984#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23438#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23478#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23201#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23202#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23408#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23409#L1041-3 assume !(0 == ~E_9~0); 23468#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23427#L472-33 assume 1 == ~m_pc~0; 23428#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24130#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24129#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24128#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24127#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24126#L491-33 assume 1 == ~t1_pc~0; 24124#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23606#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23607#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23625#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 23626#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23383#L510-33 assume 1 == ~t2_pc~0; 23384#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24119#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24118#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24117#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24116#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24115#L529-33 assume !(1 == ~t3_pc~0); 24113#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 24112#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24111#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24110#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24109#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24108#L548-33 assume 1 == ~t4_pc~0; 24106#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24105#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24104#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24103#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24102#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24101#L567-33 assume !(1 == ~t5_pc~0); 24099#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 24098#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24097#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24096#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24095#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23281#L586-33 assume 1 == ~t6_pc~0; 23282#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24094#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24093#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24092#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24091#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24090#L605-33 assume !(1 == ~t7_pc~0); 24088#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 24087#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24086#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24085#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24084#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24083#L624-33 assume 1 == ~t8_pc~0; 24081#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24080#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24079#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24078#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 24077#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24076#L643-33 assume 1 == ~t9_pc~0; 24074#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24073#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24072#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24071#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24070#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24069#L1059-3 assume !(1 == ~M_E~0); 22536#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24068#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24067#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24066#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23392#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24065#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24064#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24063#L1094-3 assume !(1 == ~T8_E~0); 24062#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24061#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24060#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24059#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24058#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24057#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24056#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24055#L1134-3 assume !(1 == ~E_6~0); 24054#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24053#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23185#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23186#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23656#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23710#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23709#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23708#L1459 assume !(0 == start_simulation_~tmp~3#1); 23563#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23704#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23695#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23694#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23693#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 23692#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23691#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23673#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 23672#L1440-2 [2023-11-26 10:45:24,569 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:24,569 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2023-11-26 10:45:24,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:24,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909350198] [2023-11-26 10:45:24,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:24,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:24,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:24,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:24,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:24,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909350198] [2023-11-26 10:45:24,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909350198] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:24,658 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:24,658 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:45:24,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [646899697] [2023-11-26 10:45:24,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:24,660 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:24,661 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:24,661 INFO L85 PathProgramCache]: Analyzing trace with hash -1619670631, now seen corresponding path program 1 times [2023-11-26 10:45:24,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:24,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751246745] [2023-11-26 10:45:24,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:24,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:24,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:24,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:24,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:24,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751246745] [2023-11-26 10:45:24,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1751246745] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:24,723 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:24,724 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:24,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030553433] [2023-11-26 10:45:24,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:24,724 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:24,725 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:24,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:24,725 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:24,726 INFO L87 Difference]: Start difference. First operand 2171 states and 3201 transitions. cyclomatic complexity: 1032 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:24,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:24,844 INFO L93 Difference]: Finished difference Result 2171 states and 3171 transitions. [2023-11-26 10:45:24,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2171 states and 3171 transitions. [2023-11-26 10:45:24,861 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2023-11-26 10:45:24,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2171 states to 2171 states and 3171 transitions. [2023-11-26 10:45:24,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2171 [2023-11-26 10:45:24,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2171 [2023-11-26 10:45:24,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2171 states and 3171 transitions. [2023-11-26 10:45:24,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:24,888 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3171 transitions. [2023-11-26 10:45:24,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2171 states and 3171 transitions. [2023-11-26 10:45:24,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2171 to 2171. [2023-11-26 10:45:24,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2171 states, 2171 states have (on average 1.460617227084293) internal successors, (3171), 2170 states have internal predecessors, (3171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:24,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2171 states to 2171 states and 3171 transitions. [2023-11-26 10:45:24,948 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2171 states and 3171 transitions. [2023-11-26 10:45:24,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:24,949 INFO L428 stractBuchiCegarLoop]: Abstraction has 2171 states and 3171 transitions. [2023-11-26 10:45:24,949 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 10:45:24,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2171 states and 3171 transitions. [2023-11-26 10:45:24,961 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2023-11-26 10:45:24,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:24,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:24,964 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:24,965 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:24,965 INFO L748 eck$LassoCheckResult]: Stem: 27127#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 27128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27921#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27922#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27615#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 27326#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27327#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27897#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27938#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27930#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27931#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27457#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27444#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27445#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27250#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27251#L951 assume !(0 == ~M_E~0); 26990#L951-2 assume !(0 == ~T1_E~0); 26991#L956-1 assume !(0 == ~T2_E~0); 27148#L961-1 assume !(0 == ~T3_E~0); 27634#L966-1 assume !(0 == ~T4_E~0); 27635#L971-1 assume !(0 == ~T5_E~0); 27769#L976-1 assume !(0 == ~T6_E~0); 27744#L981-1 assume !(0 == ~T7_E~0); 27497#L986-1 assume !(0 == ~T8_E~0); 27200#L991-1 assume !(0 == ~T9_E~0); 27201#L996-1 assume !(0 == ~E_M~0); 27968#L1001-1 assume !(0 == ~E_1~0); 27687#L1006-1 assume !(0 == ~E_2~0); 27688#L1011-1 assume !(0 == ~E_3~0); 27939#L1016-1 assume !(0 == ~E_4~0); 27948#L1021-1 assume !(0 == ~E_5~0); 26784#L1026-1 assume !(0 == ~E_6~0); 26785#L1031-1 assume !(0 == ~E_7~0); 27643#L1036-1 assume !(0 == ~E_8~0); 27639#L1041-1 assume !(0 == ~E_9~0); 27640#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27904#L472 assume 1 == ~m_pc~0; 27987#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 27668#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27669#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27677#L1179 assume !(0 != activate_threads_~tmp~1#1); 26792#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26793#L491 assume 1 == ~t1_pc~0; 27686#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27296#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26818#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26765#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 26766#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26786#L510 assume !(1 == ~t2_pc~0); 26754#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26755#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27318#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27319#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27046#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27047#L529 assume 1 == ~t3_pc~0; 27406#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27407#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26763#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26764#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 26965#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26966#L548 assume !(1 == ~t4_pc~0); 26860#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26859#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26900#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 26901#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26847#L567 assume 1 == ~t5_pc~0; 26848#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26902#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27849#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 27891#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26976#L586 assume !(1 == ~t6_pc~0); 26977#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27050#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27301#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27302#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 27885#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27886#L605 assume 1 == ~t7_pc~0; 27856#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27478#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27670#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27996#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 27995#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27609#L624 assume !(1 == ~t8_pc~0); 27041#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27040#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27728#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27791#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 27867#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26809#L643 assume 1 == ~t9_pc~0; 26810#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27814#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27369#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27205#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 27206#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27022#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 27023#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27176#L1064-1 assume !(1 == ~T2_E~0); 27177#L1069-1 assume !(1 == ~T3_E~0); 27823#L1074-1 assume !(1 == ~T4_E~0); 27865#L1079-1 assume !(1 == ~T5_E~0); 27854#L1084-1 assume !(1 == ~T6_E~0); 27855#L1089-1 assume !(1 == ~T7_E~0); 27880#L1094-1 assume !(1 == ~T8_E~0); 27534#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27535#L1104-1 assume !(1 == ~E_M~0); 27730#L1109-1 assume !(1 == ~E_1~0); 27320#L1114-1 assume !(1 == ~E_2~0); 27321#L1119-1 assume !(1 == ~E_3~0); 27381#L1124-1 assume !(1 == ~E_4~0); 26805#L1129-1 assume !(1 == ~E_5~0); 26806#L1134-1 assume !(1 == ~E_6~0); 27144#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27145#L1144-1 assume !(1 == ~E_8~0); 27334#L1149-1 assume !(1 == ~E_9~0); 26982#L1154-1 assume { :end_inline_reset_delta_events } true; 26983#L1440-2 [2023-11-26 10:45:24,966 INFO L750 eck$LassoCheckResult]: Loop: 26983#L1440-2 assume !false; 27963#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27716#L926-1 assume !false; 27383#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27384#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 27068#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27069#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28008#L795 assume !(0 != eval_~tmp~0#1); 27795#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27796#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28006#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28007#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28889#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28888#L961-3 assume !(0 == ~T3_E~0); 28887#L966-3 assume !(0 == ~T4_E~0); 28886#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28885#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28884#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28883#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28882#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28881#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28880#L1001-3 assume !(0 == ~E_1~0); 28879#L1006-3 assume !(0 == ~E_2~0); 28878#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28877#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28876#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28875#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28874#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28873#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28872#L1041-3 assume !(0 == ~E_9~0); 28871#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28870#L472-33 assume !(1 == ~m_pc~0); 28868#L472-35 is_master_triggered_~__retres1~0#1 := 0; 28867#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28866#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28865#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28864#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28863#L491-33 assume 1 == ~t1_pc~0; 28861#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28860#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28859#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28858#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 28857#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28856#L510-33 assume !(1 == ~t2_pc~0); 28854#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 28853#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28852#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28851#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28850#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28849#L529-33 assume 1 == ~t3_pc~0; 28848#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28846#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28845#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28844#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28843#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28842#L548-33 assume 1 == ~t4_pc~0; 28840#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28839#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28838#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28837#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28836#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28835#L567-33 assume !(1 == ~t5_pc~0); 28833#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 28832#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28831#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28830#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28829#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28828#L586-33 assume 1 == ~t6_pc~0; 28826#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28825#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28824#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28652#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28651#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28650#L605-33 assume !(1 == ~t7_pc~0); 28647#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 28644#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28642#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28640#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28638#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28636#L624-33 assume 1 == ~t8_pc~0; 28633#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28630#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28628#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28626#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 28624#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27015#L643-33 assume 1 == ~t9_pc~0; 27016#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27097#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27575#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27530#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27531#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26883#L1059-3 assume !(1 == ~M_E~0); 26884#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27395#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27454#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27455#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27745#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27644#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27573#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27574#L1094-3 assume !(1 == ~T8_E~0); 27488#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27489#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27767#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27753#L1114-3 assume !(1 == ~E_2~0); 27754#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27990#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27994#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27184#L1134-3 assume !(1 == ~E_6~0); 27185#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27357#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27358#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27536#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27997#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26888#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28161#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 28160#L1459 assume !(0 == start_simulation_~tmp~3#1); 27909#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28045#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28035#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28034#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 28033#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 28032#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28031#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 27828#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 26983#L1440-2 [2023-11-26 10:45:24,966 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:24,967 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2023-11-26 10:45:24,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:24,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461521699] [2023-11-26 10:45:24,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:24,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:24,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:25,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:25,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:25,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1461521699] [2023-11-26 10:45:25,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1461521699] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:25,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:25,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:45:25,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459869469] [2023-11-26 10:45:25,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:25,032 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:25,032 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:25,032 INFO L85 PathProgramCache]: Analyzing trace with hash -627598118, now seen corresponding path program 1 times [2023-11-26 10:45:25,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:25,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027285160] [2023-11-26 10:45:25,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:25,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:25,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:25,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:25,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:25,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027285160] [2023-11-26 10:45:25,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027285160] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:25,091 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:25,091 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:25,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901697281] [2023-11-26 10:45:25,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:25,092 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:25,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:25,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:25,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:25,093 INFO L87 Difference]: Start difference. First operand 2171 states and 3171 transitions. cyclomatic complexity: 1002 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:25,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:25,233 INFO L93 Difference]: Finished difference Result 4157 states and 6014 transitions. [2023-11-26 10:45:25,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4157 states and 6014 transitions. [2023-11-26 10:45:25,262 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4007 [2023-11-26 10:45:25,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4157 states to 4157 states and 6014 transitions. [2023-11-26 10:45:25,296 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4157 [2023-11-26 10:45:25,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4157 [2023-11-26 10:45:25,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4157 states and 6014 transitions. [2023-11-26 10:45:25,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:25,308 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4157 states and 6014 transitions. [2023-11-26 10:45:25,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4157 states and 6014 transitions. [2023-11-26 10:45:25,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4157 to 4019. [2023-11-26 10:45:25,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4019 states, 4019 states have (on average 1.4486190594675292) internal successors, (5822), 4018 states have internal predecessors, (5822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:25,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4019 states to 4019 states and 5822 transitions. [2023-11-26 10:45:25,419 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4019 states and 5822 transitions. [2023-11-26 10:45:25,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:25,420 INFO L428 stractBuchiCegarLoop]: Abstraction has 4019 states and 5822 transitions. [2023-11-26 10:45:25,420 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 10:45:25,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4019 states and 5822 transitions. [2023-11-26 10:45:25,441 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3869 [2023-11-26 10:45:25,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:25,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:25,443 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:25,444 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:25,444 INFO L748 eck$LassoCheckResult]: Stem: 33470#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 33471#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 34329#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34330#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33985#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 33684#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33685#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34289#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34361#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34346#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34347#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33826#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33811#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33812#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33598#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33599#L951 assume !(0 == ~M_E~0); 33328#L951-2 assume !(0 == ~T1_E~0); 33329#L956-1 assume !(0 == ~T2_E~0); 33492#L961-1 assume !(0 == ~T3_E~0); 34004#L966-1 assume !(0 == ~T4_E~0); 34005#L971-1 assume !(0 == ~T5_E~0); 34148#L976-1 assume !(0 == ~T6_E~0); 34120#L981-1 assume !(0 == ~T7_E~0); 33867#L986-1 assume !(0 == ~T8_E~0); 33546#L991-1 assume !(0 == ~T9_E~0); 33547#L996-1 assume !(0 == ~E_M~0); 34402#L1001-1 assume !(0 == ~E_1~0); 34058#L1006-1 assume !(0 == ~E_2~0); 34059#L1011-1 assume !(0 == ~E_3~0); 34362#L1016-1 assume !(0 == ~E_4~0); 34377#L1021-1 assume !(0 == ~E_5~0); 33119#L1026-1 assume !(0 == ~E_6~0); 33120#L1031-1 assume !(0 == ~E_7~0); 34012#L1036-1 assume !(0 == ~E_8~0); 34007#L1041-1 assume !(0 == ~E_9~0); 34008#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34303#L472 assume !(1 == ~m_pc~0); 34247#L472-2 is_master_triggered_~__retres1~0#1 := 0; 34038#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34039#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34048#L1179 assume !(0 != activate_threads_~tmp~1#1); 33127#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33128#L491 assume 1 == ~t1_pc~0; 34057#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33648#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33153#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33100#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 33101#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33121#L510 assume !(1 == ~t2_pc~0); 33089#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33090#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33671#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33672#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33383#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33384#L529 assume 1 == ~t3_pc~0; 33770#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33771#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33098#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33099#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 33303#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33304#L548 assume !(1 == ~t4_pc~0); 33194#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33193#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33267#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33236#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 33237#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33181#L567 assume 1 == ~t5_pc~0; 33182#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33238#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34231#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34232#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 34282#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33314#L586 assume !(1 == ~t6_pc~0); 33315#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33387#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33653#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33654#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 34274#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34275#L605 assume 1 == ~t7_pc~0; 34239#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33847#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34041#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34450#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 34446#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33979#L624 assume !(1 == ~t8_pc~0); 33378#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33377#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34103#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34172#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 34251#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33144#L643 assume 1 == ~t9_pc~0; 33145#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34195#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33733#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33553#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 33554#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33360#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 33361#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36365#L1064-1 assume !(1 == ~T2_E~0); 36364#L1069-1 assume !(1 == ~T3_E~0); 36363#L1074-1 assume !(1 == ~T4_E~0); 34442#L1079-1 assume !(1 == ~T5_E~0); 36362#L1084-1 assume !(1 == ~T6_E~0); 36361#L1089-1 assume !(1 == ~T7_E~0); 36360#L1094-1 assume !(1 == ~T8_E~0); 36359#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36358#L1104-1 assume !(1 == ~E_M~0); 36357#L1109-1 assume !(1 == ~E_1~0); 36356#L1114-1 assume !(1 == ~E_2~0); 36355#L1119-1 assume !(1 == ~E_3~0); 36354#L1124-1 assume !(1 == ~E_4~0); 36353#L1129-1 assume !(1 == ~E_5~0); 36352#L1134-1 assume !(1 == ~E_6~0); 36351#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 36350#L1144-1 assume !(1 == ~E_8~0); 36349#L1149-1 assume !(1 == ~E_9~0); 36348#L1154-1 assume { :end_inline_reset_delta_events } true; 34909#L1440-2 [2023-11-26 10:45:25,445 INFO L750 eck$LassoCheckResult]: Loop: 34909#L1440-2 assume !false; 34910#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34323#L926-1 assume !false; 34324#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34155#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 33457#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33700#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33701#L795 assume !(0 != eval_~tmp~0#1); 36288#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36860#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36859#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36858#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36857#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36856#L961-3 assume !(0 == ~T3_E~0); 36855#L966-3 assume !(0 == ~T4_E~0); 36854#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36853#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36852#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36851#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36850#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36849#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36848#L1001-3 assume !(0 == ~E_1~0); 36847#L1006-3 assume !(0 == ~E_2~0); 36846#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36845#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36844#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36843#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36842#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36841#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36840#L1041-3 assume !(0 == ~E_9~0); 36839#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36838#L472-33 assume !(1 == ~m_pc~0); 36837#L472-35 is_master_triggered_~__retres1~0#1 := 0; 36836#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36835#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36834#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36833#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36832#L491-33 assume 1 == ~t1_pc~0; 36830#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36829#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36828#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36827#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 36826#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36825#L510-33 assume !(1 == ~t2_pc~0); 36823#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 36822#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36821#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36820#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36819#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36818#L529-33 assume !(1 == ~t3_pc~0); 36816#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 36815#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36814#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36813#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36812#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36811#L548-33 assume 1 == ~t4_pc~0; 36809#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36808#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36807#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36806#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36805#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36804#L567-33 assume !(1 == ~t5_pc~0); 36802#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 36801#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36800#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36799#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36798#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36797#L586-33 assume 1 == ~t6_pc~0; 36795#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36794#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36793#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36792#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36791#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36790#L605-33 assume !(1 == ~t7_pc~0); 36788#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 36787#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36786#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36785#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36784#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36783#L624-33 assume 1 == ~t8_pc~0; 36781#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36780#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36779#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36778#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 36777#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36776#L643-33 assume 1 == ~t9_pc~0; 36774#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36773#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36772#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36771#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36770#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36769#L1059-3 assume !(1 == ~M_E~0); 33220#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36768#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36767#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36766#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34121#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36765#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36764#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36763#L1094-3 assume !(1 == ~T8_E~0); 36762#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36761#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36760#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36759#L1114-3 assume !(1 == ~E_2~0); 36758#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36757#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36756#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36755#L1134-3 assume !(1 == ~E_6~0); 36754#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36753#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36752#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36751#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 36749#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 36740#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 36739#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 36738#L1459 assume !(0 == start_simulation_~tmp~3#1); 35012#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 36736#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 36727#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 36726#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 36725#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 36724#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36723#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 36347#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 34909#L1440-2 [2023-11-26 10:45:25,445 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:25,446 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2023-11-26 10:45:25,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:25,446 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716402808] [2023-11-26 10:45:25,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:25,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:25,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:25,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:25,541 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:25,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716402808] [2023-11-26 10:45:25,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716402808] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:25,541 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:25,542 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:45:25,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489122677] [2023-11-26 10:45:25,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:25,542 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:25,543 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:25,543 INFO L85 PathProgramCache]: Analyzing trace with hash -486498597, now seen corresponding path program 1 times [2023-11-26 10:45:25,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:25,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079066818] [2023-11-26 10:45:25,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:25,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:25,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:25,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:25,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:25,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079066818] [2023-11-26 10:45:25,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079066818] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:25,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:25,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:25,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [837022866] [2023-11-26 10:45:25,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:25,601 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:25,601 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:25,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:25,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:25,602 INFO L87 Difference]: Start difference. First operand 4019 states and 5822 transitions. cyclomatic complexity: 1807 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:25,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:25,749 INFO L93 Difference]: Finished difference Result 7561 states and 10882 transitions. [2023-11-26 10:45:25,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7561 states and 10882 transitions. [2023-11-26 10:45:25,802 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7400 [2023-11-26 10:45:25,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7561 states to 7561 states and 10882 transitions. [2023-11-26 10:45:25,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7561 [2023-11-26 10:45:25,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7561 [2023-11-26 10:45:25,865 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7561 states and 10882 transitions. [2023-11-26 10:45:25,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:25,878 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7561 states and 10882 transitions. [2023-11-26 10:45:25,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7561 states and 10882 transitions. [2023-11-26 10:45:26,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7561 to 7553. [2023-11-26 10:45:26,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7553 states, 7553 states have (on average 1.4396928372831987) internal successors, (10874), 7552 states have internal predecessors, (10874), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:26,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7553 states to 7553 states and 10874 transitions. [2023-11-26 10:45:26,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7553 states and 10874 transitions. [2023-11-26 10:45:26,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:26,063 INFO L428 stractBuchiCegarLoop]: Abstraction has 7553 states and 10874 transitions. [2023-11-26 10:45:26,063 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 10:45:26,064 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7553 states and 10874 transitions. [2023-11-26 10:45:26,101 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7392 [2023-11-26 10:45:26,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:26,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:26,103 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:26,104 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:26,104 INFO L748 eck$LassoCheckResult]: Stem: 45051#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 45052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 45865#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45866#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45536#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 45252#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45253#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45840#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45893#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45876#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45877#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45388#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45373#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45374#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45173#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45174#L951 assume !(0 == ~M_E~0); 44912#L951-2 assume !(0 == ~T1_E~0); 44913#L956-1 assume !(0 == ~T2_E~0); 45072#L961-1 assume !(0 == ~T3_E~0); 45560#L966-1 assume !(0 == ~T4_E~0); 45561#L971-1 assume !(0 == ~T5_E~0); 45693#L976-1 assume !(0 == ~T6_E~0); 45667#L981-1 assume !(0 == ~T7_E~0); 45425#L986-1 assume !(0 == ~T8_E~0); 45123#L991-1 assume !(0 == ~T9_E~0); 45124#L996-1 assume !(0 == ~E_M~0); 45929#L1001-1 assume !(0 == ~E_1~0); 45616#L1006-1 assume !(0 == ~E_2~0); 45617#L1011-1 assume !(0 == ~E_3~0); 45894#L1016-1 assume !(0 == ~E_4~0); 45909#L1021-1 assume !(0 == ~E_5~0); 44706#L1026-1 assume !(0 == ~E_6~0); 44707#L1031-1 assume !(0 == ~E_7~0); 45569#L1036-1 assume !(0 == ~E_8~0); 45565#L1041-1 assume !(0 == ~E_9~0); 45566#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45851#L472 assume !(1 == ~m_pc~0); 45797#L472-2 is_master_triggered_~__retres1~0#1 := 0; 45596#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45597#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45605#L1179 assume !(0 != activate_threads_~tmp~1#1); 44714#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44715#L491 assume !(1 == ~t1_pc~0); 45218#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45219#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44740#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44687#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 44688#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44708#L510 assume !(1 == ~t2_pc~0); 44676#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 44677#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45241#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45242#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44967#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44968#L529 assume 1 == ~t3_pc~0; 45333#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45334#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44685#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44686#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 44887#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44888#L548 assume !(1 == ~t4_pc~0); 44781#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44780#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44852#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44821#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 44822#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44768#L567 assume 1 == ~t5_pc~0; 44769#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44823#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45780#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45781#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 45834#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44898#L586 assume !(1 == ~t6_pc~0); 44899#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 44971#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45224#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45225#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 45824#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45825#L605 assume 1 == ~t7_pc~0; 45788#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45408#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45598#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45968#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 45967#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45530#L624 assume !(1 == ~t8_pc~0); 44962#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44961#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45651#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45717#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 45802#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44731#L643 assume 1 == ~t9_pc~0; 44732#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45743#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45295#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45128#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 45129#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44944#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 44945#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45100#L1064-1 assume !(1 == ~T2_E~0); 45101#L1069-1 assume !(1 == ~T3_E~0); 45751#L1074-1 assume !(1 == ~T4_E~0); 45800#L1079-1 assume !(1 == ~T5_E~0); 45786#L1084-1 assume !(1 == ~T6_E~0); 45787#L1089-1 assume !(1 == ~T7_E~0); 45818#L1094-1 assume !(1 == ~T8_E~0); 45464#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45465#L1104-1 assume !(1 == ~E_M~0); 45653#L1109-1 assume !(1 == ~E_1~0); 45654#L1114-1 assume !(1 == ~E_2~0); 48599#L1119-1 assume !(1 == ~E_3~0); 48597#L1124-1 assume !(1 == ~E_4~0); 48596#L1129-1 assume !(1 == ~E_5~0); 48595#L1134-1 assume !(1 == ~E_6~0); 45068#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 45069#L1144-1 assume !(1 == ~E_8~0); 45260#L1149-1 assume !(1 == ~E_9~0); 48565#L1154-1 assume { :end_inline_reset_delta_events } true; 48557#L1440-2 [2023-11-26 10:45:26,105 INFO L750 eck$LassoCheckResult]: Loop: 48557#L1440-2 assume !false; 48551#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48547#L926-1 assume !false; 48546#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 48544#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 48535#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 48534#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48531#L795 assume !(0 != eval_~tmp~0#1); 48532#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51210#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50442#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50432#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50417#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50404#L961-3 assume !(0 == ~T3_E~0); 50403#L966-3 assume !(0 == ~T4_E~0); 50401#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50398#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50396#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50394#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50393#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50392#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50390#L1001-3 assume !(0 == ~E_1~0); 50388#L1006-3 assume !(0 == ~E_2~0); 50385#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50383#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50381#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50379#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50378#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50377#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49790#L1041-3 assume !(0 == ~E_9~0); 49789#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49787#L472-33 assume !(1 == ~m_pc~0); 49785#L472-35 is_master_triggered_~__retres1~0#1 := 0; 49784#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49783#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49638#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49635#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49633#L491-33 assume !(1 == ~t1_pc~0); 49631#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 49629#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49627#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49625#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 49624#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49621#L510-33 assume !(1 == ~t2_pc~0); 49618#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 49616#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49614#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49612#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49610#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49609#L529-33 assume !(1 == ~t3_pc~0); 49607#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 44978#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44861#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44862#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44802#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44803#L548-33 assume 1 == ~t4_pc~0; 45053#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45175#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45623#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45898#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49359#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49358#L567-33 assume !(1 == ~t5_pc~0); 49356#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 49355#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49353#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49351#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49349#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49347#L586-33 assume 1 == ~t6_pc~0; 49344#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49342#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49340#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49338#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49336#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49334#L605-33 assume !(1 == ~t7_pc~0); 49331#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 49329#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49326#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49324#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49322#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49320#L624-33 assume 1 == ~t8_pc~0; 49317#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49315#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49313#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49310#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 49308#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49306#L643-33 assume 1 == ~t9_pc~0; 45562#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45022#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45504#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45460#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45461#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44804#L1059-3 assume !(1 == ~M_E~0); 44805#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45321#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45385#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45386#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45668#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45570#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45502#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45503#L1094-3 assume !(1 == ~T8_E~0); 45417#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45418#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45691#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45677#L1114-3 assume !(1 == ~E_2~0); 45678#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45953#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49248#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49244#L1134-3 assume !(1 == ~E_6~0); 49241#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49238#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49235#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49232#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 48730#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 48719#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 48717#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 48715#L1459 assume !(0 == start_simulation_~tmp~3#1); 48712#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 48691#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 48681#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 48594#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 48593#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 48591#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48573#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 48564#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 48557#L1440-2 [2023-11-26 10:45:26,105 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:26,106 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2023-11-26 10:45:26,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:26,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487276910] [2023-11-26 10:45:26,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:26,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:26,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:26,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:26,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:26,245 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487276910] [2023-11-26 10:45:26,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [487276910] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:26,245 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:26,246 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:45:26,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [656608674] [2023-11-26 10:45:26,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:26,247 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:26,247 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:26,247 INFO L85 PathProgramCache]: Analyzing trace with hash -1971738788, now seen corresponding path program 1 times [2023-11-26 10:45:26,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:26,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [762903321] [2023-11-26 10:45:26,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:26,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:26,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:26,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:26,323 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:26,323 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [762903321] [2023-11-26 10:45:26,323 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [762903321] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:26,324 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:26,324 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:26,324 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495765164] [2023-11-26 10:45:26,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:26,325 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:26,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:26,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:45:26,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:45:26,326 INFO L87 Difference]: Start difference. First operand 7553 states and 10874 transitions. cyclomatic complexity: 3329 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:26,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:26,621 INFO L93 Difference]: Finished difference Result 9055 states and 12955 transitions. [2023-11-26 10:45:26,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9055 states and 12955 transitions. [2023-11-26 10:45:26,672 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8890 [2023-11-26 10:45:26,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9055 states to 9055 states and 12955 transitions. [2023-11-26 10:45:26,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9055 [2023-11-26 10:45:26,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9055 [2023-11-26 10:45:26,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9055 states and 12955 transitions. [2023-11-26 10:45:26,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:26,732 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9055 states and 12955 transitions. [2023-11-26 10:45:26,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9055 states and 12955 transitions. [2023-11-26 10:45:26,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9055 to 7565. [2023-11-26 10:45:26,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7565 states, 7565 states have (on average 1.4282881692002645) internal successors, (10805), 7564 states have internal predecessors, (10805), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:26,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7565 states to 7565 states and 10805 transitions. [2023-11-26 10:45:26,891 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7565 states and 10805 transitions. [2023-11-26 10:45:26,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 10:45:26,892 INFO L428 stractBuchiCegarLoop]: Abstraction has 7565 states and 10805 transitions. [2023-11-26 10:45:26,892 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 10:45:26,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7565 states and 10805 transitions. [2023-11-26 10:45:26,923 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7404 [2023-11-26 10:45:26,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:26,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:26,926 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:26,926 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:26,927 INFO L748 eck$LassoCheckResult]: Stem: 61674#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 61675#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 62654#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62655#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62226#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 61891#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61892#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62614#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62692#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62676#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62677#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62043#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 62028#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62029#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 61804#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61805#L951 assume !(0 == ~M_E~0); 61535#L951-2 assume !(0 == ~T1_E~0); 61536#L956-1 assume !(0 == ~T2_E~0); 61695#L961-1 assume !(0 == ~T3_E~0); 62253#L966-1 assume !(0 == ~T4_E~0); 62254#L971-1 assume !(0 == ~T5_E~0); 62419#L976-1 assume !(0 == ~T6_E~0); 62387#L981-1 assume !(0 == ~T7_E~0); 62089#L986-1 assume !(0 == ~T8_E~0); 61748#L991-1 assume !(0 == ~T9_E~0); 61749#L996-1 assume !(0 == ~E_M~0); 62748#L1001-1 assume !(0 == ~E_1~0); 62328#L1006-1 assume !(0 == ~E_2~0); 62329#L1011-1 assume !(0 == ~E_3~0); 62693#L1016-1 assume !(0 == ~E_4~0); 62712#L1021-1 assume !(0 == ~E_5~0); 61327#L1026-1 assume !(0 == ~E_6~0); 61328#L1031-1 assume !(0 == ~E_7~0); 62263#L1036-1 assume !(0 == ~E_8~0); 62259#L1041-1 assume !(0 == ~E_9~0); 62260#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62625#L472 assume !(1 == ~m_pc~0); 62561#L472-2 is_master_triggered_~__retres1~0#1 := 0; 62305#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62306#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62317#L1179 assume !(0 != activate_threads_~tmp~1#1); 61335#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61336#L491 assume !(1 == ~t1_pc~0); 61856#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61857#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61361#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61308#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 61309#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61329#L510 assume !(1 == ~t2_pc~0); 61297#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61298#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61880#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61881#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 61591#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61592#L529 assume 1 == ~t3_pc~0; 61984#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 61985#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61306#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61307#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 61510#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61511#L548 assume !(1 == ~t4_pc~0); 61402#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61401#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61476#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61443#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 61444#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61389#L567 assume 1 == ~t5_pc~0; 61390#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 61445#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62539#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62540#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 62605#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61521#L586 assume !(1 == ~t6_pc~0); 61522#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 61595#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61862#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61863#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 62598#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62599#L605 assume 1 == ~t7_pc~0; 62547#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62063#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62307#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62822#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 62817#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62217#L624 assume !(1 == ~t8_pc~0); 61586#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 61585#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62369#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62445#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 62567#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61352#L643 assume 1 == ~t9_pc~0; 61353#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62487#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61939#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 61754#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 61755#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61567#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 61568#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61726#L1064-1 assume !(1 == ~T2_E~0); 61727#L1069-1 assume !(1 == ~T3_E~0); 62500#L1074-1 assume !(1 == ~T4_E~0); 62563#L1079-1 assume !(1 == ~T5_E~0); 62545#L1084-1 assume !(1 == ~T6_E~0); 62546#L1089-1 assume !(1 == ~T7_E~0); 62593#L1094-1 assume !(1 == ~T8_E~0); 62127#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62128#L1104-1 assume !(1 == ~E_M~0); 62371#L1109-1 assume !(1 == ~E_1~0); 61882#L1114-1 assume !(1 == ~E_2~0); 61883#L1119-1 assume !(1 == ~E_3~0); 64862#L1124-1 assume !(1 == ~E_4~0); 64860#L1129-1 assume !(1 == ~E_5~0); 62233#L1134-1 assume !(1 == ~E_6~0); 61691#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 61692#L1144-1 assume !(1 == ~E_8~0); 61902#L1149-1 assume !(1 == ~E_9~0); 61527#L1154-1 assume { :end_inline_reset_delta_events } true; 61528#L1440-2 [2023-11-26 10:45:26,927 INFO L750 eck$LassoCheckResult]: Loop: 61528#L1440-2 assume !false; 65574#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65569#L926-1 assume !false; 65560#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65527#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 65517#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 65515#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65512#L795 assume !(0 != eval_~tmp~0#1); 65513#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68329#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68328#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 68327#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68326#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68325#L961-3 assume !(0 == ~T3_E~0); 68324#L966-3 assume !(0 == ~T4_E~0); 68323#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68322#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68321#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61772#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 61350#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 61351#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62415#L1001-3 assume !(0 == ~E_1~0); 61900#L1006-3 assume !(0 == ~E_2~0); 61901#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62443#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62515#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62146#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62147#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62407#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62408#L1041-3 assume !(0 == ~E_9~0); 62495#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62430#L472-33 assume !(1 == ~m_pc~0); 61468#L472-35 is_master_triggered_~__retres1~0#1 := 0; 61469#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62474#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62438#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61944#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61945#L491-33 assume !(1 == ~t1_pc~0); 61409#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 61410#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62729#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62764#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 62765#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62374#L510-33 assume !(1 == ~t2_pc~0); 62372#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 62373#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62421#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62422#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 61292#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61293#L529-33 assume 1 == ~t3_pc~0; 61317#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 61319#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61485#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61486#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61423#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61424#L548-33 assume 1 == ~t4_pc~0; 61676#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61806#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62337#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61849#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61611#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61612#L567-33 assume !(1 == ~t5_pc~0); 61721#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 61722#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61996#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62773#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62787#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62840#L586-33 assume !(1 == ~t6_pc~0); 66555#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 66552#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66550#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66547#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66545#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66543#L605-33 assume 1 == ~t7_pc~0; 66541#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66538#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66536#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66534#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66531#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66529#L624-33 assume !(1 == ~t8_pc~0); 66527#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 66524#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66522#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66520#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 66516#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66512#L643-33 assume !(1 == ~t9_pc~0); 66509#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 66505#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66502#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66499#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66495#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66491#L1059-3 assume !(1 == ~M_E~0); 61427#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66478#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66472#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66465#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62388#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66450#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66443#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 66436#L1094-3 assume !(1 == ~T8_E~0); 66429#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 66423#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66416#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66408#L1114-3 assume !(1 == ~E_2~0); 66401#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62863#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62811#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61733#L1134-3 assume !(1 == ~E_6~0); 61734#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 61926#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61927#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 62129#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 62827#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 61431#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 61828#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 61314#L1459 assume !(0 == start_simulation_~tmp~3#1); 61315#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65597#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 65587#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 65585#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 65583#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 65581#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65579#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 65577#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 61528#L1440-2 [2023-11-26 10:45:26,928 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:26,928 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2023-11-26 10:45:26,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:26,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932398044] [2023-11-26 10:45:26,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:26,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:26,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:26,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:26,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:26,998 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932398044] [2023-11-26 10:45:26,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932398044] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:26,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:26,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:45:26,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1358319921] [2023-11-26 10:45:26,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:27,000 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:27,000 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:27,000 INFO L85 PathProgramCache]: Analyzing trace with hash -1575070241, now seen corresponding path program 1 times [2023-11-26 10:45:27,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:27,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999643356] [2023-11-26 10:45:27,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:27,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:27,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:27,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:27,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:27,094 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999643356] [2023-11-26 10:45:27,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999643356] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:27,094 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:27,094 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:27,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089356838] [2023-11-26 10:45:27,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:27,095 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:27,096 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:27,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:27,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:27,097 INFO L87 Difference]: Start difference. First operand 7565 states and 10805 transitions. cyclomatic complexity: 3248 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:27,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:27,269 INFO L93 Difference]: Finished difference Result 14324 states and 20346 transitions. [2023-11-26 10:45:27,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14324 states and 20346 transitions. [2023-11-26 10:45:27,344 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14140 [2023-11-26 10:45:27,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14324 states to 14324 states and 20346 transitions. [2023-11-26 10:45:27,402 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14324 [2023-11-26 10:45:27,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14324 [2023-11-26 10:45:27,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14324 states and 20346 transitions. [2023-11-26 10:45:27,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:27,437 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14324 states and 20346 transitions. [2023-11-26 10:45:27,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14324 states and 20346 transitions. [2023-11-26 10:45:27,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14324 to 14308. [2023-11-26 10:45:27,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14308 states, 14308 states have (on average 1.4208834218618955) internal successors, (20330), 14307 states have internal predecessors, (20330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:27,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14308 states to 14308 states and 20330 transitions. [2023-11-26 10:45:27,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14308 states and 20330 transitions. [2023-11-26 10:45:27,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:27,882 INFO L428 stractBuchiCegarLoop]: Abstraction has 14308 states and 20330 transitions. [2023-11-26 10:45:27,882 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 10:45:27,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14308 states and 20330 transitions. [2023-11-26 10:45:28,048 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14124 [2023-11-26 10:45:28,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:28,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:28,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:28,050 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:28,051 INFO L748 eck$LassoCheckResult]: Stem: 83566#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 83567#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 84374#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84375#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84067#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 83778#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83779#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84351#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84399#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84386#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84387#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83912#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83896#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 83897#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 83693#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 83694#L951 assume !(0 == ~M_E~0); 83428#L951-2 assume !(0 == ~T1_E~0); 83429#L956-1 assume !(0 == ~T2_E~0); 83589#L961-1 assume !(0 == ~T3_E~0); 84087#L966-1 assume !(0 == ~T4_E~0); 84088#L971-1 assume !(0 == ~T5_E~0); 84213#L976-1 assume !(0 == ~T6_E~0); 84188#L981-1 assume !(0 == ~T7_E~0); 83949#L986-1 assume !(0 == ~T8_E~0); 83640#L991-1 assume !(0 == ~T9_E~0); 83641#L996-1 assume !(0 == ~E_M~0); 84432#L1001-1 assume !(0 == ~E_1~0); 84140#L1006-1 assume !(0 == ~E_2~0); 84141#L1011-1 assume !(0 == ~E_3~0); 84400#L1016-1 assume !(0 == ~E_4~0); 84412#L1021-1 assume !(0 == ~E_5~0); 83223#L1026-1 assume !(0 == ~E_6~0); 83224#L1031-1 assume !(0 == ~E_7~0); 84096#L1036-1 assume !(0 == ~E_8~0); 84092#L1041-1 assume !(0 == ~E_9~0); 84093#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84360#L472 assume !(1 == ~m_pc~0); 84312#L472-2 is_master_triggered_~__retres1~0#1 := 0; 84120#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84121#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 84129#L1179 assume !(0 != activate_threads_~tmp~1#1); 83231#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83232#L491 assume !(1 == ~t1_pc~0); 83742#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83743#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83257#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 83204#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 83205#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83225#L510 assume !(1 == ~t2_pc~0); 83193#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83194#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83765#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 83766#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 83483#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83484#L529 assume !(1 == ~t3_pc~0); 83958#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84241#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83202#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83203#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 83403#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83404#L548 assume !(1 == ~t4_pc~0); 83298#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 83297#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83368#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 83338#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 83339#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83285#L567 assume 1 == ~t5_pc~0; 83286#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83340#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84294#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84295#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 84346#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83414#L586 assume !(1 == ~t6_pc~0); 83415#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 83487#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83748#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83749#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 84337#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84338#L605 assume 1 == ~t7_pc~0; 84302#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83932#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84122#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 84471#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 84470#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84059#L624 assume !(1 == ~t8_pc~0); 83478#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 83477#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84173#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84237#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 84317#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83248#L643 assume 1 == ~t9_pc~0; 83249#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84263#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83820#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 83645#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 83646#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83460#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 83461#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 90063#L1064-1 assume !(1 == ~T2_E~0); 90062#L1069-1 assume !(1 == ~T3_E~0); 90061#L1074-1 assume !(1 == ~T4_E~0); 84469#L1079-1 assume !(1 == ~T5_E~0); 90060#L1084-1 assume !(1 == ~T6_E~0); 90059#L1089-1 assume !(1 == ~T7_E~0); 90058#L1094-1 assume !(1 == ~T8_E~0); 90057#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 84407#L1104-1 assume !(1 == ~E_M~0); 84175#L1109-1 assume !(1 == ~E_1~0); 83767#L1114-1 assume !(1 == ~E_2~0); 83768#L1119-1 assume !(1 == ~E_3~0); 83832#L1124-1 assume !(1 == ~E_4~0); 83244#L1129-1 assume !(1 == ~E_5~0); 83245#L1134-1 assume !(1 == ~E_6~0); 90022#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 90020#L1144-1 assume !(1 == ~E_8~0); 84480#L1149-1 assume !(1 == ~E_9~0); 84481#L1154-1 assume { :end_inline_reset_delta_events } true; 89897#L1440-2 [2023-11-26 10:45:28,051 INFO L750 eck$LassoCheckResult]: Loop: 89897#L1440-2 assume !false; 89889#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89822#L926-1 assume !false; 89821#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 86467#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 86459#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 86448#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 86449#L795 assume !(0 != eval_~tmp~0#1); 89695#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90932#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 90929#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 90927#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 90925#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 90923#L961-3 assume !(0 == ~T3_E~0); 90921#L966-3 assume !(0 == ~T4_E~0); 90917#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 90915#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 90913#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 90912#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 90910#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 90909#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 90908#L1001-3 assume !(0 == ~E_1~0); 90907#L1006-3 assume !(0 == ~E_2~0); 90906#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 90905#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 90904#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 90903#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 90901#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 90899#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 90897#L1041-3 assume !(0 == ~E_9~0); 90895#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90893#L472-33 assume !(1 == ~m_pc~0); 90891#L472-35 is_master_triggered_~__retres1~0#1 := 0; 90889#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90887#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 90885#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 90883#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 90881#L491-33 assume !(1 == ~t1_pc~0); 90879#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 90878#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90875#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 90873#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 90871#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90869#L510-33 assume !(1 == ~t2_pc~0); 90866#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 90864#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90862#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 90860#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 90858#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 90856#L529-33 assume !(1 == ~t3_pc~0); 90854#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 90852#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90850#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 90847#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 90845#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 90843#L548-33 assume !(1 == ~t4_pc~0); 90755#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 90752#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 90750#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 90748#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 90745#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90743#L567-33 assume 1 == ~t5_pc~0; 90741#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 90738#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 90736#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90734#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 90731#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90729#L586-33 assume !(1 == ~t6_pc~0); 90727#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 90724#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 90722#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 90720#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 90717#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90715#L605-33 assume 1 == ~t7_pc~0; 90713#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 90701#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 90691#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 90688#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 90675#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 90672#L624-33 assume 1 == ~t8_pc~0; 90669#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 90667#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 90665#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 90663#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 90661#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 90658#L643-33 assume !(1 == ~t9_pc~0); 90656#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 90653#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 90651#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 90649#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 90647#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90644#L1059-3 assume !(1 == ~M_E~0); 90599#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 90641#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90639#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90637#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90565#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 90634#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 90632#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 90630#L1094-3 assume !(1 == ~T8_E~0); 90628#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 90626#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 90624#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 90622#L1114-3 assume !(1 == ~E_2~0); 90620#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 90618#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 90616#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 90614#L1134-3 assume !(1 == ~E_6~0); 90612#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 90592#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 90588#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 90584#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 90561#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 90549#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 90545#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 90541#L1459 assume !(0 == start_simulation_~tmp~3#1); 90537#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 90015#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 90005#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 90003#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 90001#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 89999#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89997#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 89912#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 89897#L1440-2 [2023-11-26 10:45:28,052 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:28,052 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2023-11-26 10:45:28,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:28,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466442746] [2023-11-26 10:45:28,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:28,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:28,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:28,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:28,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:28,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466442746] [2023-11-26 10:45:28,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [466442746] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:28,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:28,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:45:28,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053332947] [2023-11-26 10:45:28,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:28,126 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:28,126 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:28,127 INFO L85 PathProgramCache]: Analyzing trace with hash 207199, now seen corresponding path program 1 times [2023-11-26 10:45:28,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:28,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222069208] [2023-11-26 10:45:28,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:28,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:28,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:28,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:28,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:28,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222069208] [2023-11-26 10:45:28,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [222069208] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:28,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:28,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:28,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760591196] [2023-11-26 10:45:28,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:28,189 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:28,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:28,189 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:28,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:28,190 INFO L87 Difference]: Start difference. First operand 14308 states and 20330 transitions. cyclomatic complexity: 6038 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:28,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:28,490 INFO L93 Difference]: Finished difference Result 27183 states and 38443 transitions. [2023-11-26 10:45:28,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27183 states and 38443 transitions. [2023-11-26 10:45:28,656 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26928 [2023-11-26 10:45:28,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27183 states to 27183 states and 38443 transitions. [2023-11-26 10:45:28,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27183 [2023-11-26 10:45:28,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27183 [2023-11-26 10:45:28,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27183 states and 38443 transitions. [2023-11-26 10:45:28,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:28,846 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27183 states and 38443 transitions. [2023-11-26 10:45:28,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27183 states and 38443 transitions. [2023-11-26 10:45:29,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27183 to 27151. [2023-11-26 10:45:29,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27151 states, 27151 states have (on average 1.414717689956171) internal successors, (38411), 27150 states have internal predecessors, (38411), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:29,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27151 states to 27151 states and 38411 transitions. [2023-11-26 10:45:29,568 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27151 states and 38411 transitions. [2023-11-26 10:45:29,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:29,569 INFO L428 stractBuchiCegarLoop]: Abstraction has 27151 states and 38411 transitions. [2023-11-26 10:45:29,569 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 10:45:29,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27151 states and 38411 transitions. [2023-11-26 10:45:29,661 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26896 [2023-11-26 10:45:29,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:29,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:29,663 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:29,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:29,664 INFO L748 eck$LassoCheckResult]: Stem: 125065#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 125066#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 125888#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 125889#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125561#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 125272#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 125273#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125863#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125910#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 125897#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 125898#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 125406#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 125392#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 125393#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 125191#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 125192#L951 assume !(0 == ~M_E~0); 124926#L951-2 assume !(0 == ~T1_E~0); 124927#L956-1 assume !(0 == ~T2_E~0); 125088#L961-1 assume !(0 == ~T3_E~0); 125580#L966-1 assume !(0 == ~T4_E~0); 125581#L971-1 assume !(0 == ~T5_E~0); 125706#L976-1 assume !(0 == ~T6_E~0); 125679#L981-1 assume !(0 == ~T7_E~0); 125444#L986-1 assume !(0 == ~T8_E~0); 125139#L991-1 assume !(0 == ~T9_E~0); 125140#L996-1 assume !(0 == ~E_M~0); 125939#L1001-1 assume !(0 == ~E_1~0); 125630#L1006-1 assume !(0 == ~E_2~0); 125631#L1011-1 assume !(0 == ~E_3~0); 125911#L1016-1 assume !(0 == ~E_4~0); 125923#L1021-1 assume !(0 == ~E_5~0); 124721#L1026-1 assume !(0 == ~E_6~0); 124722#L1031-1 assume !(0 == ~E_7~0); 125587#L1036-1 assume !(0 == ~E_8~0); 125583#L1041-1 assume !(0 == ~E_9~0); 125584#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 125872#L472 assume !(1 == ~m_pc~0); 125824#L472-2 is_master_triggered_~__retres1~0#1 := 0; 125612#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 125613#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 125621#L1179 assume !(0 != activate_threads_~tmp~1#1); 124729#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124730#L491 assume !(1 == ~t1_pc~0); 125236#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 125237#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 124755#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124702#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 124703#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124723#L510 assume !(1 == ~t2_pc~0); 124691#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124692#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 125259#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 125260#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 124981#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124982#L529 assume !(1 == ~t3_pc~0); 125453#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 125740#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124700#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124701#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 124901#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124902#L548 assume !(1 == ~t4_pc~0); 124795#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 124794#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124866#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 124835#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 124836#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124783#L567 assume !(1 == ~t5_pc~0); 124784#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 124837#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 125808#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 125809#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 125857#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124912#L586 assume !(1 == ~t6_pc~0); 124913#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 124985#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125242#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 125243#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 125848#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 125849#L605 assume 1 == ~t7_pc~0; 125816#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125426#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125614#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 125975#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 125973#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 125554#L624 assume !(1 == ~t8_pc~0); 124976#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 124975#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 125664#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 125736#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 125829#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124746#L643 assume 1 == ~t9_pc~0; 124747#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 125766#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125317#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125144#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 125145#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124958#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 124959#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 129697#L1064-1 assume !(1 == ~T2_E~0); 129696#L1069-1 assume !(1 == ~T3_E~0); 129695#L1074-1 assume !(1 == ~T4_E~0); 125972#L1079-1 assume !(1 == ~T5_E~0); 129694#L1084-1 assume !(1 == ~T6_E~0); 129693#L1089-1 assume !(1 == ~T7_E~0); 129692#L1094-1 assume !(1 == ~T8_E~0); 129691#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 129690#L1104-1 assume !(1 == ~E_M~0); 129689#L1109-1 assume !(1 == ~E_1~0); 129688#L1114-1 assume !(1 == ~E_2~0); 129687#L1119-1 assume !(1 == ~E_3~0); 129686#L1124-1 assume !(1 == ~E_4~0); 129685#L1129-1 assume !(1 == ~E_5~0); 129684#L1134-1 assume !(1 == ~E_6~0); 129683#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 129682#L1144-1 assume !(1 == ~E_8~0); 129681#L1149-1 assume !(1 == ~E_9~0); 129678#L1154-1 assume { :end_inline_reset_delta_events } true; 129673#L1440-2 [2023-11-26 10:45:29,665 INFO L750 eck$LassoCheckResult]: Loop: 129673#L1440-2 assume !false; 129672#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129668#L926-1 assume !false; 129667#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 129665#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 129656#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 129655#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 129653#L795 assume !(0 != eval_~tmp~0#1); 129654#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 142328#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 142325#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 142321#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 141986#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 141983#L961-3 assume !(0 == ~T3_E~0); 141981#L966-3 assume !(0 == ~T4_E~0); 141979#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 141977#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 141975#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 141973#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 141970#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 141968#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 141966#L1001-3 assume !(0 == ~E_1~0); 141964#L1006-3 assume !(0 == ~E_2~0); 141962#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 141960#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 141957#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 141955#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 141953#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 141951#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 141949#L1041-3 assume !(0 == ~E_9~0); 141948#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 141944#L472-33 assume !(1 == ~m_pc~0); 141942#L472-35 is_master_triggered_~__retres1~0#1 := 0; 141940#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141939#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 141936#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 141935#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 141934#L491-33 assume !(1 == ~t1_pc~0); 141932#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 141930#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 141928#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 141926#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 141924#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 141889#L510-33 assume !(1 == ~t2_pc~0); 141881#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 141875#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 141384#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 141383#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 141382#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 141371#L529-33 assume !(1 == ~t3_pc~0); 141369#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 141367#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 141364#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 141362#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 141360#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141358#L548-33 assume 1 == ~t4_pc~0; 141355#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 141353#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 141350#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 141348#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 141346#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 141344#L567-33 assume !(1 == ~t5_pc~0); 141342#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 141340#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 141339#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 141306#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 141302#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 141298#L586-33 assume 1 == ~t6_pc~0; 141292#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 141285#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 141279#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 141274#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 141268#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 141263#L605-33 assume 1 == ~t7_pc~0; 141258#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 141250#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 141244#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 141239#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 141233#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 141228#L624-33 assume 1 == ~t8_pc~0; 139639#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 137798#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 137797#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 137796#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 137795#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 137794#L643-33 assume !(1 == ~t9_pc~0); 137792#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 137789#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 137787#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 137785#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 137783#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137781#L1059-3 assume !(1 == ~M_E~0); 135554#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 137778#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 137776#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 137774#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 135543#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 137771#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 137768#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 137766#L1094-3 assume !(1 == ~T8_E~0); 137764#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 137762#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 137760#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 137758#L1114-3 assume !(1 == ~E_2~0); 137756#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 137754#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 137752#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 137750#L1134-3 assume !(1 == ~E_6~0); 137748#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 137746#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 137744#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 134714#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 129737#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 129727#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 129725#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 129723#L1459 assume !(0 == start_simulation_~tmp~3#1); 129721#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 129718#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 129708#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 129706#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 129705#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 129704#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129700#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 129677#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 129673#L1440-2 [2023-11-26 10:45:29,665 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:29,666 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2023-11-26 10:45:29,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:29,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968531819] [2023-11-26 10:45:29,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:29,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:29,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:29,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:29,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:29,841 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1968531819] [2023-11-26 10:45:29,841 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1968531819] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:29,841 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:29,841 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:29,842 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1943282458] [2023-11-26 10:45:29,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:29,842 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:29,843 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:29,843 INFO L85 PathProgramCache]: Analyzing trace with hash -800760354, now seen corresponding path program 1 times [2023-11-26 10:45:29,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:29,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440016392] [2023-11-26 10:45:29,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:29,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:29,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:29,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:29,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:29,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440016392] [2023-11-26 10:45:29,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440016392] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:29,900 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:29,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:29,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [210339653] [2023-11-26 10:45:29,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:29,901 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:29,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:29,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:45:29,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:45:29,902 INFO L87 Difference]: Start difference. First operand 27151 states and 38411 transitions. cyclomatic complexity: 11292 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:30,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:30,610 INFO L93 Difference]: Finished difference Result 63866 states and 89780 transitions. [2023-11-26 10:45:30,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63866 states and 89780 transitions. [2023-11-26 10:45:31,137 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 63340 [2023-11-26 10:45:31,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63866 states to 63866 states and 89780 transitions. [2023-11-26 10:45:31,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63866 [2023-11-26 10:45:31,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63866 [2023-11-26 10:45:31,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63866 states and 89780 transitions. [2023-11-26 10:45:31,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:31,597 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63866 states and 89780 transitions. [2023-11-26 10:45:31,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63866 states and 89780 transitions. [2023-11-26 10:45:32,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63866 to 51550. [2023-11-26 10:45:32,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51550 states, 51550 states have (on average 1.4092725509214354) internal successors, (72648), 51549 states have internal predecessors, (72648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:32,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51550 states to 51550 states and 72648 transitions. [2023-11-26 10:45:32,732 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51550 states and 72648 transitions. [2023-11-26 10:45:32,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:45:32,733 INFO L428 stractBuchiCegarLoop]: Abstraction has 51550 states and 72648 transitions. [2023-11-26 10:45:32,734 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 10:45:32,734 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51550 states and 72648 transitions. [2023-11-26 10:45:33,169 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 51184 [2023-11-26 10:45:33,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:33,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:33,172 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:33,172 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:33,173 INFO L748 eck$LassoCheckResult]: Stem: 216091#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 216092#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 216938#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 216939#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 216597#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 216296#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 216297#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 216905#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 216970#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 216955#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 216956#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 216433#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 216419#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 216420#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 216215#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 216216#L951 assume !(0 == ~M_E~0); 215951#L951-2 assume !(0 == ~T1_E~0); 215952#L956-1 assume !(0 == ~T2_E~0); 216114#L961-1 assume !(0 == ~T3_E~0); 216620#L966-1 assume !(0 == ~T4_E~0); 216621#L971-1 assume !(0 == ~T5_E~0); 216757#L976-1 assume !(0 == ~T6_E~0); 216731#L981-1 assume !(0 == ~T7_E~0); 216471#L986-1 assume !(0 == ~T8_E~0); 216167#L991-1 assume !(0 == ~T9_E~0); 216168#L996-1 assume !(0 == ~E_M~0); 217003#L1001-1 assume !(0 == ~E_1~0); 216674#L1006-1 assume !(0 == ~E_2~0); 216675#L1011-1 assume !(0 == ~E_3~0); 216971#L1016-1 assume !(0 == ~E_4~0); 216987#L1021-1 assume !(0 == ~E_5~0); 215748#L1026-1 assume !(0 == ~E_6~0); 215749#L1031-1 assume !(0 == ~E_7~0); 216627#L1036-1 assume !(0 == ~E_8~0); 216623#L1041-1 assume !(0 == ~E_9~0); 216624#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216916#L472 assume !(1 == ~m_pc~0); 216862#L472-2 is_master_triggered_~__retres1~0#1 := 0; 216655#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216656#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 216664#L1179 assume !(0 != activate_threads_~tmp~1#1); 215756#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215757#L491 assume !(1 == ~t1_pc~0); 216260#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 216261#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215781#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 215729#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 215730#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 215750#L510 assume !(1 == ~t2_pc~0); 215718#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 215719#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216284#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 216285#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 216007#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216008#L529 assume !(1 == ~t3_pc~0); 216480#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 216782#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 215727#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 215728#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 215926#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 215927#L548 assume !(1 == ~t4_pc~0); 215820#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 215819#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 215891#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 215859#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 215860#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215808#L567 assume !(1 == ~t5_pc~0); 215809#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 215861#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 216849#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 216897#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215937#L586 assume !(1 == ~t6_pc~0); 215938#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 216011#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 216266#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 216267#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 216891#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 216892#L605 assume !(1 == ~t7_pc~0); 216451#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 216452#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 216657#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 217048#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 217047#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 216589#L624 assume !(1 == ~t8_pc~0); 216002#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 216001#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 216715#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 216778#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 216868#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 215772#L643 assume 1 == ~t9_pc~0; 215773#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 216805#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 216342#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 216172#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 216173#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 215983#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 215984#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 217065#L1064-1 assume !(1 == ~T2_E~0); 216814#L1069-1 assume !(1 == ~T3_E~0); 216815#L1074-1 assume !(1 == ~T4_E~0); 216865#L1079-1 assume !(1 == ~T5_E~0); 216866#L1084-1 assume !(1 == ~T6_E~0); 216974#L1089-1 assume !(1 == ~T7_E~0); 216975#L1094-1 assume !(1 == ~T8_E~0); 216512#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 216513#L1104-1 assume !(1 == ~E_M~0); 216717#L1109-1 assume !(1 == ~E_1~0); 216718#L1114-1 assume !(1 == ~E_2~0); 217051#L1119-1 assume !(1 == ~E_3~0); 217052#L1124-1 assume !(1 == ~E_4~0); 215768#L1129-1 assume !(1 == ~E_5~0); 215769#L1134-1 assume !(1 == ~E_6~0); 216110#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 216111#L1144-1 assume !(1 == ~E_8~0); 217063#L1149-1 assume !(1 == ~E_9~0); 217064#L1154-1 assume { :end_inline_reset_delta_events } true; 253734#L1440-2 [2023-11-26 10:45:33,173 INFO L750 eck$LassoCheckResult]: Loop: 253734#L1440-2 assume !false; 253732#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 253727#L926-1 assume !false; 253725#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 253717#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 253707#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 253705#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 253703#L795 assume !(0 != eval_~tmp~0#1); 253704#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 264281#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 264279#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 264277#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 264275#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 264273#L961-3 assume !(0 == ~T3_E~0); 264236#L966-3 assume !(0 == ~T4_E~0); 264235#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 264234#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 264233#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 264232#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 264231#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 264229#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 264228#L1001-3 assume !(0 == ~E_1~0); 264227#L1006-3 assume !(0 == ~E_2~0); 264226#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 264225#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 264224#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 264223#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 264222#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 264221#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 264220#L1041-3 assume !(0 == ~E_9~0); 264219#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264218#L472-33 assume !(1 == ~m_pc~0); 264217#L472-35 is_master_triggered_~__retres1~0#1 := 0; 264216#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264215#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 264213#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 264210#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264208#L491-33 assume !(1 == ~t1_pc~0); 264206#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 264204#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264202#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 264200#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 264197#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264195#L510-33 assume !(1 == ~t2_pc~0); 264192#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 264190#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264188#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 264187#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 264184#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 264182#L529-33 assume !(1 == ~t3_pc~0); 264180#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 264178#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 264176#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 264174#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 264172#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 264170#L548-33 assume 1 == ~t4_pc~0; 264167#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 264165#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 264163#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 264161#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 264159#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 264156#L567-33 assume !(1 == ~t5_pc~0); 264154#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 264152#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264150#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 264148#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 264146#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 264143#L586-33 assume 1 == ~t6_pc~0; 264140#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 264138#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264136#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 264134#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 264132#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 264129#L605-33 assume !(1 == ~t7_pc~0); 226754#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 264126#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 264124#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 264122#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 264120#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 264119#L624-33 assume 1 == ~t8_pc~0; 264116#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 264114#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 264112#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 264110#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 264108#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 264105#L643-33 assume 1 == ~t9_pc~0; 264102#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 264100#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 264098#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 264096#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 264094#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264091#L1059-3 assume !(1 == ~M_E~0); 255611#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 264088#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 264086#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 264084#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 255601#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 264083#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 264079#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 264077#L1094-3 assume !(1 == ~T8_E~0); 264075#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 264074#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 264071#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 264070#L1114-3 assume !(1 == ~E_2~0); 264069#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 264067#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 264066#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 264065#L1134-3 assume !(1 == ~E_6~0); 264064#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 264063#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 264062#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 264061#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 263945#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 263935#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 263933#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 263932#L1459 assume !(0 == start_simulation_~tmp~3#1); 216923#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 253756#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 253746#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 253744#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 253742#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 253740#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 253738#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 253737#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 253734#L1440-2 [2023-11-26 10:45:33,174 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:33,174 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2023-11-26 10:45:33,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:33,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212860249] [2023-11-26 10:45:33,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:33,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:33,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:33,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:33,243 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:33,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212860249] [2023-11-26 10:45:33,244 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212860249] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:33,244 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:33,244 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:45:33,244 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [482007149] [2023-11-26 10:45:33,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:33,245 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:33,245 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:33,245 INFO L85 PathProgramCache]: Analyzing trace with hash -1944673186, now seen corresponding path program 1 times [2023-11-26 10:45:33,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:33,246 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428223197] [2023-11-26 10:45:33,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:33,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:33,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:33,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:33,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:33,298 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428223197] [2023-11-26 10:45:33,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [428223197] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:33,299 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:33,299 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:33,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303234010] [2023-11-26 10:45:33,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:33,299 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:33,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:33,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:33,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:33,300 INFO L87 Difference]: Start difference. First operand 51550 states and 72648 transitions. cyclomatic complexity: 21130 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:34,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:34,026 INFO L93 Difference]: Finished difference Result 97933 states and 137493 transitions. [2023-11-26 10:45:34,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97933 states and 137493 transitions. [2023-11-26 10:45:34,676 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 97216 [2023-11-26 10:45:35,318 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97933 states to 97933 states and 137493 transitions. [2023-11-26 10:45:35,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97933 [2023-11-26 10:45:35,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97933 [2023-11-26 10:45:35,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97933 states and 137493 transitions. [2023-11-26 10:45:35,598 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:35,598 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97933 states and 137493 transitions. [2023-11-26 10:45:35,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97933 states and 137493 transitions. [2023-11-26 10:45:36,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97933 to 97805. [2023-11-26 10:45:37,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97805 states, 97805 states have (on average 1.404478298655488) internal successors, (137365), 97804 states have internal predecessors, (137365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:37,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97805 states to 97805 states and 137365 transitions. [2023-11-26 10:45:37,376 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97805 states and 137365 transitions. [2023-11-26 10:45:37,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:37,377 INFO L428 stractBuchiCegarLoop]: Abstraction has 97805 states and 137365 transitions. [2023-11-26 10:45:37,377 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 10:45:37,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97805 states and 137365 transitions. [2023-11-26 10:45:37,663 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 97088 [2023-11-26 10:45:37,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:37,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:37,665 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:37,665 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:37,666 INFO L748 eck$LassoCheckResult]: Stem: 365578#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 365579#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 366449#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 366450#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 366086#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 365785#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 365786#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 366414#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 366480#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 366463#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 366464#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 365927#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 365910#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 365911#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 365703#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 365704#L951 assume !(0 == ~M_E~0); 365441#L951-2 assume !(0 == ~T1_E~0); 365442#L956-1 assume !(0 == ~T2_E~0); 365603#L961-1 assume !(0 == ~T3_E~0); 366105#L966-1 assume !(0 == ~T4_E~0); 366106#L971-1 assume !(0 == ~T5_E~0); 366248#L976-1 assume !(0 == ~T6_E~0); 366220#L981-1 assume !(0 == ~T7_E~0); 365965#L986-1 assume !(0 == ~T8_E~0); 365654#L991-1 assume !(0 == ~T9_E~0); 365655#L996-1 assume !(0 == ~E_M~0); 366519#L1001-1 assume !(0 == ~E_1~0); 366163#L1006-1 assume !(0 == ~E_2~0); 366164#L1011-1 assume !(0 == ~E_3~0); 366481#L1016-1 assume !(0 == ~E_4~0); 366499#L1021-1 assume !(0 == ~E_5~0); 365238#L1026-1 assume !(0 == ~E_6~0); 365239#L1031-1 assume !(0 == ~E_7~0); 366113#L1036-1 assume !(0 == ~E_8~0); 366109#L1041-1 assume !(0 == ~E_9~0); 366110#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 366425#L472 assume !(1 == ~m_pc~0); 366370#L472-2 is_master_triggered_~__retres1~0#1 := 0; 366143#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 366144#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 366152#L1179 assume !(0 != activate_threads_~tmp~1#1); 365246#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 365247#L491 assume !(1 == ~t1_pc~0); 365750#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 365751#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365270#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 365219#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 365220#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365240#L510 assume !(1 == ~t2_pc~0); 365208#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 365209#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 365773#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 365774#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 365496#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 365497#L529 assume !(1 == ~t3_pc~0); 365974#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 366281#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 365217#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 365218#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 365416#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 365417#L548 assume !(1 == ~t4_pc~0); 365310#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 365309#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 365380#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 365350#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 365351#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 365298#L567 assume !(1 == ~t5_pc~0); 365299#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 365352#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 366353#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 366354#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 366407#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 365427#L586 assume !(1 == ~t6_pc~0); 365428#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 365500#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 365756#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 365757#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 366398#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 366399#L605 assume !(1 == ~t7_pc~0); 365945#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 365946#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 366145#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 366572#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 366567#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 366076#L624 assume !(1 == ~t8_pc~0); 365491#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 365490#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 366203#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 366277#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 366374#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 365262#L643 assume !(1 == ~t9_pc~0); 365263#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 366311#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 365831#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 365659#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 365660#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 365473#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 365474#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 365631#L1064-1 assume !(1 == ~T2_E~0); 365632#L1069-1 assume !(1 == ~T3_E~0); 366320#L1074-1 assume !(1 == ~T4_E~0); 366372#L1079-1 assume !(1 == ~T5_E~0); 366358#L1084-1 assume !(1 == ~T6_E~0); 366359#L1089-1 assume !(1 == ~T7_E~0); 366394#L1094-1 assume !(1 == ~T8_E~0); 366004#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 366005#L1104-1 assume !(1 == ~E_M~0); 366206#L1109-1 assume !(1 == ~E_1~0); 365775#L1114-1 assume !(1 == ~E_2~0); 365776#L1119-1 assume !(1 == ~E_3~0); 365843#L1124-1 assume !(1 == ~E_4~0); 365258#L1129-1 assume !(1 == ~E_5~0); 365259#L1134-1 assume !(1 == ~E_6~0); 365599#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 365600#L1144-1 assume !(1 == ~E_8~0); 365796#L1149-1 assume !(1 == ~E_9~0); 365433#L1154-1 assume { :end_inline_reset_delta_events } true; 365434#L1440-2 [2023-11-26 10:45:37,666 INFO L750 eck$LassoCheckResult]: Loop: 365434#L1440-2 assume !false; 410347#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 410341#L926-1 assume !false; 410339#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 410331#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 410321#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 410319#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 410316#L795 assume !(0 != eval_~tmp~0#1); 410317#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 410591#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 410590#L951-3 assume 0 == ~M_E~0;~M_E~0 := 1; 410589#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 410588#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 410587#L961-3 assume !(0 == ~T3_E~0); 410586#L966-3 assume !(0 == ~T4_E~0); 410585#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 410584#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 410583#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 410582#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 410580#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 410578#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 410576#L1001-3 assume !(0 == ~E_1~0); 410574#L1006-3 assume !(0 == ~E_2~0); 410572#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 410570#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 410568#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 410566#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 410564#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 410562#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 410560#L1041-3 assume !(0 == ~E_9~0); 410558#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 410555#L472-33 assume !(1 == ~m_pc~0); 410553#L472-35 is_master_triggered_~__retres1~0#1 := 0; 410551#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 410549#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 410547#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 410545#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 410543#L491-33 assume !(1 == ~t1_pc~0); 410541#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 410539#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 410537#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 410535#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 410533#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 410531#L510-33 assume !(1 == ~t2_pc~0); 410527#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 410525#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 410523#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 410521#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 410519#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 410517#L529-33 assume !(1 == ~t3_pc~0); 410515#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 410513#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 410511#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 410509#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 410507#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 410505#L548-33 assume !(1 == ~t4_pc~0); 410502#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 410499#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 410497#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 410495#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 410493#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410491#L567-33 assume !(1 == ~t5_pc~0); 410490#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 410488#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 410486#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 410484#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 410482#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 410480#L586-33 assume 1 == ~t6_pc~0; 410476#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 410474#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 410472#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 410470#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 410468#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 410466#L605-33 assume !(1 == ~t7_pc~0); 406266#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 410463#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 410461#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 410459#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 410457#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 410455#L624-33 assume 1 == ~t8_pc~0; 410452#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 410450#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 410448#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 410446#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 410444#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 410442#L643-33 assume !(1 == ~t9_pc~0); 410440#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 410438#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 410436#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 410434#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 410432#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 410430#L1059-3 assume !(1 == ~M_E~0); 408070#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 410427#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 410425#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 410423#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 408061#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 410420#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 410418#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 410417#L1094-3 assume !(1 == ~T8_E~0); 410416#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 410415#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 410414#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 410413#L1114-3 assume !(1 == ~E_2~0); 410412#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 410411#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 410410#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 410408#L1134-3 assume !(1 == ~E_6~0); 410406#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 410404#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 410402#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 410400#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 410394#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 410384#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 410382#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 410380#L1459 assume !(0 == start_simulation_~tmp~3#1); 410376#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 410370#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 410360#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 410358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 410356#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 410354#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 410352#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 410350#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 365434#L1440-2 [2023-11-26 10:45:37,667 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:37,667 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2023-11-26 10:45:37,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:37,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957403390] [2023-11-26 10:45:37,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:37,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:37,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:37,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:37,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:37,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1957403390] [2023-11-26 10:45:37,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1957403390] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:37,736 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:37,736 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:45:37,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636802795] [2023-11-26 10:45:37,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:37,737 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:37,737 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:37,737 INFO L85 PathProgramCache]: Analyzing trace with hash -1763972704, now seen corresponding path program 1 times [2023-11-26 10:45:37,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:37,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573942050] [2023-11-26 10:45:37,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:37,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:37,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:37,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:37,785 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:37,785 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [573942050] [2023-11-26 10:45:37,786 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [573942050] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:37,786 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:37,786 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:37,786 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320404173] [2023-11-26 10:45:37,786 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:37,787 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:37,787 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:37,787 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:37,787 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:37,788 INFO L87 Difference]: Start difference. First operand 97805 states and 137365 transitions. cyclomatic complexity: 39624 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:38,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:38,783 INFO L93 Difference]: Finished difference Result 145065 states and 204044 transitions. [2023-11-26 10:45:38,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145065 states and 204044 transitions. [2023-11-26 10:45:39,864 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 144064 [2023-11-26 10:45:40,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145065 states to 145065 states and 204044 transitions. [2023-11-26 10:45:40,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145065 [2023-11-26 10:45:40,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145065 [2023-11-26 10:45:40,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145065 states and 204044 transitions. [2023-11-26 10:45:40,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:40,657 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145065 states and 204044 transitions. [2023-11-26 10:45:40,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145065 states and 204044 transitions. [2023-11-26 10:45:42,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145065 to 99065. [2023-11-26 10:45:42,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99065 states, 99065 states have (on average 1.4101246656235804) internal successors, (139694), 99064 states have internal predecessors, (139694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:42,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99065 states to 99065 states and 139694 transitions. [2023-11-26 10:45:42,614 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99065 states and 139694 transitions. [2023-11-26 10:45:42,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:42,615 INFO L428 stractBuchiCegarLoop]: Abstraction has 99065 states and 139694 transitions. [2023-11-26 10:45:42,615 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 10:45:42,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99065 states and 139694 transitions. [2023-11-26 10:45:42,964 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98368 [2023-11-26 10:45:42,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:42,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:42,972 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:42,972 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:42,973 INFO L748 eck$LassoCheckResult]: Stem: 608455#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 608456#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 609311#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 609312#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 608956#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 608659#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 608660#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 609280#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 609342#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 609330#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 609331#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 608790#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 608775#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 608776#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 608575#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 608576#L951 assume !(0 == ~M_E~0); 608318#L951-2 assume !(0 == ~T1_E~0); 608319#L956-1 assume !(0 == ~T2_E~0); 608473#L961-1 assume !(0 == ~T3_E~0); 608979#L966-1 assume !(0 == ~T4_E~0); 608980#L971-1 assume !(0 == ~T5_E~0); 609126#L976-1 assume !(0 == ~T6_E~0); 609099#L981-1 assume !(0 == ~T7_E~0); 608833#L986-1 assume !(0 == ~T8_E~0); 608524#L991-1 assume !(0 == ~T9_E~0); 608525#L996-1 assume !(0 == ~E_M~0); 609381#L1001-1 assume !(0 == ~E_1~0); 609035#L1006-1 assume !(0 == ~E_2~0); 609036#L1011-1 assume !(0 == ~E_3~0); 609345#L1016-1 assume !(0 == ~E_4~0); 609363#L1021-1 assume !(0 == ~E_5~0); 608115#L1026-1 assume !(0 == ~E_6~0); 608116#L1031-1 assume !(0 == ~E_7~0); 608986#L1036-1 assume !(0 == ~E_8~0); 608984#L1041-1 assume !(0 == ~E_9~0); 608985#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 609289#L472 assume !(1 == ~m_pc~0); 609237#L472-2 is_master_triggered_~__retres1~0#1 := 0; 609016#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 609017#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 609026#L1179 assume !(0 != activate_threads_~tmp~1#1); 608123#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 608124#L491 assume !(1 == ~t1_pc~0); 608622#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 608623#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 608147#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 608096#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 608097#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 608119#L510 assume !(1 == ~t2_pc~0); 608085#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 608086#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 608644#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 608645#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 608371#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 608372#L529 assume !(1 == ~t3_pc~0); 608840#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 609157#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 608094#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 608095#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 608291#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 608292#L548 assume !(1 == ~t4_pc~0); 608187#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 608186#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 608256#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 608228#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 608229#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 608179#L567 assume !(1 == ~t5_pc~0); 608180#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 608227#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 609220#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 609221#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 609273#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 608302#L586 assume !(1 == ~t6_pc~0); 608303#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 608377#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 608629#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 608630#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 609266#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 609267#L605 assume !(1 == ~t7_pc~0); 608817#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 608818#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 609019#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 609425#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 609420#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 608949#L624 assume !(1 == ~t8_pc~0); 608366#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 608365#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 609082#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 609154#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 609242#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 608139#L643 assume !(1 == ~t9_pc~0); 608140#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 609183#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 608702#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 608531#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 608532#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 608350#L1059 assume !(1 == ~M_E~0); 608351#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 608501#L1064-1 assume !(1 == ~T2_E~0); 608502#L1069-1 assume !(1 == ~T3_E~0); 609192#L1074-1 assume !(1 == ~T4_E~0); 609241#L1079-1 assume !(1 == ~T5_E~0); 609226#L1084-1 assume !(1 == ~T6_E~0); 609227#L1089-1 assume !(1 == ~T7_E~0); 609258#L1094-1 assume !(1 == ~T8_E~0); 608874#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 608875#L1104-1 assume !(1 == ~E_M~0); 609086#L1109-1 assume !(1 == ~E_1~0); 608649#L1114-1 assume !(1 == ~E_2~0); 608650#L1119-1 assume !(1 == ~E_3~0); 608713#L1124-1 assume !(1 == ~E_4~0); 608137#L1129-1 assume !(1 == ~E_5~0); 608138#L1134-1 assume !(1 == ~E_6~0); 608471#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 608472#L1144-1 assume !(1 == ~E_8~0); 608667#L1149-1 assume !(1 == ~E_9~0); 608308#L1154-1 assume { :end_inline_reset_delta_events } true; 608309#L1440-2 [2023-11-26 10:45:42,973 INFO L750 eck$LassoCheckResult]: Loop: 608309#L1440-2 assume !false; 663208#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 663202#L926-1 assume !false; 663200#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 663194#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 663184#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 663182#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 663179#L795 assume !(0 != eval_~tmp~0#1); 663180#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 706950#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 706946#L951-3 assume !(0 == ~M_E~0); 706942#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 706936#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 706932#L961-3 assume !(0 == ~T3_E~0); 706928#L966-3 assume !(0 == ~T4_E~0); 706924#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 706920#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 706916#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 706912#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 706908#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 706904#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 706900#L1001-3 assume !(0 == ~E_1~0); 706896#L1006-3 assume !(0 == ~E_2~0); 706892#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 706888#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 706882#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 706878#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 706874#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 706870#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 706866#L1041-3 assume !(0 == ~E_9~0); 706861#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 706857#L472-33 assume !(1 == ~m_pc~0); 706854#L472-35 is_master_triggered_~__retres1~0#1 := 0; 706850#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 706846#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 706842#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 706837#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 706833#L491-33 assume !(1 == ~t1_pc~0); 706830#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 706827#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 706825#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 706822#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 706820#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 706817#L510-33 assume !(1 == ~t2_pc~0); 706814#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 706812#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 706809#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 706806#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 706803#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 706800#L529-33 assume !(1 == ~t3_pc~0); 706797#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 706794#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 706791#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 706788#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 706785#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 706782#L548-33 assume 1 == ~t4_pc~0; 706778#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 706775#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 706772#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 706769#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 706766#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 706763#L567-33 assume !(1 == ~t5_pc~0); 706760#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 706757#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 706754#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 706751#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 706748#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 706745#L586-33 assume !(1 == ~t6_pc~0); 706742#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 706736#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 706735#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 609441#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 609442#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 705039#L605-33 assume !(1 == ~t7_pc~0); 705037#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 705035#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 705033#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 705031#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 705029#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 705027#L624-33 assume 1 == ~t8_pc~0; 705024#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 705022#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 705020#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 705018#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 705016#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 705014#L643-33 assume !(1 == ~t9_pc~0); 705013#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 705010#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 705008#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 705006#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 705004#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 705002#L1059-3 assume !(1 == ~M_E~0); 623579#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 704999#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 704997#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 704995#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 704993#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 704991#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 704989#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 704987#L1094-3 assume !(1 == ~T8_E~0); 704984#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 704982#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 704980#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 704978#L1114-3 assume !(1 == ~E_2~0); 704976#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 704974#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 704971#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 704969#L1134-3 assume !(1 == ~E_6~0); 704967#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 704965#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 704963#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 704961#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 704954#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 704945#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 704324#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 642377#L1459 assume !(0 == start_simulation_~tmp~3#1); 642378#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 663232#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 663223#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 663219#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 663217#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 663215#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 663214#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 663211#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 608309#L1440-2 [2023-11-26 10:45:42,974 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:42,975 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2023-11-26 10:45:42,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:42,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802597935] [2023-11-26 10:45:42,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:42,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:42,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:43,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:43,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:43,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802597935] [2023-11-26 10:45:43,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1802597935] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:43,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:43,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:45:43,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787149121] [2023-11-26 10:45:43,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:43,063 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:43,064 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:43,064 INFO L85 PathProgramCache]: Analyzing trace with hash -659447970, now seen corresponding path program 1 times [2023-11-26 10:45:43,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:43,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570581707] [2023-11-26 10:45:43,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:43,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:43,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:43,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:43,126 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:43,126 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1570581707] [2023-11-26 10:45:43,126 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1570581707] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:43,126 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:43,126 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:43,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1904925825] [2023-11-26 10:45:43,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:43,128 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:43,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:43,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:45:43,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:45:43,129 INFO L87 Difference]: Start difference. First operand 99065 states and 139694 transitions. cyclomatic complexity: 40661 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:43,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:43,983 INFO L93 Difference]: Finished difference Result 99065 states and 139308 transitions. [2023-11-26 10:45:43,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99065 states and 139308 transitions. [2023-11-26 10:45:44,407 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98368 [2023-11-26 10:45:44,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99065 states to 99065 states and 139308 transitions. [2023-11-26 10:45:44,739 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99065 [2023-11-26 10:45:44,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99065 [2023-11-26 10:45:44,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99065 states and 139308 transitions. [2023-11-26 10:45:44,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:44,868 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99065 states and 139308 transitions. [2023-11-26 10:45:44,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99065 states and 139308 transitions. [2023-11-26 10:45:46,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99065 to 99065. [2023-11-26 10:45:46,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99065 states, 99065 states have (on average 1.4062282339877858) internal successors, (139308), 99064 states have internal predecessors, (139308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:46,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99065 states to 99065 states and 139308 transitions. [2023-11-26 10:45:46,786 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99065 states and 139308 transitions. [2023-11-26 10:45:46,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:45:46,787 INFO L428 stractBuchiCegarLoop]: Abstraction has 99065 states and 139308 transitions. [2023-11-26 10:45:46,787 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 10:45:46,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99065 states and 139308 transitions. [2023-11-26 10:45:47,059 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98368 [2023-11-26 10:45:47,060 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:47,060 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:47,065 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:47,065 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:47,065 INFO L748 eck$LassoCheckResult]: Stem: 806597#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 806598#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 807461#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 807462#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 807100#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 806802#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 806803#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 807424#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 807493#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 807479#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 807480#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 806938#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 806925#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 806926#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 806722#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 806723#L951 assume !(0 == ~M_E~0); 806456#L951-2 assume !(0 == ~T1_E~0); 806457#L956-1 assume !(0 == ~T2_E~0); 806617#L961-1 assume !(0 == ~T3_E~0); 807120#L966-1 assume !(0 == ~T4_E~0); 807121#L971-1 assume !(0 == ~T5_E~0); 807261#L976-1 assume !(0 == ~T6_E~0); 807234#L981-1 assume !(0 == ~T7_E~0); 806979#L986-1 assume !(0 == ~T8_E~0); 806670#L991-1 assume !(0 == ~T9_E~0); 806671#L996-1 assume !(0 == ~E_M~0); 807534#L1001-1 assume !(0 == ~E_1~0); 807181#L1006-1 assume !(0 == ~E_2~0); 807182#L1011-1 assume !(0 == ~E_3~0); 807495#L1016-1 assume !(0 == ~E_4~0); 807513#L1021-1 assume !(0 == ~E_5~0); 806252#L1026-1 assume !(0 == ~E_6~0); 806253#L1031-1 assume !(0 == ~E_7~0); 807128#L1036-1 assume !(0 == ~E_8~0); 807126#L1041-1 assume !(0 == ~E_9~0); 807127#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 807435#L472 assume !(1 == ~m_pc~0); 807376#L472-2 is_master_triggered_~__retres1~0#1 := 0; 807159#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 807160#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 807169#L1179 assume !(0 != activate_threads_~tmp~1#1); 806260#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 806261#L491 assume !(1 == ~t1_pc~0); 806769#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 806770#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 806284#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 806233#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 806234#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 806256#L510 assume !(1 == ~t2_pc~0); 806222#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 806223#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 806791#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 806792#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 806509#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 806510#L529 assume !(1 == ~t3_pc~0); 806985#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 807292#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 806231#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 806232#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 806429#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 806430#L548 assume !(1 == ~t4_pc~0); 806324#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 806323#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 806394#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 806364#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 806365#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 806313#L567 assume !(1 == ~t5_pc~0); 806314#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 806366#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 807358#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 807359#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 807416#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 806440#L586 assume !(1 == ~t6_pc~0); 806441#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 806515#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 806773#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 806774#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 807410#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 807411#L605 assume !(1 == ~t7_pc~0); 806959#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 806960#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 807163#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 807592#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 807587#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 807093#L624 assume !(1 == ~t8_pc~0); 806504#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 806503#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 807219#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 807288#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 807382#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 806276#L643 assume !(1 == ~t9_pc~0); 806277#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 807319#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 806846#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 806675#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 806676#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 806488#L1059 assume !(1 == ~M_E~0); 806489#L1059-2 assume !(1 == ~T1_E~0); 806647#L1064-1 assume !(1 == ~T2_E~0); 806648#L1069-1 assume !(1 == ~T3_E~0); 807328#L1074-1 assume !(1 == ~T4_E~0); 807379#L1079-1 assume !(1 == ~T5_E~0); 807364#L1084-1 assume !(1 == ~T6_E~0); 807365#L1089-1 assume !(1 == ~T7_E~0); 807402#L1094-1 assume !(1 == ~T8_E~0); 807016#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 807017#L1104-1 assume !(1 == ~E_M~0); 807223#L1109-1 assume !(1 == ~E_1~0); 806793#L1114-1 assume !(1 == ~E_2~0); 806794#L1119-1 assume !(1 == ~E_3~0); 806858#L1124-1 assume !(1 == ~E_4~0); 806274#L1129-1 assume !(1 == ~E_5~0); 806275#L1134-1 assume !(1 == ~E_6~0); 806615#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 806616#L1144-1 assume !(1 == ~E_8~0); 806811#L1149-1 assume !(1 == ~E_9~0); 806446#L1154-1 assume { :end_inline_reset_delta_events } true; 806447#L1440-2 [2023-11-26 10:45:47,066 INFO L750 eck$LassoCheckResult]: Loop: 806447#L1440-2 assume !false; 823574#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 823569#L926-1 assume !false; 823567#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 823561#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 823551#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 823548#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 823545#L795 assume !(0 != eval_~tmp~0#1); 823543#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 823541#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 823539#L951-3 assume !(0 == ~M_E~0); 823537#L951-5 assume !(0 == ~T1_E~0); 823535#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 823533#L961-3 assume !(0 == ~T3_E~0); 823531#L966-3 assume !(0 == ~T4_E~0); 823529#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 823527#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 823525#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 823523#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 823520#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 823518#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 823516#L1001-3 assume !(0 == ~E_1~0); 823514#L1006-3 assume !(0 == ~E_2~0); 823512#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 823510#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 823508#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 823506#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 823504#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 823502#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 823500#L1041-3 assume !(0 == ~E_9~0); 823498#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 823495#L472-33 assume !(1 == ~m_pc~0); 823493#L472-35 is_master_triggered_~__retres1~0#1 := 0; 823491#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 823489#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 823487#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 823485#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 823484#L491-33 assume !(1 == ~t1_pc~0); 823482#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 823480#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 823478#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 823476#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 823474#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 823471#L510-33 assume !(1 == ~t2_pc~0); 823468#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 823466#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 823464#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 823462#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 823460#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 823458#L529-33 assume !(1 == ~t3_pc~0); 823456#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 823454#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 823452#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 823450#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 823449#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 823448#L548-33 assume 1 == ~t4_pc~0; 823446#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 823442#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 823440#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 823438#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 823437#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 823434#L567-33 assume !(1 == ~t5_pc~0); 823430#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 823429#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 823428#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 823427#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 823426#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 823425#L586-33 assume 1 == ~t6_pc~0; 823423#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 823422#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 823421#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 823420#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 823419#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 823418#L605-33 assume !(1 == ~t7_pc~0); 821973#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 823417#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 823416#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 823415#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 823414#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 823413#L624-33 assume !(1 == ~t8_pc~0); 823412#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 823410#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 823409#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 823408#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 823407#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 823406#L643-33 assume !(1 == ~t9_pc~0); 823405#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 823404#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 823403#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 823402#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 823401#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 823400#L1059-3 assume !(1 == ~M_E~0); 823224#L1059-5 assume !(1 == ~T1_E~0); 823397#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 823395#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 823393#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 823391#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 823389#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 823387#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 823385#L1094-3 assume !(1 == ~T8_E~0); 823383#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 823381#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 823379#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 823377#L1114-3 assume !(1 == ~E_2~0); 823375#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 823373#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 823371#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 823369#L1134-3 assume !(1 == ~E_6~0); 823367#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 823365#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 823363#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 823361#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 823355#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 823345#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 823343#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 823340#L1459 assume !(0 == start_simulation_~tmp~3#1); 823341#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 823597#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 823585#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 823584#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 823583#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 823581#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 823579#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 823577#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 806447#L1440-2 [2023-11-26 10:45:47,066 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:47,067 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times [2023-11-26 10:45:47,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:47,067 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542635391] [2023-11-26 10:45:47,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:47,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:47,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:47,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:47,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:47,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542635391] [2023-11-26 10:45:47,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542635391] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:47,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:47,857 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:47,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231629016] [2023-11-26 10:45:47,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:47,858 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:47,858 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:47,859 INFO L85 PathProgramCache]: Analyzing trace with hash 228711582, now seen corresponding path program 1 times [2023-11-26 10:45:47,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:47,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565525534] [2023-11-26 10:45:47,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:47,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:47,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:47,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:47,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:47,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565525534] [2023-11-26 10:45:47,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565525534] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:47,945 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:47,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:47,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552738011] [2023-11-26 10:45:47,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:47,946 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:47,946 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:47,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:45:47,947 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:45:47,947 INFO L87 Difference]: Start difference. First operand 99065 states and 139308 transitions. cyclomatic complexity: 40275 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:48,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:48,392 INFO L93 Difference]: Finished difference Result 156409 states and 219637 transitions. [2023-11-26 10:45:48,392 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156409 states and 219637 transitions. [2023-11-26 10:45:48,952 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 155328 [2023-11-26 10:45:49,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156409 states to 156409 states and 219637 transitions. [2023-11-26 10:45:49,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 156409 [2023-11-26 10:45:50,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 156409 [2023-11-26 10:45:50,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156409 states and 219637 transitions. [2023-11-26 10:45:50,106 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:50,106 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156409 states and 219637 transitions. [2023-11-26 10:45:50,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156409 states and 219637 transitions. [2023-11-26 10:45:51,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156409 to 110414. [2023-11-26 10:45:51,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110414 states, 110414 states have (on average 1.4082362743854946) internal successors, (155489), 110413 states have internal predecessors, (155489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:52,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110414 states to 110414 states and 155489 transitions. [2023-11-26 10:45:52,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110414 states and 155489 transitions. [2023-11-26 10:45:52,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:45:52,007 INFO L428 stractBuchiCegarLoop]: Abstraction has 110414 states and 155489 transitions. [2023-11-26 10:45:52,008 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 10:45:52,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110414 states and 155489 transitions. [2023-11-26 10:45:52,289 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 109632 [2023-11-26 10:45:52,290 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:52,290 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:52,292 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:52,292 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:52,293 INFO L748 eck$LassoCheckResult]: Stem: 1062086#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1062087#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1062948#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1062949#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1062590#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1062291#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1062292#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1062915#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1062977#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1062964#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1062965#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1062428#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1062414#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1062415#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1062214#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1062215#L951 assume !(0 == ~M_E~0); 1061946#L951-2 assume !(0 == ~T1_E~0); 1061947#L956-1 assume !(0 == ~T2_E~0); 1062108#L961-1 assume !(0 == ~T3_E~0); 1062609#L966-1 assume !(0 == ~T4_E~0); 1062610#L971-1 assume !(0 == ~T5_E~0); 1062754#L976-1 assume !(0 == ~T6_E~0); 1062724#L981-1 assume !(0 == ~T7_E~0); 1062468#L986-1 assume !(0 == ~T8_E~0); 1062160#L991-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1062161#L996-1 assume !(0 == ~E_M~0); 1063113#L1001-1 assume !(0 == ~E_1~0); 1062669#L1006-1 assume !(0 == ~E_2~0); 1062670#L1011-1 assume !(0 == ~E_3~0); 1062997#L1016-1 assume !(0 == ~E_4~0); 1062998#L1021-1 assume !(0 == ~E_5~0); 1061736#L1026-1 assume !(0 == ~E_6~0); 1061737#L1031-1 assume !(0 == ~E_7~0); 1062619#L1036-1 assume !(0 == ~E_8~0); 1062620#L1041-1 assume !(0 == ~E_9~0); 1062931#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1062932#L472 assume !(1 == ~m_pc~0); 1062868#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1062869#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1062847#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1062848#L1179 assume !(0 != activate_threads_~tmp~1#1); 1061745#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1061746#L491 assume !(1 == ~t1_pc~0); 1062261#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1062262#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1061771#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1061772#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1061740#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1061741#L510 assume !(1 == ~t2_pc~0); 1061706#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1061707#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1063018#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1063090#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1063091#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1062474#L529 assume !(1 == ~t3_pc~0); 1062475#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1062860#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1062861#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1063056#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1063057#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1063077#L548 assume !(1 == ~t4_pc~0); 1063078#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1062119#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1062120#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1061854#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1061855#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1061801#L567 assume !(1 == ~t5_pc~0); 1061802#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1063067#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1063068#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1063110#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1062906#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1062907#L586 assume !(1 == ~t6_pc~0); 1062004#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1062005#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1063039#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1063098#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1063099#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1063075#L605 assume !(1 == ~t7_pc~0); 1063076#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1062651#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1062652#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1063069#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1063070#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1063108#L624 assume !(1 == ~t8_pc~0); 1061992#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1061991#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1062777#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1062778#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1063096#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1061763#L643 assume !(1 == ~t9_pc~0); 1061764#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1063035#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1062335#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1062336#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1063074#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1061975#L1059 assume !(1 == ~M_E~0); 1061976#L1059-2 assume !(1 == ~T1_E~0); 1062138#L1064-1 assume !(1 == ~T2_E~0); 1062139#L1069-1 assume !(1 == ~T3_E~0); 1063060#L1074-1 assume !(1 == ~T4_E~0); 1063061#L1079-1 assume !(1 == ~T5_E~0); 1062856#L1084-1 assume !(1 == ~T6_E~0); 1062857#L1089-1 assume !(1 == ~T7_E~0); 1062893#L1094-1 assume !(1 == ~T8_E~0); 1062894#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1062509#L1104-1 assume !(1 == ~E_M~0); 1062713#L1109-1 assume !(1 == ~E_1~0); 1062284#L1114-1 assume !(1 == ~E_2~0); 1062285#L1119-1 assume !(1 == ~E_3~0); 1062349#L1124-1 assume !(1 == ~E_4~0); 1061758#L1129-1 assume !(1 == ~E_5~0); 1061759#L1134-1 assume !(1 == ~E_6~0); 1062104#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1062105#L1144-1 assume !(1 == ~E_8~0); 1062299#L1149-1 assume !(1 == ~E_9~0); 1061936#L1154-1 assume { :end_inline_reset_delta_events } true; 1061937#L1440-2 [2023-11-26 10:45:52,293 INFO L750 eck$LassoCheckResult]: Loop: 1061937#L1440-2 assume !false; 1121606#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1121601#L926-1 assume !false; 1121599#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1121593#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1121583#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1121581#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1121580#L795 assume !(0 != eval_~tmp~0#1); 1062784#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1062517#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1062199#L951-3 assume !(0 == ~M_E~0); 1062200#L951-5 assume !(0 == ~T1_E~0); 1062767#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1062587#L961-3 assume !(0 == ~T3_E~0); 1062332#L966-3 assume !(0 == ~T4_E~0); 1062333#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1171569#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1171566#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1171564#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1061760#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1061761#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1171747#L1001-3 assume !(0 == ~E_1~0); 1171746#L1006-3 assume !(0 == ~E_2~0); 1171745#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1171744#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1171743#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1171742#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1171741#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1171740#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1171739#L1041-3 assume !(0 == ~E_9~0); 1171738#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1171737#L472-33 assume !(1 == ~m_pc~0); 1171736#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1171735#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1171734#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1171733#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1171732#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1171731#L491-33 assume !(1 == ~t1_pc~0); 1171730#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1171729#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1171728#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1171727#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 1171726#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1171725#L510-33 assume !(1 == ~t2_pc~0); 1171723#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1171722#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1171721#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1171720#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1171719#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1171718#L529-33 assume !(1 == ~t3_pc~0); 1171717#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1171716#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1171715#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1171714#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1171713#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1171712#L548-33 assume !(1 == ~t4_pc~0); 1171711#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1171709#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1171708#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1171707#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1171706#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1171705#L567-33 assume !(1 == ~t5_pc~0); 1171704#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1171703#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1171702#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1171701#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1171700#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1171699#L586-33 assume 1 == ~t6_pc~0; 1171697#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1171696#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1171695#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1171694#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1171693#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1171692#L605-33 assume !(1 == ~t7_pc~0); 1165012#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1171691#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1171690#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1171689#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1171688#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1171687#L624-33 assume 1 == ~t8_pc~0; 1171685#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1171684#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1171683#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1171682#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 1171681#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1171680#L643-33 assume !(1 == ~t9_pc~0); 1171679#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1171678#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1171677#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1171676#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1171675#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1171674#L1059-3 assume !(1 == ~M_E~0); 1096890#L1059-5 assume !(1 == ~T1_E~0); 1171673#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1171672#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1171671#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1171670#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1171669#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1171668#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1171667#L1094-3 assume !(1 == ~T8_E~0); 1171666#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1062457#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1062752#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1062995#L1114-3 assume !(1 == ~E_2~0); 1170659#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1170658#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1170657#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1170656#L1134-3 assume !(1 == ~E_6~0); 1170655#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1170654#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1170653#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1063097#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1063071#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1061836#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1062230#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1062231#L1459 assume !(0 == start_simulation_~tmp~3#1); 1096456#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1121630#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1121620#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1121618#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1121616#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1121614#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1121612#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1121609#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1061937#L1440-2 [2023-11-26 10:45:52,294 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:52,294 INFO L85 PathProgramCache]: Analyzing trace with hash -1773294265, now seen corresponding path program 1 times [2023-11-26 10:45:52,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:52,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951390564] [2023-11-26 10:45:52,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:52,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:52,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:52,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:52,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:52,356 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951390564] [2023-11-26 10:45:52,356 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [951390564] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:52,356 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:52,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:52,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029442256] [2023-11-26 10:45:52,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:52,357 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:52,358 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:52,358 INFO L85 PathProgramCache]: Analyzing trace with hash -2055149154, now seen corresponding path program 1 times [2023-11-26 10:45:52,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:52,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297474283] [2023-11-26 10:45:52,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:52,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:52,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:52,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:52,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:52,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297474283] [2023-11-26 10:45:52,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297474283] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:52,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:52,405 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:52,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [651180323] [2023-11-26 10:45:52,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:52,405 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:52,406 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:52,406 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:45:52,406 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:45:52,406 INFO L87 Difference]: Start difference. First operand 110414 states and 155489 transitions. cyclomatic complexity: 45107 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:52,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:52,887 INFO L93 Difference]: Finished difference Result 145049 states and 202986 transitions. [2023-11-26 10:45:52,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145049 states and 202986 transitions. [2023-11-26 10:45:54,266 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 144064 [2023-11-26 10:45:54,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145049 states to 145049 states and 202986 transitions. [2023-11-26 10:45:54,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145049 [2023-11-26 10:45:54,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145049 [2023-11-26 10:45:54,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145049 states and 202986 transitions. [2023-11-26 10:45:54,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:54,653 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145049 states and 202986 transitions. [2023-11-26 10:45:54,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145049 states and 202986 transitions. [2023-11-26 10:45:56,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145049 to 99065. [2023-11-26 10:45:56,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99065 states, 99065 states have (on average 1.402331802351991) internal successors, (138922), 99064 states have internal predecessors, (138922), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:56,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99065 states to 99065 states and 138922 transitions. [2023-11-26 10:45:56,290 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99065 states and 138922 transitions. [2023-11-26 10:45:56,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:45:56,291 INFO L428 stractBuchiCegarLoop]: Abstraction has 99065 states and 138922 transitions. [2023-11-26 10:45:56,291 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 10:45:56,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99065 states and 138922 transitions. [2023-11-26 10:45:56,572 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98368 [2023-11-26 10:45:56,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:45:56,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:45:56,575 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:56,576 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:45:56,576 INFO L748 eck$LassoCheckResult]: Stem: 1317548#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1317549#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1318397#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1318398#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1318053#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1317758#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1317759#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1318363#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1318428#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1318411#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1318412#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1317891#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1317876#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1317877#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1317675#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1317676#L951 assume !(0 == ~M_E~0); 1317410#L951-2 assume !(0 == ~T1_E~0); 1317411#L956-1 assume !(0 == ~T2_E~0); 1317573#L961-1 assume !(0 == ~T3_E~0); 1318072#L966-1 assume !(0 == ~T4_E~0); 1318073#L971-1 assume !(0 == ~T5_E~0); 1318208#L976-1 assume !(0 == ~T6_E~0); 1318182#L981-1 assume !(0 == ~T7_E~0); 1317929#L986-1 assume !(0 == ~T8_E~0); 1317624#L991-1 assume !(0 == ~T9_E~0); 1317625#L996-1 assume !(0 == ~E_M~0); 1318468#L1001-1 assume !(0 == ~E_1~0); 1318128#L1006-1 assume !(0 == ~E_2~0); 1318129#L1011-1 assume !(0 == ~E_3~0); 1318429#L1016-1 assume !(0 == ~E_4~0); 1318448#L1021-1 assume !(0 == ~E_5~0); 1317209#L1026-1 assume !(0 == ~E_6~0); 1317210#L1031-1 assume !(0 == ~E_7~0); 1318082#L1036-1 assume !(0 == ~E_8~0); 1318078#L1041-1 assume !(0 == ~E_9~0); 1318079#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1318378#L472 assume !(1 == ~m_pc~0); 1318320#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1318109#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1318110#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1318119#L1179 assume !(0 != activate_threads_~tmp~1#1); 1317217#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1317218#L491 assume !(1 == ~t1_pc~0); 1317724#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1317725#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1317242#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1317190#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1317191#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1317213#L510 assume !(1 == ~t2_pc~0); 1317179#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1317180#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1317747#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1317748#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1317464#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1317465#L529 assume !(1 == ~t3_pc~0); 1317938#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1318240#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1317188#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1317189#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1317385#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1317386#L548 assume !(1 == ~t4_pc~0); 1317281#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1317280#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1317352#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1317322#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1317323#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1317269#L567 assume !(1 == ~t5_pc~0); 1317270#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1317324#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1318305#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1318306#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1318356#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1317396#L586 assume !(1 == ~t6_pc~0); 1317397#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1317468#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1317730#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1317731#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1318350#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1318351#L605 assume !(1 == ~t7_pc~0); 1317912#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1317913#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1318111#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1318506#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1318505#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1318045#L624 assume !(1 == ~t8_pc~0); 1317459#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1317458#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1318167#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1318236#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1318325#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1317234#L643 assume !(1 == ~t9_pc~0); 1317235#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1318269#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1317798#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1317629#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1317630#L1251-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1317441#L1059 assume !(1 == ~M_E~0); 1317442#L1059-2 assume !(1 == ~T1_E~0); 1317601#L1064-1 assume !(1 == ~T2_E~0); 1317602#L1069-1 assume !(1 == ~T3_E~0); 1318278#L1074-1 assume !(1 == ~T4_E~0); 1318323#L1079-1 assume !(1 == ~T5_E~0); 1318311#L1084-1 assume !(1 == ~T6_E~0); 1318312#L1089-1 assume !(1 == ~T7_E~0); 1318344#L1094-1 assume !(1 == ~T8_E~0); 1317972#L1099-1 assume !(1 == ~T9_E~0); 1317973#L1104-1 assume !(1 == ~E_M~0); 1318169#L1109-1 assume !(1 == ~E_1~0); 1317749#L1114-1 assume !(1 == ~E_2~0); 1317750#L1119-1 assume !(1 == ~E_3~0); 1317810#L1124-1 assume !(1 == ~E_4~0); 1317230#L1129-1 assume !(1 == ~E_5~0); 1317231#L1134-1 assume !(1 == ~E_6~0); 1317569#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1317570#L1144-1 assume !(1 == ~E_8~0); 1317766#L1149-1 assume !(1 == ~E_9~0); 1317402#L1154-1 assume { :end_inline_reset_delta_events } true; 1317403#L1440-2 [2023-11-26 10:45:56,577 INFO L750 eck$LassoCheckResult]: Loop: 1317403#L1440-2 assume !false; 1399619#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1395777#L926-1 assume !false; 1399557#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1372651#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1372641#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1372639#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1372636#L795 assume !(0 != eval_~tmp~0#1); 1372637#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1374337#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1374334#L951-3 assume !(0 == ~M_E~0); 1374331#L951-5 assume !(0 == ~T1_E~0); 1374327#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1374323#L961-3 assume !(0 == ~T3_E~0); 1374319#L966-3 assume !(0 == ~T4_E~0); 1374315#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1374311#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1374307#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1374303#L986-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1374302#L991-3 assume !(0 == ~T9_E~0); 1374301#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1374300#L1001-3 assume !(0 == ~E_1~0); 1374299#L1006-3 assume !(0 == ~E_2~0); 1374298#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1374296#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1374294#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1374292#L1026-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1374290#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1374288#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1374286#L1041-3 assume !(0 == ~E_9~0); 1374283#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1374281#L472-33 assume !(1 == ~m_pc~0); 1374279#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1374277#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1374275#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1374273#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1374270#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1374268#L491-33 assume !(1 == ~t1_pc~0); 1374266#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1374264#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1374262#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1374261#L1187-33 assume !(0 != activate_threads_~tmp___0~0#1); 1374260#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1374256#L510-33 assume !(1 == ~t2_pc~0); 1374253#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1374251#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1374250#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1374247#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1374243#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1374242#L529-33 assume !(1 == ~t3_pc~0); 1374241#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1374240#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1374239#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1374238#L1203-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1374237#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1374236#L548-33 assume 1 == ~t4_pc~0; 1374234#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1374214#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1374213#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1374212#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1374211#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1374210#L567-33 assume !(1 == ~t5_pc~0); 1374199#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1374197#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1374195#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1374193#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1374191#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1374189#L586-33 assume 1 == ~t6_pc~0; 1374186#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1374184#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1374179#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1374177#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1374175#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1374174#L605-33 assume !(1 == ~t7_pc~0); 1361929#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1374173#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1374162#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1374160#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1374158#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1374155#L624-33 assume 1 == ~t8_pc~0; 1374152#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1374150#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1374148#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1374146#L1243-33 assume !(0 != activate_threads_~tmp___7~0#1); 1374144#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1374142#L643-33 assume !(1 == ~t9_pc~0); 1374140#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1374138#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1374136#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1374134#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1374132#L1251-35 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1374130#L1059-3 assume !(1 == ~M_E~0); 1331687#L1059-5 assume !(1 == ~T1_E~0); 1374127#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1374125#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1374123#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1374121#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1374119#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1374117#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1374115#L1094-3 assume !(1 == ~T8_E~0); 1374113#L1099-3 assume !(1 == ~T9_E~0); 1374111#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1374109#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1374107#L1114-3 assume !(1 == ~E_2~0); 1374104#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1374102#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1374100#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1374098#L1134-3 assume !(1 == ~E_6~0); 1374096#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1374094#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1374092#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1374090#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1374082#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1374072#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1374070#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1331862#L1459 assume !(0 == start_simulation_~tmp~3#1); 1331863#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1399641#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1399631#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1399628#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1399626#L1414 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1399624#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1399622#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1399620#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1317403#L1440-2 [2023-11-26 10:45:56,577 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:56,578 INFO L85 PathProgramCache]: Analyzing trace with hash 1896329479, now seen corresponding path program 1 times [2023-11-26 10:45:56,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:56,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291092476] [2023-11-26 10:45:56,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:56,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:56,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:56,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:56,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:56,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291092476] [2023-11-26 10:45:56,655 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [291092476] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:56,655 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:56,655 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:56,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1943744510] [2023-11-26 10:45:56,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:56,656 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:45:56,656 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:45:56,656 INFO L85 PathProgramCache]: Analyzing trace with hash 1086617245, now seen corresponding path program 1 times [2023-11-26 10:45:56,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:45:56,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518198601] [2023-11-26 10:45:56,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:45:56,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:45:56,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:45:56,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:45:56,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:45:56,700 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [518198601] [2023-11-26 10:45:56,700 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [518198601] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:45:56,700 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:45:56,700 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:45:56,701 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1023117047] [2023-11-26 10:45:56,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:45:56,701 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:45:56,701 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:45:56,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:45:56,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:45:56,702 INFO L87 Difference]: Start difference. First operand 99065 states and 138922 transitions. cyclomatic complexity: 39889 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:45:57,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:45:57,954 INFO L93 Difference]: Finished difference Result 153169 states and 213971 transitions. [2023-11-26 10:45:57,955 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153169 states and 213971 transitions. [2023-11-26 10:45:58,598 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 152032 [2023-11-26 10:45:58,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153169 states to 153169 states and 213971 transitions. [2023-11-26 10:45:58,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153169 [2023-11-26 10:45:58,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153169 [2023-11-26 10:45:58,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153169 states and 213971 transitions. [2023-11-26 10:45:59,058 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:45:59,059 INFO L218 hiAutomatonCegarLoop]: Abstraction has 153169 states and 213971 transitions. [2023-11-26 10:45:59,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153169 states and 213971 transitions.