./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.12.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.12.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bc6dc2c99e05b6915f0a2e5b5d96221c996d96767aaa6be997dea59c4d6f5f0a --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:47:22,692 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:47:22,817 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:47:22,828 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:47:22,832 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:47:22,872 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:47:22,873 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:47:22,874 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:47:22,876 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:47:22,885 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:47:22,887 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:47:22,887 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:47:22,888 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:47:22,890 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:47:22,891 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:47:22,891 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:47:22,892 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:47:22,893 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:47:22,893 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:47:22,894 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:47:22,894 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:47:22,895 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:47:22,895 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:47:22,896 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:47:22,896 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:47:22,897 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:47:22,897 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:47:22,898 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:47:22,898 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:47:22,899 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:47:22,901 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:47:22,901 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:47:22,901 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:47:22,902 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:47:22,902 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:47:22,902 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:47:22,903 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:47:22,903 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:47:22,904 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bc6dc2c99e05b6915f0a2e5b5d96221c996d96767aaa6be997dea59c4d6f5f0a [2023-11-26 11:47:23,195 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:47:23,226 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:47:23,229 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:47:23,230 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:47:23,231 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:47:23,232 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/token_ring.12.cil-2.c [2023-11-26 11:47:26,402 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:47:26,726 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:47:26,727 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/sv-benchmarks/c/systemc/token_ring.12.cil-2.c [2023-11-26 11:47:26,747 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/data/2e07b6548/cdfd6dc7e7634db3b3ff68ac289c5e04/FLAG921133ae7 [2023-11-26 11:47:26,761 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/data/2e07b6548/cdfd6dc7e7634db3b3ff68ac289c5e04 [2023-11-26 11:47:26,763 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:47:26,765 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:47:26,766 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:47:26,766 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:47:26,771 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:47:26,772 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:47:26" (1/1) ... [2023-11-26 11:47:26,773 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7e0777d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:26, skipping insertion in model container [2023-11-26 11:47:26,773 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:47:26" (1/1) ... [2023-11-26 11:47:26,833 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:47:27,165 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:47:27,187 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:47:27,289 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:47:27,324 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:47:27,326 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27 WrapperNode [2023-11-26 11:47:27,326 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:47:27,327 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:47:27,328 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:47:27,328 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:47:27,336 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,352 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,511 INFO L138 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4161 [2023-11-26 11:47:27,512 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:47:27,513 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:47:27,514 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:47:27,514 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:47:27,527 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,528 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,546 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,613 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 11:47:27,620 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,620 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,671 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,759 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,772 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,808 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,842 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:47:27,843 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:47:27,844 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:47:27,844 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:47:27,845 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (1/1) ... [2023-11-26 11:47:27,854 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:47:27,876 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:47:27,897 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:47:27,928 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0b8cbed2-71e2-4378-8c0d-f95770aee8b4/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:47:27,940 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:47:27,940 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:47:27,941 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:47:27,941 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:47:28,095 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:47:28,098 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:47:30,723 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:47:30,755 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:47:30,756 INFO L309 CfgBuilder]: Removed 15 assume(true) statements. [2023-11-26 11:47:30,758 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:47:30 BoogieIcfgContainer [2023-11-26 11:47:30,758 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:47:30,760 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:47:30,760 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:47:30,764 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:47:30,765 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:47:30,766 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:47:26" (1/3) ... [2023-11-26 11:47:30,767 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2ec49997 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:47:30, skipping insertion in model container [2023-11-26 11:47:30,767 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:47:30,767 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:47:27" (2/3) ... [2023-11-26 11:47:30,768 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2ec49997 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:47:30, skipping insertion in model container [2023-11-26 11:47:30,768 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:47:30,768 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:47:30" (3/3) ... [2023-11-26 11:47:30,770 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-2.c [2023-11-26 11:47:30,897 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:47:30,898 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:47:30,898 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:47:30,898 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:47:30,898 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:47:30,898 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:47:30,898 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:47:30,899 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:47:30,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1805 states, 1804 states have (on average 1.4950110864745012) internal successors, (2697), 1804 states have internal predecessors, (2697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:31,021 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-26 11:47:31,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:31,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:31,041 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:31,041 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:31,042 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:47:31,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1805 states, 1804 states have (on average 1.4950110864745012) internal successors, (2697), 1804 states have internal predecessors, (2697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:31,071 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-26 11:47:31,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:31,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:31,086 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:31,086 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:31,117 INFO L748 eck$LassoCheckResult]: Stem: 117#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1720#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 685#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1718#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 151#L841true assume !(1 == ~m_i~0);~m_st~0 := 2; 558#L841-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 106#L846-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1737#L851-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1030#L856-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 457#L861-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 491#L866-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 392#L871-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 762#L876-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 753#L881-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1325#L886-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 251#L891-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1315#L896-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 517#L901-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1202#L1194true assume !(0 == ~M_E~0); 618#L1194-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 880#L1199-1true assume !(0 == ~T2_E~0); 1073#L1204-1true assume !(0 == ~T3_E~0); 803#L1209-1true assume !(0 == ~T4_E~0); 1362#L1214-1true assume !(0 == ~T5_E~0); 1753#L1219-1true assume !(0 == ~T6_E~0); 1673#L1224-1true assume !(0 == ~T7_E~0); 292#L1229-1true assume !(0 == ~T8_E~0); 68#L1234-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 505#L1239-1true assume !(0 == ~T10_E~0); 87#L1244-1true assume !(0 == ~T11_E~0); 1455#L1249-1true assume !(0 == ~T12_E~0); 479#L1254-1true assume !(0 == ~E_M~0); 39#L1259-1true assume !(0 == ~E_1~0); 22#L1264-1true assume !(0 == ~E_2~0); 1795#L1269-1true assume !(0 == ~E_3~0); 1723#L1274-1true assume 0 == ~E_4~0;~E_4~0 := 1; 1446#L1279-1true assume !(0 == ~E_5~0); 122#L1284-1true assume !(0 == ~E_6~0); 1580#L1289-1true assume !(0 == ~E_7~0); 523#L1294-1true assume !(0 == ~E_8~0); 530#L1299-1true assume !(0 == ~E_9~0); 1643#L1304-1true assume !(0 == ~E_10~0); 1684#L1309-1true assume !(0 == ~E_11~0); 1660#L1314-1true assume 0 == ~E_12~0;~E_12~0 := 1; 102#L1319-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67#L586true assume 1 == ~m_pc~0; 1237#L587true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 781#L597true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 571#is_master_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 199#L1485true assume !(0 != activate_threads_~tmp~1#1); 1041#L1485-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1743#L605true assume !(1 == ~t1_pc~0); 1191#L605-2true is_transmit1_triggered_~__retres1~1#1 := 0; 412#L616true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 933#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1354#L1493true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 855#L1493-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 356#L624true assume 1 == ~t2_pc~0; 89#L625true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 462#L635true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1436#L1501true assume !(0 != activate_threads_~tmp___1~0#1); 1095#L1501-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 930#L643true assume !(1 == ~t3_pc~0); 777#L643-2true is_transmit3_triggered_~__retres1~3#1 := 0; 542#L654true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 911#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 255#L1509true assume !(0 != activate_threads_~tmp___2~0#1); 1286#L1509-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132#L662true assume 1 == ~t4_pc~0; 453#L663true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 113#L673true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 562#L1517true assume !(0 != activate_threads_~tmp___3~0#1); 61#L1517-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 378#L681true assume !(1 == ~t5_pc~0); 2#L681-2true is_transmit5_triggered_~__retres1~5#1 := 0; 600#L692true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1489#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1285#L1525true assume !(0 != activate_threads_~tmp___4~0#1); 262#L1525-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 732#L700true assume 1 == ~t6_pc~0; 1794#L701true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 128#L711true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 201#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 152#L1533true assume !(0 != activate_threads_~tmp___5~0#1); 1170#L1533-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1304#L719true assume 1 == ~t7_pc~0; 1597#L720true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1615#L730true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1738#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1408#L1541true assume !(0 != activate_threads_~tmp___6~0#1); 8#L1541-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1616#L738true assume !(1 == ~t8_pc~0); 887#L738-2true is_transmit8_triggered_~__retres1~8#1 := 0; 796#L749true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1433#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 616#L1549true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1214#L1549-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 952#L757true assume 1 == ~t9_pc~0; 1655#L758true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6#L768true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 235#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1068#L1557true assume !(0 != activate_threads_~tmp___8~0#1); 594#L1557-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1598#L776true assume !(1 == ~t10_pc~0); 1104#L776-2true is_transmit10_triggered_~__retres1~10#1 := 0; 202#L787true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1208#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 123#L1565true assume !(0 != activate_threads_~tmp___9~0#1); 770#L1565-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 103#L795true assume 1 == ~t11_pc~0; 273#L796true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1065#L806true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1347#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1336#L1573true assume !(0 != activate_threads_~tmp___10~0#1); 772#L1573-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 756#L814true assume !(1 == ~t12_pc~0); 910#L814-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1004#L825true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1324#L1581true assume !(0 != activate_threads_~tmp___11~0#1); 228#L1581-2true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1110#L1332true assume !(1 == ~M_E~0); 1498#L1332-2true assume !(1 == ~T1_E~0); 1532#L1337-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 697#L1342-1true assume !(1 == ~T3_E~0); 1440#L1347-1true assume !(1 == ~T4_E~0); 1152#L1352-1true assume !(1 == ~T5_E~0); 957#L1357-1true assume !(1 == ~T6_E~0); 391#L1362-1true assume !(1 == ~T7_E~0); 1224#L1367-1true assume !(1 == ~T8_E~0); 167#L1372-1true assume !(1 == ~T9_E~0); 496#L1377-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 342#L1382-1true assume !(1 == ~T11_E~0); 852#L1387-1true assume !(1 == ~T12_E~0); 1387#L1392-1true assume !(1 == ~E_M~0); 357#L1397-1true assume !(1 == ~E_1~0); 1504#L1402-1true assume !(1 == ~E_2~0); 175#L1407-1true assume !(1 == ~E_3~0); 1635#L1412-1true assume !(1 == ~E_4~0); 1064#L1417-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1806#L1422-1true assume !(1 == ~E_6~0); 1503#L1427-1true assume !(1 == ~E_7~0); 274#L1432-1true assume !(1 == ~E_8~0); 1393#L1437-1true assume !(1 == ~E_9~0); 995#L1442-1true assume !(1 == ~E_10~0); 1309#L1447-1true assume !(1 == ~E_11~0); 841#L1452-1true assume !(1 == ~E_12~0); 75#L1457-1true assume { :end_inline_reset_delta_events } true; 1441#L1803-2true [2023-11-26 11:47:31,120 INFO L750 eck$LassoCheckResult]: Loop: 1441#L1803-2true assume !false; 241#L1804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 280#L1169-1true assume false; 515#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 306#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 619#L1194-3true assume !(0 == ~M_E~0); 1653#L1194-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 156#L1199-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 886#L1204-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 290#L1209-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 12#L1214-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 681#L1219-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 411#L1224-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1801#L1229-3true assume !(0 == ~T8_E~0); 429#L1234-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 91#L1239-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 323#L1244-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 716#L1249-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1557#L1254-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1355#L1259-3true assume 0 == ~E_1~0;~E_1~0 := 1; 827#L1264-3true assume 0 == ~E_2~0;~E_2~0 := 1; 94#L1269-3true assume !(0 == ~E_3~0); 1621#L1274-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1439#L1279-3true assume 0 == ~E_5~0;~E_5~0 := 1; 410#L1284-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1494#L1289-3true assume 0 == ~E_7~0;~E_7~0 := 1; 397#L1294-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1675#L1299-3true assume 0 == ~E_9~0;~E_9~0 := 1; 660#L1304-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1018#L1309-3true assume !(0 == ~E_11~0); 343#L1314-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1754#L1319-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 346#L586-42true assume 1 == ~m_pc~0; 1045#L587-14true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 127#L597-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 380#is_master_triggered_returnLabel#15true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1431#L1485-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 425#L1485-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 895#L605-42true assume !(1 == ~t1_pc~0); 1759#L605-44true is_transmit1_triggered_~__retres1~1#1 := 0; 635#L616-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1651#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 426#L1493-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 476#L1493-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 431#L624-42true assume !(1 == ~t2_pc~0); 528#L624-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1450#L635-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 593#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1702#L1501-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 322#L1501-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1297#L643-42true assume !(1 == ~t3_pc~0); 978#L643-44true is_transmit3_triggered_~__retres1~3#1 := 0; 516#L654-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 901#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 407#L1509-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1005#L1509-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1321#L662-42true assume !(1 == ~t4_pc~0); 1374#L662-44true is_transmit4_triggered_~__retres1~4#1 := 0; 136#L673-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 976#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1474#L1517-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1419#L1517-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1338#L681-42true assume !(1 == ~t5_pc~0); 73#L681-44true is_transmit5_triggered_~__retres1~5#1 := 0; 754#L692-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 655#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1636#L1525-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1072#L1525-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 334#L700-42true assume !(1 == ~t6_pc~0); 221#L700-44true is_transmit6_triggered_~__retres1~6#1 := 0; 959#L711-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 181#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1086#L1533-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1706#L1533-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1460#L719-42true assume !(1 == ~t7_pc~0); 162#L719-44true is_transmit7_triggered_~__retres1~7#1 := 0; 372#L730-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 670#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 541#L1541-42true assume !(0 != activate_threads_~tmp___6~0#1); 381#L1541-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1445#L738-42true assume !(1 == ~t8_pc~0); 1211#L738-44true is_transmit8_triggered_~__retres1~8#1 := 0; 351#L749-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 785#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93#L1549-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 375#L1549-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1255#L757-42true assume 1 == ~t9_pc~0; 604#L758-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 182#L768-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1664#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 643#L1557-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 245#L1557-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1044#L776-42true assume !(1 == ~t10_pc~0); 968#L776-44true is_transmit10_triggered_~__retres1~10#1 := 0; 1031#L787-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 773#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1611#L1565-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1799#L1565-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 795#L795-42true assume 1 == ~t11_pc~0; 1463#L796-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 160#L806-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1412#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 210#L1573-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 387#L1573-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1125#L814-42true assume 1 == ~t12_pc~0; 1047#L815-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 118#L825-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 637#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26#L1581-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1755#L1581-44true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100#L1332-3true assume 1 == ~M_E~0;~M_E~0 := 2; 713#L1332-5true assume !(1 == ~T1_E~0); 88#L1337-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 563#L1342-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1039#L1347-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 688#L1352-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1204#L1357-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1793#L1362-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1658#L1367-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1625#L1372-3true assume !(1 == ~T9_E~0); 19#L1377-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 433#L1382-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 332#L1387-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1001#L1392-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1713#L1397-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1493#L1402-3true assume 1 == ~E_2~0;~E_2~0 := 2; 645#L1407-3true assume 1 == ~E_3~0;~E_3~0 := 2; 140#L1412-3true assume !(1 == ~E_4~0); 1242#L1417-3true assume 1 == ~E_5~0;~E_5~0 := 2; 576#L1422-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1197#L1427-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1395#L1432-3true assume 1 == ~E_8~0;~E_8~0 := 2; 875#L1437-3true assume 1 == ~E_9~0;~E_9~0 := 2; 662#L1442-3true assume 1 == ~E_10~0;~E_10~0 := 2; 889#L1447-3true assume 1 == ~E_11~0;~E_11~0 := 2; 43#L1452-3true assume !(1 == ~E_12~0); 1767#L1457-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 366#L914-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1404#L981-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 174#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 135#L1822true assume !(0 == start_simulation_~tmp~3#1); 745#L1822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 771#L914-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 270#L981-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 704#L1777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 798#L1784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1241#stop_simulation_returnLabel#1true start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1249#L1835true assume !(0 != start_simulation_~tmp___0~1#1); 1441#L1803-2true [2023-11-26 11:47:31,129 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:31,130 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2023-11-26 11:47:31,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:31,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302875804] [2023-11-26 11:47:31,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:31,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:31,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:31,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:31,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:31,635 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302875804] [2023-11-26 11:47:31,636 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [302875804] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:31,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:31,637 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:31,638 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [837331736] [2023-11-26 11:47:31,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:31,652 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:31,652 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:31,653 INFO L85 PathProgramCache]: Analyzing trace with hash -1408546403, now seen corresponding path program 1 times [2023-11-26 11:47:31,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:31,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814461732] [2023-11-26 11:47:31,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:31,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:31,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:31,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:31,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:31,796 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814461732] [2023-11-26 11:47:31,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814461732] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:31,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:31,797 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:31,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140461557] [2023-11-26 11:47:31,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:31,799 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:31,800 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:31,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-26 11:47:31,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-26 11:47:31,839 INFO L87 Difference]: Start difference. First operand has 1805 states, 1804 states have (on average 1.4950110864745012) internal successors, (2697), 1804 states have internal predecessors, (2697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:31,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:31,925 INFO L93 Difference]: Finished difference Result 1803 states and 2664 transitions. [2023-11-26 11:47:31,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2664 transitions. [2023-11-26 11:47:31,959 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:31,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1798 states and 2659 transitions. [2023-11-26 11:47:31,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:31,989 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:31,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2659 transitions. [2023-11-26 11:47:32,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:32,003 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2659 transitions. [2023-11-26 11:47:32,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2659 transitions. [2023-11-26 11:47:32,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:32,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4788654060066742) internal successors, (2659), 1797 states have internal predecessors, (2659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:32,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2659 transitions. [2023-11-26 11:47:32,124 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2659 transitions. [2023-11-26 11:47:32,125 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-26 11:47:32,130 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2659 transitions. [2023-11-26 11:47:32,131 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:47:32,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2659 transitions. [2023-11-26 11:47:32,146 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:32,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:32,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:32,154 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:32,154 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:32,157 INFO L748 eck$LassoCheckResult]: Stem: 3859#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3860#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4794#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4795#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3929#L841 assume !(1 == ~m_i~0);~m_st~0 := 2; 3930#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3834#L846-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3835#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5122#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4475#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4476#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4367#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4368#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4876#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4877#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4126#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4127#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4561#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4562#L1194 assume !(0 == ~M_E~0); 4714#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4715#L1199-1 assume !(0 == ~T2_E~0); 5001#L1204-1 assume !(0 == ~T3_E~0); 4926#L1209-1 assume !(0 == ~T4_E~0); 4927#L1214-1 assume !(0 == ~T5_E~0); 5325#L1219-1 assume !(0 == ~T6_E~0); 5411#L1224-1 assume !(0 == ~T7_E~0); 4200#L1229-1 assume !(0 == ~T8_E~0); 3754#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3755#L1239-1 assume !(0 == ~T10_E~0); 3797#L1244-1 assume !(0 == ~T11_E~0); 3798#L1249-1 assume !(0 == ~T12_E~0); 4505#L1254-1 assume !(0 == ~E_M~0); 3696#L1259-1 assume !(0 == ~E_1~0); 3661#L1264-1 assume !(0 == ~E_2~0); 3662#L1269-1 assume !(0 == ~E_3~0); 5413#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5357#L1279-1 assume !(0 == ~E_5~0); 3870#L1284-1 assume !(0 == ~E_6~0); 3871#L1289-1 assume !(0 == ~E_7~0); 4568#L1294-1 assume !(0 == ~E_8~0); 4569#L1299-1 assume !(0 == ~E_9~0); 4580#L1304-1 assume !(0 == ~E_10~0); 5404#L1309-1 assume !(0 == ~E_11~0); 5409#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3827#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3751#L586 assume 1 == ~m_pc~0; 3752#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3819#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4640#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4026#L1485 assume !(0 != activate_threads_~tmp~1#1); 4027#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5128#L605 assume !(1 == ~t1_pc~0); 4654#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4396#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4397#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5040#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4975#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4304#L624 assume 1 == ~t2_pc~0; 3801#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3802#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4053#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4054#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 5160#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5038#L643 assume !(1 == ~t3_pc~0); 4896#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4598#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4599#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4133#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 4134#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3891#L662 assume 1 == ~t4_pc~0; 3892#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3850#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3713#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3714#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 3740#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3741#L681 assume !(1 == ~t5_pc~0); 3617#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3618#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4680#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5286#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 4145#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4146#L700 assume 1 == ~t6_pc~0; 4856#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3883#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3884#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3931#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 3932#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5214#L719 assume 1 == ~t7_pc~0; 5295#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4102#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5401#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5343#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 3631#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3632#L738 assume !(1 == ~t8_pc~0); 5008#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4917#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4918#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4710#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4711#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5060#L757 assume 1 == ~t9_pc~0; 5061#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3626#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3627#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4100#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 4672#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4673#L776 assume !(1 == ~t10_pc~0); 3648#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3647#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4030#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3872#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 3873#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3828#L795 assume 1 == ~t11_pc~0; 3829#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4165#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5142#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5313#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 4890#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4880#L814 assume !(1 == ~t12_pc~0); 4740#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4741#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3674#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3675#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 4084#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4085#L1332 assume !(1 == ~M_E~0); 5173#L1332-2 assume !(1 == ~T1_E~0); 5375#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4811#L1342-1 assume !(1 == ~T3_E~0); 4812#L1347-1 assume !(1 == ~T4_E~0); 5201#L1352-1 assume !(1 == ~T5_E~0); 5066#L1357-1 assume !(1 == ~T6_E~0); 4365#L1362-1 assume !(1 == ~T7_E~0); 4366#L1367-1 assume !(1 == ~T8_E~0); 3965#L1372-1 assume !(1 == ~T9_E~0); 3966#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4276#L1382-1 assume !(1 == ~T11_E~0); 4277#L1387-1 assume !(1 == ~T12_E~0); 4973#L1392-1 assume !(1 == ~E_M~0); 4305#L1397-1 assume !(1 == ~E_1~0); 4306#L1402-1 assume !(1 == ~E_2~0); 3980#L1407-1 assume !(1 == ~E_3~0); 3981#L1412-1 assume !(1 == ~E_4~0); 5140#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5141#L1422-1 assume !(1 == ~E_6~0); 5377#L1427-1 assume !(1 == ~E_7~0); 4166#L1432-1 assume !(1 == ~E_8~0); 4167#L1437-1 assume !(1 == ~E_9~0); 5093#L1442-1 assume !(1 == ~E_10~0); 5094#L1447-1 assume !(1 == ~E_11~0); 4965#L1452-1 assume !(1 == ~E_12~0); 3771#L1457-1 assume { :end_inline_reset_delta_events } true; 3772#L1803-2 [2023-11-26 11:47:32,160 INFO L750 eck$LassoCheckResult]: Loop: 3772#L1803-2 assume !false; 4108#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4057#L1169-1 assume !false; 4177#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4347#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3836#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3837#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5181#L996 assume !(0 != eval_~tmp~0#1); 4558#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4222#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4223#L1194-3 assume !(0 == ~M_E~0); 4716#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3939#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3940#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4196#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3640#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3641#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4394#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4395#L1229-3 assume !(0 == ~T8_E~0); 4429#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3807#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3808#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4245#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4835#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5319#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4948#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3813#L1269-3 assume !(0 == ~E_3~0); 3814#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5354#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4392#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4393#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4374#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4375#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4767#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4768#L1309-3 assume !(0 == ~E_11~0); 4278#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4279#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4284#L586-42 assume !(1 == ~m_pc~0); 4285#L586-44 is_master_triggered_~__retres1~0#1 := 0; 3881#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3882#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4348#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4422#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4423#L605-42 assume 1 == ~t1_pc~0; 5013#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4733#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4734#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4424#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4425#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4433#L624-42 assume !(1 == ~t2_pc~0); 4434#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 4578#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4670#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4671#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4243#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4244#L643-42 assume 1 == ~t3_pc~0; 4602#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4559#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4560#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4389#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4390#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5103#L662-42 assume !(1 == ~t4_pc~0); 5306#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3902#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3903#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5081#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5347#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5314#L681-42 assume 1 == ~t5_pc~0; 4612#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3768#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4760#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4761#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5149#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4262#L700-42 assume 1 == ~t6_pc~0; 4263#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4072#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3992#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3993#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5156#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5364#L719-42 assume !(1 == ~t7_pc~0); 3953#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 3954#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4334#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4597#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 4349#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4350#L738-42 assume 1 == ~t8_pc~0; 4548#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4293#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4294#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3811#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3812#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4343#L757-42 assume 1 == ~t9_pc~0; 4686#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3994#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3995#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4747#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4113#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4114#L776-42 assume !(1 == ~t10_pc~0); 5073#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 5074#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4891#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4892#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5399#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4914#L795-42 assume !(1 == ~t11_pc~0); 4915#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3948#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3949#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4047#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4048#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4359#L814-42 assume !(1 == ~t12_pc~0); 4228#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 3861#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3862#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3669#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3670#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3823#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3824#L1332-5 assume !(1 == ~T1_E~0); 3799#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3800#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4629#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4799#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4800#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5235#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5407#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5403#L1372-3 assume !(1 == ~T9_E~0); 3655#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3656#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4259#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4260#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5099#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5374#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4749#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3907#L1412-3 assume !(1 == ~E_4~0); 3908#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4649#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4650#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5232#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4994#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4769#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4770#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3703#L1452-3 assume !(1 == ~E_12~0); 3704#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4322#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4164#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3979#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 3899#L1822 assume !(0 == start_simulation_~tmp~3#1); 3900#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4865#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4160#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3657#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 3658#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4821#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4920#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 5260#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 3772#L1803-2 [2023-11-26 11:47:32,161 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:32,161 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2023-11-26 11:47:32,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:32,162 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855063326] [2023-11-26 11:47:32,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:32,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:32,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:32,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:32,283 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:32,283 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855063326] [2023-11-26 11:47:32,283 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855063326] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:32,283 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:32,283 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:32,284 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086285887] [2023-11-26 11:47:32,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:32,284 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:32,285 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:32,285 INFO L85 PathProgramCache]: Analyzing trace with hash 1102292536, now seen corresponding path program 1 times [2023-11-26 11:47:32,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:32,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [325119040] [2023-11-26 11:47:32,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:32,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:32,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:32,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:32,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:32,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [325119040] [2023-11-26 11:47:32,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [325119040] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:32,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:32,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:32,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [516269781] [2023-11-26 11:47:32,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:32,461 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:32,462 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:32,462 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:32,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:32,463 INFO L87 Difference]: Start difference. First operand 1798 states and 2659 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:32,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:32,522 INFO L93 Difference]: Finished difference Result 1798 states and 2658 transitions. [2023-11-26 11:47:32,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2658 transitions. [2023-11-26 11:47:32,539 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:32,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2658 transitions. [2023-11-26 11:47:32,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:32,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:32,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2658 transitions. [2023-11-26 11:47:32,560 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:32,560 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2658 transitions. [2023-11-26 11:47:32,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2658 transitions. [2023-11-26 11:47:32,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:32,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.478309232480534) internal successors, (2658), 1797 states have internal predecessors, (2658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:32,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2658 transitions. [2023-11-26 11:47:32,602 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2658 transitions. [2023-11-26 11:47:32,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:32,604 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2658 transitions. [2023-11-26 11:47:32,604 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:47:32,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2658 transitions. [2023-11-26 11:47:32,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:32,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:32,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:32,619 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:32,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:32,620 INFO L748 eck$LassoCheckResult]: Stem: 7462#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7463#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8397#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8398#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7532#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 7533#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7437#L846-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7438#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8725#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8078#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8079#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7970#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7971#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8479#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8480#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7729#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7730#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8164#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8165#L1194 assume !(0 == ~M_E~0); 8317#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8318#L1199-1 assume !(0 == ~T2_E~0); 8604#L1204-1 assume !(0 == ~T3_E~0); 8529#L1209-1 assume !(0 == ~T4_E~0); 8530#L1214-1 assume !(0 == ~T5_E~0); 8928#L1219-1 assume !(0 == ~T6_E~0); 9014#L1224-1 assume !(0 == ~T7_E~0); 7803#L1229-1 assume !(0 == ~T8_E~0); 7357#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7358#L1239-1 assume !(0 == ~T10_E~0); 7400#L1244-1 assume !(0 == ~T11_E~0); 7401#L1249-1 assume !(0 == ~T12_E~0); 8108#L1254-1 assume !(0 == ~E_M~0); 7299#L1259-1 assume !(0 == ~E_1~0); 7264#L1264-1 assume !(0 == ~E_2~0); 7265#L1269-1 assume !(0 == ~E_3~0); 9016#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8960#L1279-1 assume !(0 == ~E_5~0); 7473#L1284-1 assume !(0 == ~E_6~0); 7474#L1289-1 assume !(0 == ~E_7~0); 8171#L1294-1 assume !(0 == ~E_8~0); 8172#L1299-1 assume !(0 == ~E_9~0); 8183#L1304-1 assume !(0 == ~E_10~0); 9007#L1309-1 assume !(0 == ~E_11~0); 9012#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 7430#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7354#L586 assume 1 == ~m_pc~0; 7355#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7422#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8243#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7629#L1485 assume !(0 != activate_threads_~tmp~1#1); 7630#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8731#L605 assume !(1 == ~t1_pc~0); 8257#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7999#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8000#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8643#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8578#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7907#L624 assume 1 == ~t2_pc~0; 7404#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7405#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7656#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7657#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 8763#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8641#L643 assume !(1 == ~t3_pc~0); 8499#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8201#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8202#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7736#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 7737#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7494#L662 assume 1 == ~t4_pc~0; 7495#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7453#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7316#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7317#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 7343#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7344#L681 assume !(1 == ~t5_pc~0); 7220#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7221#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8283#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8889#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 7748#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7749#L700 assume 1 == ~t6_pc~0; 8459#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7486#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7487#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7534#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 7535#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8817#L719 assume 1 == ~t7_pc~0; 8898#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7705#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9004#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8946#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 7234#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7235#L738 assume !(1 == ~t8_pc~0); 8611#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8520#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8521#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8313#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8314#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8663#L757 assume 1 == ~t9_pc~0; 8664#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7229#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7230#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7703#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 8275#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8276#L776 assume !(1 == ~t10_pc~0); 7251#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7250#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7633#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7475#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 7476#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7431#L795 assume 1 == ~t11_pc~0; 7432#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7768#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8745#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8916#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 8493#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8483#L814 assume !(1 == ~t12_pc~0); 8343#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8344#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7277#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7278#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 7687#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7688#L1332 assume !(1 == ~M_E~0); 8776#L1332-2 assume !(1 == ~T1_E~0); 8978#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8414#L1342-1 assume !(1 == ~T3_E~0); 8415#L1347-1 assume !(1 == ~T4_E~0); 8804#L1352-1 assume !(1 == ~T5_E~0); 8669#L1357-1 assume !(1 == ~T6_E~0); 7968#L1362-1 assume !(1 == ~T7_E~0); 7969#L1367-1 assume !(1 == ~T8_E~0); 7568#L1372-1 assume !(1 == ~T9_E~0); 7569#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7879#L1382-1 assume !(1 == ~T11_E~0); 7880#L1387-1 assume !(1 == ~T12_E~0); 8576#L1392-1 assume !(1 == ~E_M~0); 7908#L1397-1 assume !(1 == ~E_1~0); 7909#L1402-1 assume !(1 == ~E_2~0); 7583#L1407-1 assume !(1 == ~E_3~0); 7584#L1412-1 assume !(1 == ~E_4~0); 8743#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 8744#L1422-1 assume !(1 == ~E_6~0); 8980#L1427-1 assume !(1 == ~E_7~0); 7769#L1432-1 assume !(1 == ~E_8~0); 7770#L1437-1 assume !(1 == ~E_9~0); 8696#L1442-1 assume !(1 == ~E_10~0); 8697#L1447-1 assume !(1 == ~E_11~0); 8568#L1452-1 assume !(1 == ~E_12~0); 7374#L1457-1 assume { :end_inline_reset_delta_events } true; 7375#L1803-2 [2023-11-26 11:47:32,621 INFO L750 eck$LassoCheckResult]: Loop: 7375#L1803-2 assume !false; 7711#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7660#L1169-1 assume !false; 7780#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7950#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7439#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7440#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8784#L996 assume !(0 != eval_~tmp~0#1); 8161#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7825#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7826#L1194-3 assume !(0 == ~M_E~0); 8319#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7542#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7543#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7799#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7243#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7244#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7997#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7998#L1229-3 assume !(0 == ~T8_E~0); 8032#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7410#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7411#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7848#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8438#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8922#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8551#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7416#L1269-3 assume !(0 == ~E_3~0); 7417#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8957#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7995#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7996#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7977#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7978#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8370#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8371#L1309-3 assume !(0 == ~E_11~0); 7881#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7882#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7887#L586-42 assume !(1 == ~m_pc~0); 7888#L586-44 is_master_triggered_~__retres1~0#1 := 0; 7484#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7485#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7951#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8025#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8026#L605-42 assume 1 == ~t1_pc~0; 8616#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8336#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8337#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8027#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8028#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8036#L624-42 assume !(1 == ~t2_pc~0); 8037#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 8181#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8273#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8274#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7846#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7847#L643-42 assume 1 == ~t3_pc~0; 8205#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8162#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8163#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7992#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7993#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8706#L662-42 assume !(1 == ~t4_pc~0); 8909#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 7505#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7506#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8684#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8950#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8917#L681-42 assume 1 == ~t5_pc~0; 8215#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7371#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8363#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8364#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8752#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7865#L700-42 assume 1 == ~t6_pc~0; 7866#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7675#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7595#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7596#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8759#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8967#L719-42 assume !(1 == ~t7_pc~0); 7556#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 7557#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7937#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8200#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 7952#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7953#L738-42 assume 1 == ~t8_pc~0; 8151#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7896#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7897#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7414#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7415#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7946#L757-42 assume 1 == ~t9_pc~0; 8289#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7597#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7598#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8350#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7716#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7717#L776-42 assume !(1 == ~t10_pc~0); 8676#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 8677#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8494#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8495#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9002#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8517#L795-42 assume !(1 == ~t11_pc~0); 8518#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 7551#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7552#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7650#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7651#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7962#L814-42 assume !(1 == ~t12_pc~0); 7831#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 7464#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7465#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7272#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7273#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7426#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7427#L1332-5 assume !(1 == ~T1_E~0); 7402#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7403#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8232#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8402#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8403#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8838#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9010#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9006#L1372-3 assume !(1 == ~T9_E~0); 7258#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7259#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7862#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 7863#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8702#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8977#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8352#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7510#L1412-3 assume !(1 == ~E_4~0); 7511#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8252#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8253#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8835#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8597#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 8372#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8373#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7306#L1452-3 assume !(1 == ~E_12~0); 7307#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7925#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7767#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7582#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7502#L1822 assume !(0 == start_simulation_~tmp~3#1); 7503#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8468#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7763#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7260#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 7261#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8424#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8523#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8863#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 7375#L1803-2 [2023-11-26 11:47:32,622 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:32,622 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2023-11-26 11:47:32,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:32,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457193309] [2023-11-26 11:47:32,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:32,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:32,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:32,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:32,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:32,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [457193309] [2023-11-26 11:47:32,733 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [457193309] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:32,733 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:32,733 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:32,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514792076] [2023-11-26 11:47:32,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:32,735 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:32,735 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:32,735 INFO L85 PathProgramCache]: Analyzing trace with hash 1102292536, now seen corresponding path program 2 times [2023-11-26 11:47:32,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:32,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994095363] [2023-11-26 11:47:32,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:32,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:32,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:32,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:32,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:32,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [994095363] [2023-11-26 11:47:32,850 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [994095363] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:32,850 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:32,851 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:32,851 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293578961] [2023-11-26 11:47:32,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:32,852 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:32,853 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:32,853 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:32,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:32,854 INFO L87 Difference]: Start difference. First operand 1798 states and 2658 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:32,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:32,908 INFO L93 Difference]: Finished difference Result 1798 states and 2657 transitions. [2023-11-26 11:47:32,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2657 transitions. [2023-11-26 11:47:32,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:32,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2657 transitions. [2023-11-26 11:47:32,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:32,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:32,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2657 transitions. [2023-11-26 11:47:32,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:32,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2657 transitions. [2023-11-26 11:47:32,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2657 transitions. [2023-11-26 11:47:32,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:32,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4777530589543937) internal successors, (2657), 1797 states have internal predecessors, (2657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:32,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2657 transitions. [2023-11-26 11:47:32,986 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2657 transitions. [2023-11-26 11:47:32,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:32,988 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2657 transitions. [2023-11-26 11:47:32,988 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:47:32,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2657 transitions. [2023-11-26 11:47:33,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:33,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:33,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:33,006 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:33,006 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:33,007 INFO L748 eck$LassoCheckResult]: Stem: 11065#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11066#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 12000#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12001#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11135#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 11136#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11040#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11041#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12328#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11681#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11682#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11573#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11574#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12082#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12083#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11332#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11333#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11767#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11768#L1194 assume !(0 == ~M_E~0); 11920#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11921#L1199-1 assume !(0 == ~T2_E~0); 12207#L1204-1 assume !(0 == ~T3_E~0); 12132#L1209-1 assume !(0 == ~T4_E~0); 12133#L1214-1 assume !(0 == ~T5_E~0); 12531#L1219-1 assume !(0 == ~T6_E~0); 12617#L1224-1 assume !(0 == ~T7_E~0); 11406#L1229-1 assume !(0 == ~T8_E~0); 10960#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10961#L1239-1 assume !(0 == ~T10_E~0); 11003#L1244-1 assume !(0 == ~T11_E~0); 11004#L1249-1 assume !(0 == ~T12_E~0); 11711#L1254-1 assume !(0 == ~E_M~0); 10902#L1259-1 assume !(0 == ~E_1~0); 10867#L1264-1 assume !(0 == ~E_2~0); 10868#L1269-1 assume !(0 == ~E_3~0); 12619#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12563#L1279-1 assume !(0 == ~E_5~0); 11076#L1284-1 assume !(0 == ~E_6~0); 11077#L1289-1 assume !(0 == ~E_7~0); 11774#L1294-1 assume !(0 == ~E_8~0); 11775#L1299-1 assume !(0 == ~E_9~0); 11786#L1304-1 assume !(0 == ~E_10~0); 12610#L1309-1 assume !(0 == ~E_11~0); 12615#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11033#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10957#L586 assume 1 == ~m_pc~0; 10958#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11025#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11846#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11232#L1485 assume !(0 != activate_threads_~tmp~1#1); 11233#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12334#L605 assume !(1 == ~t1_pc~0); 11860#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11602#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11603#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12246#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12181#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11510#L624 assume 1 == ~t2_pc~0; 11007#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11008#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11259#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11260#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 12366#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12244#L643 assume !(1 == ~t3_pc~0); 12102#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11804#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11805#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11339#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 11340#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11097#L662 assume 1 == ~t4_pc~0; 11098#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11056#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10919#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10920#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 10946#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10947#L681 assume !(1 == ~t5_pc~0); 10823#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10824#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11886#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12492#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 11351#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11352#L700 assume 1 == ~t6_pc~0; 12062#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11089#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11090#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11137#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 11138#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12420#L719 assume 1 == ~t7_pc~0; 12501#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11308#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12607#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12549#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 10837#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10838#L738 assume !(1 == ~t8_pc~0); 12214#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12123#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12124#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11916#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11917#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12266#L757 assume 1 == ~t9_pc~0; 12267#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10832#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10833#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11306#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 11878#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11879#L776 assume !(1 == ~t10_pc~0); 10854#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10853#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11236#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11078#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 11079#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11034#L795 assume 1 == ~t11_pc~0; 11035#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11371#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12348#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12519#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 12096#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12086#L814 assume !(1 == ~t12_pc~0); 11946#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11947#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10880#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10881#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 11290#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11291#L1332 assume !(1 == ~M_E~0); 12379#L1332-2 assume !(1 == ~T1_E~0); 12581#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12017#L1342-1 assume !(1 == ~T3_E~0); 12018#L1347-1 assume !(1 == ~T4_E~0); 12407#L1352-1 assume !(1 == ~T5_E~0); 12272#L1357-1 assume !(1 == ~T6_E~0); 11571#L1362-1 assume !(1 == ~T7_E~0); 11572#L1367-1 assume !(1 == ~T8_E~0); 11171#L1372-1 assume !(1 == ~T9_E~0); 11172#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11482#L1382-1 assume !(1 == ~T11_E~0); 11483#L1387-1 assume !(1 == ~T12_E~0); 12179#L1392-1 assume !(1 == ~E_M~0); 11511#L1397-1 assume !(1 == ~E_1~0); 11512#L1402-1 assume !(1 == ~E_2~0); 11186#L1407-1 assume !(1 == ~E_3~0); 11187#L1412-1 assume !(1 == ~E_4~0); 12346#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 12347#L1422-1 assume !(1 == ~E_6~0); 12583#L1427-1 assume !(1 == ~E_7~0); 11372#L1432-1 assume !(1 == ~E_8~0); 11373#L1437-1 assume !(1 == ~E_9~0); 12299#L1442-1 assume !(1 == ~E_10~0); 12300#L1447-1 assume !(1 == ~E_11~0); 12171#L1452-1 assume !(1 == ~E_12~0); 10977#L1457-1 assume { :end_inline_reset_delta_events } true; 10978#L1803-2 [2023-11-26 11:47:33,007 INFO L750 eck$LassoCheckResult]: Loop: 10978#L1803-2 assume !false; 11314#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11263#L1169-1 assume !false; 11383#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11553#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11042#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11043#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12387#L996 assume !(0 != eval_~tmp~0#1); 11764#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11429#L1194-3 assume !(0 == ~M_E~0); 11922#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11145#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11146#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11402#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10846#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10847#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11600#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11601#L1229-3 assume !(0 == ~T8_E~0); 11635#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11013#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11014#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11451#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12041#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12525#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12154#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11019#L1269-3 assume !(0 == ~E_3~0); 11020#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12560#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11598#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11599#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11580#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11581#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11973#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11974#L1309-3 assume !(0 == ~E_11~0); 11484#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11485#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11490#L586-42 assume !(1 == ~m_pc~0); 11491#L586-44 is_master_triggered_~__retres1~0#1 := 0; 11087#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11088#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11554#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11628#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11629#L605-42 assume 1 == ~t1_pc~0; 12219#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11939#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11940#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11630#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11631#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11639#L624-42 assume !(1 == ~t2_pc~0); 11640#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 11784#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11876#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11877#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11449#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11450#L643-42 assume 1 == ~t3_pc~0; 11808#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11765#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11766#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11595#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11596#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12309#L662-42 assume !(1 == ~t4_pc~0); 12512#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 11108#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11109#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12287#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12553#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12520#L681-42 assume 1 == ~t5_pc~0; 11818#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10974#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11966#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11967#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12355#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11468#L700-42 assume 1 == ~t6_pc~0; 11469#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11278#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11198#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11199#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12362#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12570#L719-42 assume !(1 == ~t7_pc~0); 11159#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 11160#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11540#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11803#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 11555#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11556#L738-42 assume 1 == ~t8_pc~0; 11754#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11499#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11500#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11017#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11018#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11549#L757-42 assume 1 == ~t9_pc~0; 11892#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11200#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11201#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11953#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11319#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11320#L776-42 assume !(1 == ~t10_pc~0); 12279#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 12280#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12097#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12098#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12605#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12120#L795-42 assume !(1 == ~t11_pc~0); 12121#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 11154#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11155#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11253#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11254#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11565#L814-42 assume 1 == ~t12_pc~0; 12337#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11067#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11068#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10875#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10876#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11029#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11030#L1332-5 assume !(1 == ~T1_E~0); 11005#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11006#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11835#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12005#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12006#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12441#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12613#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12609#L1372-3 assume !(1 == ~T9_E~0); 10861#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10862#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11465#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11466#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12305#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12580#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11955#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11113#L1412-3 assume !(1 == ~E_4~0); 11114#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11855#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11856#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12438#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12200#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11975#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11976#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10909#L1452-3 assume !(1 == ~E_12~0); 10910#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11528#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11370#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11185#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 11105#L1822 assume !(0 == start_simulation_~tmp~3#1); 11106#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12071#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11366#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10863#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 10864#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12027#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12126#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12466#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 10978#L1803-2 [2023-11-26 11:47:33,008 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:33,009 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2023-11-26 11:47:33,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:33,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349130606] [2023-11-26 11:47:33,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:33,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:33,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:33,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:33,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:33,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1349130606] [2023-11-26 11:47:33,106 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1349130606] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:33,106 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:33,106 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:33,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005558140] [2023-11-26 11:47:33,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:33,112 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:33,112 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:33,113 INFO L85 PathProgramCache]: Analyzing trace with hash 1975770231, now seen corresponding path program 1 times [2023-11-26 11:47:33,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:33,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1032135101] [2023-11-26 11:47:33,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:33,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:33,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:33,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:33,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:33,225 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1032135101] [2023-11-26 11:47:33,225 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1032135101] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:33,225 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:33,225 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:33,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057975707] [2023-11-26 11:47:33,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:33,226 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:33,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:33,227 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:33,227 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:33,227 INFO L87 Difference]: Start difference. First operand 1798 states and 2657 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:33,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:33,279 INFO L93 Difference]: Finished difference Result 1798 states and 2656 transitions. [2023-11-26 11:47:33,279 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2656 transitions. [2023-11-26 11:47:33,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:33,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2656 transitions. [2023-11-26 11:47:33,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:33,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:33,313 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2656 transitions. [2023-11-26 11:47:33,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:33,317 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2656 transitions. [2023-11-26 11:47:33,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2656 transitions. [2023-11-26 11:47:33,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:33,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4771968854282536) internal successors, (2656), 1797 states have internal predecessors, (2656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:33,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2656 transitions. [2023-11-26 11:47:33,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2656 transitions. [2023-11-26 11:47:33,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:33,363 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2656 transitions. [2023-11-26 11:47:33,363 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:47:33,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2656 transitions. [2023-11-26 11:47:33,374 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:33,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:33,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:33,378 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:33,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:33,383 INFO L748 eck$LassoCheckResult]: Stem: 14668#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 14669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15603#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15604#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14738#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 14739#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14643#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14644#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15931#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15284#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15285#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15176#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15177#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15685#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15686#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14935#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14936#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15370#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15371#L1194 assume !(0 == ~M_E~0); 15523#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15524#L1199-1 assume !(0 == ~T2_E~0); 15810#L1204-1 assume !(0 == ~T3_E~0); 15735#L1209-1 assume !(0 == ~T4_E~0); 15736#L1214-1 assume !(0 == ~T5_E~0); 16134#L1219-1 assume !(0 == ~T6_E~0); 16220#L1224-1 assume !(0 == ~T7_E~0); 15009#L1229-1 assume !(0 == ~T8_E~0); 14563#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14564#L1239-1 assume !(0 == ~T10_E~0); 14606#L1244-1 assume !(0 == ~T11_E~0); 14607#L1249-1 assume !(0 == ~T12_E~0); 15314#L1254-1 assume !(0 == ~E_M~0); 14505#L1259-1 assume !(0 == ~E_1~0); 14470#L1264-1 assume !(0 == ~E_2~0); 14471#L1269-1 assume !(0 == ~E_3~0); 16222#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16166#L1279-1 assume !(0 == ~E_5~0); 14679#L1284-1 assume !(0 == ~E_6~0); 14680#L1289-1 assume !(0 == ~E_7~0); 15377#L1294-1 assume !(0 == ~E_8~0); 15378#L1299-1 assume !(0 == ~E_9~0); 15389#L1304-1 assume !(0 == ~E_10~0); 16213#L1309-1 assume !(0 == ~E_11~0); 16218#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 14636#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14560#L586 assume 1 == ~m_pc~0; 14561#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14628#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15449#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14835#L1485 assume !(0 != activate_threads_~tmp~1#1); 14836#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15937#L605 assume !(1 == ~t1_pc~0); 15463#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15205#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15849#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15784#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15113#L624 assume 1 == ~t2_pc~0; 14610#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14611#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14862#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14863#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 15969#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15847#L643 assume !(1 == ~t3_pc~0); 15705#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15407#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15408#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14942#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 14943#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14700#L662 assume 1 == ~t4_pc~0; 14701#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14659#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14522#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14523#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 14549#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14550#L681 assume !(1 == ~t5_pc~0); 14426#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14427#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15489#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16095#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 14954#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14955#L700 assume 1 == ~t6_pc~0; 15665#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14692#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14693#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14740#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 14741#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16023#L719 assume 1 == ~t7_pc~0; 16104#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14911#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16210#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16152#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 14440#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14441#L738 assume !(1 == ~t8_pc~0); 15817#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15726#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15727#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15519#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15520#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15869#L757 assume 1 == ~t9_pc~0; 15870#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14435#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14436#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14909#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 15481#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15482#L776 assume !(1 == ~t10_pc~0); 14457#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14456#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14839#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14681#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 14682#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14637#L795 assume 1 == ~t11_pc~0; 14638#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14974#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15951#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16122#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 15699#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15689#L814 assume !(1 == ~t12_pc~0); 15549#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15550#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14483#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14484#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 14893#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14894#L1332 assume !(1 == ~M_E~0); 15982#L1332-2 assume !(1 == ~T1_E~0); 16184#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15620#L1342-1 assume !(1 == ~T3_E~0); 15621#L1347-1 assume !(1 == ~T4_E~0); 16010#L1352-1 assume !(1 == ~T5_E~0); 15875#L1357-1 assume !(1 == ~T6_E~0); 15174#L1362-1 assume !(1 == ~T7_E~0); 15175#L1367-1 assume !(1 == ~T8_E~0); 14774#L1372-1 assume !(1 == ~T9_E~0); 14775#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15085#L1382-1 assume !(1 == ~T11_E~0); 15086#L1387-1 assume !(1 == ~T12_E~0); 15782#L1392-1 assume !(1 == ~E_M~0); 15114#L1397-1 assume !(1 == ~E_1~0); 15115#L1402-1 assume !(1 == ~E_2~0); 14789#L1407-1 assume !(1 == ~E_3~0); 14790#L1412-1 assume !(1 == ~E_4~0); 15949#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15950#L1422-1 assume !(1 == ~E_6~0); 16186#L1427-1 assume !(1 == ~E_7~0); 14975#L1432-1 assume !(1 == ~E_8~0); 14976#L1437-1 assume !(1 == ~E_9~0); 15902#L1442-1 assume !(1 == ~E_10~0); 15903#L1447-1 assume !(1 == ~E_11~0); 15774#L1452-1 assume !(1 == ~E_12~0); 14580#L1457-1 assume { :end_inline_reset_delta_events } true; 14581#L1803-2 [2023-11-26 11:47:33,384 INFO L750 eck$LassoCheckResult]: Loop: 14581#L1803-2 assume !false; 14917#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14866#L1169-1 assume !false; 14986#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15156#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14645#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14646#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15990#L996 assume !(0 != eval_~tmp~0#1); 15367#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15031#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15032#L1194-3 assume !(0 == ~M_E~0); 15525#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14748#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14749#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15005#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14449#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14450#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15203#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15204#L1229-3 assume !(0 == ~T8_E~0); 15238#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14616#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14617#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15054#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 15644#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16128#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15757#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14622#L1269-3 assume !(0 == ~E_3~0); 14623#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16163#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15201#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15202#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15183#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15184#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15576#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15577#L1309-3 assume !(0 == ~E_11~0); 15087#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 15088#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15093#L586-42 assume !(1 == ~m_pc~0); 15094#L586-44 is_master_triggered_~__retres1~0#1 := 0; 14690#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14691#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15157#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15231#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15232#L605-42 assume 1 == ~t1_pc~0; 15822#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15542#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15543#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15233#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15234#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15242#L624-42 assume !(1 == ~t2_pc~0); 15243#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 15387#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15479#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15480#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15052#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15053#L643-42 assume 1 == ~t3_pc~0; 15411#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15368#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15369#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15198#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15199#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15912#L662-42 assume !(1 == ~t4_pc~0); 16115#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 14711#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14712#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15890#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16156#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16123#L681-42 assume !(1 == ~t5_pc~0); 14576#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 14577#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15569#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15570#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15958#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15071#L700-42 assume 1 == ~t6_pc~0; 15072#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14881#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14801#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14802#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15965#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16173#L719-42 assume 1 == ~t7_pc~0; 15682#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14763#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15143#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15406#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 15158#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15159#L738-42 assume 1 == ~t8_pc~0; 15357#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15102#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15103#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14620#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14621#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15152#L757-42 assume 1 == ~t9_pc~0; 15495#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14803#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14804#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15556#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14922#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14923#L776-42 assume !(1 == ~t10_pc~0); 15882#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 15883#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15700#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15701#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16208#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15723#L795-42 assume !(1 == ~t11_pc~0); 15724#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 14757#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14758#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14856#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14857#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15168#L814-42 assume 1 == ~t12_pc~0; 15940#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 14670#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14671#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14478#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14479#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14632#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14633#L1332-5 assume !(1 == ~T1_E~0); 14608#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14609#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15438#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15608#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15609#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16044#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16216#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16212#L1372-3 assume !(1 == ~T9_E~0); 14464#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14465#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15068#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15069#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15908#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16183#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15558#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14716#L1412-3 assume !(1 == ~E_4~0); 14717#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15458#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15459#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16041#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15803#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15578#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15579#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14512#L1452-3 assume !(1 == ~E_12~0); 14513#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15131#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14973#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14788#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14708#L1822 assume !(0 == start_simulation_~tmp~3#1); 14709#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15674#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14969#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14466#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 14467#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15630#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15729#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16069#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 14581#L1803-2 [2023-11-26 11:47:33,384 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:33,385 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2023-11-26 11:47:33,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:33,385 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1929935297] [2023-11-26 11:47:33,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:33,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:33,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:33,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:33,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:33,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1929935297] [2023-11-26 11:47:33,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1929935297] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:33,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:33,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:33,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308417730] [2023-11-26 11:47:33,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:33,457 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:33,457 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:33,457 INFO L85 PathProgramCache]: Analyzing trace with hash 349430519, now seen corresponding path program 1 times [2023-11-26 11:47:33,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:33,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259464449] [2023-11-26 11:47:33,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:33,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:33,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:33,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:33,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:33,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1259464449] [2023-11-26 11:47:33,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1259464449] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:33,545 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:33,545 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:33,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649661682] [2023-11-26 11:47:33,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:33,546 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:33,546 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:33,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:33,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:33,547 INFO L87 Difference]: Start difference. First operand 1798 states and 2656 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:33,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:33,602 INFO L93 Difference]: Finished difference Result 1798 states and 2655 transitions. [2023-11-26 11:47:33,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2655 transitions. [2023-11-26 11:47:33,645 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:33,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2655 transitions. [2023-11-26 11:47:33,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:33,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:33,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2655 transitions. [2023-11-26 11:47:33,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:33,669 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2655 transitions. [2023-11-26 11:47:33,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2655 transitions. [2023-11-26 11:47:33,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:33,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4766407119021134) internal successors, (2655), 1797 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:33,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2655 transitions. [2023-11-26 11:47:33,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2655 transitions. [2023-11-26 11:47:33,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:33,721 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2655 transitions. [2023-11-26 11:47:33,722 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:47:33,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2655 transitions. [2023-11-26 11:47:33,732 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:33,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:33,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:33,736 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:33,736 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:33,737 INFO L748 eck$LassoCheckResult]: Stem: 18273#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19207#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19208#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18341#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 18342#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18246#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18247#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19534#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18887#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18888#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18779#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18780#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19288#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19289#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18538#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18539#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18975#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18976#L1194 assume !(0 == ~M_E~0); 19126#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19127#L1199-1 assume !(0 == ~T2_E~0); 19413#L1204-1 assume !(0 == ~T3_E~0); 19338#L1209-1 assume !(0 == ~T4_E~0); 19339#L1214-1 assume !(0 == ~T5_E~0); 19737#L1219-1 assume !(0 == ~T6_E~0); 19823#L1224-1 assume !(0 == ~T7_E~0); 18614#L1229-1 assume !(0 == ~T8_E~0); 18174#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18175#L1239-1 assume !(0 == ~T10_E~0); 18211#L1244-1 assume !(0 == ~T11_E~0); 18212#L1249-1 assume !(0 == ~T12_E~0); 18917#L1254-1 assume !(0 == ~E_M~0); 18108#L1259-1 assume !(0 == ~E_1~0); 18073#L1264-1 assume !(0 == ~E_2~0); 18074#L1269-1 assume !(0 == ~E_3~0); 19825#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19769#L1279-1 assume !(0 == ~E_5~0); 18282#L1284-1 assume !(0 == ~E_6~0); 18283#L1289-1 assume !(0 == ~E_7~0); 18982#L1294-1 assume !(0 == ~E_8~0); 18983#L1299-1 assume !(0 == ~E_9~0); 18994#L1304-1 assume !(0 == ~E_10~0); 19816#L1309-1 assume !(0 == ~E_11~0); 19821#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18240#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18163#L586 assume 1 == ~m_pc~0; 18164#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18231#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19052#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18438#L1485 assume !(0 != activate_threads_~tmp~1#1); 18439#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19540#L605 assume !(1 == ~t1_pc~0); 19066#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18808#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18809#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19452#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19388#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18716#L624 assume 1 == ~t2_pc~0; 18216#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18217#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18465#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18466#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 19572#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19450#L643 assume !(1 == ~t3_pc~0); 19310#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19016#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19017#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18545#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 18546#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18303#L662 assume 1 == ~t4_pc~0; 18304#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18262#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18128#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18129#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 18154#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18155#L681 assume !(1 == ~t5_pc~0); 18029#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18030#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19092#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19698#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 18557#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18558#L700 assume 1 == ~t6_pc~0; 19268#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18295#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18296#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18343#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 18344#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19626#L719 assume 1 == ~t7_pc~0; 19710#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18515#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19813#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19755#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 18043#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18044#L738 assume !(1 == ~t8_pc~0); 19420#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19329#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19330#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19122#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19123#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19472#L757 assume 1 == ~t9_pc~0; 19473#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18038#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18039#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18512#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 19084#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19085#L776 assume !(1 == ~t10_pc~0); 18060#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 18059#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18445#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18284#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 18285#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18241#L795 assume 1 == ~t11_pc~0; 18242#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18581#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19554#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19726#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 19302#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19292#L814 assume !(1 == ~t12_pc~0); 19152#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 19153#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18089#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18090#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 18496#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18497#L1332 assume !(1 == ~M_E~0); 19585#L1332-2 assume !(1 == ~T1_E~0); 19788#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19225#L1342-1 assume !(1 == ~T3_E~0); 19226#L1347-1 assume !(1 == ~T4_E~0); 19614#L1352-1 assume !(1 == ~T5_E~0); 19478#L1357-1 assume !(1 == ~T6_E~0); 18777#L1362-1 assume !(1 == ~T7_E~0); 18778#L1367-1 assume !(1 == ~T8_E~0); 18379#L1372-1 assume !(1 == ~T9_E~0); 18380#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18688#L1382-1 assume !(1 == ~T11_E~0); 18689#L1387-1 assume !(1 == ~T12_E~0); 19385#L1392-1 assume !(1 == ~E_M~0); 18717#L1397-1 assume !(1 == ~E_1~0); 18718#L1402-1 assume !(1 == ~E_2~0); 18394#L1407-1 assume !(1 == ~E_3~0); 18395#L1412-1 assume !(1 == ~E_4~0); 19552#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19553#L1422-1 assume !(1 == ~E_6~0); 19789#L1427-1 assume !(1 == ~E_7~0); 18577#L1432-1 assume !(1 == ~E_8~0); 18578#L1437-1 assume !(1 == ~E_9~0); 19505#L1442-1 assume !(1 == ~E_10~0); 19506#L1447-1 assume !(1 == ~E_11~0); 19377#L1452-1 assume !(1 == ~E_12~0); 18183#L1457-1 assume { :end_inline_reset_delta_events } true; 18184#L1803-2 [2023-11-26 11:47:33,738 INFO L750 eck$LassoCheckResult]: Loop: 18184#L1803-2 assume !false; 18520#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18469#L1169-1 assume !false; 18589#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18759#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18248#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18249#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19593#L996 assume !(0 != eval_~tmp~0#1); 18970#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18634#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18635#L1194-3 assume !(0 == ~M_E~0); 19128#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18351#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18352#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18608#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18052#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18053#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18806#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18807#L1229-3 assume !(0 == ~T8_E~0); 18841#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18219#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18220#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18657#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 19247#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19731#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19360#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18225#L1269-3 assume !(0 == ~E_3~0); 18226#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19766#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18804#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18805#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18786#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18787#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19179#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19180#L1309-3 assume !(0 == ~E_11~0); 18690#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18691#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18696#L586-42 assume !(1 == ~m_pc~0); 18697#L586-44 is_master_triggered_~__retres1~0#1 := 0; 18293#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18294#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18760#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18834#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18835#L605-42 assume 1 == ~t1_pc~0; 19425#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19145#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19146#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18836#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18837#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18845#L624-42 assume !(1 == ~t2_pc~0); 18846#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18990#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19082#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19083#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18655#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18656#L643-42 assume 1 == ~t3_pc~0; 19012#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18971#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18972#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18801#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18802#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19515#L662-42 assume !(1 == ~t4_pc~0); 19718#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 18314#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18315#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19493#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19759#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19725#L681-42 assume 1 == ~t5_pc~0; 19024#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18180#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19172#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19173#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19561#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18674#L700-42 assume 1 == ~t6_pc~0; 18675#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18484#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18404#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18405#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19568#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19776#L719-42 assume 1 == ~t7_pc~0; 19285#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18366#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18746#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19009#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 18761#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18762#L738-42 assume 1 == ~t8_pc~0; 18960#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18705#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18706#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18223#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18224#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18755#L757-42 assume 1 == ~t9_pc~0; 19098#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18406#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18407#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19159#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18525#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18526#L776-42 assume !(1 == ~t10_pc~0); 19485#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 19486#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19303#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19304#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19811#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19326#L795-42 assume 1 == ~t11_pc~0; 19328#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18360#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18361#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18459#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18460#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18771#L814-42 assume !(1 == ~t12_pc~0); 18640#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 18271#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18272#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18081#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18082#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18235#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18236#L1332-5 assume !(1 == ~T1_E~0); 18209#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18210#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19041#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19211#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19212#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19647#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19819#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19815#L1372-3 assume !(1 == ~T9_E~0); 18067#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18068#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18671#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18672#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19511#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19786#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19161#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18319#L1412-3 assume !(1 == ~E_4~0); 18320#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19061#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19062#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19644#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19406#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19181#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19182#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18115#L1452-3 assume !(1 == ~E_12~0); 18116#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18734#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18576#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18391#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 18311#L1822 assume !(0 == start_simulation_~tmp~3#1); 18312#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19277#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18572#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18069#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 18070#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19233#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19332#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19672#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 18184#L1803-2 [2023-11-26 11:47:33,739 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:33,739 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2023-11-26 11:47:33,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:33,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211867322] [2023-11-26 11:47:33,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:33,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:33,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:33,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:33,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:33,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211867322] [2023-11-26 11:47:33,817 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [211867322] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:33,817 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:33,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:33,818 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139683809] [2023-11-26 11:47:33,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:33,819 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:33,819 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:33,819 INFO L85 PathProgramCache]: Analyzing trace with hash -1232933066, now seen corresponding path program 1 times [2023-11-26 11:47:33,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:33,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861898770] [2023-11-26 11:47:33,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:33,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:33,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:33,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:33,913 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:33,913 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861898770] [2023-11-26 11:47:33,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [861898770] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:33,913 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:33,913 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:33,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2014327303] [2023-11-26 11:47:33,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:33,915 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:33,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:33,916 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:33,916 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:33,917 INFO L87 Difference]: Start difference. First operand 1798 states and 2655 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:33,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:33,965 INFO L93 Difference]: Finished difference Result 1798 states and 2654 transitions. [2023-11-26 11:47:33,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2654 transitions. [2023-11-26 11:47:33,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:33,992 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2654 transitions. [2023-11-26 11:47:33,992 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:33,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:33,995 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2654 transitions. [2023-11-26 11:47:33,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:33,998 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2654 transitions. [2023-11-26 11:47:34,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2654 transitions. [2023-11-26 11:47:34,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:34,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4760845383759733) internal successors, (2654), 1797 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:34,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2654 transitions. [2023-11-26 11:47:34,038 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2654 transitions. [2023-11-26 11:47:34,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:34,041 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2654 transitions. [2023-11-26 11:47:34,043 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:47:34,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2654 transitions. [2023-11-26 11:47:34,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:34,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:34,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:34,055 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:34,055 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:34,056 INFO L748 eck$LassoCheckResult]: Stem: 21876#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 21877#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22809#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22810#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21944#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 21945#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21849#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21850#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23137#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22490#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22491#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22382#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22383#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22891#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22892#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22141#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22142#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22578#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22579#L1194 assume !(0 == ~M_E~0); 22729#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22730#L1199-1 assume !(0 == ~T2_E~0); 23016#L1204-1 assume !(0 == ~T3_E~0); 22941#L1209-1 assume !(0 == ~T4_E~0); 22942#L1214-1 assume !(0 == ~T5_E~0); 23340#L1219-1 assume !(0 == ~T6_E~0); 23426#L1224-1 assume !(0 == ~T7_E~0); 22217#L1229-1 assume !(0 == ~T8_E~0); 21777#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21778#L1239-1 assume !(0 == ~T10_E~0); 21814#L1244-1 assume !(0 == ~T11_E~0); 21815#L1249-1 assume !(0 == ~T12_E~0); 22520#L1254-1 assume !(0 == ~E_M~0); 21711#L1259-1 assume !(0 == ~E_1~0); 21676#L1264-1 assume !(0 == ~E_2~0); 21677#L1269-1 assume !(0 == ~E_3~0); 23428#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 23372#L1279-1 assume !(0 == ~E_5~0); 21885#L1284-1 assume !(0 == ~E_6~0); 21886#L1289-1 assume !(0 == ~E_7~0); 22583#L1294-1 assume !(0 == ~E_8~0); 22584#L1299-1 assume !(0 == ~E_9~0); 22597#L1304-1 assume !(0 == ~E_10~0); 23419#L1309-1 assume !(0 == ~E_11~0); 23424#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 21843#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21766#L586 assume 1 == ~m_pc~0; 21767#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21834#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22655#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22041#L1485 assume !(0 != activate_threads_~tmp~1#1); 22042#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23143#L605 assume !(1 == ~t1_pc~0); 22669#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22411#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22412#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23055#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22991#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22319#L624 assume 1 == ~t2_pc~0; 21819#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21820#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22068#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22069#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 23175#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23053#L643 assume !(1 == ~t3_pc~0); 22911#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22619#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22620#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22148#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 22149#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21906#L662 assume 1 == ~t4_pc~0; 21907#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21865#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21731#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21732#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 21757#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21758#L681 assume !(1 == ~t5_pc~0); 21632#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21633#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22695#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23301#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 22160#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22161#L700 assume 1 == ~t6_pc~0; 22871#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21898#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21899#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21946#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 21947#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23229#L719 assume 1 == ~t7_pc~0; 23310#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22117#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23416#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23358#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 21646#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21647#L738 assume !(1 == ~t8_pc~0); 23023#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22932#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22933#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22725#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22726#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23075#L757 assume 1 == ~t9_pc~0; 23076#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21641#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21642#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22115#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 22687#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22688#L776 assume !(1 == ~t10_pc~0); 21663#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21662#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22045#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21887#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 21888#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21844#L795 assume 1 == ~t11_pc~0; 21845#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22180#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23157#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23329#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 22905#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22895#L814 assume !(1 == ~t12_pc~0); 22755#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22756#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21689#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21690#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 22099#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22100#L1332 assume !(1 == ~M_E~0); 23188#L1332-2 assume !(1 == ~T1_E~0); 23391#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22826#L1342-1 assume !(1 == ~T3_E~0); 22827#L1347-1 assume !(1 == ~T4_E~0); 23217#L1352-1 assume !(1 == ~T5_E~0); 23081#L1357-1 assume !(1 == ~T6_E~0); 22380#L1362-1 assume !(1 == ~T7_E~0); 22381#L1367-1 assume !(1 == ~T8_E~0); 21982#L1372-1 assume !(1 == ~T9_E~0); 21983#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22291#L1382-1 assume !(1 == ~T11_E~0); 22292#L1387-1 assume !(1 == ~T12_E~0); 22988#L1392-1 assume !(1 == ~E_M~0); 22320#L1397-1 assume !(1 == ~E_1~0); 22321#L1402-1 assume !(1 == ~E_2~0); 21997#L1407-1 assume !(1 == ~E_3~0); 21998#L1412-1 assume !(1 == ~E_4~0); 23155#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 23156#L1422-1 assume !(1 == ~E_6~0); 23392#L1427-1 assume !(1 == ~E_7~0); 22181#L1432-1 assume !(1 == ~E_8~0); 22182#L1437-1 assume !(1 == ~E_9~0); 23108#L1442-1 assume !(1 == ~E_10~0); 23109#L1447-1 assume !(1 == ~E_11~0); 22980#L1452-1 assume !(1 == ~E_12~0); 21786#L1457-1 assume { :end_inline_reset_delta_events } true; 21787#L1803-2 [2023-11-26 11:47:34,057 INFO L750 eck$LassoCheckResult]: Loop: 21787#L1803-2 assume !false; 22123#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22072#L1169-1 assume !false; 22192#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22362#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21851#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21852#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23196#L996 assume !(0 != eval_~tmp~0#1); 22575#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22240#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22241#L1194-3 assume !(0 == ~M_E~0); 22731#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21954#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21955#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22211#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21659#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21660#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22409#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22410#L1229-3 assume !(0 == ~T8_E~0); 22447#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21822#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21823#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22260#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22850#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23334#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22963#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21828#L1269-3 assume !(0 == ~E_3~0); 21829#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23369#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22407#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22408#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22389#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22390#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22782#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22783#L1309-3 assume !(0 == ~E_11~0); 22293#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22294#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22301#L586-42 assume !(1 == ~m_pc~0); 22302#L586-44 is_master_triggered_~__retres1~0#1 := 0; 21893#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21894#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22363#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22437#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22438#L605-42 assume 1 == ~t1_pc~0; 23027#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22748#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22749#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22439#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22440#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22444#L624-42 assume !(1 == ~t2_pc~0); 22445#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 22590#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22685#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22686#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22258#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22259#L643-42 assume 1 == ~t3_pc~0; 22615#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22573#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22574#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22404#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22405#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23118#L662-42 assume !(1 == ~t4_pc~0); 23320#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 21917#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21918#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23096#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23362#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23328#L681-42 assume 1 == ~t5_pc~0; 22627#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21783#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22775#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22776#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23164#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22277#L700-42 assume 1 == ~t6_pc~0; 22278#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22087#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22007#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22008#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23171#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23379#L719-42 assume !(1 == ~t7_pc~0); 21968#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 21969#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22349#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22612#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 22364#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22365#L738-42 assume 1 == ~t8_pc~0; 22563#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22308#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22309#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21826#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21827#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22358#L757-42 assume 1 == ~t9_pc~0; 22698#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22009#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22010#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22762#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22127#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22128#L776-42 assume !(1 == ~t10_pc~0); 23088#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 23089#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22906#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22907#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23414#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22929#L795-42 assume !(1 == ~t11_pc~0); 22930#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 21963#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21964#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22062#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22063#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22374#L814-42 assume !(1 == ~t12_pc~0); 22243#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 21874#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21875#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21684#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21685#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21838#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21839#L1332-5 assume !(1 == ~T1_E~0); 21812#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21813#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22644#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22814#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22815#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23250#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23422#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23418#L1372-3 assume !(1 == ~T9_E~0); 21670#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21671#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22274#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22275#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23114#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23389#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22764#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21922#L1412-3 assume !(1 == ~E_4~0); 21923#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22664#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22665#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23247#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23008#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22784#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22785#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21718#L1452-3 assume !(1 == ~E_12~0); 21719#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22337#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22179#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21994#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 21914#L1822 assume !(0 == start_simulation_~tmp~3#1); 21915#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22880#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22172#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21672#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 21673#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22836#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22935#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23274#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 21787#L1803-2 [2023-11-26 11:47:34,058 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:34,058 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2023-11-26 11:47:34,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:34,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088575873] [2023-11-26 11:47:34,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:34,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:34,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:34,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:34,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:34,119 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088575873] [2023-11-26 11:47:34,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088575873] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:34,120 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:34,120 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:34,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [403411643] [2023-11-26 11:47:34,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:34,121 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:34,121 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:34,121 INFO L85 PathProgramCache]: Analyzing trace with hash 1102292536, now seen corresponding path program 3 times [2023-11-26 11:47:34,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:34,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212052494] [2023-11-26 11:47:34,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:34,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:34,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:34,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:34,217 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:34,218 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212052494] [2023-11-26 11:47:34,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212052494] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:34,218 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:34,218 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:34,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707835057] [2023-11-26 11:47:34,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:34,219 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:34,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:34,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:34,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:34,220 INFO L87 Difference]: Start difference. First operand 1798 states and 2654 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:34,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:34,269 INFO L93 Difference]: Finished difference Result 1798 states and 2653 transitions. [2023-11-26 11:47:34,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2653 transitions. [2023-11-26 11:47:34,282 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:34,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2653 transitions. [2023-11-26 11:47:34,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:34,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:34,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2653 transitions. [2023-11-26 11:47:34,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:34,350 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2653 transitions. [2023-11-26 11:47:34,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2653 transitions. [2023-11-26 11:47:34,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:34,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4755283648498332) internal successors, (2653), 1797 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:34,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2653 transitions. [2023-11-26 11:47:34,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2653 transitions. [2023-11-26 11:47:34,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:34,407 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2653 transitions. [2023-11-26 11:47:34,407 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:47:34,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2653 transitions. [2023-11-26 11:47:34,416 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:34,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:34,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:34,419 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:34,420 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:34,420 INFO L748 eck$LassoCheckResult]: Stem: 25479#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26412#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26413#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25547#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 25548#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25452#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25453#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26740#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26093#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26094#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25985#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25986#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26494#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26495#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25744#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25745#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26181#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26182#L1194 assume !(0 == ~M_E~0); 26332#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26333#L1199-1 assume !(0 == ~T2_E~0); 26619#L1204-1 assume !(0 == ~T3_E~0); 26544#L1209-1 assume !(0 == ~T4_E~0); 26545#L1214-1 assume !(0 == ~T5_E~0); 26943#L1219-1 assume !(0 == ~T6_E~0); 27029#L1224-1 assume !(0 == ~T7_E~0); 25818#L1229-1 assume !(0 == ~T8_E~0); 25378#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25379#L1239-1 assume !(0 == ~T10_E~0); 25417#L1244-1 assume !(0 == ~T11_E~0); 25418#L1249-1 assume !(0 == ~T12_E~0); 26123#L1254-1 assume !(0 == ~E_M~0); 25314#L1259-1 assume !(0 == ~E_1~0); 25279#L1264-1 assume !(0 == ~E_2~0); 25280#L1269-1 assume !(0 == ~E_3~0); 27031#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26975#L1279-1 assume !(0 == ~E_5~0); 25488#L1284-1 assume !(0 == ~E_6~0); 25489#L1289-1 assume !(0 == ~E_7~0); 26186#L1294-1 assume !(0 == ~E_8~0); 26187#L1299-1 assume !(0 == ~E_9~0); 26200#L1304-1 assume !(0 == ~E_10~0); 27022#L1309-1 assume !(0 == ~E_11~0); 27027#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25446#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25369#L586 assume 1 == ~m_pc~0; 25370#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25437#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26258#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25644#L1485 assume !(0 != activate_threads_~tmp~1#1); 25645#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26746#L605 assume !(1 == ~t1_pc~0); 26272#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26014#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26015#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26658#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26594#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25922#L624 assume 1 == ~t2_pc~0; 25422#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25423#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25671#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25672#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 26778#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26656#L643 assume !(1 == ~t3_pc~0); 26514#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26218#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26219#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25751#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 25752#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25509#L662 assume 1 == ~t4_pc~0; 25510#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25468#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25331#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25332#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 25360#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25361#L681 assume !(1 == ~t5_pc~0); 25235#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25236#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26298#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26904#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 25763#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25764#L700 assume 1 == ~t6_pc~0; 26474#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25501#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25502#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25549#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 25550#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26832#L719 assume 1 == ~t7_pc~0; 26913#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25720#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27019#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26961#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 25249#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25250#L738 assume !(1 == ~t8_pc~0); 26626#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26535#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26536#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26328#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26329#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26678#L757 assume 1 == ~t9_pc~0; 26679#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25244#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25245#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25718#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 26290#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26291#L776 assume !(1 == ~t10_pc~0); 25266#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25265#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25648#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25490#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 25491#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25447#L795 assume 1 == ~t11_pc~0; 25448#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25783#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26760#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26931#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 26508#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26498#L814 assume !(1 == ~t12_pc~0); 26358#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26359#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25292#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25293#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 25702#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25703#L1332 assume !(1 == ~M_E~0); 26791#L1332-2 assume !(1 == ~T1_E~0); 26994#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26429#L1342-1 assume !(1 == ~T3_E~0); 26430#L1347-1 assume !(1 == ~T4_E~0); 26819#L1352-1 assume !(1 == ~T5_E~0); 26684#L1357-1 assume !(1 == ~T6_E~0); 25983#L1362-1 assume !(1 == ~T7_E~0); 25984#L1367-1 assume !(1 == ~T8_E~0); 25583#L1372-1 assume !(1 == ~T9_E~0); 25584#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25894#L1382-1 assume !(1 == ~T11_E~0); 25895#L1387-1 assume !(1 == ~T12_E~0); 26591#L1392-1 assume !(1 == ~E_M~0); 25923#L1397-1 assume !(1 == ~E_1~0); 25924#L1402-1 assume !(1 == ~E_2~0); 25600#L1407-1 assume !(1 == ~E_3~0); 25601#L1412-1 assume !(1 == ~E_4~0); 26758#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26759#L1422-1 assume !(1 == ~E_6~0); 26995#L1427-1 assume !(1 == ~E_7~0); 25784#L1432-1 assume !(1 == ~E_8~0); 25785#L1437-1 assume !(1 == ~E_9~0); 26711#L1442-1 assume !(1 == ~E_10~0); 26712#L1447-1 assume !(1 == ~E_11~0); 26583#L1452-1 assume !(1 == ~E_12~0); 25389#L1457-1 assume { :end_inline_reset_delta_events } true; 25390#L1803-2 [2023-11-26 11:47:34,421 INFO L750 eck$LassoCheckResult]: Loop: 25390#L1803-2 assume !false; 25726#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25675#L1169-1 assume !false; 25795#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25965#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25454#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25455#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26799#L996 assume !(0 != eval_~tmp~0#1); 26176#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25844#L1194-3 assume !(0 == ~M_E~0); 26334#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25557#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25558#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25814#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25262#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25263#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26012#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26013#L1229-3 assume !(0 == ~T8_E~0); 26047#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25425#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25426#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25863#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26453#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26937#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26566#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25431#L1269-3 assume !(0 == ~E_3~0); 25432#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26972#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26010#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26011#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25992#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25993#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26385#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26386#L1309-3 assume !(0 == ~E_11~0); 25896#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25897#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25902#L586-42 assume 1 == ~m_pc~0; 25904#L587-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25499#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25500#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25968#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26040#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26041#L605-42 assume 1 == ~t1_pc~0; 26632#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26351#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26352#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26045#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26046#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26051#L624-42 assume !(1 == ~t2_pc~0); 26052#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26197#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26288#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26289#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25861#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25862#L643-42 assume 1 == ~t3_pc~0; 26222#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26177#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26178#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26007#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26008#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26721#L662-42 assume !(1 == ~t4_pc~0); 26924#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 25520#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25521#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26699#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26965#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26932#L681-42 assume 1 == ~t5_pc~0; 26233#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25386#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26378#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26379#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26767#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25879#L700-42 assume !(1 == ~t6_pc~0); 25686#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 25687#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25610#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25611#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26774#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26980#L719-42 assume !(1 == ~t7_pc~0); 25568#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 25569#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25952#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26215#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 25966#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25967#L738-42 assume 1 == ~t8_pc~0; 26166#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25909#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25910#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25429#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25430#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25961#L757-42 assume 1 == ~t9_pc~0; 26301#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25612#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25613#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26365#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25730#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25731#L776-42 assume !(1 == ~t10_pc~0); 26691#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 26692#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26509#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26510#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27017#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26532#L795-42 assume !(1 == ~t11_pc~0); 26533#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 25564#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25565#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25663#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25664#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25977#L814-42 assume !(1 == ~t12_pc~0); 25846#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25477#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25478#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25287#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25288#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25441#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25442#L1332-5 assume !(1 == ~T1_E~0); 25415#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25416#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26247#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26417#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26418#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26852#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27025#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27021#L1372-3 assume !(1 == ~T9_E~0); 25273#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25274#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25877#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25878#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26717#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26992#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26367#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25525#L1412-3 assume !(1 == ~E_4~0); 25526#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26267#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26268#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26850#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26611#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26387#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26388#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25321#L1452-3 assume !(1 == ~E_12~0); 25322#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25938#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25782#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25597#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 25517#L1822 assume !(0 == start_simulation_~tmp~3#1); 25518#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26483#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25775#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25275#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 25276#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26439#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26538#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 26877#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 25390#L1803-2 [2023-11-26 11:47:34,422 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:34,422 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2023-11-26 11:47:34,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:34,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [19202031] [2023-11-26 11:47:34,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:34,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:34,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:34,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:34,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:34,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [19202031] [2023-11-26 11:47:34,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [19202031] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:34,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:34,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:34,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [210213033] [2023-11-26 11:47:34,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:34,482 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:34,483 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:34,483 INFO L85 PathProgramCache]: Analyzing trace with hash -1150192968, now seen corresponding path program 1 times [2023-11-26 11:47:34,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:34,486 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096268949] [2023-11-26 11:47:34,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:34,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:34,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:34,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:34,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:34,561 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2096268949] [2023-11-26 11:47:34,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2096268949] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:34,563 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:34,564 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:34,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445001280] [2023-11-26 11:47:34,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:34,564 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:34,565 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:34,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:34,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:34,566 INFO L87 Difference]: Start difference. First operand 1798 states and 2653 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:34,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:34,617 INFO L93 Difference]: Finished difference Result 1798 states and 2652 transitions. [2023-11-26 11:47:34,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2652 transitions. [2023-11-26 11:47:34,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:34,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2652 transitions. [2023-11-26 11:47:34,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:34,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:34,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2652 transitions. [2023-11-26 11:47:34,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:34,654 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2652 transitions. [2023-11-26 11:47:34,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2652 transitions. [2023-11-26 11:47:34,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:34,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.474972191323693) internal successors, (2652), 1797 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:34,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2652 transitions. [2023-11-26 11:47:34,704 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2652 transitions. [2023-11-26 11:47:34,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:34,707 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2652 transitions. [2023-11-26 11:47:34,707 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 11:47:34,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2652 transitions. [2023-11-26 11:47:34,716 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:34,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:34,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:34,719 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:34,719 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:34,720 INFO L748 eck$LassoCheckResult]: Stem: 29080#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29081#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 30015#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30016#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29150#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 29151#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29055#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29056#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30343#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29696#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29697#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29588#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29589#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30097#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30098#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29347#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29348#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29782#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29783#L1194 assume !(0 == ~M_E~0); 29935#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29936#L1199-1 assume !(0 == ~T2_E~0); 30222#L1204-1 assume !(0 == ~T3_E~0); 30147#L1209-1 assume !(0 == ~T4_E~0); 30148#L1214-1 assume !(0 == ~T5_E~0); 30546#L1219-1 assume !(0 == ~T6_E~0); 30632#L1224-1 assume !(0 == ~T7_E~0); 29421#L1229-1 assume !(0 == ~T8_E~0); 28975#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28976#L1239-1 assume !(0 == ~T10_E~0); 29018#L1244-1 assume !(0 == ~T11_E~0); 29019#L1249-1 assume !(0 == ~T12_E~0); 29726#L1254-1 assume !(0 == ~E_M~0); 28917#L1259-1 assume !(0 == ~E_1~0); 28882#L1264-1 assume !(0 == ~E_2~0); 28883#L1269-1 assume !(0 == ~E_3~0); 30634#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 30578#L1279-1 assume !(0 == ~E_5~0); 29091#L1284-1 assume !(0 == ~E_6~0); 29092#L1289-1 assume !(0 == ~E_7~0); 29789#L1294-1 assume !(0 == ~E_8~0); 29790#L1299-1 assume !(0 == ~E_9~0); 29801#L1304-1 assume !(0 == ~E_10~0); 30625#L1309-1 assume !(0 == ~E_11~0); 30630#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 29049#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28972#L586 assume 1 == ~m_pc~0; 28973#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29040#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29861#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29247#L1485 assume !(0 != activate_threads_~tmp~1#1); 29248#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30349#L605 assume !(1 == ~t1_pc~0); 29875#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29617#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29618#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30261#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30196#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29525#L624 assume 1 == ~t2_pc~0; 29022#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29023#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29274#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29275#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 30381#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30259#L643 assume !(1 == ~t3_pc~0); 30117#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29821#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29822#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29354#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 29355#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29112#L662 assume 1 == ~t4_pc~0; 29113#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29071#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28934#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28935#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 28963#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28964#L681 assume !(1 == ~t5_pc~0); 28838#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28839#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29901#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30507#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 29366#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29367#L700 assume 1 == ~t6_pc~0; 30077#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29104#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29105#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29152#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 29153#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30435#L719 assume 1 == ~t7_pc~0; 30516#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29323#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30622#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30564#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 28852#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28853#L738 assume !(1 == ~t8_pc~0); 30229#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30138#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30139#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29931#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29932#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30281#L757 assume 1 == ~t9_pc~0; 30282#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28847#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28848#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29321#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 29893#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29894#L776 assume !(1 == ~t10_pc~0); 28869#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28868#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29251#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29093#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 29094#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29050#L795 assume 1 == ~t11_pc~0; 29051#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29386#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30363#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30534#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 30111#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30101#L814 assume !(1 == ~t12_pc~0); 29961#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29962#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28895#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28896#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 29305#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29306#L1332 assume !(1 == ~M_E~0); 30394#L1332-2 assume !(1 == ~T1_E~0); 30596#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30032#L1342-1 assume !(1 == ~T3_E~0); 30033#L1347-1 assume !(1 == ~T4_E~0); 30422#L1352-1 assume !(1 == ~T5_E~0); 30287#L1357-1 assume !(1 == ~T6_E~0); 29586#L1362-1 assume !(1 == ~T7_E~0); 29587#L1367-1 assume !(1 == ~T8_E~0); 29186#L1372-1 assume !(1 == ~T9_E~0); 29187#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29497#L1382-1 assume !(1 == ~T11_E~0); 29498#L1387-1 assume !(1 == ~T12_E~0); 30194#L1392-1 assume !(1 == ~E_M~0); 29526#L1397-1 assume !(1 == ~E_1~0); 29527#L1402-1 assume !(1 == ~E_2~0); 29201#L1407-1 assume !(1 == ~E_3~0); 29202#L1412-1 assume !(1 == ~E_4~0); 30361#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30362#L1422-1 assume !(1 == ~E_6~0); 30598#L1427-1 assume !(1 == ~E_7~0); 29387#L1432-1 assume !(1 == ~E_8~0); 29388#L1437-1 assume !(1 == ~E_9~0); 30314#L1442-1 assume !(1 == ~E_10~0); 30315#L1447-1 assume !(1 == ~E_11~0); 30186#L1452-1 assume !(1 == ~E_12~0); 28992#L1457-1 assume { :end_inline_reset_delta_events } true; 28993#L1803-2 [2023-11-26 11:47:34,722 INFO L750 eck$LassoCheckResult]: Loop: 28993#L1803-2 assume !false; 29329#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29278#L1169-1 assume !false; 29398#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29568#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29057#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29058#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30402#L996 assume !(0 != eval_~tmp~0#1); 29779#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29443#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29444#L1194-3 assume !(0 == ~M_E~0); 29937#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29160#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29161#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29417#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28863#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28864#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29615#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29616#L1229-3 assume !(0 == ~T8_E~0); 29650#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29028#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29029#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29466#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 30056#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30540#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30169#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29034#L1269-3 assume !(0 == ~E_3~0); 29035#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30575#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29613#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29614#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29595#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29596#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29988#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29989#L1309-3 assume !(0 == ~E_11~0); 29499#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29500#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29505#L586-42 assume !(1 == ~m_pc~0); 29506#L586-44 is_master_triggered_~__retres1~0#1 := 0; 29102#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29103#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29569#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29643#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29644#L605-42 assume 1 == ~t1_pc~0; 30234#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29954#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29955#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29647#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29648#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29654#L624-42 assume !(1 == ~t2_pc~0); 29655#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 29799#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29891#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29892#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29464#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29465#L643-42 assume 1 == ~t3_pc~0; 29825#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29780#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29781#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29610#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29611#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30324#L662-42 assume 1 == ~t4_pc~0; 30528#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29123#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29124#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30302#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30568#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30535#L681-42 assume 1 == ~t5_pc~0; 29836#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28989#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29981#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29982#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30370#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29483#L700-42 assume 1 == ~t6_pc~0; 29484#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29293#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29213#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29214#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30377#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30585#L719-42 assume !(1 == ~t7_pc~0); 29174#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 29175#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29555#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29818#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 29570#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29571#L738-42 assume 1 == ~t8_pc~0; 29770#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29514#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29515#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29032#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29033#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29564#L757-42 assume 1 == ~t9_pc~0; 29910#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29215#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29216#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29968#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29334#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29335#L776-42 assume !(1 == ~t10_pc~0); 30294#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 30295#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30113#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30114#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30620#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30135#L795-42 assume !(1 == ~t11_pc~0); 30136#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 29169#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29170#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29268#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29269#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29580#L814-42 assume 1 == ~t12_pc~0; 30352#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29082#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29083#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28890#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28891#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29044#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29045#L1332-5 assume !(1 == ~T1_E~0); 29020#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29021#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29850#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30020#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30021#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30456#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30628#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30624#L1372-3 assume !(1 == ~T9_E~0); 28876#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28877#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29480#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29481#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30320#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30595#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29970#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29128#L1412-3 assume !(1 == ~E_4~0); 29129#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29870#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29871#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30451#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30214#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29990#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29991#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28924#L1452-3 assume !(1 == ~E_12~0); 28925#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29539#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29385#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29198#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 29120#L1822 assume !(0 == start_simulation_~tmp~3#1); 29121#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30086#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29376#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28878#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 28879#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30042#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30141#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 30479#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 28993#L1803-2 [2023-11-26 11:47:34,722 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:34,723 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2023-11-26 11:47:34,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:34,723 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804336605] [2023-11-26 11:47:34,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:34,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:34,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:34,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:34,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:34,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804336605] [2023-11-26 11:47:34,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [804336605] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:34,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:34,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:34,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110751159] [2023-11-26 11:47:34,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:34,777 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:34,778 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:34,778 INFO L85 PathProgramCache]: Analyzing trace with hash 858585270, now seen corresponding path program 1 times [2023-11-26 11:47:34,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:34,778 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323340576] [2023-11-26 11:47:34,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:34,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:34,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:34,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:34,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:34,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323340576] [2023-11-26 11:47:34,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323340576] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:34,847 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:34,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:34,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1515725638] [2023-11-26 11:47:34,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:34,848 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:34,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:34,848 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:34,848 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:34,849 INFO L87 Difference]: Start difference. First operand 1798 states and 2652 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:34,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:34,897 INFO L93 Difference]: Finished difference Result 1798 states and 2651 transitions. [2023-11-26 11:47:34,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2651 transitions. [2023-11-26 11:47:34,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:34,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2651 transitions. [2023-11-26 11:47:34,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:34,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:34,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2651 transitions. [2023-11-26 11:47:34,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:34,929 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2651 transitions. [2023-11-26 11:47:34,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2651 transitions. [2023-11-26 11:47:34,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:34,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.474416017797553) internal successors, (2651), 1797 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:34,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2651 transitions. [2023-11-26 11:47:34,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2651 transitions. [2023-11-26 11:47:34,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:34,971 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2651 transitions. [2023-11-26 11:47:34,972 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 11:47:34,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2651 transitions. [2023-11-26 11:47:35,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:35,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:35,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:35,016 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:35,016 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:35,017 INFO L748 eck$LassoCheckResult]: Stem: 32683#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 32684#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33618#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33619#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32753#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 32754#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32658#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32659#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33946#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33299#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33300#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33191#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33192#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33700#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33701#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32950#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32951#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33385#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33386#L1194 assume !(0 == ~M_E~0); 33538#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33539#L1199-1 assume !(0 == ~T2_E~0); 33825#L1204-1 assume !(0 == ~T3_E~0); 33750#L1209-1 assume !(0 == ~T4_E~0); 33751#L1214-1 assume !(0 == ~T5_E~0); 34149#L1219-1 assume !(0 == ~T6_E~0); 34235#L1224-1 assume !(0 == ~T7_E~0); 33024#L1229-1 assume !(0 == ~T8_E~0); 32578#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32579#L1239-1 assume !(0 == ~T10_E~0); 32621#L1244-1 assume !(0 == ~T11_E~0); 32622#L1249-1 assume !(0 == ~T12_E~0); 33329#L1254-1 assume !(0 == ~E_M~0); 32520#L1259-1 assume !(0 == ~E_1~0); 32485#L1264-1 assume !(0 == ~E_2~0); 32486#L1269-1 assume !(0 == ~E_3~0); 34237#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 34181#L1279-1 assume !(0 == ~E_5~0); 32694#L1284-1 assume !(0 == ~E_6~0); 32695#L1289-1 assume !(0 == ~E_7~0); 33392#L1294-1 assume !(0 == ~E_8~0); 33393#L1299-1 assume !(0 == ~E_9~0); 33404#L1304-1 assume !(0 == ~E_10~0); 34228#L1309-1 assume !(0 == ~E_11~0); 34233#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32651#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32575#L586 assume 1 == ~m_pc~0; 32576#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32643#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33464#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32850#L1485 assume !(0 != activate_threads_~tmp~1#1); 32851#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33952#L605 assume !(1 == ~t1_pc~0); 33478#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33220#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33221#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33864#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33799#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33128#L624 assume 1 == ~t2_pc~0; 32625#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32626#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32877#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32878#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 33984#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33862#L643 assume !(1 == ~t3_pc~0); 33720#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33422#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32957#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 32958#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32715#L662 assume 1 == ~t4_pc~0; 32716#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32674#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32537#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32538#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 32564#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32565#L681 assume !(1 == ~t5_pc~0); 32441#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32442#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33504#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34110#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 32969#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32970#L700 assume 1 == ~t6_pc~0; 33680#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32707#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32708#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32755#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 32756#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34038#L719 assume 1 == ~t7_pc~0; 34119#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32926#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34167#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 32455#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32456#L738 assume !(1 == ~t8_pc~0); 33832#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33741#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33742#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33534#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33535#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33884#L757 assume 1 == ~t9_pc~0; 33885#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32450#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32451#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32924#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 33496#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33497#L776 assume !(1 == ~t10_pc~0); 32472#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32471#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32854#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32696#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 32697#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32652#L795 assume 1 == ~t11_pc~0; 32653#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32989#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33966#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34137#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 33714#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33704#L814 assume !(1 == ~t12_pc~0); 33564#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33565#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32498#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32499#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 32908#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32909#L1332 assume !(1 == ~M_E~0); 33997#L1332-2 assume !(1 == ~T1_E~0); 34199#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33635#L1342-1 assume !(1 == ~T3_E~0); 33636#L1347-1 assume !(1 == ~T4_E~0); 34025#L1352-1 assume !(1 == ~T5_E~0); 33890#L1357-1 assume !(1 == ~T6_E~0); 33189#L1362-1 assume !(1 == ~T7_E~0); 33190#L1367-1 assume !(1 == ~T8_E~0); 32789#L1372-1 assume !(1 == ~T9_E~0); 32790#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33100#L1382-1 assume !(1 == ~T11_E~0); 33101#L1387-1 assume !(1 == ~T12_E~0); 33797#L1392-1 assume !(1 == ~E_M~0); 33129#L1397-1 assume !(1 == ~E_1~0); 33130#L1402-1 assume !(1 == ~E_2~0); 32804#L1407-1 assume !(1 == ~E_3~0); 32805#L1412-1 assume !(1 == ~E_4~0); 33964#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33965#L1422-1 assume !(1 == ~E_6~0); 34201#L1427-1 assume !(1 == ~E_7~0); 32990#L1432-1 assume !(1 == ~E_8~0); 32991#L1437-1 assume !(1 == ~E_9~0); 33917#L1442-1 assume !(1 == ~E_10~0); 33918#L1447-1 assume !(1 == ~E_11~0); 33789#L1452-1 assume !(1 == ~E_12~0); 32595#L1457-1 assume { :end_inline_reset_delta_events } true; 32596#L1803-2 [2023-11-26 11:47:35,017 INFO L750 eck$LassoCheckResult]: Loop: 32596#L1803-2 assume !false; 32932#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32881#L1169-1 assume !false; 33001#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33171#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32660#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32661#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34005#L996 assume !(0 != eval_~tmp~0#1); 33382#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33046#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33047#L1194-3 assume !(0 == ~M_E~0); 33540#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32763#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32764#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33020#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32464#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32465#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33218#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33219#L1229-3 assume !(0 == ~T8_E~0); 33253#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32631#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32632#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33069#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33659#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34143#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33772#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32637#L1269-3 assume !(0 == ~E_3~0); 32638#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34178#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33216#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33217#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33198#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33199#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33591#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33592#L1309-3 assume !(0 == ~E_11~0); 33102#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33103#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33108#L586-42 assume !(1 == ~m_pc~0); 33109#L586-44 is_master_triggered_~__retres1~0#1 := 0; 32705#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32706#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33172#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33246#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33247#L605-42 assume 1 == ~t1_pc~0; 33837#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33557#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33558#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33248#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33249#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33257#L624-42 assume !(1 == ~t2_pc~0); 33258#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 33402#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33494#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33495#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33067#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33068#L643-42 assume 1 == ~t3_pc~0; 33426#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33383#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33384#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33213#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33214#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33927#L662-42 assume !(1 == ~t4_pc~0); 34130#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32726#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32727#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33905#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34171#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34138#L681-42 assume 1 == ~t5_pc~0; 33436#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32592#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33584#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33585#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33973#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33086#L700-42 assume 1 == ~t6_pc~0; 33087#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32896#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32816#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32817#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33980#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34188#L719-42 assume 1 == ~t7_pc~0; 33697#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32778#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33158#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33421#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 33173#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33174#L738-42 assume 1 == ~t8_pc~0; 33372#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33117#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33118#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32635#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32636#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33167#L757-42 assume 1 == ~t9_pc~0; 33510#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32818#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32819#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33571#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32937#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32938#L776-42 assume !(1 == ~t10_pc~0); 33897#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 33898#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33715#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33716#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34223#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33738#L795-42 assume !(1 == ~t11_pc~0); 33739#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 32772#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32773#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32871#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32872#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33183#L814-42 assume 1 == ~t12_pc~0; 33955#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32685#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32686#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32493#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32494#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32647#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32648#L1332-5 assume !(1 == ~T1_E~0); 32623#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32624#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33453#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33623#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33624#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34059#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34231#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34227#L1372-3 assume !(1 == ~T9_E~0); 32479#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32480#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33083#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33084#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33923#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34198#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33573#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32731#L1412-3 assume !(1 == ~E_4~0); 32732#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33473#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33474#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34056#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33818#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33593#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33594#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32527#L1452-3 assume !(1 == ~E_12~0); 32528#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33146#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32988#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32723#L1822 assume !(0 == start_simulation_~tmp~3#1); 32724#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33689#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32984#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32481#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 32482#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33645#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33744#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 34084#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 32596#L1803-2 [2023-11-26 11:47:35,018 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:35,019 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2023-11-26 11:47:35,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:35,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317951645] [2023-11-26 11:47:35,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:35,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:35,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:35,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:35,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:35,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317951645] [2023-11-26 11:47:35,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [317951645] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:35,088 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:35,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:35,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [309395018] [2023-11-26 11:47:35,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:35,090 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:35,090 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:35,091 INFO L85 PathProgramCache]: Analyzing trace with hash 1834670710, now seen corresponding path program 1 times [2023-11-26 11:47:35,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:35,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1250549648] [2023-11-26 11:47:35,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:35,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:35,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:35,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:35,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:35,160 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1250549648] [2023-11-26 11:47:35,160 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1250549648] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:35,160 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:35,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:35,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [51650812] [2023-11-26 11:47:35,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:35,161 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:35,162 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:35,162 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:35,162 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:35,163 INFO L87 Difference]: Start difference. First operand 1798 states and 2651 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:35,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:35,209 INFO L93 Difference]: Finished difference Result 1798 states and 2650 transitions. [2023-11-26 11:47:35,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2650 transitions. [2023-11-26 11:47:35,221 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:35,244 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2650 transitions. [2023-11-26 11:47:35,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:35,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:35,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2650 transitions. [2023-11-26 11:47:35,250 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:35,250 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2650 transitions. [2023-11-26 11:47:35,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2650 transitions. [2023-11-26 11:47:35,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:35,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4738598442714126) internal successors, (2650), 1797 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:35,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2650 transitions. [2023-11-26 11:47:35,300 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2650 transitions. [2023-11-26 11:47:35,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:35,301 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2650 transitions. [2023-11-26 11:47:35,301 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 11:47:35,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2650 transitions. [2023-11-26 11:47:35,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:35,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:35,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:35,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:35,314 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:35,314 INFO L748 eck$LassoCheckResult]: Stem: 36286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 37221#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37222#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36356#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 36357#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36261#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36262#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37549#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36902#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36903#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36794#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36795#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37303#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37304#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36553#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36554#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36988#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36989#L1194 assume !(0 == ~M_E~0); 37141#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37142#L1199-1 assume !(0 == ~T2_E~0); 37428#L1204-1 assume !(0 == ~T3_E~0); 37353#L1209-1 assume !(0 == ~T4_E~0); 37354#L1214-1 assume !(0 == ~T5_E~0); 37752#L1219-1 assume !(0 == ~T6_E~0); 37838#L1224-1 assume !(0 == ~T7_E~0); 36627#L1229-1 assume !(0 == ~T8_E~0); 36181#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36182#L1239-1 assume !(0 == ~T10_E~0); 36224#L1244-1 assume !(0 == ~T11_E~0); 36225#L1249-1 assume !(0 == ~T12_E~0); 36932#L1254-1 assume !(0 == ~E_M~0); 36123#L1259-1 assume !(0 == ~E_1~0); 36088#L1264-1 assume !(0 == ~E_2~0); 36089#L1269-1 assume !(0 == ~E_3~0); 37840#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37784#L1279-1 assume !(0 == ~E_5~0); 36297#L1284-1 assume !(0 == ~E_6~0); 36298#L1289-1 assume !(0 == ~E_7~0); 36995#L1294-1 assume !(0 == ~E_8~0); 36996#L1299-1 assume !(0 == ~E_9~0); 37007#L1304-1 assume !(0 == ~E_10~0); 37831#L1309-1 assume !(0 == ~E_11~0); 37836#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36254#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36178#L586 assume 1 == ~m_pc~0; 36179#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36246#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37067#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36453#L1485 assume !(0 != activate_threads_~tmp~1#1); 36454#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37555#L605 assume !(1 == ~t1_pc~0); 37081#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36823#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36824#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37467#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37402#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36731#L624 assume 1 == ~t2_pc~0; 36228#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36229#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36480#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36481#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 37587#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37465#L643 assume !(1 == ~t3_pc~0); 37323#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37025#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37026#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36560#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 36561#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36318#L662 assume 1 == ~t4_pc~0; 36319#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36277#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36141#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 36167#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36168#L681 assume !(1 == ~t5_pc~0); 36044#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36045#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37107#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37713#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 36572#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36573#L700 assume 1 == ~t6_pc~0; 37283#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36310#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36311#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36358#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 36359#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37641#L719 assume 1 == ~t7_pc~0; 37722#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36529#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37828#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37770#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 36058#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36059#L738 assume !(1 == ~t8_pc~0); 37435#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37344#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37345#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37137#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37138#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37487#L757 assume 1 == ~t9_pc~0; 37488#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36053#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36054#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36527#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 37099#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37100#L776 assume !(1 == ~t10_pc~0); 36075#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36074#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36457#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36299#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 36300#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36255#L795 assume 1 == ~t11_pc~0; 36256#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36592#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37569#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37740#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 37317#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37307#L814 assume !(1 == ~t12_pc~0); 37167#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37168#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36101#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36102#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 36511#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36512#L1332 assume !(1 == ~M_E~0); 37600#L1332-2 assume !(1 == ~T1_E~0); 37802#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37238#L1342-1 assume !(1 == ~T3_E~0); 37239#L1347-1 assume !(1 == ~T4_E~0); 37628#L1352-1 assume !(1 == ~T5_E~0); 37493#L1357-1 assume !(1 == ~T6_E~0); 36792#L1362-1 assume !(1 == ~T7_E~0); 36793#L1367-1 assume !(1 == ~T8_E~0); 36392#L1372-1 assume !(1 == ~T9_E~0); 36393#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36703#L1382-1 assume !(1 == ~T11_E~0); 36704#L1387-1 assume !(1 == ~T12_E~0); 37400#L1392-1 assume !(1 == ~E_M~0); 36732#L1397-1 assume !(1 == ~E_1~0); 36733#L1402-1 assume !(1 == ~E_2~0); 36407#L1407-1 assume !(1 == ~E_3~0); 36408#L1412-1 assume !(1 == ~E_4~0); 37567#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 37568#L1422-1 assume !(1 == ~E_6~0); 37804#L1427-1 assume !(1 == ~E_7~0); 36593#L1432-1 assume !(1 == ~E_8~0); 36594#L1437-1 assume !(1 == ~E_9~0); 37520#L1442-1 assume !(1 == ~E_10~0); 37521#L1447-1 assume !(1 == ~E_11~0); 37392#L1452-1 assume !(1 == ~E_12~0); 36198#L1457-1 assume { :end_inline_reset_delta_events } true; 36199#L1803-2 [2023-11-26 11:47:35,315 INFO L750 eck$LassoCheckResult]: Loop: 36199#L1803-2 assume !false; 36535#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36484#L1169-1 assume !false; 36604#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36774#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36263#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36264#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37608#L996 assume !(0 != eval_~tmp~0#1); 36985#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36649#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36650#L1194-3 assume !(0 == ~M_E~0); 37143#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36366#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36367#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36623#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36067#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36068#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36821#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36822#L1229-3 assume !(0 == ~T8_E~0); 36856#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36234#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36235#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36672#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37262#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37746#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37375#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36240#L1269-3 assume !(0 == ~E_3~0); 36241#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37781#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36819#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36820#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36801#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36802#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37194#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37195#L1309-3 assume !(0 == ~E_11~0); 36705#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36706#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36711#L586-42 assume !(1 == ~m_pc~0); 36712#L586-44 is_master_triggered_~__retres1~0#1 := 0; 36308#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36309#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36775#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36849#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36850#L605-42 assume 1 == ~t1_pc~0; 37440#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37160#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37161#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36851#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36852#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36860#L624-42 assume !(1 == ~t2_pc~0); 36861#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 37005#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37097#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37098#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36670#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36671#L643-42 assume 1 == ~t3_pc~0; 37029#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36986#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36987#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36816#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36817#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37530#L662-42 assume !(1 == ~t4_pc~0); 37733#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 36329#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36330#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37508#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37774#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37741#L681-42 assume !(1 == ~t5_pc~0); 36194#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 36195#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37187#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37188#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37576#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36689#L700-42 assume 1 == ~t6_pc~0; 36690#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36499#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36419#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36420#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37583#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37791#L719-42 assume 1 == ~t7_pc~0; 37300#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36381#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36761#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37024#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 36776#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36777#L738-42 assume !(1 == ~t8_pc~0); 36976#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 36720#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36721#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36238#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36239#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36770#L757-42 assume 1 == ~t9_pc~0; 37113#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36421#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36422#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37174#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36540#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36541#L776-42 assume !(1 == ~t10_pc~0); 37500#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 37501#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37318#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37319#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37826#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37341#L795-42 assume !(1 == ~t11_pc~0); 37342#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 36375#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36376#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36474#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36475#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36786#L814-42 assume 1 == ~t12_pc~0; 37558#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36288#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36289#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36096#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36097#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36250#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36251#L1332-5 assume !(1 == ~T1_E~0); 36226#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36227#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37056#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37226#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37227#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37662#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37834#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37830#L1372-3 assume !(1 == ~T9_E~0); 36082#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36083#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36686#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36687#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37526#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37801#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37176#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36334#L1412-3 assume !(1 == ~E_4~0); 36335#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37076#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37077#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37659#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37421#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37196#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37197#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36130#L1452-3 assume !(1 == ~E_12~0); 36131#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36749#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36591#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36406#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 36326#L1822 assume !(0 == start_simulation_~tmp~3#1); 36327#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37292#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36587#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36084#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 36085#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37248#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37347#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 37687#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 36199#L1803-2 [2023-11-26 11:47:35,316 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:35,316 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2023-11-26 11:47:35,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:35,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761287118] [2023-11-26 11:47:35,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:35,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:35,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:35,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:35,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:35,372 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761287118] [2023-11-26 11:47:35,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1761287118] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:35,373 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:35,373 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:35,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2142282893] [2023-11-26 11:47:35,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:35,374 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:35,374 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:35,374 INFO L85 PathProgramCache]: Analyzing trace with hash 1487059384, now seen corresponding path program 1 times [2023-11-26 11:47:35,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:35,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508146672] [2023-11-26 11:47:35,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:35,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:35,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:35,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:35,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:35,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [508146672] [2023-11-26 11:47:35,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [508146672] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:35,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:35,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:35,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686013590] [2023-11-26 11:47:35,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:35,446 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:35,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:35,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:35,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:35,449 INFO L87 Difference]: Start difference. First operand 1798 states and 2650 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:35,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:35,495 INFO L93 Difference]: Finished difference Result 1798 states and 2649 transitions. [2023-11-26 11:47:35,495 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2649 transitions. [2023-11-26 11:47:35,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:35,517 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2649 transitions. [2023-11-26 11:47:35,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:35,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:35,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2649 transitions. [2023-11-26 11:47:35,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:35,523 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2649 transitions. [2023-11-26 11:47:35,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2649 transitions. [2023-11-26 11:47:35,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:35,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4733036707452725) internal successors, (2649), 1797 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:35,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2649 transitions. [2023-11-26 11:47:35,592 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2649 transitions. [2023-11-26 11:47:35,593 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:35,593 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2649 transitions. [2023-11-26 11:47:35,594 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 11:47:35,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2649 transitions. [2023-11-26 11:47:35,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:35,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:35,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:35,621 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:35,621 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:35,621 INFO L748 eck$LassoCheckResult]: Stem: 39889#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 39890#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40824#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40825#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39959#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 39960#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39864#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39865#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41152#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40505#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40506#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40397#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40398#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40906#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40907#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40156#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40157#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40591#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40592#L1194 assume !(0 == ~M_E~0); 40744#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40745#L1199-1 assume !(0 == ~T2_E~0); 41031#L1204-1 assume !(0 == ~T3_E~0); 40956#L1209-1 assume !(0 == ~T4_E~0); 40957#L1214-1 assume !(0 == ~T5_E~0); 41355#L1219-1 assume !(0 == ~T6_E~0); 41441#L1224-1 assume !(0 == ~T7_E~0); 40230#L1229-1 assume !(0 == ~T8_E~0); 39784#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39785#L1239-1 assume !(0 == ~T10_E~0); 39827#L1244-1 assume !(0 == ~T11_E~0); 39828#L1249-1 assume !(0 == ~T12_E~0); 40535#L1254-1 assume !(0 == ~E_M~0); 39726#L1259-1 assume !(0 == ~E_1~0); 39691#L1264-1 assume !(0 == ~E_2~0); 39692#L1269-1 assume !(0 == ~E_3~0); 41443#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 41387#L1279-1 assume !(0 == ~E_5~0); 39900#L1284-1 assume !(0 == ~E_6~0); 39901#L1289-1 assume !(0 == ~E_7~0); 40598#L1294-1 assume !(0 == ~E_8~0); 40599#L1299-1 assume !(0 == ~E_9~0); 40610#L1304-1 assume !(0 == ~E_10~0); 41434#L1309-1 assume !(0 == ~E_11~0); 41439#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39857#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39781#L586 assume 1 == ~m_pc~0; 39782#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39849#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40670#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40056#L1485 assume !(0 != activate_threads_~tmp~1#1); 40057#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41158#L605 assume !(1 == ~t1_pc~0); 40684#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40426#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40427#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41070#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41005#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40334#L624 assume 1 == ~t2_pc~0; 39831#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39832#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40083#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40084#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 41190#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41068#L643 assume !(1 == ~t3_pc~0); 40926#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40628#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40629#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40163#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 40164#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39921#L662 assume 1 == ~t4_pc~0; 39922#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39880#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39743#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39744#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 39770#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39771#L681 assume !(1 == ~t5_pc~0); 39647#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39648#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40710#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41316#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 40175#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40176#L700 assume 1 == ~t6_pc~0; 40886#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39913#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39914#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39961#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 39962#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41244#L719 assume 1 == ~t7_pc~0; 41325#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40132#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41431#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41373#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 39661#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39662#L738 assume !(1 == ~t8_pc~0); 41038#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40947#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40948#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40740#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40741#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41090#L757 assume 1 == ~t9_pc~0; 41091#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39656#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39657#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40130#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 40702#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40703#L776 assume !(1 == ~t10_pc~0); 39678#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39677#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40060#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39902#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 39903#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39858#L795 assume 1 == ~t11_pc~0; 39859#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40195#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41172#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41343#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 40920#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40910#L814 assume !(1 == ~t12_pc~0); 40770#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40771#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39704#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39705#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 40114#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40115#L1332 assume !(1 == ~M_E~0); 41203#L1332-2 assume !(1 == ~T1_E~0); 41405#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40841#L1342-1 assume !(1 == ~T3_E~0); 40842#L1347-1 assume !(1 == ~T4_E~0); 41231#L1352-1 assume !(1 == ~T5_E~0); 41096#L1357-1 assume !(1 == ~T6_E~0); 40395#L1362-1 assume !(1 == ~T7_E~0); 40396#L1367-1 assume !(1 == ~T8_E~0); 39995#L1372-1 assume !(1 == ~T9_E~0); 39996#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40306#L1382-1 assume !(1 == ~T11_E~0); 40307#L1387-1 assume !(1 == ~T12_E~0); 41003#L1392-1 assume !(1 == ~E_M~0); 40335#L1397-1 assume !(1 == ~E_1~0); 40336#L1402-1 assume !(1 == ~E_2~0); 40010#L1407-1 assume !(1 == ~E_3~0); 40011#L1412-1 assume !(1 == ~E_4~0); 41170#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 41171#L1422-1 assume !(1 == ~E_6~0); 41407#L1427-1 assume !(1 == ~E_7~0); 40196#L1432-1 assume !(1 == ~E_8~0); 40197#L1437-1 assume !(1 == ~E_9~0); 41123#L1442-1 assume !(1 == ~E_10~0); 41124#L1447-1 assume !(1 == ~E_11~0); 40995#L1452-1 assume !(1 == ~E_12~0); 39801#L1457-1 assume { :end_inline_reset_delta_events } true; 39802#L1803-2 [2023-11-26 11:47:35,622 INFO L750 eck$LassoCheckResult]: Loop: 39802#L1803-2 assume !false; 40138#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40087#L1169-1 assume !false; 40207#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40377#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39866#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39867#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 41211#L996 assume !(0 != eval_~tmp~0#1); 40588#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40252#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40253#L1194-3 assume !(0 == ~M_E~0); 40746#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39969#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39970#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40226#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39670#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39671#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40424#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40425#L1229-3 assume !(0 == ~T8_E~0); 40459#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39837#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39838#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40275#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40865#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41349#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40978#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39843#L1269-3 assume !(0 == ~E_3~0); 39844#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41384#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40422#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40423#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40404#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40405#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40797#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40798#L1309-3 assume !(0 == ~E_11~0); 40308#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40309#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40314#L586-42 assume !(1 == ~m_pc~0); 40315#L586-44 is_master_triggered_~__retres1~0#1 := 0; 39911#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39912#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40378#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40452#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40453#L605-42 assume 1 == ~t1_pc~0; 41043#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40763#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40764#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40454#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40455#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40463#L624-42 assume !(1 == ~t2_pc~0); 40464#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40608#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40700#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40701#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40273#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40274#L643-42 assume 1 == ~t3_pc~0; 40632#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40589#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40590#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40419#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40420#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41133#L662-42 assume !(1 == ~t4_pc~0); 41336#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39932#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39933#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41111#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41377#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41344#L681-42 assume 1 == ~t5_pc~0; 40642#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39798#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40790#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40791#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41179#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40292#L700-42 assume 1 == ~t6_pc~0; 40293#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40102#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40022#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40023#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41186#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41394#L719-42 assume 1 == ~t7_pc~0; 40903#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39984#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40364#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40627#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 40379#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40380#L738-42 assume 1 == ~t8_pc~0; 40578#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40323#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40324#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39841#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39842#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40373#L757-42 assume 1 == ~t9_pc~0; 40716#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40024#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40025#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40777#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40143#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40144#L776-42 assume 1 == ~t10_pc~0; 41120#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41104#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40921#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40922#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41429#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40944#L795-42 assume !(1 == ~t11_pc~0); 40945#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 39978#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39979#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40077#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40078#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40389#L814-42 assume !(1 == ~t12_pc~0); 40258#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39891#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39892#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39699#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39700#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39853#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39854#L1332-5 assume !(1 == ~T1_E~0); 39829#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39830#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40659#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40829#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40830#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41265#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41437#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41433#L1372-3 assume !(1 == ~T9_E~0); 39685#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39686#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40289#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40290#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41129#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41404#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40779#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39937#L1412-3 assume !(1 == ~E_4~0); 39938#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40679#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40680#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41262#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41024#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40799#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40800#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 39733#L1452-3 assume !(1 == ~E_12~0); 39734#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40352#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40194#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40009#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 39929#L1822 assume !(0 == start_simulation_~tmp~3#1); 39930#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40895#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40190#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39687#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 39688#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40851#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40950#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 41290#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 39802#L1803-2 [2023-11-26 11:47:35,623 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:35,623 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2023-11-26 11:47:35,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:35,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784996879] [2023-11-26 11:47:35,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:35,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:35,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:35,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:35,697 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:35,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1784996879] [2023-11-26 11:47:35,698 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1784996879] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:35,698 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:35,698 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:35,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023467696] [2023-11-26 11:47:35,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:35,700 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:35,700 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:35,701 INFO L85 PathProgramCache]: Analyzing trace with hash 720925686, now seen corresponding path program 1 times [2023-11-26 11:47:35,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:35,701 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123221488] [2023-11-26 11:47:35,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:35,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:35,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:35,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:35,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:35,788 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123221488] [2023-11-26 11:47:35,788 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [123221488] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:35,789 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:35,789 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:35,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395560277] [2023-11-26 11:47:35,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:35,790 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:35,790 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:35,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:35,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:35,791 INFO L87 Difference]: Start difference. First operand 1798 states and 2649 transitions. cyclomatic complexity: 852 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:35,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:35,837 INFO L93 Difference]: Finished difference Result 1798 states and 2648 transitions. [2023-11-26 11:47:35,837 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2648 transitions. [2023-11-26 11:47:35,848 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:35,858 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2648 transitions. [2023-11-26 11:47:35,858 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:35,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:35,861 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2648 transitions. [2023-11-26 11:47:35,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:35,864 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2648 transitions. [2023-11-26 11:47:35,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2648 transitions. [2023-11-26 11:47:35,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:35,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4727474972191323) internal successors, (2648), 1797 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:35,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2648 transitions. [2023-11-26 11:47:35,904 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2648 transitions. [2023-11-26 11:47:35,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:35,905 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2648 transitions. [2023-11-26 11:47:35,906 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 11:47:35,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2648 transitions. [2023-11-26 11:47:35,914 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:35,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:35,915 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:35,917 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:35,918 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:35,918 INFO L748 eck$LassoCheckResult]: Stem: 43492#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43493#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44427#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44428#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43562#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 43563#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43467#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43468#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44755#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44108#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44109#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44000#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44001#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44509#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44510#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43759#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43760#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44194#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44195#L1194 assume !(0 == ~M_E~0); 44347#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44348#L1199-1 assume !(0 == ~T2_E~0); 44634#L1204-1 assume !(0 == ~T3_E~0); 44559#L1209-1 assume !(0 == ~T4_E~0); 44560#L1214-1 assume !(0 == ~T5_E~0); 44958#L1219-1 assume !(0 == ~T6_E~0); 45044#L1224-1 assume !(0 == ~T7_E~0); 43833#L1229-1 assume !(0 == ~T8_E~0); 43387#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43388#L1239-1 assume !(0 == ~T10_E~0); 43430#L1244-1 assume !(0 == ~T11_E~0); 43431#L1249-1 assume !(0 == ~T12_E~0); 44138#L1254-1 assume !(0 == ~E_M~0); 43329#L1259-1 assume !(0 == ~E_1~0); 43294#L1264-1 assume !(0 == ~E_2~0); 43295#L1269-1 assume !(0 == ~E_3~0); 45046#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44990#L1279-1 assume !(0 == ~E_5~0); 43503#L1284-1 assume !(0 == ~E_6~0); 43504#L1289-1 assume !(0 == ~E_7~0); 44201#L1294-1 assume !(0 == ~E_8~0); 44202#L1299-1 assume !(0 == ~E_9~0); 44213#L1304-1 assume !(0 == ~E_10~0); 45037#L1309-1 assume !(0 == ~E_11~0); 45042#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 43460#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43384#L586 assume 1 == ~m_pc~0; 43385#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43452#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44273#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43659#L1485 assume !(0 != activate_threads_~tmp~1#1); 43660#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44761#L605 assume !(1 == ~t1_pc~0); 44287#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44029#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44030#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44673#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44608#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43937#L624 assume 1 == ~t2_pc~0; 43434#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43435#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43686#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43687#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 44793#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44671#L643 assume !(1 == ~t3_pc~0); 44529#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44231#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44232#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43766#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 43767#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43524#L662 assume 1 == ~t4_pc~0; 43525#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43483#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43346#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43347#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 43373#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43374#L681 assume !(1 == ~t5_pc~0); 43250#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43251#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44313#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44919#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 43778#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43779#L700 assume 1 == ~t6_pc~0; 44489#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43516#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43517#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43564#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 43565#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44847#L719 assume 1 == ~t7_pc~0; 44928#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43735#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45034#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44976#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 43264#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43265#L738 assume !(1 == ~t8_pc~0); 44641#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44550#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44551#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44343#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44344#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44693#L757 assume 1 == ~t9_pc~0; 44694#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43259#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43260#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43733#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 44305#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44306#L776 assume !(1 == ~t10_pc~0); 43281#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43280#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43663#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43505#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 43506#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43461#L795 assume 1 == ~t11_pc~0; 43462#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43798#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44775#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44946#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 44523#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44513#L814 assume !(1 == ~t12_pc~0); 44373#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44374#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43307#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43308#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 43717#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43718#L1332 assume !(1 == ~M_E~0); 44806#L1332-2 assume !(1 == ~T1_E~0); 45008#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44444#L1342-1 assume !(1 == ~T3_E~0); 44445#L1347-1 assume !(1 == ~T4_E~0); 44834#L1352-1 assume !(1 == ~T5_E~0); 44699#L1357-1 assume !(1 == ~T6_E~0); 43998#L1362-1 assume !(1 == ~T7_E~0); 43999#L1367-1 assume !(1 == ~T8_E~0); 43598#L1372-1 assume !(1 == ~T9_E~0); 43599#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43909#L1382-1 assume !(1 == ~T11_E~0); 43910#L1387-1 assume !(1 == ~T12_E~0); 44606#L1392-1 assume !(1 == ~E_M~0); 43938#L1397-1 assume !(1 == ~E_1~0); 43939#L1402-1 assume !(1 == ~E_2~0); 43613#L1407-1 assume !(1 == ~E_3~0); 43614#L1412-1 assume !(1 == ~E_4~0); 44773#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 44774#L1422-1 assume !(1 == ~E_6~0); 45010#L1427-1 assume !(1 == ~E_7~0); 43799#L1432-1 assume !(1 == ~E_8~0); 43800#L1437-1 assume !(1 == ~E_9~0); 44726#L1442-1 assume !(1 == ~E_10~0); 44727#L1447-1 assume !(1 == ~E_11~0); 44598#L1452-1 assume !(1 == ~E_12~0); 43404#L1457-1 assume { :end_inline_reset_delta_events } true; 43405#L1803-2 [2023-11-26 11:47:35,919 INFO L750 eck$LassoCheckResult]: Loop: 43405#L1803-2 assume !false; 43741#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43690#L1169-1 assume !false; 43810#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43980#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43469#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43470#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44814#L996 assume !(0 != eval_~tmp~0#1); 44191#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43855#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43856#L1194-3 assume !(0 == ~M_E~0); 44349#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43572#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43573#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43829#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43273#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43274#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44027#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44028#L1229-3 assume !(0 == ~T8_E~0); 44062#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43440#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43441#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43878#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44468#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 44952#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44581#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43446#L1269-3 assume !(0 == ~E_3~0); 43447#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44987#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44025#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44026#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44007#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44008#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44400#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44401#L1309-3 assume !(0 == ~E_11~0); 43911#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43912#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43917#L586-42 assume !(1 == ~m_pc~0); 43918#L586-44 is_master_triggered_~__retres1~0#1 := 0; 43514#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43515#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43981#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44055#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44056#L605-42 assume 1 == ~t1_pc~0; 44646#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44366#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44367#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44057#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44058#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44066#L624-42 assume !(1 == ~t2_pc~0); 44067#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 44211#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44303#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44304#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43876#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43877#L643-42 assume 1 == ~t3_pc~0; 44235#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44192#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44193#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44022#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44023#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44736#L662-42 assume !(1 == ~t4_pc~0); 44939#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43535#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43536#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44714#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44980#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44947#L681-42 assume 1 == ~t5_pc~0; 44245#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43401#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44393#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44394#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44782#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43895#L700-42 assume 1 == ~t6_pc~0; 43896#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43705#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43625#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43626#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44789#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44997#L719-42 assume !(1 == ~t7_pc~0); 43586#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43587#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43967#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44230#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 43982#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43983#L738-42 assume 1 == ~t8_pc~0; 44181#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43926#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43927#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43444#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43445#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43976#L757-42 assume !(1 == ~t9_pc~0); 44320#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 43627#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43628#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44380#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43746#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43747#L776-42 assume !(1 == ~t10_pc~0); 44706#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 44707#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44524#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44525#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45032#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44547#L795-42 assume !(1 == ~t11_pc~0); 44548#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 43581#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43582#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43680#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43681#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43992#L814-42 assume !(1 == ~t12_pc~0); 43861#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 43494#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43495#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43302#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43303#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43456#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43457#L1332-5 assume !(1 == ~T1_E~0); 43432#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43433#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44262#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44432#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44433#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44868#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45040#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45036#L1372-3 assume !(1 == ~T9_E~0); 43288#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43289#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43892#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43893#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44732#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45007#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44382#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43540#L1412-3 assume !(1 == ~E_4~0); 43541#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44282#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44283#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44865#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44627#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 44402#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44403#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43336#L1452-3 assume !(1 == ~E_12~0); 43337#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43955#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43797#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43612#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 43532#L1822 assume !(0 == start_simulation_~tmp~3#1); 43533#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44498#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43793#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43290#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 43291#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44454#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44553#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 44893#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 43405#L1803-2 [2023-11-26 11:47:35,920 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:35,920 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2023-11-26 11:47:35,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:35,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128840335] [2023-11-26 11:47:35,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:35,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:35,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:36,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:36,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:36,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1128840335] [2023-11-26 11:47:36,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1128840335] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:36,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:36,014 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:36,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818012510] [2023-11-26 11:47:36,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:36,015 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:36,015 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:36,016 INFO L85 PathProgramCache]: Analyzing trace with hash 1679221177, now seen corresponding path program 1 times [2023-11-26 11:47:36,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:36,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [701345351] [2023-11-26 11:47:36,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:36,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:36,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:36,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:36,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:36,084 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [701345351] [2023-11-26 11:47:36,084 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [701345351] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:36,084 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:36,085 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:36,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [871412693] [2023-11-26 11:47:36,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:36,086 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:36,086 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:36,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:36,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:36,087 INFO L87 Difference]: Start difference. First operand 1798 states and 2648 transitions. cyclomatic complexity: 851 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:36,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:36,168 INFO L93 Difference]: Finished difference Result 1798 states and 2643 transitions. [2023-11-26 11:47:36,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2643 transitions. [2023-11-26 11:47:36,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:36,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2643 transitions. [2023-11-26 11:47:36,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2023-11-26 11:47:36,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2023-11-26 11:47:36,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2643 transitions. [2023-11-26 11:47:36,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:36,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2643 transitions. [2023-11-26 11:47:36,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2643 transitions. [2023-11-26 11:47:36,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2023-11-26 11:47:36,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4699666295884315) internal successors, (2643), 1797 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:36,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2643 transitions. [2023-11-26 11:47:36,233 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2643 transitions. [2023-11-26 11:47:36,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:36,234 INFO L428 stractBuchiCegarLoop]: Abstraction has 1798 states and 2643 transitions. [2023-11-26 11:47:36,235 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 11:47:36,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2643 transitions. [2023-11-26 11:47:36,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2023-11-26 11:47:36,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:36,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:36,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:36,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:36,248 INFO L748 eck$LassoCheckResult]: Stem: 47097#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47098#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 48030#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48031#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47165#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 47166#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47070#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47071#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48358#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47711#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47712#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47603#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47604#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48112#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48113#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47362#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47363#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47797#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47798#L1194 assume !(0 == ~M_E~0); 47950#L1194-2 assume !(0 == ~T1_E~0); 47951#L1199-1 assume !(0 == ~T2_E~0); 48237#L1204-1 assume !(0 == ~T3_E~0); 48162#L1209-1 assume !(0 == ~T4_E~0); 48163#L1214-1 assume !(0 == ~T5_E~0); 48561#L1219-1 assume !(0 == ~T6_E~0); 48647#L1224-1 assume !(0 == ~T7_E~0); 47436#L1229-1 assume !(0 == ~T8_E~0); 46990#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46991#L1239-1 assume !(0 == ~T10_E~0); 47033#L1244-1 assume !(0 == ~T11_E~0); 47034#L1249-1 assume !(0 == ~T12_E~0); 47741#L1254-1 assume !(0 == ~E_M~0); 46932#L1259-1 assume !(0 == ~E_1~0); 46897#L1264-1 assume !(0 == ~E_2~0); 46898#L1269-1 assume !(0 == ~E_3~0); 48649#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 48593#L1279-1 assume !(0 == ~E_5~0); 47106#L1284-1 assume !(0 == ~E_6~0); 47107#L1289-1 assume !(0 == ~E_7~0); 47804#L1294-1 assume !(0 == ~E_8~0); 47805#L1299-1 assume !(0 == ~E_9~0); 47816#L1304-1 assume !(0 == ~E_10~0); 48640#L1309-1 assume !(0 == ~E_11~0); 48645#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 47063#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46987#L586 assume 1 == ~m_pc~0; 46988#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47055#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47876#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47262#L1485 assume !(0 != activate_threads_~tmp~1#1); 47263#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48364#L605 assume !(1 == ~t1_pc~0); 47890#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47632#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47633#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48276#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48211#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47540#L624 assume 1 == ~t2_pc~0; 47037#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47038#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47289#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47290#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 48396#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48274#L643 assume !(1 == ~t3_pc~0); 48132#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47834#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47835#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47369#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 47370#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47127#L662 assume 1 == ~t4_pc~0; 47128#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47086#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46949#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46950#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 46976#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46977#L681 assume !(1 == ~t5_pc~0); 46853#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46854#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47916#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48522#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 47381#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47382#L700 assume 1 == ~t6_pc~0; 48092#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47119#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47120#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47167#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 47168#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48450#L719 assume 1 == ~t7_pc~0; 48531#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47338#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48637#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48579#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 46867#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46868#L738 assume !(1 == ~t8_pc~0); 48244#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48153#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48154#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47946#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47947#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48296#L757 assume 1 == ~t9_pc~0; 48297#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46862#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46863#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47336#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 47908#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47909#L776 assume !(1 == ~t10_pc~0); 46884#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46883#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47266#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47108#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 47109#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47064#L795 assume 1 == ~t11_pc~0; 47065#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47401#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48378#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48549#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 48126#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48116#L814 assume !(1 == ~t12_pc~0); 47976#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47977#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46910#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46911#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 47320#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47321#L1332 assume !(1 == ~M_E~0); 48409#L1332-2 assume !(1 == ~T1_E~0); 48611#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48047#L1342-1 assume !(1 == ~T3_E~0); 48048#L1347-1 assume !(1 == ~T4_E~0); 48437#L1352-1 assume !(1 == ~T5_E~0); 48302#L1357-1 assume !(1 == ~T6_E~0); 47601#L1362-1 assume !(1 == ~T7_E~0); 47602#L1367-1 assume !(1 == ~T8_E~0); 47201#L1372-1 assume !(1 == ~T9_E~0); 47202#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47512#L1382-1 assume !(1 == ~T11_E~0); 47513#L1387-1 assume !(1 == ~T12_E~0); 48209#L1392-1 assume !(1 == ~E_M~0); 47541#L1397-1 assume !(1 == ~E_1~0); 47542#L1402-1 assume !(1 == ~E_2~0); 47216#L1407-1 assume !(1 == ~E_3~0); 47217#L1412-1 assume !(1 == ~E_4~0); 48376#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 48377#L1422-1 assume !(1 == ~E_6~0); 48613#L1427-1 assume !(1 == ~E_7~0); 47402#L1432-1 assume !(1 == ~E_8~0); 47403#L1437-1 assume !(1 == ~E_9~0); 48329#L1442-1 assume !(1 == ~E_10~0); 48330#L1447-1 assume !(1 == ~E_11~0); 48201#L1452-1 assume !(1 == ~E_12~0); 47007#L1457-1 assume { :end_inline_reset_delta_events } true; 47008#L1803-2 [2023-11-26 11:47:36,249 INFO L750 eck$LassoCheckResult]: Loop: 47008#L1803-2 assume !false; 47344#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47293#L1169-1 assume !false; 47413#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47583#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47072#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47073#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 48417#L996 assume !(0 != eval_~tmp~0#1); 47794#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47458#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47459#L1194-3 assume !(0 == ~M_E~0); 47952#L1194-5 assume !(0 == ~T1_E~0); 47175#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47176#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47432#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46876#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46877#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47630#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47631#L1229-3 assume !(0 == ~T8_E~0); 47665#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47043#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47044#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47481#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 48071#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48555#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48184#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47049#L1269-3 assume !(0 == ~E_3~0); 47050#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48590#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47628#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47629#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47610#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47611#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 48003#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48004#L1309-3 assume !(0 == ~E_11~0); 47514#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47515#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47520#L586-42 assume !(1 == ~m_pc~0); 47521#L586-44 is_master_triggered_~__retres1~0#1 := 0; 47117#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47118#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47584#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47658#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47659#L605-42 assume 1 == ~t1_pc~0; 48249#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47969#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47970#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47660#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47661#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47669#L624-42 assume !(1 == ~t2_pc~0); 47670#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47814#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47906#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47907#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47479#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47480#L643-42 assume 1 == ~t3_pc~0; 47838#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47795#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47796#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47625#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47626#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48339#L662-42 assume !(1 == ~t4_pc~0); 48542#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 47138#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47139#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48317#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48583#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48550#L681-42 assume 1 == ~t5_pc~0; 47848#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47004#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47996#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47997#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48385#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47498#L700-42 assume 1 == ~t6_pc~0; 47499#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47308#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47228#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47229#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48392#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48600#L719-42 assume !(1 == ~t7_pc~0); 47189#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 47190#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47570#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47833#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 47585#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47586#L738-42 assume 1 == ~t8_pc~0; 47784#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47529#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47530#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47047#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47048#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47579#L757-42 assume 1 == ~t9_pc~0; 47922#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47230#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47231#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47983#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47349#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47350#L776-42 assume !(1 == ~t10_pc~0); 48309#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 48310#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48127#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48128#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48635#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48150#L795-42 assume !(1 == ~t11_pc~0); 48151#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 47184#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47185#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47283#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47284#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47595#L814-42 assume !(1 == ~t12_pc~0); 47464#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 47095#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47096#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46905#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46906#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47059#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47060#L1332-5 assume !(1 == ~T1_E~0); 47035#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47036#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47865#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48035#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48036#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48471#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48643#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48639#L1372-3 assume !(1 == ~T9_E~0); 46891#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46892#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47495#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47496#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48335#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48610#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47985#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47143#L1412-3 assume !(1 == ~E_4~0); 47144#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47885#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47886#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48468#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48230#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 48005#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 48006#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46939#L1452-3 assume !(1 == ~E_12~0); 46940#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47558#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47400#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47215#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 47135#L1822 assume !(0 == start_simulation_~tmp~3#1); 47136#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48101#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47396#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 46894#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48057#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48156#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 48496#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 47008#L1803-2 [2023-11-26 11:47:36,249 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:36,250 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2023-11-26 11:47:36,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:36,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941903060] [2023-11-26 11:47:36,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:36,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:36,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:36,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:36,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:36,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941903060] [2023-11-26 11:47:36,377 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [941903060] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:36,377 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:36,377 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:36,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147511319] [2023-11-26 11:47:36,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:36,378 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:36,378 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:36,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1528847034, now seen corresponding path program 1 times [2023-11-26 11:47:36,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:36,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1871719388] [2023-11-26 11:47:36,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:36,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:36,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:36,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:36,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:36,490 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1871719388] [2023-11-26 11:47:36,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1871719388] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:36,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:36,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:36,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193715934] [2023-11-26 11:47:36,492 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:36,493 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:36,493 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:36,494 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:47:36,494 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:47:36,494 INFO L87 Difference]: Start difference. First operand 1798 states and 2643 transitions. cyclomatic complexity: 846 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:36,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:36,712 INFO L93 Difference]: Finished difference Result 3340 states and 4894 transitions. [2023-11-26 11:47:36,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3340 states and 4894 transitions. [2023-11-26 11:47:36,735 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3151 [2023-11-26 11:47:36,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3340 states to 3340 states and 4894 transitions. [2023-11-26 11:47:36,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3340 [2023-11-26 11:47:36,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3340 [2023-11-26 11:47:36,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3340 states and 4894 transitions. [2023-11-26 11:47:36,774 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:36,774 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3340 states and 4894 transitions. [2023-11-26 11:47:36,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3340 states and 4894 transitions. [2023-11-26 11:47:36,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3340 to 3340. [2023-11-26 11:47:36,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3340 states, 3340 states have (on average 1.4652694610778443) internal successors, (4894), 3339 states have internal predecessors, (4894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:36,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3340 states to 3340 states and 4894 transitions. [2023-11-26 11:47:36,861 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3340 states and 4894 transitions. [2023-11-26 11:47:36,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:47:36,862 INFO L428 stractBuchiCegarLoop]: Abstraction has 3340 states and 4894 transitions. [2023-11-26 11:47:36,862 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 11:47:36,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3340 states and 4894 transitions. [2023-11-26 11:47:36,878 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3151 [2023-11-26 11:47:36,878 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:36,878 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:36,881 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:36,881 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:36,882 INFO L748 eck$LassoCheckResult]: Stem: 52245#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 53205#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53206#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52313#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 52314#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52218#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52219#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53557#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52871#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52872#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52760#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52761#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53286#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53287#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52512#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 52513#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 52964#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52965#L1194 assume !(0 == ~M_E~0); 53120#L1194-2 assume !(0 == ~T1_E~0); 53121#L1199-1 assume !(0 == ~T2_E~0); 53422#L1204-1 assume !(0 == ~T3_E~0); 53344#L1209-1 assume !(0 == ~T4_E~0); 53345#L1214-1 assume !(0 == ~T5_E~0); 53788#L1219-1 assume !(0 == ~T6_E~0); 53903#L1224-1 assume !(0 == ~T7_E~0); 52590#L1229-1 assume !(0 == ~T8_E~0); 52146#L1234-1 assume !(0 == ~T9_E~0); 52147#L1239-1 assume !(0 == ~T10_E~0); 52183#L1244-1 assume !(0 == ~T11_E~0); 52184#L1249-1 assume !(0 == ~T12_E~0); 52902#L1254-1 assume !(0 == ~E_M~0); 52080#L1259-1 assume !(0 == ~E_1~0); 52045#L1264-1 assume !(0 == ~E_2~0); 52046#L1269-1 assume !(0 == ~E_3~0); 53907#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53826#L1279-1 assume !(0 == ~E_5~0); 52254#L1284-1 assume !(0 == ~E_6~0); 52255#L1289-1 assume !(0 == ~E_7~0); 52971#L1294-1 assume !(0 == ~E_8~0); 52972#L1299-1 assume !(0 == ~E_9~0); 52983#L1304-1 assume !(0 == ~E_10~0); 53890#L1309-1 assume !(0 == ~E_11~0); 53900#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 52212#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52135#L586 assume 1 == ~m_pc~0; 52136#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52203#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53044#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52410#L1485 assume !(0 != activate_threads_~tmp~1#1); 52411#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53566#L605 assume !(1 == ~t1_pc~0); 53059#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52791#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52792#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53465#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53394#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52695#L624 assume 1 == ~t2_pc~0; 52188#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52189#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52438#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52439#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 53604#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53463#L643 assume !(1 == ~t3_pc~0); 53309#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53008#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53009#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52520#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 52521#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52275#L662 assume 1 == ~t4_pc~0; 52276#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52234#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52100#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52101#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 52126#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52127#L681 assume !(1 == ~t5_pc~0); 52001#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52002#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53085#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53746#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 52532#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52533#L700 assume 1 == ~t6_pc~0; 53266#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52267#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52268#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52315#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 52316#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53665#L719 assume 1 == ~t7_pc~0; 53758#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52487#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53881#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53810#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 52015#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52016#L738 assume !(1 == ~t8_pc~0); 53429#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 53334#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53335#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53116#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53117#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53490#L757 assume 1 == ~t9_pc~0; 53491#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52010#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52011#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52485#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 53077#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53078#L776 assume !(1 == ~t10_pc~0); 52032#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52031#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52417#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52256#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 52257#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52213#L795 assume 1 == ~t11_pc~0; 52214#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52555#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53584#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53776#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 53303#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53290#L814 assume !(1 == ~t12_pc~0); 53147#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53148#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52061#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52062#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 52469#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52470#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 53618#L1332-2 assume !(1 == ~T1_E~0); 53850#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53223#L1342-1 assume !(1 == ~T3_E~0); 53224#L1347-1 assume !(1 == ~T4_E~0); 53653#L1352-1 assume !(1 == ~T5_E~0); 53496#L1357-1 assume !(1 == ~T6_E~0); 52758#L1362-1 assume !(1 == ~T7_E~0); 52759#L1367-1 assume !(1 == ~T8_E~0); 52351#L1372-1 assume !(1 == ~T9_E~0); 52352#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52667#L1382-1 assume !(1 == ~T11_E~0); 52668#L1387-1 assume !(1 == ~T12_E~0); 53391#L1392-1 assume !(1 == ~E_M~0); 52696#L1397-1 assume !(1 == ~E_1~0); 52697#L1402-1 assume !(1 == ~E_2~0); 52366#L1407-1 assume !(1 == ~E_3~0); 52367#L1412-1 assume !(1 == ~E_4~0); 53582#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 53583#L1422-1 assume !(1 == ~E_6~0); 53851#L1427-1 assume !(1 == ~E_7~0); 52556#L1432-1 assume !(1 == ~E_8~0); 52557#L1437-1 assume !(1 == ~E_9~0); 53525#L1442-1 assume !(1 == ~E_10~0); 53526#L1447-1 assume !(1 == ~E_11~0); 53383#L1452-1 assume !(1 == ~E_12~0); 52155#L1457-1 assume { :end_inline_reset_delta_events } true; 52156#L1803-2 [2023-11-26 11:47:36,883 INFO L750 eck$LassoCheckResult]: Loop: 52156#L1803-2 assume !false; 52493#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52442#L1169-1 assume !false; 52571#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52740#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52220#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52221#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 53627#L996 assume !(0 != eval_~tmp~0#1); 53629#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52614#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52615#L1194-3 assume !(0 == ~M_E~0); 53893#L1194-5 assume !(0 == ~T1_E~0); 52323#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52324#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52584#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52028#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52029#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52789#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52790#L1229-3 assume !(0 == ~T8_E~0); 52830#L1234-3 assume !(0 == ~T9_E~0); 52191#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 52192#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52634#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53245#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53781#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53366#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52197#L1269-3 assume !(0 == ~E_3~0); 52198#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53823#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52787#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52788#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 52768#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 52769#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53175#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53176#L1309-3 assume !(0 == ~E_11~0); 52669#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52670#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52675#L586-42 assume !(1 == ~m_pc~0); 52676#L586-44 is_master_triggered_~__retres1~0#1 := 0; 52262#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52263#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52741#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52817#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52818#L605-42 assume 1 == ~t1_pc~0; 53434#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53140#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53141#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52819#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52820#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52827#L624-42 assume !(1 == ~t2_pc~0); 52828#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 52979#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53075#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53076#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52632#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52633#L643-42 assume 1 == ~t3_pc~0; 53004#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52958#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52959#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52784#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52785#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53536#L662-42 assume !(1 == ~t4_pc~0); 53766#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 52286#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52287#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53511#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53814#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53775#L681-42 assume !(1 == ~t5_pc~0); 52151#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 52152#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53168#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53169#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53591#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52652#L700-42 assume !(1 == ~t6_pc~0); 52456#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 52457#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52376#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52377#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53600#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53836#L719-42 assume !(1 == ~t7_pc~0); 52337#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 52338#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52727#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53001#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 52742#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52743#L738-42 assume 1 == ~t8_pc~0; 52948#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52684#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52685#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52195#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52196#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52736#L757-42 assume 1 == ~t9_pc~0; 53089#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52378#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52379#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53155#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52497#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52498#L776-42 assume 1 == ~t10_pc~0; 53522#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53504#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53304#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53305#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53879#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53331#L795-42 assume !(1 == ~t11_pc~0); 53332#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 52332#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52333#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52432#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52433#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52752#L814-42 assume 1 == ~t12_pc~0; 53572#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52243#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52244#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52053#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 52054#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52207#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 52208#L1332-5 assume !(1 == ~T1_E~0); 52181#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52182#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53033#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53209#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53210#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53687#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53898#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53883#L1372-3 assume !(1 == ~T9_E~0); 52039#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52040#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52649#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52650#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53532#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53848#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53157#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 52291#L1412-3 assume !(1 == ~E_4~0); 52292#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53053#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53054#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53683#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53415#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53177#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53178#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 52087#L1452-3 assume !(1 == ~E_12~0); 52088#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52713#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52552#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52363#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 52283#L1822 assume !(0 == start_simulation_~tmp~3#1); 52284#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53275#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52548#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 52042#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53231#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53338#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 53715#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 52156#L1803-2 [2023-11-26 11:47:36,884 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:36,885 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2023-11-26 11:47:36,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:36,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982477481] [2023-11-26 11:47:36,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:36,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:36,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:36,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:36,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:36,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982477481] [2023-11-26 11:47:36,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1982477481] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:36,986 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:36,986 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:36,986 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1114496127] [2023-11-26 11:47:36,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:36,987 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:36,987 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:36,988 INFO L85 PathProgramCache]: Analyzing trace with hash -759202564, now seen corresponding path program 1 times [2023-11-26 11:47:36,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:36,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195414684] [2023-11-26 11:47:36,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:36,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:37,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:37,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:37,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:37,058 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195414684] [2023-11-26 11:47:37,058 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195414684] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:37,058 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:37,058 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:37,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171551179] [2023-11-26 11:47:37,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:37,059 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:37,059 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:37,059 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:47:37,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:47:37,060 INFO L87 Difference]: Start difference. First operand 3340 states and 4894 transitions. cyclomatic complexity: 1556 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:37,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:37,291 INFO L93 Difference]: Finished difference Result 6214 states and 9085 transitions. [2023-11-26 11:47:37,291 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6214 states and 9085 transitions. [2023-11-26 11:47:37,326 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5997 [2023-11-26 11:47:37,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6214 states to 6214 states and 9085 transitions. [2023-11-26 11:47:37,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6214 [2023-11-26 11:47:37,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6214 [2023-11-26 11:47:37,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6214 states and 9085 transitions. [2023-11-26 11:47:37,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:37,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6214 states and 9085 transitions. [2023-11-26 11:47:37,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6214 states and 9085 transitions. [2023-11-26 11:47:37,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6214 to 6212. [2023-11-26 11:47:37,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6212 states, 6212 states have (on average 1.4621699935608499) internal successors, (9083), 6211 states have internal predecessors, (9083), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:37,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6212 states to 6212 states and 9083 transitions. [2023-11-26 11:47:37,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6212 states and 9083 transitions. [2023-11-26 11:47:37,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:47:37,573 INFO L428 stractBuchiCegarLoop]: Abstraction has 6212 states and 9083 transitions. [2023-11-26 11:47:37,573 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 11:47:37,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6212 states and 9083 transitions. [2023-11-26 11:47:37,598 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5997 [2023-11-26 11:47:37,599 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:37,599 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:37,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:37,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:37,602 INFO L748 eck$LassoCheckResult]: Stem: 61808#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 61809#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 62764#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62765#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61879#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 61880#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61783#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61784#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63117#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62438#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62439#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62329#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 62330#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62851#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62852#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62082#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 62083#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 62528#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62529#L1194 assume !(0 == ~M_E~0); 62684#L1194-2 assume !(0 == ~T1_E~0); 62685#L1199-1 assume !(0 == ~T2_E~0); 62985#L1204-1 assume !(0 == ~T3_E~0); 62901#L1209-1 assume !(0 == ~T4_E~0); 62902#L1214-1 assume !(0 == ~T5_E~0); 63350#L1219-1 assume !(0 == ~T6_E~0); 63466#L1224-1 assume !(0 == ~T7_E~0); 62157#L1229-1 assume !(0 == ~T8_E~0); 61702#L1234-1 assume !(0 == ~T9_E~0); 61703#L1239-1 assume !(0 == ~T10_E~0); 61745#L1244-1 assume !(0 == ~T11_E~0); 61746#L1249-1 assume !(0 == ~T12_E~0); 62470#L1254-1 assume !(0 == ~E_M~0); 61644#L1259-1 assume !(0 == ~E_1~0); 61609#L1264-1 assume !(0 == ~E_2~0); 61610#L1269-1 assume !(0 == ~E_3~0); 63472#L1274-1 assume !(0 == ~E_4~0); 63387#L1279-1 assume !(0 == ~E_5~0); 61819#L1284-1 assume !(0 == ~E_6~0); 61820#L1289-1 assume !(0 == ~E_7~0); 62535#L1294-1 assume !(0 == ~E_8~0); 62536#L1299-1 assume !(0 == ~E_9~0); 62547#L1304-1 assume !(0 == ~E_10~0); 63454#L1309-1 assume !(0 == ~E_11~0); 63462#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 61776#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61699#L586 assume 1 == ~m_pc~0; 61700#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61767#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62609#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61979#L1485 assume !(0 != activate_threads_~tmp~1#1); 61980#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63125#L605 assume !(1 == ~t1_pc~0); 62623#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62359#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62360#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63026#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62952#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62264#L624 assume 1 == ~t2_pc~0; 61749#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61750#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62006#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62007#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 63160#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63024#L643 assume !(1 == ~t3_pc~0); 62871#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62567#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62568#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62089#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 62090#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61840#L662 assume 1 == ~t4_pc~0; 61841#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61799#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61661#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61662#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 61688#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61689#L681 assume !(1 == ~t5_pc~0); 61565#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 61566#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62650#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63299#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 62101#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62102#L700 assume 1 == ~t6_pc~0; 62831#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61832#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61833#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61881#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 61882#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63223#L719 assume 1 == ~t7_pc~0; 63311#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62055#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63445#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63372#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 61579#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61580#L738 assume !(1 == ~t8_pc~0); 62992#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62892#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62893#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62680#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62681#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63046#L757 assume 1 == ~t9_pc~0; 63047#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61574#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61575#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62053#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 62642#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62643#L776 assume !(1 == ~t10_pc~0); 61596#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 61595#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61983#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 61821#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 61822#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61777#L795 assume 1 == ~t11_pc~0; 61778#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62121#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63142#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 63334#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 62865#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62855#L814 assume !(1 == ~t12_pc~0); 62710#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62711#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61622#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61623#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 62037#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62038#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 63177#L1332-2 assume !(1 == ~T1_E~0); 63791#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63790#L1342-1 assume !(1 == ~T3_E~0); 63789#L1347-1 assume !(1 == ~T4_E~0); 63788#L1352-1 assume !(1 == ~T5_E~0); 63787#L1357-1 assume !(1 == ~T6_E~0); 63786#L1362-1 assume !(1 == ~T7_E~0); 63785#L1367-1 assume !(1 == ~T8_E~0); 61915#L1372-1 assume !(1 == ~T9_E~0); 61916#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62236#L1382-1 assume !(1 == ~T11_E~0); 62237#L1387-1 assume !(1 == ~T12_E~0); 62950#L1392-1 assume !(1 == ~E_M~0); 62265#L1397-1 assume !(1 == ~E_1~0); 62266#L1402-1 assume !(1 == ~E_2~0); 61930#L1407-1 assume !(1 == ~E_3~0); 61931#L1412-1 assume !(1 == ~E_4~0); 63728#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 63714#L1422-1 assume !(1 == ~E_6~0); 63712#L1427-1 assume !(1 == ~E_7~0); 63710#L1432-1 assume !(1 == ~E_8~0); 63709#L1437-1 assume !(1 == ~E_9~0); 63708#L1442-1 assume !(1 == ~E_10~0); 63706#L1447-1 assume !(1 == ~E_11~0); 63528#L1452-1 assume !(1 == ~E_12~0); 63519#L1457-1 assume { :end_inline_reset_delta_events } true; 63512#L1803-2 [2023-11-26 11:47:37,603 INFO L750 eck$LassoCheckResult]: Loop: 63512#L1803-2 assume !false; 63506#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63502#L1169-1 assume !false; 63501#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63498#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63487#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63486#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 63484#L996 assume !(0 != eval_~tmp~0#1); 63483#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63482#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63480#L1194-3 assume !(0 == ~M_E~0); 63481#L1194-5 assume !(0 == ~T1_E~0); 65039#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65037#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65035#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65033#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65031#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65029#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 65027#L1229-3 assume !(0 == ~T8_E~0); 65025#L1234-3 assume !(0 == ~T9_E~0); 65023#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 65021#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 65019#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 65017#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 65015#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 65013#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65011#L1269-3 assume !(0 == ~E_3~0); 65009#L1274-3 assume !(0 == ~E_4~0); 65007#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65005#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65003#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 65001#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64999#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 64997#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 64995#L1309-3 assume !(0 == ~E_11~0); 64993#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 64991#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64989#L586-42 assume 1 == ~m_pc~0; 64985#L587-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 64983#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64981#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64979#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 64977#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64975#L605-42 assume 1 == ~t1_pc~0; 64971#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64969#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64967#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64965#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64963#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64961#L624-42 assume !(1 == ~t2_pc~0); 64957#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 64955#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64953#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64951#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64949#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64947#L643-42 assume !(1 == ~t3_pc~0); 64944#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 64941#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64939#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64937#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64935#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64933#L662-42 assume !(1 == ~t4_pc~0); 64929#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 64927#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64925#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64923#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64921#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64919#L681-42 assume 1 == ~t5_pc~0; 64915#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64913#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64911#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64909#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64907#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64905#L700-42 assume !(1 == ~t6_pc~0); 64901#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 64899#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64897#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64895#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64893#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64891#L719-42 assume 1 == ~t7_pc~0; 64887#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64885#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64883#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64881#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 64879#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64877#L738-42 assume 1 == ~t8_pc~0; 64873#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 64871#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64869#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64867#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 64865#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64863#L757-42 assume !(1 == ~t9_pc~0); 64859#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 64857#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64855#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64853#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64851#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64849#L776-42 assume 1 == ~t10_pc~0; 64845#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64843#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64841#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64839#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 64837#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64835#L795-42 assume !(1 == ~t11_pc~0); 64830#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 64826#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64823#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64820#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 64817#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64814#L814-42 assume 1 == ~t12_pc~0; 64809#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 64805#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64802#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64799#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64796#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64793#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61772#L1332-5 assume !(1 == ~T1_E~0); 64787#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64784#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64781#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64778#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64775#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64772#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64768#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64764#L1372-3 assume !(1 == ~T9_E~0); 64762#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64760#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 64758#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64756#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64753#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64751#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64749#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64492#L1412-3 assume !(1 == ~E_4~0); 64490#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64489#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 64488#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64479#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 64467#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64460#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 64455#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 64451#L1452-3 assume !(1 == ~E_12~0); 64444#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64425#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64418#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64415#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 64411#L1822 assume !(0 == start_simulation_~tmp~3#1); 63050#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64401#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64385#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64381#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 64375#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63533#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63529#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 63520#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 63512#L1803-2 [2023-11-26 11:47:37,604 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:37,604 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2023-11-26 11:47:37,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:37,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034279334] [2023-11-26 11:47:37,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:37,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:37,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:37,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:37,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:37,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1034279334] [2023-11-26 11:47:37,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1034279334] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:37,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:37,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:37,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523425140] [2023-11-26 11:47:37,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:37,705 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:37,705 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:37,705 INFO L85 PathProgramCache]: Analyzing trace with hash -800717635, now seen corresponding path program 1 times [2023-11-26 11:47:37,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:37,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [991003315] [2023-11-26 11:47:37,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:37,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:37,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:37,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:37,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:37,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [991003315] [2023-11-26 11:47:37,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [991003315] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:37,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:37,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:37,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136719011] [2023-11-26 11:47:37,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:37,777 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:37,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:37,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:47:37,778 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:47:37,778 INFO L87 Difference]: Start difference. First operand 6212 states and 9083 transitions. cyclomatic complexity: 2875 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:38,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:38,049 INFO L93 Difference]: Finished difference Result 11734 states and 17118 transitions. [2023-11-26 11:47:38,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11734 states and 17118 transitions. [2023-11-26 11:47:38,102 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11503 [2023-11-26 11:47:38,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11734 states to 11734 states and 17118 transitions. [2023-11-26 11:47:38,145 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11734 [2023-11-26 11:47:38,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11734 [2023-11-26 11:47:38,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11734 states and 17118 transitions. [2023-11-26 11:47:38,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:38,260 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11734 states and 17118 transitions. [2023-11-26 11:47:38,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11734 states and 17118 transitions. [2023-11-26 11:47:38,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11734 to 11730. [2023-11-26 11:47:38,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11730 states, 11730 states have (on average 1.458994032395567) internal successors, (17114), 11729 states have internal predecessors, (17114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:38,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11730 states to 11730 states and 17114 transitions. [2023-11-26 11:47:38,489 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11730 states and 17114 transitions. [2023-11-26 11:47:38,490 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:47:38,490 INFO L428 stractBuchiCegarLoop]: Abstraction has 11730 states and 17114 transitions. [2023-11-26 11:47:38,490 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 11:47:38,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11730 states and 17114 transitions. [2023-11-26 11:47:38,530 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11503 [2023-11-26 11:47:38,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:38,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:38,534 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:38,534 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:38,534 INFO L748 eck$LassoCheckResult]: Stem: 79765#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 79766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 80713#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80714#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79836#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 79837#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79740#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79741#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81059#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80386#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 80387#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 80277#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 80278#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 80796#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 80797#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 80034#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 80035#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 80473#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80474#L1194 assume !(0 == ~M_E~0); 80631#L1194-2 assume !(0 == ~T1_E~0); 80632#L1199-1 assume !(0 == ~T2_E~0); 80931#L1204-1 assume !(0 == ~T3_E~0); 80849#L1209-1 assume !(0 == ~T4_E~0); 80850#L1214-1 assume !(0 == ~T5_E~0); 81274#L1219-1 assume !(0 == ~T6_E~0); 81375#L1224-1 assume !(0 == ~T7_E~0); 80109#L1229-1 assume !(0 == ~T8_E~0); 79659#L1234-1 assume !(0 == ~T9_E~0); 79660#L1239-1 assume !(0 == ~T10_E~0); 79702#L1244-1 assume !(0 == ~T11_E~0); 79703#L1249-1 assume !(0 == ~T12_E~0); 80416#L1254-1 assume !(0 == ~E_M~0); 79601#L1259-1 assume !(0 == ~E_1~0); 79565#L1264-1 assume !(0 == ~E_2~0); 79566#L1269-1 assume !(0 == ~E_3~0); 81378#L1274-1 assume !(0 == ~E_4~0); 81310#L1279-1 assume !(0 == ~E_5~0); 79776#L1284-1 assume !(0 == ~E_6~0); 79777#L1289-1 assume !(0 == ~E_7~0); 80480#L1294-1 assume !(0 == ~E_8~0); 80481#L1299-1 assume !(0 == ~E_9~0); 80493#L1304-1 assume !(0 == ~E_10~0); 81367#L1309-1 assume !(0 == ~E_11~0); 81372#L1314-1 assume !(0 == ~E_12~0); 79733#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79656#L586 assume 1 == ~m_pc~0; 79657#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 79724#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80555#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 79934#L1485 assume !(0 != activate_threads_~tmp~1#1); 79935#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81066#L605 assume !(1 == ~t1_pc~0); 80569#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 80306#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80307#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80972#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80902#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80213#L624 assume 1 == ~t2_pc~0; 79706#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79707#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79961#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79962#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 81099#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80970#L643 assume !(1 == ~t3_pc~0); 80816#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 80512#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80513#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 80041#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 80042#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79797#L662 assume 1 == ~t4_pc~0; 79798#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79756#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79618#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79619#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 79645#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79646#L681 assume !(1 == ~t5_pc~0); 79521#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 79522#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80597#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81231#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 80053#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80054#L700 assume 1 == ~t6_pc~0; 80776#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 79789#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79790#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 79838#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 79839#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81155#L719 assume 1 == ~t7_pc~0; 81243#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 80010#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81360#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81293#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 79535#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79536#L738 assume !(1 == ~t8_pc~0); 80938#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 80840#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80841#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 80627#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 80628#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80992#L757 assume 1 == ~t9_pc~0; 80993#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 79530#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 79531#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80008#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 80589#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80590#L776 assume !(1 == ~t10_pc~0); 79552#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 79551#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 79938#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 79778#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 79779#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79734#L795 assume 1 == ~t11_pc~0; 79735#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80074#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81081#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81262#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 80810#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 80800#L814 assume !(1 == ~t12_pc~0); 80657#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 80658#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 79578#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 79579#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 79992#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79993#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 81112#L1332-2 assume !(1 == ~T1_E~0); 81332#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80730#L1342-1 assume !(1 == ~T3_E~0); 80731#L1347-1 assume !(1 == ~T4_E~0); 81306#L1352-1 assume !(1 == ~T5_E~0); 82021#L1357-1 assume !(1 == ~T6_E~0); 82019#L1362-1 assume !(1 == ~T7_E~0); 81190#L1367-1 assume !(1 == ~T8_E~0); 81191#L1372-1 assume !(1 == ~T9_E~0); 81991#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 81985#L1382-1 assume !(1 == ~T11_E~0); 81983#L1387-1 assume !(1 == ~T12_E~0); 81966#L1392-1 assume !(1 == ~E_M~0); 81959#L1397-1 assume !(1 == ~E_1~0); 81952#L1402-1 assume !(1 == ~E_2~0); 81946#L1407-1 assume !(1 == ~E_3~0); 81939#L1412-1 assume !(1 == ~E_4~0); 81933#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 81929#L1422-1 assume !(1 == ~E_6~0); 81926#L1427-1 assume !(1 == ~E_7~0); 81923#L1432-1 assume !(1 == ~E_8~0); 81921#L1437-1 assume !(1 == ~E_9~0); 81918#L1442-1 assume !(1 == ~E_10~0); 81434#L1447-1 assume !(1 == ~E_11~0); 81432#L1452-1 assume !(1 == ~E_12~0); 81421#L1457-1 assume { :end_inline_reset_delta_events } true; 81414#L1803-2 [2023-11-26 11:47:38,535 INFO L750 eck$LassoCheckResult]: Loop: 81414#L1803-2 assume !false; 81408#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81404#L1169-1 assume !false; 81403#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81400#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81389#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81388#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 81386#L996 assume !(0 != eval_~tmp~0#1); 81385#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81384#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81382#L1194-3 assume !(0 == ~M_E~0); 81383#L1194-5 assume !(0 == ~T1_E~0); 83387#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 83384#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 83381#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83378#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 83375#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 83372#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 83369#L1229-3 assume !(0 == ~T8_E~0); 83366#L1234-3 assume !(0 == ~T9_E~0); 83363#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 83360#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 83357#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 83354#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 83351#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 83348#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 83345#L1269-3 assume !(0 == ~E_3~0); 83342#L1274-3 assume !(0 == ~E_4~0); 83339#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 83336#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 83333#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 83330#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 83327#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 83324#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 83321#L1309-3 assume !(0 == ~E_11~0); 83318#L1314-3 assume !(0 == ~E_12~0); 83315#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83312#L586-42 assume !(1 == ~m_pc~0); 83307#L586-44 is_master_triggered_~__retres1~0#1 := 0; 83303#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83300#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 83297#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 83294#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83291#L605-42 assume 1 == ~t1_pc~0; 83285#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 83282#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83279#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83276#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 83273#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83270#L624-42 assume 1 == ~t2_pc~0; 83265#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 83261#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83258#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 83255#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 83252#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83249#L643-42 assume 1 == ~t3_pc~0; 83243#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83240#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83237#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83234#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 83231#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83228#L662-42 assume 1 == ~t4_pc~0; 83223#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 83219#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83216#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83213#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83210#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83207#L681-42 assume 1 == ~t5_pc~0; 83201#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83198#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83195#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83192#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 83189#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83186#L700-42 assume 1 == ~t6_pc~0; 83181#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 83177#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83174#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 83171#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 83168#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83165#L719-42 assume 1 == ~t7_pc~0; 83159#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83156#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 83153#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 83150#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 83147#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83144#L738-42 assume !(1 == ~t8_pc~0); 83139#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 83135#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83132#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 83129#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 83126#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83123#L757-42 assume !(1 == ~t9_pc~0); 83117#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 83114#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83111#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 83108#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 83105#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 83102#L776-42 assume !(1 == ~t10_pc~0); 83097#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 83093#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 83090#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83087#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 83084#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 83081#L795-42 assume !(1 == ~t11_pc~0); 83075#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 83072#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 83069#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 83066#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 83063#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 83060#L814-42 assume !(1 == ~t12_pc~0); 83055#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 83051#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83048#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 83045#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 83042#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83038#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 79729#L1332-5 assume !(1 == ~T1_E~0); 83030#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83026#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83022#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83018#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 83014#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 83009#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 83005#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 83000#L1372-3 assume !(1 == ~T9_E~0); 82998#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 82995#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 82992#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 82988#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 82985#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 82982#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 82979#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 82976#L1412-3 assume !(1 == ~E_4~0); 82399#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82971#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 82968#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 82965#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 82962#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 82959#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 82956#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 82951#L1452-3 assume !(1 == ~E_12~0); 82950#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 82940#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82934#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82932#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 82930#L1822 assume !(0 == start_simulation_~tmp~3#1); 80996#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 82710#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82696#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82694#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 82692#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81710#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81433#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 81422#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 81414#L1803-2 [2023-11-26 11:47:38,536 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:38,536 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2023-11-26 11:47:38,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:38,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672496658] [2023-11-26 11:47:38,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:38,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:38,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:38,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:38,604 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:38,604 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672496658] [2023-11-26 11:47:38,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1672496658] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:38,605 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:38,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:38,605 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422741346] [2023-11-26 11:47:38,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:38,606 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:38,606 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:38,606 INFO L85 PathProgramCache]: Analyzing trace with hash 1379935871, now seen corresponding path program 1 times [2023-11-26 11:47:38,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:38,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657181642] [2023-11-26 11:47:38,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:38,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:38,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:38,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:38,666 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:38,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657181642] [2023-11-26 11:47:38,667 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657181642] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:38,667 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:38,667 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:38,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295414348] [2023-11-26 11:47:38,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:38,668 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:38,668 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:38,669 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:38,669 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:38,669 INFO L87 Difference]: Start difference. First operand 11730 states and 17114 transitions. cyclomatic complexity: 5392 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:39,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:39,068 INFO L93 Difference]: Finished difference Result 23111 states and 33516 transitions. [2023-11-26 11:47:39,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23111 states and 33516 transitions. [2023-11-26 11:47:39,184 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22869 [2023-11-26 11:47:39,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23111 states to 23111 states and 33516 transitions. [2023-11-26 11:47:39,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23111 [2023-11-26 11:47:39,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23111 [2023-11-26 11:47:39,299 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23111 states and 33516 transitions. [2023-11-26 11:47:39,321 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:39,321 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23111 states and 33516 transitions. [2023-11-26 11:47:39,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23111 states and 33516 transitions. [2023-11-26 11:47:39,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23111 to 22391. [2023-11-26 11:47:39,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22391 states, 22391 states have (on average 1.4514760394801483) internal successors, (32500), 22390 states have internal predecessors, (32500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:40,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22391 states to 22391 states and 32500 transitions. [2023-11-26 11:47:40,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22391 states and 32500 transitions. [2023-11-26 11:47:40,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:40,056 INFO L428 stractBuchiCegarLoop]: Abstraction has 22391 states and 32500 transitions. [2023-11-26 11:47:40,057 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 11:47:40,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22391 states and 32500 transitions. [2023-11-26 11:47:40,145 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22149 [2023-11-26 11:47:40,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:40,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:40,149 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:40,149 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:40,150 INFO L748 eck$LassoCheckResult]: Stem: 114613#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 114614#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 115595#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115596#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114684#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 114685#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114586#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114587#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115991#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115253#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115254#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 115137#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 115138#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 115686#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 115687#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 114883#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 114884#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 115348#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115349#L1194 assume !(0 == ~M_E~0); 115507#L1194-2 assume !(0 == ~T1_E~0); 115508#L1199-1 assume !(0 == ~T2_E~0); 115836#L1204-1 assume !(0 == ~T3_E~0); 115745#L1209-1 assume !(0 == ~T4_E~0); 115746#L1214-1 assume !(0 == ~T5_E~0); 116287#L1219-1 assume !(0 == ~T6_E~0); 116464#L1224-1 assume !(0 == ~T7_E~0); 114961#L1229-1 assume !(0 == ~T8_E~0); 114513#L1234-1 assume !(0 == ~T9_E~0); 114514#L1239-1 assume !(0 == ~T10_E~0); 114549#L1244-1 assume !(0 == ~T11_E~0); 114550#L1249-1 assume !(0 == ~T12_E~0); 115284#L1254-1 assume !(0 == ~E_M~0); 114448#L1259-1 assume !(0 == ~E_1~0); 114413#L1264-1 assume !(0 == ~E_2~0); 114414#L1269-1 assume !(0 == ~E_3~0); 116477#L1274-1 assume !(0 == ~E_4~0); 116346#L1279-1 assume !(0 == ~E_5~0); 114622#L1284-1 assume !(0 == ~E_6~0); 114623#L1289-1 assume !(0 == ~E_7~0); 115358#L1294-1 assume !(0 == ~E_8~0); 115359#L1299-1 assume !(0 == ~E_9~0); 115370#L1304-1 assume !(0 == ~E_10~0); 116446#L1309-1 assume !(0 == ~E_11~0); 116459#L1314-1 assume !(0 == ~E_12~0); 114580#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114503#L586 assume !(1 == ~m_pc~0); 114504#L586-2 is_master_triggered_~__retres1~0#1 := 0; 114569#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115430#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 114781#L1485 assume !(0 != activate_threads_~tmp~1#1); 114782#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115998#L605 assume !(1 == ~t1_pc~0); 115444#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115169#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115170#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 115888#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 115809#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115074#L624 assume 1 == ~t2_pc~0; 114554#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 114555#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114809#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 114810#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 116043#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115886#L643 assume !(1 == ~t3_pc~0); 115713#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 115394#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115395#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 114890#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 114891#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114643#L662 assume 1 == ~t4_pc~0; 114644#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 114602#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114468#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 114469#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 114494#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114495#L681 assume !(1 == ~t5_pc~0); 114369#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 114370#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115471#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 116227#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 114904#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114905#L700 assume 1 == ~t6_pc~0; 115662#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 114634#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 114635#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114686#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 114687#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116119#L719 assume 1 == ~t7_pc~0; 116249#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 114860#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116438#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116323#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 114383#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 114384#L738 assume !(1 == ~t8_pc~0); 115843#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 115736#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 115737#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 115503#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 115504#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 115913#L757 assume 1 == ~t9_pc~0; 115914#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 114378#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 114379#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 114857#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 115463#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 115464#L776 assume !(1 == ~t10_pc~0); 114400#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 114399#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 114788#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 114624#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 114625#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 114581#L795 assume 1 == ~t11_pc~0; 114582#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 114926#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 116022#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 116273#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 115703#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 115690#L814 assume !(1 == ~t12_pc~0); 115533#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 115534#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 114429#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 114430#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 114841#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114842#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 116059#L1332-2 assume !(1 == ~T1_E~0); 116382#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 115614#L1342-1 assume !(1 == ~T3_E~0); 115615#L1347-1 assume !(1 == ~T4_E~0); 116096#L1352-1 assume !(1 == ~T5_E~0); 116097#L1357-1 assume !(1 == ~T6_E~0); 115135#L1362-1 assume !(1 == ~T7_E~0); 115136#L1367-1 assume !(1 == ~T8_E~0); 114722#L1372-1 assume !(1 == ~T9_E~0); 114723#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 115316#L1382-1 assume !(1 == ~T11_E~0); 115805#L1387-1 assume !(1 == ~T12_E~0); 115806#L1392-1 assume !(1 == ~E_M~0); 115075#L1397-1 assume !(1 == ~E_1~0); 115076#L1402-1 assume !(1 == ~E_2~0); 116384#L1407-1 assume !(1 == ~E_3~0); 118131#L1412-1 assume !(1 == ~E_4~0); 118127#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 118124#L1422-1 assume !(1 == ~E_6~0); 118121#L1427-1 assume !(1 == ~E_7~0); 118118#L1432-1 assume !(1 == ~E_8~0); 117962#L1437-1 assume !(1 == ~E_9~0); 117942#L1442-1 assume !(1 == ~E_10~0); 117940#L1447-1 assume !(1 == ~E_11~0); 117927#L1452-1 assume !(1 == ~E_12~0); 117916#L1457-1 assume { :end_inline_reset_delta_events } true; 117909#L1803-2 [2023-11-26 11:47:40,151 INFO L750 eck$LassoCheckResult]: Loop: 117909#L1803-2 assume !false; 117903#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117899#L1169-1 assume !false; 117898#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 117895#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 117884#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117883#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 117881#L996 assume !(0 != eval_~tmp~0#1); 117880#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117879#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117877#L1194-3 assume !(0 == ~M_E~0); 117878#L1194-5 assume !(0 == ~T1_E~0); 122423#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 122420#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 122418#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 122416#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 122414#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 121507#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 121505#L1229-3 assume !(0 == ~T8_E~0); 121503#L1234-3 assume !(0 == ~T9_E~0); 121501#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 121499#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 121497#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 121495#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 121493#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 121491#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 121489#L1269-3 assume !(0 == ~E_3~0); 121133#L1274-3 assume !(0 == ~E_4~0); 120946#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 120944#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 120942#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 120940#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 120938#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 120936#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 120934#L1309-3 assume !(0 == ~E_11~0); 120932#L1314-3 assume !(0 == ~E_12~0); 120930#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 120928#L586-42 assume !(1 == ~m_pc~0); 120806#L586-44 is_master_triggered_~__retres1~0#1 := 0; 120803#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 120801#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 120799#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 120797#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 120795#L605-42 assume !(1 == ~t1_pc~0); 120793#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 120789#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120787#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 120785#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 120784#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 120783#L624-42 assume !(1 == ~t2_pc~0); 120781#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 120780#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 120778#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 120776#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 120774#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 120771#L643-42 assume !(1 == ~t3_pc~0); 120645#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 120527#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120525#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 120523#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 120521#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120519#L662-42 assume 1 == ~t4_pc~0; 120517#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 120513#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 120511#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 120509#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 120508#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 120507#L681-42 assume 1 == ~t5_pc~0; 120505#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 120504#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 120344#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 120341#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 120339#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 120337#L700-42 assume 1 == ~t6_pc~0; 120335#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 120332#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 120330#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 120327#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 120325#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 120324#L719-42 assume 1 == ~t7_pc~0; 120321#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 120318#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 120316#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 120314#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 120312#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 120310#L738-42 assume !(1 == ~t8_pc~0); 120307#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 120304#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 120302#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 120300#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 120298#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 120295#L757-42 assume 1 == ~t9_pc~0; 120137#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 119936#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 119642#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 119640#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 119638#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117629#L776-42 assume !(1 == ~t10_pc~0); 117631#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 119569#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 119567#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 119565#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 117621#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 117622#L795-42 assume !(1 == ~t11_pc~0); 119419#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 119412#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 119405#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 119398#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 119391#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 119369#L814-42 assume 1 == ~t12_pc~0; 119365#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 119356#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 117604#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 117605#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 119342#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119335#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 117598#L1332-5 assume !(1 == ~T1_E~0); 119322#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 119315#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119308#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119301#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 119293#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 119285#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 119277#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 119267#L1372-3 assume !(1 == ~T9_E~0); 119263#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 119258#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 119252#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 119247#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 119242#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 119237#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 119232#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 119225#L1412-3 assume !(1 == ~E_4~0); 119221#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 119218#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 119215#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 119212#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 119209#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 119206#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 119202#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 119198#L1452-3 assume !(1 == ~E_12~0); 119196#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 119186#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 119180#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 119178#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 119175#L1822 assume !(0 == start_simulation_~tmp~3#1); 115917#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 119172#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 117974#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117951#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 117949#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117948#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117931#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 117917#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 117909#L1803-2 [2023-11-26 11:47:40,152 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:40,152 INFO L85 PathProgramCache]: Analyzing trace with hash 1218722231, now seen corresponding path program 1 times [2023-11-26 11:47:40,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:40,153 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294048914] [2023-11-26 11:47:40,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:40,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:40,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:40,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:40,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:40,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294048914] [2023-11-26 11:47:40,261 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294048914] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:40,262 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:40,262 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:47:40,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1649553476] [2023-11-26 11:47:40,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:40,263 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:40,263 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:40,264 INFO L85 PathProgramCache]: Analyzing trace with hash 578457600, now seen corresponding path program 1 times [2023-11-26 11:47:40,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:40,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308158241] [2023-11-26 11:47:40,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:40,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:40,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:40,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:40,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:40,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308158241] [2023-11-26 11:47:40,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308158241] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:40,462 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:40,462 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:40,462 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642945612] [2023-11-26 11:47:40,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:40,463 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:40,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:40,463 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:47:40,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:47:40,464 INFO L87 Difference]: Start difference. First operand 22391 states and 32500 transitions. cyclomatic complexity: 10125 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:41,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:41,224 INFO L93 Difference]: Finished difference Result 59956 states and 86240 transitions. [2023-11-26 11:47:41,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59956 states and 86240 transitions. [2023-11-26 11:47:41,647 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 59448 [2023-11-26 11:47:41,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59956 states to 59956 states and 86240 transitions. [2023-11-26 11:47:41,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59956 [2023-11-26 11:47:42,041 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59956 [2023-11-26 11:47:42,041 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59956 states and 86240 transitions. [2023-11-26 11:47:42,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:42,110 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59956 states and 86240 transitions. [2023-11-26 11:47:42,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59956 states and 86240 transitions. [2023-11-26 11:47:42,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59956 to 23000. [2023-11-26 11:47:42,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23000 states, 23000 states have (on average 1.4395217391304347) internal successors, (33109), 22999 states have internal predecessors, (33109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:42,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23000 states to 23000 states and 33109 transitions. [2023-11-26 11:47:42,739 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23000 states and 33109 transitions. [2023-11-26 11:47:42,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:47:42,740 INFO L428 stractBuchiCegarLoop]: Abstraction has 23000 states and 33109 transitions. [2023-11-26 11:47:42,740 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 11:47:42,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23000 states and 33109 transitions. [2023-11-26 11:47:42,806 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22755 [2023-11-26 11:47:42,806 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:42,806 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:42,809 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:42,809 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:42,810 INFO L748 eck$LassoCheckResult]: Stem: 196973#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 196974#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 197939#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 197940#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 197044#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 197045#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 196948#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 196949#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 198332#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 197608#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 197609#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 197493#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 197494#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 198030#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 198031#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 197244#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 197245#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 197695#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 197696#L1194 assume !(0 == ~M_E~0); 197854#L1194-2 assume !(0 == ~T1_E~0); 197855#L1199-1 assume !(0 == ~T2_E~0); 198180#L1204-1 assume !(0 == ~T3_E~0); 198089#L1209-1 assume !(0 == ~T4_E~0); 198090#L1214-1 assume !(0 == ~T5_E~0); 198594#L1219-1 assume !(0 == ~T6_E~0); 198745#L1224-1 assume !(0 == ~T7_E~0); 197324#L1229-1 assume !(0 == ~T8_E~0); 196867#L1234-1 assume !(0 == ~T9_E~0); 196868#L1239-1 assume !(0 == ~T10_E~0); 196909#L1244-1 assume !(0 == ~T11_E~0); 196910#L1249-1 assume !(0 == ~T12_E~0); 197638#L1254-1 assume !(0 == ~E_M~0); 196809#L1259-1 assume !(0 == ~E_1~0); 196773#L1264-1 assume !(0 == ~E_2~0); 196774#L1269-1 assume !(0 == ~E_3~0); 198755#L1274-1 assume !(0 == ~E_4~0); 198643#L1279-1 assume !(0 == ~E_5~0); 196984#L1284-1 assume !(0 == ~E_6~0); 196985#L1289-1 assume !(0 == ~E_7~0); 197702#L1294-1 assume !(0 == ~E_8~0); 197703#L1299-1 assume !(0 == ~E_9~0); 197714#L1304-1 assume !(0 == ~E_10~0); 198731#L1309-1 assume !(0 == ~E_11~0); 198742#L1314-1 assume !(0 == ~E_12~0); 196940#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 196865#L586 assume !(1 == ~m_pc~0); 196866#L586-2 is_master_triggered_~__retres1~0#1 := 0; 196931#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 197776#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 197141#L1485 assume !(0 != activate_threads_~tmp~1#1); 197142#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 198341#L605 assume !(1 == ~t1_pc~0); 197791#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 197524#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 197525#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 198587#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 198148#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 197430#L624 assume 1 == ~t2_pc~0; 196913#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 196914#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 197168#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 197169#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 198387#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 198222#L643 assume !(1 == ~t3_pc~0); 198056#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 197734#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 197735#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 197251#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 197252#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 197005#L662 assume 1 == ~t4_pc~0; 197006#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 196964#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 196827#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 196828#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 196854#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 196855#L681 assume !(1 == ~t5_pc~0); 196729#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 196730#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 197818#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 198541#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 197266#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 197267#L700 assume 1 == ~t6_pc~0; 198007#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 196996#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 196997#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 197046#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 197047#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 198449#L719 assume 1 == ~t7_pc~0; 198555#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 197217#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 198723#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 198625#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 196743#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 196744#L738 assume !(1 == ~t8_pc~0); 198188#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 198080#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 198081#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 197850#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 197851#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 198246#L757 assume 1 == ~t9_pc~0; 198247#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 196738#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 196739#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 197215#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 197810#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 197811#L776 assume !(1 == ~t10_pc~0); 196760#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 196759#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 197145#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 196986#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 196987#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 196941#L795 assume 1 == ~t11_pc~0; 196942#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 197289#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 198364#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 198581#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 198049#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 198034#L814 assume !(1 == ~t12_pc~0); 197881#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 197882#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 196786#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 196787#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 197199#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 197200#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 198400#L1332-2 assume !(1 == ~T1_E~0); 199133#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 197960#L1342-1 assume !(1 == ~T3_E~0); 197961#L1347-1 assume !(1 == ~T4_E~0); 198433#L1352-1 assume !(1 == ~T5_E~0); 198434#L1357-1 assume !(1 == ~T6_E~0); 199120#L1362-1 assume !(1 == ~T7_E~0); 199118#L1367-1 assume !(1 == ~T8_E~0); 197080#L1372-1 assume !(1 == ~T9_E~0); 197081#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 197403#L1382-1 assume !(1 == ~T11_E~0); 197404#L1387-1 assume !(1 == ~T12_E~0); 198146#L1392-1 assume !(1 == ~E_M~0); 197431#L1397-1 assume !(1 == ~E_1~0); 197432#L1402-1 assume !(1 == ~E_2~0); 199085#L1407-1 assume !(1 == ~E_3~0); 199081#L1412-1 assume !(1 == ~E_4~0); 199078#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 199074#L1422-1 assume !(1 == ~E_6~0); 199067#L1427-1 assume !(1 == ~E_7~0); 199062#L1432-1 assume !(1 == ~E_8~0); 199009#L1437-1 assume !(1 == ~E_9~0); 198957#L1442-1 assume !(1 == ~E_10~0); 198955#L1447-1 assume !(1 == ~E_11~0); 198932#L1452-1 assume !(1 == ~E_12~0); 198921#L1457-1 assume { :end_inline_reset_delta_events } true; 198914#L1803-2 [2023-11-26 11:47:42,810 INFO L750 eck$LassoCheckResult]: Loop: 198914#L1803-2 assume !false; 198908#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 198904#L1169-1 assume !false; 198903#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 198900#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 198889#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 198888#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 198886#L996 assume !(0 != eval_~tmp~0#1); 198885#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 198884#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 198882#L1194-3 assume !(0 == ~M_E~0); 198883#L1194-5 assume !(0 == ~T1_E~0); 200458#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 200457#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 200456#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 200455#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 200454#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 200453#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 200452#L1229-3 assume !(0 == ~T8_E~0); 200451#L1234-3 assume !(0 == ~T9_E~0); 200450#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 200449#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 200448#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 200447#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 200446#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 200445#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 200444#L1269-3 assume !(0 == ~E_3~0); 200443#L1274-3 assume !(0 == ~E_4~0); 200442#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 200441#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 200440#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 200439#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 200438#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 200437#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 200436#L1309-3 assume !(0 == ~E_11~0); 200435#L1314-3 assume !(0 == ~E_12~0); 200434#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 200433#L586-42 assume !(1 == ~m_pc~0); 200432#L586-44 is_master_triggered_~__retres1~0#1 := 0; 200431#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 200430#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 200429#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 200428#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 200427#L605-42 assume !(1 == ~t1_pc~0); 200426#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 200424#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 200422#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 200420#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 200417#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 200415#L624-42 assume 1 == ~t2_pc~0; 200161#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 200153#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 200150#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 200148#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 200142#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200125#L643-42 assume 1 == ~t3_pc~0; 200119#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 200112#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 200106#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 200101#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 200096#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 200091#L662-42 assume 1 == ~t4_pc~0; 200087#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 200081#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 200076#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 199627#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 199624#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199622#L681-42 assume 1 == ~t5_pc~0; 199619#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 199617#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 199614#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 199612#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 199610#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 199608#L700-42 assume 1 == ~t6_pc~0; 199606#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 199603#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 199600#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 199598#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 199596#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 199594#L719-42 assume !(1 == ~t7_pc~0); 199590#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 199586#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 199584#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 199582#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 199580#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 199578#L738-42 assume 1 == ~t8_pc~0; 199575#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 199574#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 199571#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 199569#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 199567#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 199565#L757-42 assume 1 == ~t9_pc~0; 199563#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 199560#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 199557#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 199555#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 199553#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 199551#L776-42 assume !(1 == ~t10_pc~0); 199546#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 199543#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 199541#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 199539#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 199537#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 199535#L795-42 assume 1 == ~t11_pc~0; 199319#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 199316#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 199314#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 199312#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 199310#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 199308#L814-42 assume !(1 == ~t12_pc~0); 199305#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 199302#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 199300#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 199298#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 199296#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 199295#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 199151#L1332-5 assume !(1 == ~T1_E~0); 199291#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 199289#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 199285#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 199281#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 199277#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 199271#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 199265#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 199258#L1372-3 assume !(1 == ~T9_E~0); 199253#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 199248#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 199243#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 199238#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 199232#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 199228#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 199224#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 199165#L1412-3 assume !(1 == ~E_4~0); 199163#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 199161#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 199159#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 199157#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 199153#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 199148#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 199145#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 199106#L1452-3 assume !(1 == ~E_12~0); 199104#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 199090#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 199082#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 199079#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 199075#L1822 assume !(0 == start_simulation_~tmp~3#1); 199068#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 199026#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 199012#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 199011#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 198958#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 198956#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 198933#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 198922#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 198914#L1803-2 [2023-11-26 11:47:42,811 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:42,811 INFO L85 PathProgramCache]: Analyzing trace with hash -1724859847, now seen corresponding path program 1 times [2023-11-26 11:47:42,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:42,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28249464] [2023-11-26 11:47:42,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:42,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:42,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:43,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:43,037 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:43,037 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [28249464] [2023-11-26 11:47:43,037 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [28249464] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:43,037 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:43,037 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:43,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903073343] [2023-11-26 11:47:43,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:43,039 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:43,039 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:43,040 INFO L85 PathProgramCache]: Analyzing trace with hash 490538048, now seen corresponding path program 1 times [2023-11-26 11:47:43,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:43,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64441581] [2023-11-26 11:47:43,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:43,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:43,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:43,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:43,117 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:43,117 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64441581] [2023-11-26 11:47:43,117 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [64441581] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:43,118 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:43,118 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:43,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1065998782] [2023-11-26 11:47:43,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:43,119 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:43,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:43,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:43,120 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:43,120 INFO L87 Difference]: Start difference. First operand 23000 states and 33109 transitions. cyclomatic complexity: 10125 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:43,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:43,519 INFO L93 Difference]: Finished difference Result 44040 states and 63119 transitions. [2023-11-26 11:47:43,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44040 states and 63119 transitions. [2023-11-26 11:47:43,739 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43748 [2023-11-26 11:47:43,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44040 states to 44040 states and 63119 transitions. [2023-11-26 11:47:43,914 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44040 [2023-11-26 11:47:43,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44040 [2023-11-26 11:47:43,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44040 states and 63119 transitions. [2023-11-26 11:47:43,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:43,988 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44040 states and 63119 transitions. [2023-11-26 11:47:44,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44040 states and 63119 transitions. [2023-11-26 11:47:44,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44040 to 44008. [2023-11-26 11:47:44,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44008 states, 44008 states have (on average 1.4335348118523905) internal successors, (63087), 44007 states have internal predecessors, (63087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:44,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44008 states to 44008 states and 63087 transitions. [2023-11-26 11:47:44,996 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44008 states and 63087 transitions. [2023-11-26 11:47:44,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:44,997 INFO L428 stractBuchiCegarLoop]: Abstraction has 44008 states and 63087 transitions. [2023-11-26 11:47:44,997 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 11:47:44,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44008 states and 63087 transitions. [2023-11-26 11:47:45,128 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43716 [2023-11-26 11:47:45,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:45,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:45,132 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:45,132 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:45,133 INFO L748 eck$LassoCheckResult]: Stem: 264015#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 264016#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 264999#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 265000#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 264083#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 264084#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 263989#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 263990#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 265400#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 264647#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 264648#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 264536#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 264537#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 265090#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 265091#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 264282#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 264283#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 264739#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 264740#L1194 assume !(0 == ~M_E~0); 264908#L1194-2 assume !(0 == ~T1_E~0); 264909#L1199-1 assume !(0 == ~T2_E~0); 265238#L1204-1 assume !(0 == ~T3_E~0); 265145#L1209-1 assume !(0 == ~T4_E~0); 265146#L1214-1 assume !(0 == ~T5_E~0); 265666#L1219-1 assume !(0 == ~T6_E~0); 265842#L1224-1 assume !(0 == ~T7_E~0); 264359#L1229-1 assume !(0 == ~T8_E~0); 263912#L1234-1 assume !(0 == ~T9_E~0); 263913#L1239-1 assume !(0 == ~T10_E~0); 263957#L1244-1 assume !(0 == ~T11_E~0); 263958#L1249-1 assume !(0 == ~T12_E~0); 264680#L1254-1 assume !(0 == ~E_M~0); 263854#L1259-1 assume !(0 == ~E_1~0); 263820#L1264-1 assume !(0 == ~E_2~0); 263821#L1269-1 assume !(0 == ~E_3~0); 265859#L1274-1 assume !(0 == ~E_4~0); 265712#L1279-1 assume !(0 == ~E_5~0); 264024#L1284-1 assume !(0 == ~E_6~0); 264025#L1289-1 assume !(0 == ~E_7~0); 264746#L1294-1 assume !(0 == ~E_8~0); 264747#L1299-1 assume !(0 == ~E_9~0); 264759#L1304-1 assume !(0 == ~E_10~0); 265824#L1309-1 assume !(0 == ~E_11~0); 265837#L1314-1 assume !(0 == ~E_12~0); 263983#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 263910#L586 assume !(1 == ~m_pc~0); 263911#L586-2 is_master_triggered_~__retres1~0#1 := 0; 263974#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264824#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 264182#L1485 assume !(0 != activate_threads_~tmp~1#1); 264183#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 265408#L605 assume !(1 == ~t1_pc~0); 264842#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 264566#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264567#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 265292#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 265208#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264469#L624 assume !(1 == ~t2_pc~0); 264470#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 264653#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264208#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 264209#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 265450#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 265290#L643 assume !(1 == ~t3_pc~0); 265114#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 264781#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 264782#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 264290#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 264291#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 264045#L662 assume 1 == ~t4_pc~0; 264046#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 264004#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263872#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 263873#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 263901#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 263902#L681 assume !(1 == ~t5_pc~0); 263776#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 263777#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264872#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 265613#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 264303#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 264304#L700 assume 1 == ~t6_pc~0; 265064#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 264036#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264037#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 264085#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 264086#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 265514#L719 assume 1 == ~t7_pc~0; 265626#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 264256#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 265808#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 265694#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 263790#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 263791#L738 assume !(1 == ~t8_pc~0); 265245#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 265137#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 265138#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 264904#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 264905#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 265314#L757 assume 1 == ~t9_pc~0; 265315#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 263785#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 263786#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 264254#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 264863#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 264864#L776 assume !(1 == ~t10_pc~0); 263807#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 263806#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 264186#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 264026#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 264027#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 263984#L795 assume 1 == ~t11_pc~0; 263985#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 264323#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 265430#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 265650#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 265108#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 265095#L814 assume !(1 == ~t12_pc~0); 264934#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 264935#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 263833#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 263834#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 264239#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264240#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 265462#L1332-2 assume !(1 == ~T1_E~0); 265768#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 265769#L1342-1 assume !(1 == ~T3_E~0); 265708#L1347-1 assume !(1 == ~T4_E~0); 265709#L1352-1 assume !(1 == ~T5_E~0); 265321#L1357-1 assume !(1 == ~T6_E~0); 265322#L1362-1 assume !(1 == ~T7_E~0); 265553#L1367-1 assume !(1 == ~T8_E~0); 265554#L1372-1 assume !(1 == ~T9_E~0); 297370#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 297363#L1382-1 assume !(1 == ~T11_E~0); 297356#L1387-1 assume !(1 == ~T12_E~0); 265687#L1392-1 assume !(1 == ~E_M~0); 264471#L1397-1 assume !(1 == ~E_1~0); 264472#L1402-1 assume !(1 == ~E_2~0); 294340#L1407-1 assume !(1 == ~E_3~0); 294332#L1412-1 assume !(1 == ~E_4~0); 294326#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 294319#L1422-1 assume !(1 == ~E_6~0); 289908#L1427-1 assume !(1 == ~E_7~0); 289906#L1432-1 assume !(1 == ~E_8~0); 288955#L1437-1 assume !(1 == ~E_9~0); 288953#L1442-1 assume !(1 == ~E_10~0); 288951#L1447-1 assume !(1 == ~E_11~0); 288894#L1452-1 assume !(1 == ~E_12~0); 288880#L1457-1 assume { :end_inline_reset_delta_events } true; 288869#L1803-2 [2023-11-26 11:47:45,134 INFO L750 eck$LassoCheckResult]: Loop: 288869#L1803-2 assume !false; 288860#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 288854#L1169-1 assume !false; 288852#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 288623#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 288604#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 288597#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 288587#L996 assume !(0 != eval_~tmp~0#1); 288588#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 292159#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 292157#L1194-3 assume !(0 == ~M_E~0); 292155#L1194-5 assume !(0 == ~T1_E~0); 292153#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 292151#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 292149#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 292146#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 292144#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 292142#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 292140#L1229-3 assume !(0 == ~T8_E~0); 292138#L1234-3 assume !(0 == ~T9_E~0); 292136#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 292133#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 292131#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 292129#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 292127#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 292125#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 292123#L1269-3 assume !(0 == ~E_3~0); 292120#L1274-3 assume !(0 == ~E_4~0); 292118#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 292116#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 292114#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 292112#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 292110#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 292107#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 292105#L1309-3 assume !(0 == ~E_11~0); 292103#L1314-3 assume !(0 == ~E_12~0); 292101#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 292099#L586-42 assume !(1 == ~m_pc~0); 292097#L586-44 is_master_triggered_~__retres1~0#1 := 0; 292094#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 292092#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 292090#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 292088#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 292086#L605-42 assume 1 == ~t1_pc~0; 292084#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 292085#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 292174#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 292074#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 292072#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 292070#L624-42 assume !(1 == ~t2_pc~0); 292068#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 292066#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 292064#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 292062#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 292060#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 292058#L643-42 assume 1 == ~t3_pc~0; 292055#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 292053#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 292051#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 292050#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 292049#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 292048#L662-42 assume !(1 == ~t4_pc~0); 292046#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 292045#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 292044#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 292043#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 292042#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 292041#L681-42 assume 1 == ~t5_pc~0; 292038#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 292037#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 292036#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 292035#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 292034#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 292033#L700-42 assume !(1 == ~t6_pc~0); 292030#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 292028#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 292026#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 292024#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 292022#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 292020#L719-42 assume 1 == ~t7_pc~0; 292017#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 292015#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 292013#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 292011#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 292009#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 292007#L738-42 assume 1 == ~t8_pc~0; 292004#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 292002#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 292000#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 291998#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 291996#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 291994#L757-42 assume !(1 == ~t9_pc~0); 291990#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 291988#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 291986#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 291984#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 291982#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 291980#L776-42 assume 1 == ~t10_pc~0; 291977#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 291975#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 291973#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 291971#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 291969#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 291967#L795-42 assume !(1 == ~t11_pc~0); 291964#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 291960#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 291958#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 291956#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 291954#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 291951#L814-42 assume 1 == ~t12_pc~0; 291948#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 291946#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 291944#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 291942#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 291940#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 291938#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 285978#L1332-5 assume !(1 == ~T1_E~0); 291933#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 291930#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 291928#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 291926#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 291924#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 291922#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 291920#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 291838#L1372-3 assume !(1 == ~T9_E~0); 291836#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 291834#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 291832#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 291830#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 291827#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 291825#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 291823#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 291770#L1412-3 assume !(1 == ~E_4~0); 291768#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 291764#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 291762#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 291760#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 291758#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 291756#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 291754#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 291730#L1452-3 assume !(1 == ~E_12~0); 291728#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 289518#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 289512#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 289509#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 289507#L1822 assume !(0 == start_simulation_~tmp~3#1); 289504#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 288918#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 288904#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 288902#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 288900#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 288898#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 288895#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 288881#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 288869#L1803-2 [2023-11-26 11:47:45,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:45,135 INFO L85 PathProgramCache]: Analyzing trace with hash -607674886, now seen corresponding path program 1 times [2023-11-26 11:47:45,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:45,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897141642] [2023-11-26 11:47:45,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:45,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:45,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:45,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:45,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:45,213 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897141642] [2023-11-26 11:47:45,213 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [897141642] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:45,213 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:45,213 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:45,213 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190879695] [2023-11-26 11:47:45,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:45,215 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:45,215 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:45,216 INFO L85 PathProgramCache]: Analyzing trace with hash -554811137, now seen corresponding path program 1 times [2023-11-26 11:47:45,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:45,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863971300] [2023-11-26 11:47:45,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:45,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:45,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:45,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:45,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:45,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863971300] [2023-11-26 11:47:45,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1863971300] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:45,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:45,450 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:45,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485224944] [2023-11-26 11:47:45,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:45,450 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:45,451 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:45,451 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:45,451 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:45,451 INFO L87 Difference]: Start difference. First operand 44008 states and 63087 transitions. cyclomatic complexity: 19111 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:45,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:45,858 INFO L93 Difference]: Finished difference Result 84359 states and 120448 transitions. [2023-11-26 11:47:45,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84359 states and 120448 transitions. [2023-11-26 11:47:46,529 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 83940 [2023-11-26 11:47:46,867 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84359 states to 84359 states and 120448 transitions. [2023-11-26 11:47:46,868 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84359 [2023-11-26 11:47:46,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84359 [2023-11-26 11:47:46,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84359 states and 120448 transitions. [2023-11-26 11:47:47,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:47,024 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84359 states and 120448 transitions. [2023-11-26 11:47:47,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84359 states and 120448 transitions. [2023-11-26 11:47:48,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84359 to 84295. [2023-11-26 11:47:48,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84295 states, 84295 states have (on average 1.4281274096921526) internal successors, (120384), 84294 states have internal predecessors, (120384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:48,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84295 states to 84295 states and 120384 transitions. [2023-11-26 11:47:48,506 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84295 states and 120384 transitions. [2023-11-26 11:47:48,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:48,507 INFO L428 stractBuchiCegarLoop]: Abstraction has 84295 states and 120384 transitions. [2023-11-26 11:47:48,507 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 11:47:48,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84295 states and 120384 transitions. [2023-11-26 11:47:49,157 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 83876 [2023-11-26 11:47:49,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:49,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:49,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:49,161 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:49,162 INFO L748 eck$LassoCheckResult]: Stem: 392391#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 392392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 393365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 393366#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 392462#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 392463#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 392366#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 392367#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 393746#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 393026#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 393027#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 392912#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 392913#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 393453#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 393454#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 392663#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 392664#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 393115#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 393116#L1194 assume !(0 == ~M_E~0); 393278#L1194-2 assume !(0 == ~T1_E~0); 393279#L1199-1 assume !(0 == ~T2_E~0); 393591#L1204-1 assume !(0 == ~T3_E~0); 393507#L1209-1 assume !(0 == ~T4_E~0); 393508#L1214-1 assume !(0 == ~T5_E~0); 394011#L1219-1 assume !(0 == ~T6_E~0); 394160#L1224-1 assume !(0 == ~T7_E~0); 392739#L1229-1 assume !(0 == ~T8_E~0); 392288#L1234-1 assume !(0 == ~T9_E~0); 392289#L1239-1 assume !(0 == ~T10_E~0); 392330#L1244-1 assume !(0 == ~T11_E~0); 392331#L1249-1 assume !(0 == ~T12_E~0); 393057#L1254-1 assume !(0 == ~E_M~0); 392229#L1259-1 assume !(0 == ~E_1~0); 392194#L1264-1 assume !(0 == ~E_2~0); 392195#L1269-1 assume !(0 == ~E_3~0); 394169#L1274-1 assume !(0 == ~E_4~0); 394056#L1279-1 assume !(0 == ~E_5~0); 392402#L1284-1 assume !(0 == ~E_6~0); 392403#L1289-1 assume !(0 == ~E_7~0); 393123#L1294-1 assume !(0 == ~E_8~0); 393124#L1299-1 assume !(0 == ~E_9~0); 393135#L1304-1 assume !(0 == ~E_10~0); 394142#L1309-1 assume !(0 == ~E_11~0); 394156#L1314-1 assume !(0 == ~E_12~0); 392359#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 392286#L586 assume !(1 == ~m_pc~0); 392287#L586-2 is_master_triggered_~__retres1~0#1 := 0; 392349#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 393200#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 392563#L1485 assume !(0 != activate_threads_~tmp~1#1); 392564#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 393755#L605 assume !(1 == ~t1_pc~0); 393215#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 392942#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 392943#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 393637#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 393562#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 392848#L624 assume !(1 == ~t2_pc~0); 392849#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 393032#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 392589#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 392590#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 393795#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 393635#L643 assume !(1 == ~t3_pc~0); 393476#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 393154#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 393155#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 392671#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 392672#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 392423#L662 assume !(1 == ~t4_pc~0); 392424#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 392382#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 392248#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 392249#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 392275#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 392276#L681 assume !(1 == ~t5_pc~0); 392150#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 392151#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 393244#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 393955#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 392684#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 392685#L700 assume 1 == ~t6_pc~0; 393433#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 392414#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 392415#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 392464#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 392465#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 393859#L719 assume 1 == ~t7_pc~0; 393971#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 392638#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 394132#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 394037#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 392164#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 392165#L738 assume !(1 == ~t8_pc~0); 393599#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 393497#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 393498#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 393274#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 393275#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 393661#L757 assume 1 == ~t9_pc~0; 393662#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 392159#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 392160#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 392636#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 393236#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 393237#L776 assume !(1 == ~t10_pc~0); 392181#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 392180#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 392567#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 392404#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 392405#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 392360#L795 assume 1 == ~t11_pc~0; 392361#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 392704#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 393776#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 393998#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 393468#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 393457#L814 assume !(1 == ~t12_pc~0); 393306#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 393307#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 392207#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 392208#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 392620#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392621#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 393809#L1332-2 assume !(1 == ~T1_E~0); 394097#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 393384#L1342-1 assume !(1 == ~T3_E~0); 393385#L1347-1 assume !(1 == ~T4_E~0); 394053#L1352-1 assume !(1 == ~T5_E~0); 393669#L1357-1 assume !(1 == ~T6_E~0); 393670#L1362-1 assume !(1 == ~T7_E~0); 395152#L1367-1 assume !(1 == ~T8_E~0); 395150#L1372-1 assume !(1 == ~T9_E~0); 395149#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 395148#L1382-1 assume !(1 == ~T11_E~0); 395147#L1387-1 assume !(1 == ~T12_E~0); 395146#L1392-1 assume !(1 == ~E_M~0); 395145#L1397-1 assume !(1 == ~E_1~0); 395144#L1402-1 assume !(1 == ~E_2~0); 395143#L1407-1 assume !(1 == ~E_3~0); 395142#L1412-1 assume !(1 == ~E_4~0); 395141#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 395140#L1422-1 assume !(1 == ~E_6~0); 395139#L1427-1 assume !(1 == ~E_7~0); 395138#L1432-1 assume !(1 == ~E_8~0); 395137#L1437-1 assume !(1 == ~E_9~0); 395040#L1442-1 assume !(1 == ~E_10~0); 395037#L1447-1 assume !(1 == ~E_11~0); 395018#L1452-1 assume !(1 == ~E_12~0); 395007#L1457-1 assume { :end_inline_reset_delta_events } true; 395000#L1803-2 [2023-11-26 11:47:49,162 INFO L750 eck$LassoCheckResult]: Loop: 395000#L1803-2 assume !false; 394994#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 394990#L1169-1 assume !false; 394989#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 394986#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 394975#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 394974#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 394972#L996 assume !(0 != eval_~tmp~0#1); 394971#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 394970#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 394968#L1194-3 assume !(0 == ~M_E~0); 394969#L1194-5 assume !(0 == ~T1_E~0); 400107#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 400105#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 400103#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 400101#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 400098#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 400096#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 400094#L1229-3 assume !(0 == ~T8_E~0); 400092#L1234-3 assume !(0 == ~T9_E~0); 400090#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 400088#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 400087#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 400084#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 400082#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 400080#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 400078#L1269-3 assume !(0 == ~E_3~0); 400076#L1274-3 assume !(0 == ~E_4~0); 400074#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 400071#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 400069#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 400067#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 400065#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 400063#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 400061#L1309-3 assume !(0 == ~E_11~0); 400058#L1314-3 assume !(0 == ~E_12~0); 400056#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 400054#L586-42 assume !(1 == ~m_pc~0); 400052#L586-44 is_master_triggered_~__retres1~0#1 := 0; 400050#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 400048#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 400047#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 397505#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 397503#L605-42 assume 1 == ~t1_pc~0; 397500#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 397497#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 397495#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 397490#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 397488#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 397486#L624-42 assume !(1 == ~t2_pc~0); 397484#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 397483#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 397482#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 397481#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 397480#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 397479#L643-42 assume !(1 == ~t3_pc~0); 397478#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 397476#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 397474#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 397472#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 397470#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 397468#L662-42 assume !(1 == ~t4_pc~0); 397466#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 397464#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 397462#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 397460#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 397458#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 397456#L681-42 assume !(1 == ~t5_pc~0); 397454#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 397451#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 397449#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 397446#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 397444#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 397442#L700-42 assume 1 == ~t6_pc~0; 397440#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 397437#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 397435#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 397433#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 397431#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 397429#L719-42 assume !(1 == ~t7_pc~0); 397426#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 396730#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 396727#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 396725#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 396723#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 396721#L738-42 assume 1 == ~t8_pc~0; 396718#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 396716#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 396274#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 396271#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 396269#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 396267#L757-42 assume !(1 == ~t9_pc~0); 396263#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 396261#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 396258#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 395959#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 395957#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 395955#L776-42 assume 1 == ~t10_pc~0; 395948#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 395946#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 395944#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 395942#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 395940#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 395939#L795-42 assume 1 == ~t11_pc~0; 395938#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 395936#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 395935#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 395634#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 395632#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 395631#L814-42 assume 1 == ~t12_pc~0; 395628#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 395626#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 395625#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 395624#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 395623#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 395622#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 394514#L1332-5 assume !(1 == ~T1_E~0); 395619#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 395617#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 395615#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 395613#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 395611#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 395609#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 395607#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 395604#L1372-3 assume !(1 == ~T9_E~0); 395603#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 395602#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 395601#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 395600#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 395599#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 395598#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 395597#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 395571#L1412-3 assume !(1 == ~E_4~0); 395570#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 395569#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 395568#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 395567#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 395566#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 395565#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 395564#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 395558#L1452-3 assume !(1 == ~E_12~0); 395556#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 395408#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 395402#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 395398#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 395154#L1822 assume !(0 == start_simulation_~tmp~3#1); 395151#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 395060#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 395046#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 395044#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 395042#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 395041#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 395019#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 395008#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 395000#L1803-2 [2023-11-26 11:47:49,163 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:49,163 INFO L85 PathProgramCache]: Analyzing trace with hash 852319035, now seen corresponding path program 1 times [2023-11-26 11:47:49,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:49,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127058449] [2023-11-26 11:47:49,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:49,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:49,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:49,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:49,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:49,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127058449] [2023-11-26 11:47:49,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127058449] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:49,252 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:49,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:47:49,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709261196] [2023-11-26 11:47:49,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:49,253 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:49,254 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:49,254 INFO L85 PathProgramCache]: Analyzing trace with hash 926296128, now seen corresponding path program 1 times [2023-11-26 11:47:49,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:49,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597670107] [2023-11-26 11:47:49,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:49,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:49,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:49,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:49,308 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:49,308 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597670107] [2023-11-26 11:47:49,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597670107] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:49,309 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:49,309 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:49,309 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647857872] [2023-11-26 11:47:49,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:49,310 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:49,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:49,310 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:47:49,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:47:49,311 INFO L87 Difference]: Start difference. First operand 84295 states and 120384 transitions. cyclomatic complexity: 36153 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:50,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:50,011 INFO L93 Difference]: Finished difference Result 161570 states and 229881 transitions. [2023-11-26 11:47:50,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 161570 states and 229881 transitions. [2023-11-26 11:47:50,968 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 160832 [2023-11-26 11:47:51,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 161570 states to 161570 states and 229881 transitions. [2023-11-26 11:47:51,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161570 [2023-11-26 11:47:52,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161570 [2023-11-26 11:47:52,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 161570 states and 229881 transitions. [2023-11-26 11:47:52,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:47:52,144 INFO L218 hiAutomatonCegarLoop]: Abstraction has 161570 states and 229881 transitions. [2023-11-26 11:47:52,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161570 states and 229881 transitions. [2023-11-26 11:47:53,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161570 to 161442. [2023-11-26 11:47:53,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 161442 states, 161442 states have (on average 1.4231302882769044) internal successors, (229753), 161441 states have internal predecessors, (229753), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:54,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161442 states to 161442 states and 229753 transitions. [2023-11-26 11:47:54,336 INFO L240 hiAutomatonCegarLoop]: Abstraction has 161442 states and 229753 transitions. [2023-11-26 11:47:54,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:47:54,337 INFO L428 stractBuchiCegarLoop]: Abstraction has 161442 states and 229753 transitions. [2023-11-26 11:47:54,337 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 11:47:54,337 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 161442 states and 229753 transitions. [2023-11-26 11:47:55,399 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 160704 [2023-11-26 11:47:55,400 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:47:55,400 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:47:55,402 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:55,402 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:47:55,402 INFO L748 eck$LassoCheckResult]: Stem: 638263#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 638264#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 639231#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 639232#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 638329#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 638330#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 638236#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 638237#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 639613#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 638889#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 638890#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 638775#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 638776#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 639321#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 639322#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 638529#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 638530#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 638983#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 638984#L1194 assume !(0 == ~M_E~0); 639143#L1194-2 assume !(0 == ~T1_E~0); 639144#L1199-1 assume !(0 == ~T2_E~0); 639465#L1204-1 assume !(0 == ~T3_E~0); 639380#L1209-1 assume !(0 == ~T4_E~0); 639381#L1214-1 assume !(0 == ~T5_E~0); 639899#L1219-1 assume !(0 == ~T6_E~0); 640051#L1224-1 assume !(0 == ~T7_E~0); 638606#L1229-1 assume !(0 == ~T8_E~0); 638167#L1234-1 assume !(0 == ~T9_E~0); 638168#L1239-1 assume !(0 == ~T10_E~0); 638203#L1244-1 assume !(0 == ~T11_E~0); 638204#L1249-1 assume !(0 == ~T12_E~0); 638923#L1254-1 assume !(0 == ~E_M~0); 638101#L1259-1 assume !(0 == ~E_1~0); 638066#L1264-1 assume !(0 == ~E_2~0); 638067#L1269-1 assume !(0 == ~E_3~0); 640060#L1274-1 assume !(0 == ~E_4~0); 639941#L1279-1 assume !(0 == ~E_5~0); 638272#L1284-1 assume !(0 == ~E_6~0); 638273#L1289-1 assume !(0 == ~E_7~0); 638992#L1294-1 assume !(0 == ~E_8~0); 638993#L1299-1 assume !(0 == ~E_9~0); 639004#L1304-1 assume !(0 == ~E_10~0); 640041#L1309-1 assume !(0 == ~E_11~0); 640048#L1314-1 assume !(0 == ~E_12~0); 638230#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 638157#L586 assume !(1 == ~m_pc~0); 638158#L586-2 is_master_triggered_~__retres1~0#1 := 0; 638220#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 639062#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 638429#L1485 assume !(0 != activate_threads_~tmp~1#1); 638430#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 639621#L605 assume !(1 == ~t1_pc~0); 639079#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 638806#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 638807#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 639513#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 639438#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 638711#L624 assume !(1 == ~t2_pc~0); 638712#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 638895#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 638455#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 638456#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 639673#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 639511#L643 assume !(1 == ~t3_pc~0); 639351#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 639026#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 639027#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 638536#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 638537#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 638293#L662 assume !(1 == ~t4_pc~0); 638294#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 638252#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 638122#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 638123#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 638148#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 638149#L681 assume !(1 == ~t5_pc~0); 638022#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 638023#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 639107#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 639848#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 638549#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 638550#L700 assume !(1 == ~t6_pc~0); 638372#L700-2 is_transmit6_triggered_~__retres1~6#1 := 0; 638284#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 638285#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 638331#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 638332#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 639745#L719 assume 1 == ~t7_pc~0; 639861#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 638505#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 640029#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 639923#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 638036#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 638037#L738 assume !(1 == ~t8_pc~0); 639472#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 639371#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 639372#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 639139#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 639140#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 639537#L757 assume 1 == ~t9_pc~0; 639538#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 638031#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 638032#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 638502#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 639098#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 639099#L776 assume !(1 == ~t10_pc~0); 638053#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 638052#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 638433#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 638274#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 638275#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 638231#L795 assume 1 == ~t11_pc~0; 638232#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 638571#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 639646#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 639886#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 639341#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 639326#L814 assume !(1 == ~t12_pc~0); 639170#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 639171#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 638082#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 638083#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 638486#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 638487#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 639688#L1332-2 assume !(1 == ~T1_E~0); 639974#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 639251#L1342-1 assume !(1 == ~T3_E~0); 639252#L1347-1 assume !(1 == ~T4_E~0); 639727#L1352-1 assume !(1 == ~T5_E~0); 639544#L1357-1 assume !(1 == ~T6_E~0); 638773#L1362-1 assume !(1 == ~T7_E~0); 638774#L1367-1 assume !(1 == ~T8_E~0); 638368#L1372-1 assume !(1 == ~T9_E~0); 638369#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 638684#L1382-1 assume !(1 == ~T11_E~0); 638685#L1387-1 assume !(1 == ~T12_E~0); 639435#L1392-1 assume !(1 == ~E_M~0); 638713#L1397-1 assume !(1 == ~E_1~0); 638714#L1402-1 assume !(1 == ~E_2~0); 638384#L1407-1 assume !(1 == ~E_3~0); 638385#L1412-1 assume !(1 == ~E_4~0); 639644#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 639645#L1422-1 assume !(1 == ~E_6~0); 639975#L1427-1 assume !(1 == ~E_7~0); 638572#L1432-1 assume !(1 == ~E_8~0); 638573#L1437-1 assume !(1 == ~E_9~0); 639578#L1442-1 assume !(1 == ~E_10~0); 639579#L1447-1 assume !(1 == ~E_11~0); 639423#L1452-1 assume !(1 == ~E_12~0); 639424#L1457-1 assume { :end_inline_reset_delta_events } true; 651875#L1803-2 [2023-11-26 11:47:55,403 INFO L750 eck$LassoCheckResult]: Loop: 651875#L1803-2 assume !false; 651873#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 651866#L1169-1 assume !false; 651864#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 651857#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 651846#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 651845#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 651842#L996 assume !(0 != eval_~tmp~0#1); 651843#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 717490#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 717489#L1194-3 assume !(0 == ~M_E~0); 717488#L1194-5 assume !(0 == ~T1_E~0); 717487#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 717486#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 717485#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 717484#L1214-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 717483#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 717482#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 717481#L1229-3 assume !(0 == ~T8_E~0); 717480#L1234-3 assume !(0 == ~T9_E~0); 717479#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 717478#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 717477#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 717476#L1254-3 assume 0 == ~E_M~0;~E_M~0 := 1; 717475#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 717474#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 717473#L1269-3 assume !(0 == ~E_3~0); 717472#L1274-3 assume !(0 == ~E_4~0); 717471#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 717470#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 717469#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 717468#L1294-3 assume 0 == ~E_8~0;~E_8~0 := 1; 717467#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 717466#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 717465#L1309-3 assume !(0 == ~E_11~0); 717464#L1314-3 assume !(0 == ~E_12~0); 717463#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 717462#L586-42 assume !(1 == ~m_pc~0); 717461#L586-44 is_master_triggered_~__retres1~0#1 := 0; 717460#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 717459#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 717458#L1485-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 717457#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 717456#L605-42 assume 1 == ~t1_pc~0; 717454#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 717452#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 717450#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 717448#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 717447#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 717446#L624-42 assume !(1 == ~t2_pc~0); 717445#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 717444#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 717443#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 717442#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 717441#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 717440#L643-42 assume 1 == ~t3_pc~0; 717438#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 717437#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 717436#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 717435#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 717434#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 717433#L662-42 assume !(1 == ~t4_pc~0); 717432#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 717431#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 717430#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 717429#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 717428#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 717427#L681-42 assume !(1 == ~t5_pc~0); 717426#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 717424#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 717423#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 717422#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 717421#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 717420#L700-42 assume !(1 == ~t6_pc~0); 717419#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 717418#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 717417#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 717416#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 717415#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 717414#L719-42 assume 1 == ~t7_pc~0; 717412#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 717411#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 717410#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 717409#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 717408#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 717407#L738-42 assume !(1 == ~t8_pc~0); 717406#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 717404#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 717403#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 717402#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 717401#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 717400#L757-42 assume !(1 == ~t9_pc~0); 717398#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 717397#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 717396#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 717395#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 717394#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 717393#L776-42 assume 1 == ~t10_pc~0; 717391#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 717390#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 717389#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 717388#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 717387#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 717386#L795-42 assume !(1 == ~t11_pc~0); 717384#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 717383#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 717382#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 717381#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 717380#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 717379#L814-42 assume !(1 == ~t12_pc~0); 717378#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 717376#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 717375#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 717374#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 717373#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 717372#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 667062#L1332-5 assume !(1 == ~T1_E~0); 717371#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 717370#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 717369#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 717368#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 717367#L1357-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 717366#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 717365#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 717364#L1372-3 assume !(1 == ~T9_E~0); 699920#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 717363#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 717362#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 717361#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 717360#L1397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 717359#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 717358#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 717357#L1412-3 assume !(1 == ~E_4~0); 705061#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 717356#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 717355#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 717354#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 717353#L1437-3 assume 1 == ~E_9~0;~E_9~0 := 2; 717352#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 717351#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 717350#L1452-3 assume !(1 == ~E_12~0); 708576#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 717341#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 717336#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 717335#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 640279#L1822 assume !(0 == start_simulation_~tmp~3#1); 640280#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 712055#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 712041#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 712039#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 712038#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 712037#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 704475#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 651877#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 651875#L1803-2 [2023-11-26 11:47:55,404 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:55,404 INFO L85 PathProgramCache]: Analyzing trace with hash 1989947900, now seen corresponding path program 1 times [2023-11-26 11:47:55,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:55,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058883001] [2023-11-26 11:47:55,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:55,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:55,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:55,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:55,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:55,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058883001] [2023-11-26 11:47:55,554 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058883001] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:55,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:55,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:47:55,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [10988734] [2023-11-26 11:47:55,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:55,555 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:47:55,557 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:47:55,558 INFO L85 PathProgramCache]: Analyzing trace with hash -1775900158, now seen corresponding path program 1 times [2023-11-26 11:47:55,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:47:55,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290933282] [2023-11-26 11:47:55,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:47:55,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:47:55,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:47:55,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:47:55,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:47:55,648 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290933282] [2023-11-26 11:47:55,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290933282] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:47:55,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:47:55,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:47:55,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2041998022] [2023-11-26 11:47:55,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:47:55,650 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:47:55,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:47:55,650 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:47:55,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:47:55,651 INFO L87 Difference]: Start difference. First operand 161442 states and 229753 transitions. cyclomatic complexity: 68439 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:47:57,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:47:57,932 INFO L93 Difference]: Finished difference Result 454896 states and 642499 transitions. [2023-11-26 11:47:57,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454896 states and 642499 transitions. [2023-11-26 11:48:00,800 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 452112 [2023-11-26 11:48:02,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454896 states to 454896 states and 642499 transitions. [2023-11-26 11:48:02,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454896 [2023-11-26 11:48:02,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454896 [2023-11-26 11:48:02,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454896 states and 642499 transitions. [2023-11-26 11:48:02,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:48:02,769 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454896 states and 642499 transitions. [2023-11-26 11:48:02,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454896 states and 642499 transitions. [2023-11-26 11:48:07,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454896 to 448624. [2023-11-26 11:48:07,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 448624 states, 448624 states have (on average 1.413323852491173) internal successors, (634051), 448623 states have internal predecessors, (634051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)