./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/bist_cell.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 12:04:14,737 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 12:04:14,844 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 12:04:14,848 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 12:04:14,848 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 12:04:14,883 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 12:04:14,885 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 12:04:14,886 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 12:04:14,887 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 12:04:14,892 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 12:04:14,892 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 12:04:14,893 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 12:04:14,893 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 12:04:14,895 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 12:04:14,896 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 12:04:14,896 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 12:04:14,896 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 12:04:14,897 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 12:04:14,897 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 12:04:14,898 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 12:04:14,898 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 12:04:14,899 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 12:04:14,899 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 12:04:14,900 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 12:04:14,900 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 12:04:14,901 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 12:04:14,901 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 12:04:14,902 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 12:04:14,902 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 12:04:14,903 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 12:04:14,903 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 12:04:14,904 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 12:04:14,904 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 12:04:14,904 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 12:04:14,905 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 12:04:14,905 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 12:04:14,905 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 12:04:14,906 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 12:04:14,906 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2023-11-26 12:04:15,197 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 12:04:15,227 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 12:04:15,230 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 12:04:15,232 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 12:04:15,233 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 12:04:15,234 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/bist_cell.cil.c [2023-11-26 12:04:18,429 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 12:04:18,636 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 12:04:18,636 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/sv-benchmarks/c/systemc/bist_cell.cil.c [2023-11-26 12:04:18,648 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/data/693533587/27af448b0b2d4a8488e9585d4dcedbfc/FLAGc9841d2c8 [2023-11-26 12:04:18,663 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/data/693533587/27af448b0b2d4a8488e9585d4dcedbfc [2023-11-26 12:04:18,666 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 12:04:18,668 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 12:04:18,669 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 12:04:18,670 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 12:04:18,675 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 12:04:18,676 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:04:18" (1/1) ... [2023-11-26 12:04:18,678 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60ad5553 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:18, skipping insertion in model container [2023-11-26 12:04:18,678 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:04:18" (1/1) ... [2023-11-26 12:04:18,715 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 12:04:18,936 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:04:18,956 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 12:04:19,013 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:04:19,030 INFO L206 MainTranslator]: Completed translation [2023-11-26 12:04:19,030 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19 WrapperNode [2023-11-26 12:04:19,031 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 12:04:19,032 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 12:04:19,032 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 12:04:19,032 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 12:04:19,040 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,050 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,085 INFO L138 Inliner]: procedures = 30, calls = 31, calls flagged for inlining = 26, calls inlined = 32, statements flattened = 345 [2023-11-26 12:04:19,085 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 12:04:19,086 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 12:04:19,086 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 12:04:19,086 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 12:04:19,099 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,100 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,103 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,128 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 12:04:19,131 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,140 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,148 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,158 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,160 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,162 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,171 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 12:04:19,172 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 12:04:19,185 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 12:04:19,185 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 12:04:19,186 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (1/1) ... [2023-11-26 12:04:19,192 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:19,209 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:19,224 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:19,247 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 12:04:19,283 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 12:04:19,283 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 12:04:19,284 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 12:04:19,284 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 12:04:19,407 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 12:04:19,410 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 12:04:19,912 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 12:04:19,931 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 12:04:19,931 INFO L309 CfgBuilder]: Removed 2 assume(true) statements. [2023-11-26 12:04:19,933 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:04:19 BoogieIcfgContainer [2023-11-26 12:04:19,933 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 12:04:19,935 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 12:04:19,935 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 12:04:19,939 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 12:04:19,940 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:04:19,941 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 12:04:18" (1/3) ... [2023-11-26 12:04:19,942 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2391842b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:04:19, skipping insertion in model container [2023-11-26 12:04:19,942 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:04:19,942 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:04:19" (2/3) ... [2023-11-26 12:04:19,943 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2391842b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:04:19, skipping insertion in model container [2023-11-26 12:04:19,943 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:04:19,943 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:04:19" (3/3) ... [2023-11-26 12:04:19,945 INFO L332 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2023-11-26 12:04:20,021 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 12:04:20,022 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 12:04:20,022 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 12:04:20,022 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 12:04:20,022 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 12:04:20,022 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 12:04:20,023 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 12:04:20,023 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 12:04:20,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 126 states, 125 states have (on average 1.584) internal successors, (198), 125 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:20,056 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:20,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:20,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:20,065 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:20,065 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:20,065 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 12:04:20,066 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 126 states, 125 states have (on average 1.584) internal successors, (198), 125 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:20,078 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:20,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:20,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:20,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:20,081 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:20,090 INFO L748 eck$LassoCheckResult]: Stem: 27#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 41#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 118#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70#L212true assume !(1 == ~b0_req_up~0); 122#L212-2true assume !(1 == ~b1_req_up~0); 78#L219-1true assume !(1 == ~d0_req_up~0); 42#L226-1true assume !(1 == ~d1_req_up~0); 61#L233-1true assume !(1 == ~z_req_up~0); 105#L240-1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13#L255true assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 115#L255-2true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62#L321true assume !(0 == ~b0_ev~0); 77#L321-2true assume !(0 == ~b1_ev~0); 22#L326-1true assume !(0 == ~d0_ev~0); 25#L331-1true assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 5#L336-1true assume !(0 == ~z_ev~0); 120#L341-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 116#L107true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 104#L129true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 75#is_method1_triggered_returnLabel#1true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 87#L390true assume !(0 != activate_threads_~tmp~1#1); 110#L390-2true havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53#L354true assume !(1 == ~b0_ev~0); 38#L354-2true assume !(1 == ~b1_ev~0); 85#L359-1true assume !(1 == ~d0_ev~0); 40#L364-1true assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 45#L369-1true assume !(1 == ~z_ev~0); 92#L374-1true assume { :end_inline_reset_delta_events } true; 33#L432-2true [2023-11-26 12:04:20,091 INFO L750 eck$LassoCheckResult]: Loop: 33#L432-2true assume !false; 64#L433true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 4#L295true assume !true; 84#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79#L212-3true assume !(1 == ~b0_req_up~0); 107#L212-5true assume !(1 == ~b1_req_up~0); 83#L219-3true assume !(1 == ~d0_req_up~0); 3#L226-3true assume !(1 == ~d1_req_up~0); 36#L233-3true assume !(1 == ~z_req_up~0); 14#L240-3true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74#L321-3true assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 60#L321-5true assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 89#L326-3true assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 48#L331-3true assume !(0 == ~d1_ev~0); 9#L336-3true assume 0 == ~z_ev~0;~z_ev~0 := 1; 15#L341-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 112#L107-1true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 43#L129-1true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 113#is_method1_triggered_returnLabel#2true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 6#L390-3true assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 21#L390-5true havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31#L354-3true assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 97#L354-5true assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 95#L359-3true assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 76#L364-3true assume !(1 == ~d1_ev~0); 73#L369-3true assume 1 == ~z_ev~0;~z_ev~0 := 2; 47#L374-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 66#L268-1true assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 117#L275-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 90#exists_runnable_thread_returnLabel#2true stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 11#L407true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 114#L414true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123#stop_simulation_returnLabel#1true start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 67#L449true assume !(0 != start_simulation_~tmp~3#1); 33#L432-2true [2023-11-26 12:04:20,098 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:20,098 INFO L85 PathProgramCache]: Analyzing trace with hash -1345002148, now seen corresponding path program 1 times [2023-11-26 12:04:20,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:20,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881780598] [2023-11-26 12:04:20,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:20,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:20,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:20,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:20,366 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:20,366 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881780598] [2023-11-26 12:04:20,367 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881780598] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:20,367 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:20,367 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:20,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246128556] [2023-11-26 12:04:20,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:20,375 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:20,376 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:20,376 INFO L85 PathProgramCache]: Analyzing trace with hash 972845291, now seen corresponding path program 1 times [2023-11-26 12:04:20,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:20,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672621204] [2023-11-26 12:04:20,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:20,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:20,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:20,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:20,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:20,409 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672621204] [2023-11-26 12:04:20,409 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1672621204] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:20,409 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:20,409 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:04:20,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648392155] [2023-11-26 12:04:20,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:20,411 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:04:20,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:20,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:20,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:20,452 INFO L87 Difference]: Start difference. First operand has 126 states, 125 states have (on average 1.584) internal successors, (198), 125 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:20,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:20,491 INFO L93 Difference]: Finished difference Result 124 states and 190 transitions. [2023-11-26 12:04:20,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 190 transitions. [2023-11-26 12:04:20,497 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:20,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 117 states and 183 transitions. [2023-11-26 12:04:20,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2023-11-26 12:04:20,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2023-11-26 12:04:20,506 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 183 transitions. [2023-11-26 12:04:20,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:04:20,507 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2023-11-26 12:04:20,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 183 transitions. [2023-11-26 12:04:20,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2023-11-26 12:04:20,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.564102564102564) internal successors, (183), 116 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:20,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 183 transitions. [2023-11-26 12:04:20,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2023-11-26 12:04:20,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:20,544 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 183 transitions. [2023-11-26 12:04:20,545 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 12:04:20,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 183 transitions. [2023-11-26 12:04:20,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:20,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:20,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:20,550 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:20,550 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:20,550 INFO L748 eck$LassoCheckResult]: Stem: 302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 355#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 343#L137 assume !(~b0_val~0 != ~b0_val_t~0); 344#L137-2 ~b0_req_up~0 := 0; 371#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 375#L212-2 assume !(1 == ~b1_req_up~0); 278#L219-1 assume !(1 == ~d0_req_up~0); 325#L226-1 assume !(1 == ~d1_req_up~0); 327#L233-1 assume !(1 == ~z_req_up~0); 348#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 279#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 280#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 349#L321 assume !(0 == ~b0_ev~0); 350#L321-2 assume !(0 == ~b1_ev~0); 295#L326-1 assume !(0 == ~d0_ev~0); 296#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 264#L336-1 assume !(0 == ~z_ev~0); 265#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 374#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 288#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 358#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 359#L390 assume !(0 != activate_threads_~tmp~1#1); 364#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336#L354 assume !(1 == ~b0_ev~0); 318#L354-2 assume !(1 == ~b1_ev~0); 319#L359-1 assume !(1 == ~d0_ev~0); 322#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 323#L369-1 assume !(1 == ~z_ev~0); 329#L374-1 assume { :end_inline_reset_delta_events } true; 310#L432-2 [2023-11-26 12:04:20,551 INFO L750 eck$LassoCheckResult]: Loop: 310#L432-2 assume !false; 311#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 262#L295 assume !false; 263#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 292#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 293#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 273#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 274#L290 assume !(0 != eval_~tmp___0~0#1); 363#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 361#L212-3 assume !(1 == ~b0_req_up~0); 314#L212-5 assume !(1 == ~b1_req_up~0); 321#L219-3 assume !(1 == ~d0_req_up~0); 259#L226-3 assume !(1 == ~d1_req_up~0); 260#L233-3 assume !(1 == ~z_req_up~0); 281#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 345#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 346#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 332#L331-3 assume !(0 == ~d1_ev~0); 271#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 272#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 283#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 301#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 328#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 266#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 267#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 294#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 307#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 368#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 360#L364-3 assume !(1 == ~d1_ev~0); 357#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 330#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 331#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 351#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 365#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 275#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 276#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 373#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 352#L449 assume !(0 != start_simulation_~tmp~3#1); 310#L432-2 [2023-11-26 12:04:20,551 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:20,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1840469421, now seen corresponding path program 1 times [2023-11-26 12:04:20,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:20,552 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855090121] [2023-11-26 12:04:20,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:20,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:20,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:20,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:20,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:20,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855090121] [2023-11-26 12:04:20,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855090121] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:20,736 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:20,736 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:20,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187626282] [2023-11-26 12:04:20,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:20,737 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:20,738 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:20,738 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 1 times [2023-11-26 12:04:20,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:20,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431697095] [2023-11-26 12:04:20,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:20,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:20,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:20,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:20,833 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:20,833 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431697095] [2023-11-26 12:04:20,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431697095] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:20,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:20,834 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:04:20,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2062281750] [2023-11-26 12:04:20,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:20,834 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:04:20,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:20,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:20,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:20,836 INFO L87 Difference]: Start difference. First operand 117 states and 183 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:20,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:20,860 INFO L93 Difference]: Finished difference Result 117 states and 182 transitions. [2023-11-26 12:04:20,860 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 182 transitions. [2023-11-26 12:04:20,863 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:20,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 182 transitions. [2023-11-26 12:04:20,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2023-11-26 12:04:20,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2023-11-26 12:04:20,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 182 transitions. [2023-11-26 12:04:20,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:04:20,867 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2023-11-26 12:04:20,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 182 transitions. [2023-11-26 12:04:20,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2023-11-26 12:04:20,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5555555555555556) internal successors, (182), 116 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:20,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 182 transitions. [2023-11-26 12:04:20,876 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2023-11-26 12:04:20,876 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:20,877 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 182 transitions. [2023-11-26 12:04:20,878 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 12:04:20,878 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 182 transitions. [2023-11-26 12:04:20,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:20,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:20,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:20,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:20,882 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:20,882 INFO L748 eck$LassoCheckResult]: Stem: 545#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 567#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 598#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 586#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 587#L137-2 ~b0_req_up~0 := 0; 614#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 618#L212-2 assume !(1 == ~b1_req_up~0); 521#L219-1 assume !(1 == ~d0_req_up~0); 568#L226-1 assume !(1 == ~d1_req_up~0); 570#L233-1 assume !(1 == ~z_req_up~0); 591#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 522#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 523#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 592#L321 assume !(0 == ~b0_ev~0); 593#L321-2 assume !(0 == ~b1_ev~0); 538#L326-1 assume !(0 == ~d0_ev~0); 539#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 507#L336-1 assume !(0 == ~z_ev~0); 508#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 617#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 531#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 601#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 602#L390 assume !(0 != activate_threads_~tmp~1#1); 607#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 579#L354 assume !(1 == ~b0_ev~0); 561#L354-2 assume !(1 == ~b1_ev~0); 562#L359-1 assume !(1 == ~d0_ev~0); 565#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 566#L369-1 assume !(1 == ~z_ev~0); 572#L374-1 assume { :end_inline_reset_delta_events } true; 553#L432-2 [2023-11-26 12:04:20,882 INFO L750 eck$LassoCheckResult]: Loop: 553#L432-2 assume !false; 554#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 505#L295 assume !false; 506#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 535#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 536#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 516#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 517#L290 assume !(0 != eval_~tmp___0~0#1); 606#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 604#L212-3 assume !(1 == ~b0_req_up~0); 557#L212-5 assume !(1 == ~b1_req_up~0); 564#L219-3 assume !(1 == ~d0_req_up~0); 502#L226-3 assume !(1 == ~d1_req_up~0); 503#L233-3 assume !(1 == ~z_req_up~0); 524#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 525#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 588#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 589#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 575#L331-3 assume !(0 == ~d1_ev~0); 514#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 515#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 526#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 544#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 571#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 509#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 510#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 537#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 550#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 611#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 603#L364-3 assume !(1 == ~d1_ev~0); 600#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 573#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 574#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 594#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 608#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 518#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 519#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 616#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 595#L449 assume !(0 != start_simulation_~tmp~3#1); 553#L432-2 [2023-11-26 12:04:20,883 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:20,883 INFO L85 PathProgramCache]: Analyzing trace with hash 531269841, now seen corresponding path program 1 times [2023-11-26 12:04:20,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:20,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72810414] [2023-11-26 12:04:20,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:20,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:20,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:20,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:20,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:20,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [72810414] [2023-11-26 12:04:20,961 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [72810414] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:20,961 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:20,961 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:20,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677954369] [2023-11-26 12:04:20,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:20,962 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:20,962 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:20,962 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 2 times [2023-11-26 12:04:20,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:20,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936292812] [2023-11-26 12:04:20,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:20,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:20,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:21,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:21,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:21,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936292812] [2023-11-26 12:04:21,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936292812] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:21,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:21,033 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:04:21,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110370008] [2023-11-26 12:04:21,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:21,034 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:04:21,034 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:21,035 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:21,035 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:21,035 INFO L87 Difference]: Start difference. First operand 117 states and 182 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:21,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:21,058 INFO L93 Difference]: Finished difference Result 117 states and 181 transitions. [2023-11-26 12:04:21,058 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 181 transitions. [2023-11-26 12:04:21,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:21,061 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 181 transitions. [2023-11-26 12:04:21,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2023-11-26 12:04:21,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2023-11-26 12:04:21,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 181 transitions. [2023-11-26 12:04:21,063 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:04:21,063 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2023-11-26 12:04:21,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 181 transitions. [2023-11-26 12:04:21,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2023-11-26 12:04:21,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.547008547008547) internal successors, (181), 116 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:21,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 181 transitions. [2023-11-26 12:04:21,072 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2023-11-26 12:04:21,073 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:21,074 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 181 transitions. [2023-11-26 12:04:21,074 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 12:04:21,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 181 transitions. [2023-11-26 12:04:21,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:21,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:21,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:21,077 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:21,077 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:21,078 INFO L748 eck$LassoCheckResult]: Stem: 788#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 810#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 841#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 829#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 830#L137-2 ~b0_req_up~0 := 0; 857#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 861#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 790#L152 assume !(~b1_val~0 != ~b1_val_t~0); 791#L152-2 ~b1_req_up~0 := 0; 763#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 764#L219-1 assume !(1 == ~d0_req_up~0); 811#L226-1 assume !(1 == ~d1_req_up~0); 813#L233-1 assume !(1 == ~z_req_up~0); 834#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 765#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 766#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 835#L321 assume !(0 == ~b0_ev~0); 836#L321-2 assume !(0 == ~b1_ev~0); 781#L326-1 assume !(0 == ~d0_ev~0); 782#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 750#L336-1 assume !(0 == ~z_ev~0); 751#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 860#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 774#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 844#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 845#L390 assume !(0 != activate_threads_~tmp~1#1); 850#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 822#L354 assume !(1 == ~b0_ev~0); 804#L354-2 assume !(1 == ~b1_ev~0); 805#L359-1 assume !(1 == ~d0_ev~0); 808#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 809#L369-1 assume !(1 == ~z_ev~0); 815#L374-1 assume { :end_inline_reset_delta_events } true; 796#L432-2 [2023-11-26 12:04:21,078 INFO L750 eck$LassoCheckResult]: Loop: 796#L432-2 assume !false; 797#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 748#L295 assume !false; 749#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 778#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 779#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 759#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 760#L290 assume !(0 != eval_~tmp___0~0#1); 849#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 847#L212-3 assume !(1 == ~b0_req_up~0); 800#L212-5 assume !(1 == ~b1_req_up~0); 807#L219-3 assume !(1 == ~d0_req_up~0); 745#L226-3 assume !(1 == ~d1_req_up~0); 746#L233-3 assume !(1 == ~z_req_up~0); 767#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 768#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 831#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 832#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 818#L331-3 assume !(0 == ~d1_ev~0); 757#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 758#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 769#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 787#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 814#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 752#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 753#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 780#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 793#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 854#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 846#L364-3 assume !(1 == ~d1_ev~0); 843#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 816#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 817#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 837#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 851#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 761#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 762#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 859#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 838#L449 assume !(0 != start_simulation_~tmp~3#1); 796#L432-2 [2023-11-26 12:04:21,079 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:21,079 INFO L85 PathProgramCache]: Analyzing trace with hash 1296388927, now seen corresponding path program 1 times [2023-11-26 12:04:21,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:21,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509992686] [2023-11-26 12:04:21,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:21,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:21,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:21,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:21,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:21,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1509992686] [2023-11-26 12:04:21,240 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1509992686] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:21,240 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:21,240 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:04:21,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [624500040] [2023-11-26 12:04:21,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:21,241 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:21,241 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:21,242 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 3 times [2023-11-26 12:04:21,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:21,242 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534486697] [2023-11-26 12:04:21,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:21,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:21,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:21,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:21,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:21,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534486697] [2023-11-26 12:04:21,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534486697] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:21,304 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:21,305 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:04:21,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1370603461] [2023-11-26 12:04:21,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:21,306 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:04:21,306 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:21,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:04:21,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:04:21,307 INFO L87 Difference]: Start difference. First operand 117 states and 181 transitions. cyclomatic complexity: 65 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:21,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:21,355 INFO L93 Difference]: Finished difference Result 117 states and 180 transitions. [2023-11-26 12:04:21,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 180 transitions. [2023-11-26 12:04:21,357 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:21,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 180 transitions. [2023-11-26 12:04:21,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2023-11-26 12:04:21,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2023-11-26 12:04:21,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 180 transitions. [2023-11-26 12:04:21,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:04:21,361 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2023-11-26 12:04:21,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 180 transitions. [2023-11-26 12:04:21,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2023-11-26 12:04:21,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5384615384615385) internal successors, (180), 116 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:21,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 180 transitions. [2023-11-26 12:04:21,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2023-11-26 12:04:21,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-26 12:04:21,371 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 180 transitions. [2023-11-26 12:04:21,372 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 12:04:21,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 180 transitions. [2023-11-26 12:04:21,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:21,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:21,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:21,375 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:21,375 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:21,376 INFO L748 eck$LassoCheckResult]: Stem: 1034#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1056#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1087#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1075#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1076#L137-2 ~b0_req_up~0 := 0; 1103#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1107#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1036#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1037#L152-2 ~b1_req_up~0 := 0; 1009#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1010#L219-1 assume !(1 == ~d0_req_up~0); 1057#L226-1 assume !(1 == ~d1_req_up~0); 1059#L233-1 assume !(1 == ~z_req_up~0); 1080#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1011#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1012#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1081#L321 assume !(0 == ~b0_ev~0); 1082#L321-2 assume !(0 == ~b1_ev~0); 1027#L326-1 assume !(0 == ~d0_ev~0); 1028#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 996#L336-1 assume !(0 == ~z_ev~0); 997#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1106#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1020#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1090#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1091#L390 assume !(0 != activate_threads_~tmp~1#1); 1096#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1068#L354 assume !(1 == ~b0_ev~0); 1050#L354-2 assume !(1 == ~b1_ev~0); 1051#L359-1 assume !(1 == ~d0_ev~0); 1054#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1055#L369-1 assume !(1 == ~z_ev~0); 1061#L374-1 assume { :end_inline_reset_delta_events } true; 1042#L432-2 [2023-11-26 12:04:21,396 INFO L750 eck$LassoCheckResult]: Loop: 1042#L432-2 assume !false; 1043#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 994#L295 assume !false; 995#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1024#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1025#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1005#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1006#L290 assume !(0 != eval_~tmp___0~0#1); 1095#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1093#L212-3 assume !(1 == ~b0_req_up~0); 1046#L212-5 assume !(1 == ~b1_req_up~0); 1053#L219-3 assume !(1 == ~d0_req_up~0); 991#L226-3 assume !(1 == ~d1_req_up~0); 992#L233-3 assume !(1 == ~z_req_up~0); 1013#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1014#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1077#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1078#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1064#L331-3 assume !(0 == ~d1_ev~0); 1003#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1004#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1015#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1033#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1060#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 998#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 999#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1026#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1039#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1100#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1092#L364-3 assume !(1 == ~d1_ev~0); 1089#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1062#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1063#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1083#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1097#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1007#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1008#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1105#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1084#L449 assume !(0 != start_simulation_~tmp~3#1); 1042#L432-2 [2023-11-26 12:04:21,397 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:21,397 INFO L85 PathProgramCache]: Analyzing trace with hash 1234349313, now seen corresponding path program 1 times [2023-11-26 12:04:21,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:21,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209316992] [2023-11-26 12:04:21,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:21,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:21,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:21,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:21,451 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:21,451 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209316992] [2023-11-26 12:04:21,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209316992] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:21,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:21,452 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:21,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993027293] [2023-11-26 12:04:21,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:21,453 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:21,454 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:21,454 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 4 times [2023-11-26 12:04:21,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:21,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340046608] [2023-11-26 12:04:21,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:21,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:21,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:21,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:21,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:21,535 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340046608] [2023-11-26 12:04:21,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340046608] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:21,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:21,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:04:21,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129338654] [2023-11-26 12:04:21,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:21,537 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:04:21,539 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:21,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:21,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:21,540 INFO L87 Difference]: Start difference. First operand 117 states and 180 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:21,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:21,561 INFO L93 Difference]: Finished difference Result 117 states and 179 transitions. [2023-11-26 12:04:21,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 179 transitions. [2023-11-26 12:04:21,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:21,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 179 transitions. [2023-11-26 12:04:21,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2023-11-26 12:04:21,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2023-11-26 12:04:21,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 179 transitions. [2023-11-26 12:04:21,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:04:21,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2023-11-26 12:04:21,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 179 transitions. [2023-11-26 12:04:21,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2023-11-26 12:04:21,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5299145299145298) internal successors, (179), 116 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:21,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 179 transitions. [2023-11-26 12:04:21,586 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2023-11-26 12:04:21,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:21,594 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 179 transitions. [2023-11-26 12:04:21,594 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 12:04:21,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 179 transitions. [2023-11-26 12:04:21,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:21,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:21,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:21,597 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:21,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:21,598 INFO L748 eck$LassoCheckResult]: Stem: 1277#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1278#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1299#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1330#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1318#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1319#L137-2 ~b0_req_up~0 := 0; 1346#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1350#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1279#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1280#L152-2 ~b1_req_up~0 := 0; 1252#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1253#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1259#L167 assume !(~d0_val~0 != ~d0_val_t~0); 1260#L167-2 ~d0_req_up~0 := 0; 1274#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 1300#L226-1 assume !(1 == ~d1_req_up~0); 1302#L233-1 assume !(1 == ~z_req_up~0); 1323#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1254#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1255#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1324#L321 assume !(0 == ~b0_ev~0); 1325#L321-2 assume !(0 == ~b1_ev~0); 1270#L326-1 assume !(0 == ~d0_ev~0); 1271#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1239#L336-1 assume !(0 == ~z_ev~0); 1240#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1349#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1263#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1333#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1334#L390 assume !(0 != activate_threads_~tmp~1#1); 1339#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1311#L354 assume !(1 == ~b0_ev~0); 1293#L354-2 assume !(1 == ~b1_ev~0); 1294#L359-1 assume !(1 == ~d0_ev~0); 1297#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1298#L369-1 assume !(1 == ~z_ev~0); 1304#L374-1 assume { :end_inline_reset_delta_events } true; 1285#L432-2 [2023-11-26 12:04:21,598 INFO L750 eck$LassoCheckResult]: Loop: 1285#L432-2 assume !false; 1286#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1237#L295 assume !false; 1238#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1267#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1268#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1248#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1249#L290 assume !(0 != eval_~tmp___0~0#1); 1338#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1336#L212-3 assume !(1 == ~b0_req_up~0); 1289#L212-5 assume !(1 == ~b1_req_up~0); 1296#L219-3 assume !(1 == ~d0_req_up~0); 1234#L226-3 assume !(1 == ~d1_req_up~0); 1235#L233-3 assume !(1 == ~z_req_up~0); 1256#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1257#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1320#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1321#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1307#L331-3 assume !(0 == ~d1_ev~0); 1246#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1247#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1258#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1276#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1303#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1241#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1242#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1269#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1282#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1343#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1335#L364-3 assume !(1 == ~d1_ev~0); 1332#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1305#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1306#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1326#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1340#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1250#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1251#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1348#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1327#L449 assume !(0 != start_simulation_~tmp~3#1); 1285#L432-2 [2023-11-26 12:04:21,598 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:21,599 INFO L85 PathProgramCache]: Analyzing trace with hash -2115080082, now seen corresponding path program 1 times [2023-11-26 12:04:21,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:21,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512059642] [2023-11-26 12:04:21,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:21,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:21,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:21,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:21,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:21,714 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512059642] [2023-11-26 12:04:21,719 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1512059642] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:21,719 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:21,719 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:04:21,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [745003423] [2023-11-26 12:04:21,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:21,721 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:21,722 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:21,722 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 5 times [2023-11-26 12:04:21,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:21,723 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808810744] [2023-11-26 12:04:21,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:21,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:21,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:21,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:21,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:21,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808810744] [2023-11-26 12:04:21,812 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808810744] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:21,812 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:21,812 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:04:21,812 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965467623] [2023-11-26 12:04:21,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:21,813 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:04:21,813 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:21,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:04:21,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:04:21,815 INFO L87 Difference]: Start difference. First operand 117 states and 179 transitions. cyclomatic complexity: 63 Second operand has 4 states, 4 states have (on average 9.25) internal successors, (37), 4 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:21,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:21,858 INFO L93 Difference]: Finished difference Result 117 states and 178 transitions. [2023-11-26 12:04:21,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 178 transitions. [2023-11-26 12:04:21,860 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:21,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 178 transitions. [2023-11-26 12:04:21,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2023-11-26 12:04:21,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2023-11-26 12:04:21,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 178 transitions. [2023-11-26 12:04:21,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:04:21,864 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2023-11-26 12:04:21,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 178 transitions. [2023-11-26 12:04:21,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2023-11-26 12:04:21,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5213675213675213) internal successors, (178), 116 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:21,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 178 transitions. [2023-11-26 12:04:21,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2023-11-26 12:04:21,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-26 12:04:21,883 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 178 transitions. [2023-11-26 12:04:21,884 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 12:04:21,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 178 transitions. [2023-11-26 12:04:21,885 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:21,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:21,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:21,887 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:21,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:21,888 INFO L748 eck$LassoCheckResult]: Stem: 1523#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1524#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1545#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1576#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1564#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1565#L137-2 ~b0_req_up~0 := 0; 1592#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1596#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1525#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1526#L152-2 ~b1_req_up~0 := 0; 1498#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1499#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1505#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1506#L167-2 ~d0_req_up~0 := 0; 1520#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 1546#L226-1 assume !(1 == ~d1_req_up~0); 1548#L233-1 assume !(1 == ~z_req_up~0); 1569#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1500#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1501#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1570#L321 assume !(0 == ~b0_ev~0); 1571#L321-2 assume !(0 == ~b1_ev~0); 1516#L326-1 assume !(0 == ~d0_ev~0); 1517#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1485#L336-1 assume !(0 == ~z_ev~0); 1486#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1595#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1509#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1579#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1580#L390 assume !(0 != activate_threads_~tmp~1#1); 1585#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1557#L354 assume !(1 == ~b0_ev~0); 1539#L354-2 assume !(1 == ~b1_ev~0); 1540#L359-1 assume !(1 == ~d0_ev~0); 1543#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1544#L369-1 assume !(1 == ~z_ev~0); 1550#L374-1 assume { :end_inline_reset_delta_events } true; 1531#L432-2 [2023-11-26 12:04:21,888 INFO L750 eck$LassoCheckResult]: Loop: 1531#L432-2 assume !false; 1532#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1483#L295 assume !false; 1484#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1513#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1514#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1494#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1495#L290 assume !(0 != eval_~tmp___0~0#1); 1584#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1582#L212-3 assume !(1 == ~b0_req_up~0); 1535#L212-5 assume !(1 == ~b1_req_up~0); 1542#L219-3 assume !(1 == ~d0_req_up~0); 1480#L226-3 assume !(1 == ~d1_req_up~0); 1481#L233-3 assume !(1 == ~z_req_up~0); 1502#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1503#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1566#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1567#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1553#L331-3 assume !(0 == ~d1_ev~0); 1492#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1493#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1504#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1522#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1549#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1487#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1488#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1515#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1528#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1589#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1581#L364-3 assume !(1 == ~d1_ev~0); 1578#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1551#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1552#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1572#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1586#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1496#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1497#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1594#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1573#L449 assume !(0 != start_simulation_~tmp~3#1); 1531#L432-2 [2023-11-26 12:04:21,889 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:21,889 INFO L85 PathProgramCache]: Analyzing trace with hash 2039338604, now seen corresponding path program 1 times [2023-11-26 12:04:21,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:21,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495952850] [2023-11-26 12:04:21,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:21,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:21,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:21,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:21,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:21,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1495952850] [2023-11-26 12:04:21,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1495952850] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:21,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:21,925 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:21,925 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498366992] [2023-11-26 12:04:21,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:21,926 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:21,926 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:21,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 6 times [2023-11-26 12:04:21,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:21,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363564500] [2023-11-26 12:04:21,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:21,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:21,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:21,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:21,993 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:21,993 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [363564500] [2023-11-26 12:04:21,994 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [363564500] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:21,994 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:21,994 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:04:21,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306494472] [2023-11-26 12:04:21,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:21,995 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:04:21,995 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:21,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:21,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:21,996 INFO L87 Difference]: Start difference. First operand 117 states and 178 transitions. cyclomatic complexity: 62 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:22,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:22,008 INFO L93 Difference]: Finished difference Result 117 states and 177 transitions. [2023-11-26 12:04:22,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 177 transitions. [2023-11-26 12:04:22,010 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:22,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 177 transitions. [2023-11-26 12:04:22,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2023-11-26 12:04:22,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2023-11-26 12:04:22,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 177 transitions. [2023-11-26 12:04:22,012 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:04:22,012 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2023-11-26 12:04:22,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 177 transitions. [2023-11-26 12:04:22,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2023-11-26 12:04:22,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5128205128205128) internal successors, (177), 116 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:22,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 177 transitions. [2023-11-26 12:04:22,020 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2023-11-26 12:04:22,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:22,023 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 177 transitions. [2023-11-26 12:04:22,023 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 12:04:22,023 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 177 transitions. [2023-11-26 12:04:22,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2023-11-26 12:04:22,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:22,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:22,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:22,030 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:22,030 INFO L748 eck$LassoCheckResult]: Stem: 1766#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1788#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1819#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1806#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1807#L137-2 ~b0_req_up~0 := 0; 1835#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1839#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1768#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1769#L152-2 ~b1_req_up~0 := 0; 1741#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1742#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1748#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1749#L167-2 ~d0_req_up~0 := 0; 1763#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 1789#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 1790#L182 assume !(~d1_val~0 != ~d1_val_t~0); 1754#L182-2 ~d1_req_up~0 := 0; 1755#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 1810#L233-1 assume !(1 == ~z_req_up~0); 1812#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1743#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1744#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1813#L321 assume !(0 == ~b0_ev~0); 1814#L321-2 assume !(0 == ~b1_ev~0); 1759#L326-1 assume !(0 == ~d0_ev~0); 1760#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1728#L336-1 assume !(0 == ~z_ev~0); 1729#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1838#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1752#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1822#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1823#L390 assume !(0 != activate_threads_~tmp~1#1); 1828#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1799#L354 assume !(1 == ~b0_ev~0); 1782#L354-2 assume !(1 == ~b1_ev~0); 1783#L359-1 assume !(1 == ~d0_ev~0); 1786#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1787#L369-1 assume !(1 == ~z_ev~0); 1792#L374-1 assume { :end_inline_reset_delta_events } true; 1774#L432-2 [2023-11-26 12:04:22,030 INFO L750 eck$LassoCheckResult]: Loop: 1774#L432-2 assume !false; 1775#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1726#L295 assume !false; 1727#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1756#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1757#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1737#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1738#L290 assume !(0 != eval_~tmp___0~0#1); 1827#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1825#L212-3 assume !(1 == ~b0_req_up~0); 1778#L212-5 assume !(1 == ~b1_req_up~0); 1785#L219-3 assume !(1 == ~d0_req_up~0); 1723#L226-3 assume !(1 == ~d1_req_up~0); 1724#L233-3 assume !(1 == ~z_req_up~0); 1745#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1746#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1808#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1809#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1795#L331-3 assume !(0 == ~d1_ev~0); 1735#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1736#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1747#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1765#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1791#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1730#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1731#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1758#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1771#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1832#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1824#L364-3 assume !(1 == ~d1_ev~0); 1821#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1793#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1794#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1815#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1829#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1739#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1740#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1837#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1816#L449 assume !(0 != start_simulation_~tmp~3#1); 1774#L432-2 [2023-11-26 12:04:22,031 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:22,031 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 1 times [2023-11-26 12:04:22,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:22,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552696713] [2023-11-26 12:04:22,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:22,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:22,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:22,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:22,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:22,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552696713] [2023-11-26 12:04:22,109 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552696713] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:22,109 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:22,109 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:04:22,109 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615619259] [2023-11-26 12:04:22,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:22,110 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:22,110 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:22,110 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 7 times [2023-11-26 12:04:22,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:22,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931715026] [2023-11-26 12:04:22,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:22,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:22,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:22,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:22,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:22,169 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [931715026] [2023-11-26 12:04:22,171 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [931715026] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:22,171 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:22,172 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:04:22,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207511812] [2023-11-26 12:04:22,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:22,172 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:04:22,173 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:22,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 12:04:22,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 12:04:22,173 INFO L87 Difference]: Start difference. First operand 117 states and 177 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:22,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:22,266 INFO L93 Difference]: Finished difference Result 151 states and 225 transitions. [2023-11-26 12:04:22,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 225 transitions. [2023-11-26 12:04:22,268 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 105 [2023-11-26 12:04:22,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 151 states and 225 transitions. [2023-11-26 12:04:22,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 151 [2023-11-26 12:04:22,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 151 [2023-11-26 12:04:22,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 151 states and 225 transitions. [2023-11-26 12:04:22,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:04:22,271 INFO L218 hiAutomatonCegarLoop]: Abstraction has 151 states and 225 transitions. [2023-11-26 12:04:22,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states and 225 transitions. [2023-11-26 12:04:22,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 120. [2023-11-26 12:04:22,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120 states, 120 states have (on average 1.5) internal successors, (180), 119 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:22,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 180 transitions. [2023-11-26 12:04:22,275 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120 states and 180 transitions. [2023-11-26 12:04:22,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 12:04:22,279 INFO L428 stractBuchiCegarLoop]: Abstraction has 120 states and 180 transitions. [2023-11-26 12:04:22,279 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 12:04:22,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120 states and 180 transitions. [2023-11-26 12:04:22,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2023-11-26 12:04:22,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:22,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:22,286 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:22,286 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:22,287 INFO L748 eck$LassoCheckResult]: Stem: 2054#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 2055#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 2076#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2107#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 2094#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 2095#L137-2 ~b0_req_up~0 := 0; 2124#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 2128#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 2056#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 2057#L152-2 ~b1_req_up~0 := 0; 2028#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 2029#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 2035#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 2036#L167-2 ~d0_req_up~0 := 0; 2051#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 2077#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 2078#L182 assume !(~d1_val~0 != ~d1_val_t~0); 2041#L182-2 ~d1_req_up~0 := 0; 2042#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 2098#L233-1 assume !(1 == ~z_req_up~0); 2100#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2030#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 2031#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2101#L321 assume !(0 == ~b0_ev~0); 2102#L321-2 assume !(0 == ~b1_ev~0); 2047#L326-1 assume !(0 == ~d0_ev~0); 2048#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 2015#L336-1 assume !(0 == ~z_ev~0); 2016#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2127#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2039#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2110#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2111#L390 assume !(0 != activate_threads_~tmp~1#1); 2116#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2087#L354 assume !(1 == ~b0_ev~0); 2070#L354-2 assume !(1 == ~b1_ev~0); 2071#L359-1 assume !(1 == ~d0_ev~0); 2074#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 2075#L369-1 assume !(1 == ~z_ev~0); 2080#L374-1 assume { :end_inline_reset_delta_events } true; 2062#L432-2 [2023-11-26 12:04:22,288 INFO L750 eck$LassoCheckResult]: Loop: 2062#L432-2 assume !false; 2063#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 2013#L295 assume !false; 2014#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2043#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 2045#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2122#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2129#L290 assume !(0 != eval_~tmp___0~0#1); 2115#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2113#L212-3 assume !(1 == ~b0_req_up~0); 2066#L212-5 assume !(1 == ~b1_req_up~0); 2073#L219-3 assume !(1 == ~d0_req_up~0); 2010#L226-3 assume !(1 == ~d1_req_up~0); 2011#L233-3 assume !(1 == ~z_req_up~0); 2032#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2033#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 2096#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 2097#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 2083#L331-3 assume !(0 == ~d1_ev~0); 2022#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 2023#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2034#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2053#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2079#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2017#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 2018#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2046#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 2059#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 2120#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 2112#L364-3 assume !(1 == ~d1_ev~0); 2109#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 2081#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2082#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 2103#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2117#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 2026#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2027#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2126#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 2104#L449 assume !(0 != start_simulation_~tmp~3#1); 2062#L432-2 [2023-11-26 12:04:22,289 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:22,289 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 2 times [2023-11-26 12:04:22,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:22,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687290280] [2023-11-26 12:04:22,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:22,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:22,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:22,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:22,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:22,418 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687290280] [2023-11-26 12:04:22,419 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687290280] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:22,419 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:22,419 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:04:22,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [525269276] [2023-11-26 12:04:22,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:22,420 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:22,421 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:22,421 INFO L85 PathProgramCache]: Analyzing trace with hash 356628037, now seen corresponding path program 1 times [2023-11-26 12:04:22,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:22,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455878385] [2023-11-26 12:04:22,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:22,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:22,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:22,433 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:22,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:22,473 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:23,017 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 12:04:23,018 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 12:04:23,018 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 12:04:23,018 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 12:04:23,018 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-26 12:04:23,018 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:23,018 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 12:04:23,018 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 12:04:23,019 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2023-11-26 12:04:23,019 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 12:04:23,019 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 12:04:23,041 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,051 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,054 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,060 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,065 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,068 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,071 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,073 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,087 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,093 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,099 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,109 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,112 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,115 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,118 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,122 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,124 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,127 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,130 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,133 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,136 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,138 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,141 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,144 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,146 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,149 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,152 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,445 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 12:04:23,445 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-26 12:04:23,448 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:23,448 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:23,451 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:23,460 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-26 12:04:23,463 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:23,464 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:23,481 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 12:04:23,481 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 12:04:23,496 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:23,497 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:23,497 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:23,498 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:23,510 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:23,510 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:23,523 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-26 12:04:23,534 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 12:04:23,534 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=0} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 12:04:23,542 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:23,543 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:23,543 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:23,544 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:23,548 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-26 12:04:23,560 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:23,560 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:23,604 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:23,604 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:23,605 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:23,606 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:23,618 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-26 12:04:23,618 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:23,631 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-26 12:04:23,643 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-26 12:04:23,649 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:23,649 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 12:04:23,649 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 12:04:23,649 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 12:04:23,649 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 12:04:23,649 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-26 12:04:23,650 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:23,650 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 12:04:23,650 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 12:04:23,650 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2023-11-26 12:04:23,650 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 12:04:23,650 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 12:04:23,653 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,656 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,673 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,679 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,727 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,730 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,734 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,737 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,741 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,745 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,755 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,758 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,761 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,775 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,794 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:23,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:24,039 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 12:04:24,044 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-26 12:04:24,046 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:24,046 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:24,049 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:24,065 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-26 12:04:24,066 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:24,079 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:24,079 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:24,080 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:24,080 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:24,081 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:24,083 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:24,083 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:24,093 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 12:04:24,104 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:24,104 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:24,105 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:24,106 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:24,114 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:24,127 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-26 12:04:24,127 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:24,127 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:24,128 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:24,128 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:24,128 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:24,128 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:24,129 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:24,138 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 12:04:24,146 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:24,147 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:24,147 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:24,148 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:24,188 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:24,201 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-26 12:04:24,201 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:24,202 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:24,202 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:24,202 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:24,202 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:24,204 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:24,204 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:24,213 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 12:04:24,222 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:24,223 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:24,223 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:24,224 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:24,237 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:24,249 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-26 12:04:24,250 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:24,250 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:24,250 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:24,250 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:24,250 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:24,252 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:24,252 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:24,272 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-26 12:04:24,276 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-26 12:04:24,276 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-26 12:04:24,278 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:24,278 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:24,331 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:24,333 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-26 12:04:24,334 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-26 12:04:24,334 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-26 12:04:24,334 INFO L513 LassoAnalysis]: Proved termination. [2023-11-26 12:04:24,334 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~z_ev~0) = -1*~z_ev~0 + 1 Supporting invariants [] [2023-11-26 12:04:24,343 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:24,346 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-26 12:04:24,372 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:24,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:24,417 INFO L262 TraceCheckSpWp]: Trace formula consists of 179 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-26 12:04:24,421 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 12:04:24,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:24,518 INFO L262 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-26 12:04:24,522 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 12:04:24,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:24,680 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-26 12:04:24,682 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:24,782 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61. Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 274 states and 418 transitions. Complement of second has 5 states. [2023-11-26 12:04:24,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-26 12:04:24,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:24,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 179 transitions. [2023-11-26 12:04:24,787 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 179 transitions. Stem has 40 letters. Loop has 39 letters. [2023-11-26 12:04:24,790 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 12:04:24,790 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 179 transitions. Stem has 79 letters. Loop has 39 letters. [2023-11-26 12:04:24,791 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 12:04:24,791 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 179 transitions. Stem has 40 letters. Loop has 78 letters. [2023-11-26 12:04:24,794 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 12:04:24,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 274 states and 418 transitions. [2023-11-26 12:04:24,797 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2023-11-26 12:04:24,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 274 states to 274 states and 418 transitions. [2023-11-26 12:04:24,800 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2023-11-26 12:04:24,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2023-11-26 12:04:24,801 INFO L73 IsDeterministic]: Start isDeterministic. Operand 274 states and 418 transitions. [2023-11-26 12:04:24,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:24,801 INFO L218 hiAutomatonCegarLoop]: Abstraction has 274 states and 418 transitions. [2023-11-26 12:04:24,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states and 418 transitions. [2023-11-26 12:04:24,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 271. [2023-11-26 12:04:24,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5239852398523985) internal successors, (413), 270 states have internal predecessors, (413), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:24,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 413 transitions. [2023-11-26 12:04:24,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 413 transitions. [2023-11-26 12:04:24,809 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:24,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:04:24,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:04:24,810 INFO L87 Difference]: Start difference. First operand 271 states and 413 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:24,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:24,847 INFO L93 Difference]: Finished difference Result 271 states and 412 transitions. [2023-11-26 12:04:24,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 412 transitions. [2023-11-26 12:04:24,850 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2023-11-26 12:04:24,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 271 states and 412 transitions. [2023-11-26 12:04:24,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2023-11-26 12:04:24,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2023-11-26 12:04:24,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271 states and 412 transitions. [2023-11-26 12:04:24,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:24,854 INFO L218 hiAutomatonCegarLoop]: Abstraction has 271 states and 412 transitions. [2023-11-26 12:04:24,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states and 412 transitions. [2023-11-26 12:04:24,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 271. [2023-11-26 12:04:24,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5202952029520296) internal successors, (412), 270 states have internal predecessors, (412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:24,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 412 transitions. [2023-11-26 12:04:24,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 412 transitions. [2023-11-26 12:04:24,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-26 12:04:24,864 INFO L428 stractBuchiCegarLoop]: Abstraction has 271 states and 412 transitions. [2023-11-26 12:04:24,864 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 12:04:24,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 412 transitions. [2023-11-26 12:04:24,866 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2023-11-26 12:04:24,866 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:24,867 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:24,868 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:24,868 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:24,869 INFO L748 eck$LassoCheckResult]: Stem: 3280#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 3281#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 3316#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3367#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 3347#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 3348#L137-2 ~b0_req_up~0 := 0; 3399#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 3407#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 3282#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 3283#L152-2 ~b1_req_up~0 := 0; 3241#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 3242#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 3254#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 3255#L167-2 ~d0_req_up~0 := 0; 3275#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 3319#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 3320#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 3265#L182-2 ~d1_req_up~0 := 0; 3266#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 3353#L233-1 assume !(1 == ~z_req_up~0); 3355#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3247#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 3248#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3356#L321 assume !(0 == ~b0_ev~0); 3357#L321-2 assume !(0 == ~b1_ev~0); 3273#L326-1 assume !(0 == ~d0_ev~0); 3274#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 3220#L336-1 assume !(0 == ~z_ev~0); 3221#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3405#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3257#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3376#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3377#L390 assume !(0 != activate_threads_~tmp~1#1); 3384#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3335#L354 assume !(1 == ~b0_ev~0); 3312#L354-2 assume !(1 == ~b1_ev~0); 3313#L359-1 assume !(1 == ~d0_ev~0); 3314#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 3315#L369-1 assume !(1 == ~z_ev~0); 3321#L374-1 assume { :end_inline_reset_delta_events } true; 3390#L432-2 assume !false; 3293#L433 [2023-11-26 12:04:24,869 INFO L750 eck$LassoCheckResult]: Loop: 3293#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 3445#L295 assume !false; 3380#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3259#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 3261#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3476#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3475#L290 assume !(0 != eval_~tmp___0~0#1); 3382#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3378#L212-3 assume !(1 == ~b0_req_up~0); 3299#L212-5 assume !(1 == ~b1_req_up~0); 3309#L219-3 assume !(1 == ~d0_req_up~0); 3206#L226-3 assume !(1 == ~d1_req_up~0); 3207#L233-3 assume !(1 == ~z_req_up~0); 3243#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3244#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 3349#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 3350#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 3326#L331-3 assume !(0 == ~d1_ev~0); 3222#L336-3 assume !(0 == ~z_ev~0); 3223#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3410#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3457#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3456#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3216#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 3217#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3267#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 3284#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 3391#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 3374#L364-3 assume !(1 == ~d1_ev~0); 3370#L369-3 assume !(1 == ~z_ev~0); 3371#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3440#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 3464#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3463#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 3237#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3238#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3403#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 3360#L449 assume !(0 != start_simulation_~tmp~3#1); 3292#L432-2 assume !false; 3293#L433 [2023-11-26 12:04:24,870 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:24,870 INFO L85 PathProgramCache]: Analyzing trace with hash 750743388, now seen corresponding path program 1 times [2023-11-26 12:04:24,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:24,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1924757525] [2023-11-26 12:04:24,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:24,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:24,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:24,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:24,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:24,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1924757525] [2023-11-26 12:04:24,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1924757525] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:24,906 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:24,906 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:24,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235093555] [2023-11-26 12:04:24,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:24,907 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:24,907 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:24,908 INFO L85 PathProgramCache]: Analyzing trace with hash 1518804285, now seen corresponding path program 1 times [2023-11-26 12:04:24,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:24,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960475735] [2023-11-26 12:04:24,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:24,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:24,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:24,916 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:24,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:24,927 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:25,330 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 12:04:25,330 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 12:04:25,330 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 12:04:25,331 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 12:04:25,331 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-26 12:04:25,331 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:25,331 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 12:04:25,331 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 12:04:25,331 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2023-11-26 12:04:25,331 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 12:04:25,331 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 12:04:25,337 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,341 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,343 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,345 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,347 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,351 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,353 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,356 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,366 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,371 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,373 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,376 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,379 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,384 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,387 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,390 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,398 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,400 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,403 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,406 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,413 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,416 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,421 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,424 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,427 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,432 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:25,608 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2023-11-26 12:04:25,711 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 12:04:25,711 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-26 12:04:25,712 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:25,712 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:25,713 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:25,726 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:25,727 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:25,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-26 12:04:25,749 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 12:04:25,750 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 12:04:25,760 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:25,761 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:25,761 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:25,762 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:25,772 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:25,772 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:25,780 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-26 12:04:25,794 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 12:04:25,794 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret8#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret8#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 12:04:25,803 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:25,803 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:25,803 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:25,804 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:25,813 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:25,813 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:25,826 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-26 12:04:25,852 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 12:04:25,852 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet5#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet5#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 12:04:25,861 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:25,861 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:25,862 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:25,863 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:25,867 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:25,867 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:25,881 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-26 12:04:25,891 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 12:04:25,891 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 12:04:25,895 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:25,895 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:25,895 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:25,897 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:25,904 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-26 12:04:25,904 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:25,904 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:25,917 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 12:04:25,917 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 12:04:25,924 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:25,928 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:25,928 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:25,929 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:25,934 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:25,934 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:25,944 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-26 12:04:25,948 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 12:04:25,948 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp___0~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp___0~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 12:04:25,952 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:25,953 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:25,953 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:25,954 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:25,956 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-26 12:04:25,957 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:25,957 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:25,972 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-26 12:04:25,972 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~ret4#1=0} Honda state: {ULTIMATE.start_eval_#t~ret4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-26 12:04:25,976 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:25,976 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:25,976 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:25,978 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:25,986 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-26 12:04:25,986 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:25,989 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-26 12:04:26,002 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:26,003 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:26,003 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:26,004 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:26,005 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-26 12:04:26,008 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-26 12:04:26,008 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-26 12:04:26,044 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-26 12:04:26,048 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:26,049 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 12:04:26,049 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 12:04:26,049 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 12:04:26,049 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 12:04:26,049 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-26 12:04:26,049 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:26,049 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 12:04:26,049 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 12:04:26,049 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2023-11-26 12:04:26,049 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 12:04:26,049 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 12:04:26,052 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,058 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,062 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,064 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,067 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,071 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,081 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,084 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,087 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,092 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,096 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,099 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,102 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,104 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,110 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,112 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,114 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,117 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,120 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,122 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,125 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,130 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,132 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,135 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,138 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,142 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 12:04:26,395 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 12:04:26,396 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-26 12:04:26,396 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:26,396 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:26,397 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:26,402 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-26 12:04:26,403 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:26,415 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:26,416 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:26,416 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:26,416 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:26,416 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:26,417 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:26,417 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:26,426 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 12:04:26,436 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:26,436 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:26,437 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:26,438 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:26,448 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-26 12:04:26,449 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:26,465 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:26,465 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:26,465 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:26,465 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:26,465 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:26,466 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:26,466 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:26,475 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 12:04:26,485 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:26,485 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:26,485 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:26,486 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:26,493 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:26,506 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:26,506 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:26,507 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:26,507 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:26,507 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:26,508 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-26 12:04:26,508 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:26,509 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:26,518 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 12:04:26,526 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:26,527 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:26,527 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:26,528 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:26,532 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:26,545 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:26,545 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:26,545 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:26,545 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:26,545 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:26,546 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:26,546 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:26,548 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2023-11-26 12:04:26,555 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 12:04:26,559 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:26,559 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:26,559 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:26,560 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:26,565 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:26,580 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2023-11-26 12:04:26,581 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:26,581 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:26,581 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:26,581 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:26,581 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:26,582 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:26,582 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:26,600 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 12:04:26,609 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:26,609 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:26,609 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:26,610 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:26,614 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:26,627 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:26,627 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:26,627 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:26,627 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:26,627 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:26,628 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:26,628 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:26,629 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2023-11-26 12:04:26,644 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 12:04:26,652 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:26,653 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:26,653 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:26,654 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:26,657 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-26 12:04:26,658 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 12:04:26,670 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 12:04:26,671 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 12:04:26,671 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 12:04:26,671 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 12:04:26,671 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 12:04:26,672 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 12:04:26,672 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 12:04:26,681 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-26 12:04:26,684 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-26 12:04:26,684 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-26 12:04:26,685 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:04:26,685 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:04:26,686 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:04:26,691 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-26 12:04:26,691 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-26 12:04:26,691 INFO L513 LassoAnalysis]: Proved termination. [2023-11-26 12:04:26,691 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~b0_ev~0) = -1*~b0_ev~0 + 1 Supporting invariants [] [2023-11-26 12:04:26,695 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-26 12:04:26,698 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2023-11-26 12:04:26,699 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-26 12:04:26,713 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:26,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:26,749 INFO L262 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-26 12:04:26,751 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 12:04:26,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:26,824 INFO L262 TraceCheckSpWp]: Trace formula consists of 84 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-26 12:04:26,826 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 12:04:26,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:26,942 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-26 12:04:26,942 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 271 states and 412 transitions. cyclomatic complexity: 144 Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:26,991 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 271 states and 412 transitions. cyclomatic complexity: 144. Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 734 states and 1136 transitions. Complement of second has 5 states. [2023-11-26 12:04:26,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-26 12:04:26,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:26,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2023-11-26 12:04:26,994 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 39 letters. [2023-11-26 12:04:26,994 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 12:04:26,995 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 80 letters. Loop has 39 letters. [2023-11-26 12:04:26,995 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 12:04:26,995 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 78 letters. [2023-11-26 12:04:26,996 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 12:04:26,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 734 states and 1136 transitions. [2023-11-26 12:04:27,006 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 296 [2023-11-26 12:04:27,013 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 734 states to 734 states and 1136 transitions. [2023-11-26 12:04:27,013 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 346 [2023-11-26 12:04:27,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 351 [2023-11-26 12:04:27,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 734 states and 1136 transitions. [2023-11-26 12:04:27,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:27,015 INFO L218 hiAutomatonCegarLoop]: Abstraction has 734 states and 1136 transitions. [2023-11-26 12:04:27,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 734 states and 1136 transitions. [2023-11-26 12:04:27,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 734 to 729. [2023-11-26 12:04:27,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 729 states have (on average 1.5459533607681757) internal successors, (1127), 728 states have internal predecessors, (1127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1127 transitions. [2023-11-26 12:04:27,040 INFO L240 hiAutomatonCegarLoop]: Abstraction has 729 states and 1127 transitions. [2023-11-26 12:04:27,040 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:27,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:27,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:27,041 INFO L87 Difference]: Start difference. First operand 729 states and 1127 transitions. Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:27,071 INFO L93 Difference]: Finished difference Result 789 states and 1209 transitions. [2023-11-26 12:04:27,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 789 states and 1209 transitions. [2023-11-26 12:04:27,079 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 336 [2023-11-26 12:04:27,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 789 states to 789 states and 1209 transitions. [2023-11-26 12:04:27,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 386 [2023-11-26 12:04:27,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 386 [2023-11-26 12:04:27,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 789 states and 1209 transitions. [2023-11-26 12:04:27,088 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:27,088 INFO L218 hiAutomatonCegarLoop]: Abstraction has 789 states and 1209 transitions. [2023-11-26 12:04:27,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 789 states and 1209 transitions. [2023-11-26 12:04:27,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 789 to 789. [2023-11-26 12:04:27,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 789 states, 789 states have (on average 1.532319391634981) internal successors, (1209), 788 states have internal predecessors, (1209), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 789 states to 789 states and 1209 transitions. [2023-11-26 12:04:27,109 INFO L240 hiAutomatonCegarLoop]: Abstraction has 789 states and 1209 transitions. [2023-11-26 12:04:27,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:27,110 INFO L428 stractBuchiCegarLoop]: Abstraction has 789 states and 1209 transitions. [2023-11-26 12:04:27,110 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 12:04:27,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 789 states and 1209 transitions. [2023-11-26 12:04:27,115 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 336 [2023-11-26 12:04:27,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:27,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:27,119 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:27,119 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:27,120 INFO L748 eck$LassoCheckResult]: Stem: 6063#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 6064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 6101#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6155#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 6135#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 6136#L137-2 ~b0_req_up~0 := 0; 6196#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 6208#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 6065#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 6066#L152-2 ~b1_req_up~0 := 0; 6023#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 6024#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 6035#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 6036#L167-2 ~d0_req_up~0 := 0; 6058#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 6102#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 6103#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 6042#L182-2 ~d1_req_up~0 := 0; 6043#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 6141#L233-1 assume !(1 == ~z_req_up~0); 6143#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6025#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 6026#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6144#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 6145#L321-2 assume !(0 == ~b1_ev~0); 6052#L326-1 assume !(0 == ~d0_ev~0); 6053#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 5999#L336-1 assume !(0 == ~z_ev~0); 6000#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 6204#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 6040#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 6163#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 6164#L390 assume !(0 != activate_threads_~tmp~1#1); 6176#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6122#L354 assume !(1 == ~b0_ev~0); 6093#L354-2 assume !(1 == ~b1_ev~0); 6094#L359-1 assume !(1 == ~d0_ev~0); 6099#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 6100#L369-1 assume !(1 == ~z_ev~0); 6107#L374-1 assume { :end_inline_reset_delta_events } true; 6181#L432-2 assume !false; 6461#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 6515#L295 [2023-11-26 12:04:27,120 INFO L750 eck$LassoCheckResult]: Loop: 6515#L295 assume !false; 6511#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 6506#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 6502#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 6501#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6499#L290 assume 0 != eval_~tmp___0~0#1; 6500#L290-1 assume !(0 == ~comp_m1_st~0); 6515#L295 [2023-11-26 12:04:27,120 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:27,121 INFO L85 PathProgramCache]: Analyzing trace with hash -807814810, now seen corresponding path program 1 times [2023-11-26 12:04:27,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:27,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225848608] [2023-11-26 12:04:27,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:27,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:27,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:27,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:27,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:27,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225848608] [2023-11-26 12:04:27,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1225848608] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:27,186 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:27,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:27,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704645763] [2023-11-26 12:04:27,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:27,187 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:27,187 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:27,187 INFO L85 PathProgramCache]: Analyzing trace with hash 831114558, now seen corresponding path program 1 times [2023-11-26 12:04:27,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:27,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1243067324] [2023-11-26 12:04:27,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:27,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:27,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:27,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:27,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:27,221 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1243067324] [2023-11-26 12:04:27,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1243067324] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:27,222 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:27,222 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:04:27,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794569774] [2023-11-26 12:04:27,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:27,222 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:04:27,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:27,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 12:04:27,223 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 12:04:27,223 INFO L87 Difference]: Start difference. First operand 789 states and 1209 transitions. cyclomatic complexity: 429 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:27,288 INFO L93 Difference]: Finished difference Result 879 states and 1299 transitions. [2023-11-26 12:04:27,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 879 states and 1299 transitions. [2023-11-26 12:04:27,344 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 376 [2023-11-26 12:04:27,352 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 879 states to 879 states and 1299 transitions. [2023-11-26 12:04:27,352 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 426 [2023-11-26 12:04:27,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 426 [2023-11-26 12:04:27,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 879 states and 1299 transitions. [2023-11-26 12:04:27,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:27,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 879 states and 1299 transitions. [2023-11-26 12:04:27,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 879 states and 1299 transitions. [2023-11-26 12:04:27,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 879 to 789. [2023-11-26 12:04:27,367 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2023-11-26 12:04:27,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 789 states, 789 states have (on average 1.520912547528517) internal successors, (1200), 788 states have internal predecessors, (1200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 789 states to 789 states and 1200 transitions. [2023-11-26 12:04:27,373 INFO L240 hiAutomatonCegarLoop]: Abstraction has 789 states and 1200 transitions. [2023-11-26 12:04:27,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-26 12:04:27,374 INFO L428 stractBuchiCegarLoop]: Abstraction has 789 states and 1200 transitions. [2023-11-26 12:04:27,375 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 12:04:27,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 789 states and 1200 transitions. [2023-11-26 12:04:27,380 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 336 [2023-11-26 12:04:27,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:27,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:27,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:27,381 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:27,381 INFO L748 eck$LassoCheckResult]: Stem: 7745#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 7746#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 7781#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7836#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 7813#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 7814#L137-2 ~b0_req_up~0 := 0; 7875#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 7888#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 7747#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 7748#L152-2 ~b1_req_up~0 := 0; 7706#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 7707#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 7716#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 7717#L167-2 ~d0_req_up~0 := 0; 7740#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 7782#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 7783#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 7724#L182-2 ~d1_req_up~0 := 0; 7725#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 7819#L233-1 assume !(1 == ~z_req_up~0); 7821#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7708#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 7709#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7822#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 7823#L321-2 assume !(0 == ~b1_ev~0); 7734#L326-1 assume !(0 == ~d0_ev~0); 7735#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 7680#L336-1 assume !(0 == ~z_ev~0); 7681#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 7885#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 7722#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 7844#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 7845#L390 assume !(0 != activate_threads_~tmp~1#1); 7857#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7800#L354 assume !(1 == ~b0_ev~0); 7773#L354-2 assume !(1 == ~b1_ev~0); 7774#L359-1 assume !(1 == ~d0_ev~0); 7779#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 7780#L369-1 assume !(1 == ~z_ev~0); 7787#L374-1 assume { :end_inline_reset_delta_events } true; 7861#L432-2 assume !false; 8376#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 8207#L295 [2023-11-26 12:04:27,382 INFO L750 eck$LassoCheckResult]: Loop: 8207#L295 assume !false; 8171#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 8167#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 8168#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 8283#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8264#L290 assume 0 != eval_~tmp___0~0#1; 8240#L290-1 assume !(0 == ~comp_m1_st~0); 8207#L295 [2023-11-26 12:04:27,382 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:27,382 INFO L85 PathProgramCache]: Analyzing trace with hash -807814810, now seen corresponding path program 2 times [2023-11-26 12:04:27,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:27,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895793595] [2023-11-26 12:04:27,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:27,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:27,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:27,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:27,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:27,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895793595] [2023-11-26 12:04:27,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895793595] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:27,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:27,413 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:27,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844598044] [2023-11-26 12:04:27,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:27,413 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:27,413 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:27,414 INFO L85 PathProgramCache]: Analyzing trace with hash 829267516, now seen corresponding path program 1 times [2023-11-26 12:04:27,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:27,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677168805] [2023-11-26 12:04:27,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:27,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:27,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:27,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:27,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:27,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [677168805] [2023-11-26 12:04:27,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [677168805] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:27,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:27,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:04:27,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408243427] [2023-11-26 12:04:27,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:27,441 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:04:27,441 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:27,441 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:27,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:27,441 INFO L87 Difference]: Start difference. First operand 789 states and 1200 transitions. cyclomatic complexity: 420 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:27,470 INFO L93 Difference]: Finished difference Result 991 states and 1470 transitions. [2023-11-26 12:04:27,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 991 states and 1470 transitions. [2023-11-26 12:04:27,479 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 412 [2023-11-26 12:04:27,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 991 states to 991 states and 1470 transitions. [2023-11-26 12:04:27,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 486 [2023-11-26 12:04:27,491 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 486 [2023-11-26 12:04:27,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 991 states and 1470 transitions. [2023-11-26 12:04:27,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:27,492 INFO L218 hiAutomatonCegarLoop]: Abstraction has 991 states and 1470 transitions. [2023-11-26 12:04:27,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states and 1470 transitions. [2023-11-26 12:04:27,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 991. [2023-11-26 12:04:27,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 991 states, 991 states have (on average 1.4833501513622604) internal successors, (1470), 990 states have internal predecessors, (1470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 991 states to 991 states and 1470 transitions. [2023-11-26 12:04:27,517 INFO L240 hiAutomatonCegarLoop]: Abstraction has 991 states and 1470 transitions. [2023-11-26 12:04:27,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:27,518 INFO L428 stractBuchiCegarLoop]: Abstraction has 991 states and 1470 transitions. [2023-11-26 12:04:27,519 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 12:04:27,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 991 states and 1470 transitions. [2023-11-26 12:04:27,525 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 412 [2023-11-26 12:04:27,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:27,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:27,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:27,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:27,526 INFO L748 eck$LassoCheckResult]: Stem: 9534#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 9535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 9574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9640#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 9614#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 9615#L137-2 ~b0_req_up~0 := 0; 9701#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 9719#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 9536#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 9537#L152-2 ~b1_req_up~0 := 0; 9494#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 9495#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 9505#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 9506#L167-2 ~d0_req_up~0 := 0; 9527#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 9575#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 9576#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 9513#L182-2 ~d1_req_up~0 := 0; 9514#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 9620#L233-1 assume !(1 == ~z_req_up~0); 9622#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9496#L255 assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0; 9497#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9623#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 9624#L321-2 assume !(0 == ~b1_ev~0); 9521#L326-1 assume !(0 == ~d0_ev~0); 9522#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 9467#L336-1 assume !(0 == ~z_ev~0); 9468#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 9711#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 9511#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 9649#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 9650#L390 assume !(0 != activate_threads_~tmp~1#1); 9672#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9704#L354 assume !(1 == ~b0_ev~0); 9566#L354-2 assume !(1 == ~b1_ev~0); 9567#L359-1 assume !(1 == ~d0_ev~0); 9572#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 9573#L369-1 assume !(1 == ~z_ev~0); 9680#L374-1 assume { :end_inline_reset_delta_events } true; 9681#L432-2 assume !false; 9915#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 9625#L295 [2023-11-26 12:04:27,532 INFO L750 eck$LassoCheckResult]: Loop: 9625#L295 assume !false; 10425#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 10418#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 10416#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 10415#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10414#L290 assume 0 != eval_~tmp___0~0#1; 10413#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10411#L299 assume !(0 != eval_~tmp~0#1); 9625#L295 [2023-11-26 12:04:27,533 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:27,533 INFO L85 PathProgramCache]: Analyzing trace with hash -1230516636, now seen corresponding path program 1 times [2023-11-26 12:04:27,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:27,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795603376] [2023-11-26 12:04:27,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:27,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:27,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:27,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:27,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:27,592 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1795603376] [2023-11-26 12:04:27,592 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1795603376] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:27,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:27,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:04:27,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1733863416] [2023-11-26 12:04:27,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:27,596 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:27,596 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:27,596 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 1 times [2023-11-26 12:04:27,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:27,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502200901] [2023-11-26 12:04:27,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:27,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:27,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:27,602 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:27,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:27,607 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:27,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:27,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:04:27,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:04:27,644 INFO L87 Difference]: Start difference. First operand 991 states and 1470 transitions. cyclomatic complexity: 488 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:27,674 INFO L93 Difference]: Finished difference Result 977 states and 1446 transitions. [2023-11-26 12:04:27,674 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 977 states and 1446 transitions. [2023-11-26 12:04:27,684 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 412 [2023-11-26 12:04:27,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 977 states to 977 states and 1446 transitions. [2023-11-26 12:04:27,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 472 [2023-11-26 12:04:27,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 472 [2023-11-26 12:04:27,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 977 states and 1446 transitions. [2023-11-26 12:04:27,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:27,694 INFO L218 hiAutomatonCegarLoop]: Abstraction has 977 states and 1446 transitions. [2023-11-26 12:04:27,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 977 states and 1446 transitions. [2023-11-26 12:04:27,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 977 to 977. [2023-11-26 12:04:27,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 977 states, 977 states have (on average 1.480040941658137) internal successors, (1446), 976 states have internal predecessors, (1446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 977 states to 977 states and 1446 transitions. [2023-11-26 12:04:27,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 977 states and 1446 transitions. [2023-11-26 12:04:27,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:04:27,719 INFO L428 stractBuchiCegarLoop]: Abstraction has 977 states and 1446 transitions. [2023-11-26 12:04:27,719 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 12:04:27,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 977 states and 1446 transitions. [2023-11-26 12:04:27,725 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 412 [2023-11-26 12:04:27,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:27,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:27,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:27,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:27,729 INFO L748 eck$LassoCheckResult]: Stem: 11510#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 11511#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 11548#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11610#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 11585#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 11586#L137-2 ~b0_req_up~0 := 0; 11655#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 11669#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 11512#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 11513#L152-2 ~b1_req_up~0 := 0; 11471#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 11472#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 11482#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 11483#L167-2 ~d0_req_up~0 := 0; 11505#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 11549#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 11550#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 11491#L182-2 ~d1_req_up~0 := 0; 11492#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 11591#L233-1 assume !(1 == ~z_req_up~0); 11593#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11473#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 11474#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11594#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 11595#L321-2 assume !(0 == ~b1_ev~0); 11499#L326-1 assume !(0 == ~d0_ev~0); 11500#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 11444#L336-1 assume !(0 == ~z_ev~0); 11445#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 11663#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 11489#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 11616#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 11617#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 11630#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11659#L354 assume !(1 == ~b0_ev~0); 11540#L354-2 assume !(1 == ~b1_ev~0); 11541#L359-1 assume !(1 == ~d0_ev~0); 11546#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 11547#L369-1 assume !(1 == ~z_ev~0); 11636#L374-1 assume { :end_inline_reset_delta_events } true; 11637#L432-2 assume !false; 11857#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 11858#L295 [2023-11-26 12:04:27,729 INFO L750 eck$LassoCheckResult]: Loop: 11858#L295 assume !false; 12305#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 12301#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 12213#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 12292#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12282#L290 assume 0 != eval_~tmp___0~0#1; 12278#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 12272#L299 assume !(0 != eval_~tmp~0#1); 11858#L295 [2023-11-26 12:04:27,729 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:27,730 INFO L85 PathProgramCache]: Analyzing trace with hash -414787800, now seen corresponding path program 1 times [2023-11-26 12:04:27,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:27,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079737555] [2023-11-26 12:04:27,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:27,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:27,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:27,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:27,760 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:27,760 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079737555] [2023-11-26 12:04:27,760 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079737555] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:27,761 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:27,761 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:27,761 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [826292295] [2023-11-26 12:04:27,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:27,764 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:27,765 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:27,765 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 2 times [2023-11-26 12:04:27,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:27,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201980795] [2023-11-26 12:04:27,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:27,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:27,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:27,770 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:27,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:27,781 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:27,815 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:27,816 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:27,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:27,816 INFO L87 Difference]: Start difference. First operand 977 states and 1446 transitions. cyclomatic complexity: 478 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:27,861 INFO L93 Difference]: Finished difference Result 1181 states and 1726 transitions. [2023-11-26 12:04:27,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1181 states and 1726 transitions. [2023-11-26 12:04:27,871 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 512 [2023-11-26 12:04:27,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1181 states to 1181 states and 1726 transitions. [2023-11-26 12:04:27,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 572 [2023-11-26 12:04:27,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 572 [2023-11-26 12:04:27,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1181 states and 1726 transitions. [2023-11-26 12:04:27,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:27,883 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1181 states and 1726 transitions. [2023-11-26 12:04:27,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1181 states and 1726 transitions. [2023-11-26 12:04:27,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1181 to 1181. [2023-11-26 12:04:27,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1181 states, 1181 states have (on average 1.4614733276883998) internal successors, (1726), 1180 states have internal predecessors, (1726), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:27,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1181 states to 1181 states and 1726 transitions. [2023-11-26 12:04:27,912 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1181 states and 1726 transitions. [2023-11-26 12:04:27,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:27,913 INFO L428 stractBuchiCegarLoop]: Abstraction has 1181 states and 1726 transitions. [2023-11-26 12:04:27,913 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 12:04:27,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1181 states and 1726 transitions. [2023-11-26 12:04:27,920 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 512 [2023-11-26 12:04:27,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:27,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:27,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:27,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:27,922 INFO L748 eck$LassoCheckResult]: Stem: 13676#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 13677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 13718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13774#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 13754#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 13755#L137-2 ~b0_req_up~0 := 0; 13830#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 13839#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 13678#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 13679#L152-2 ~b1_req_up~0 := 0; 13636#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 13637#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 13646#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 13647#L167-2 ~d0_req_up~0 := 0; 13671#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 13719#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 13720#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 13655#L182-2 ~d1_req_up~0 := 0; 13656#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 13760#L233-1 assume !(1 == ~z_req_up~0); 13762#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13638#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 13639#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13763#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 13764#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 13665#L326-1 assume !(0 == ~d0_ev~0); 13666#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 13608#L336-1 assume !(0 == ~z_ev~0); 13609#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 13837#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 13653#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 13784#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 13785#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 13800#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13833#L354 assume !(1 == ~b0_ev~0); 13710#L354-2 assume !(1 == ~b1_ev~0); 13711#L359-1 assume !(1 == ~d0_ev~0); 13716#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 13717#L369-1 assume !(1 == ~z_ev~0); 13806#L374-1 assume { :end_inline_reset_delta_events } true; 13807#L432-2 assume !false; 14059#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 14060#L295 [2023-11-26 12:04:27,922 INFO L750 eck$LassoCheckResult]: Loop: 14060#L295 assume !false; 14736#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 14735#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 14594#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 14734#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14733#L290 assume 0 != eval_~tmp___0~0#1; 14732#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 14731#L299 assume !(0 != eval_~tmp~0#1); 14060#L295 [2023-11-26 12:04:27,922 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:27,923 INFO L85 PathProgramCache]: Analyzing trace with hash 1579356906, now seen corresponding path program 1 times [2023-11-26 12:04:27,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:27,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495484143] [2023-11-26 12:04:27,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:27,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:27,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:27,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:27,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:27,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [495484143] [2023-11-26 12:04:27,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [495484143] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:27,952 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:27,952 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:27,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493990976] [2023-11-26 12:04:27,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:27,952 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:27,953 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:27,953 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 3 times [2023-11-26 12:04:27,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:27,953 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117387375] [2023-11-26 12:04:27,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:27,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:27,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:27,957 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:27,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:27,960 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:27,995 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:27,996 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:27,996 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:27,996 INFO L87 Difference]: Start difference. First operand 1181 states and 1726 transitions. cyclomatic complexity: 554 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:28,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:28,033 INFO L93 Difference]: Finished difference Result 1502 states and 2167 transitions. [2023-11-26 12:04:28,034 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1502 states and 2167 transitions. [2023-11-26 12:04:28,046 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 668 [2023-11-26 12:04:28,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1502 states to 1502 states and 2167 transitions. [2023-11-26 12:04:28,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 728 [2023-11-26 12:04:28,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 728 [2023-11-26 12:04:28,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1502 states and 2167 transitions. [2023-11-26 12:04:28,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:28,060 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1502 states and 2167 transitions. [2023-11-26 12:04:28,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1502 states and 2167 transitions. [2023-11-26 12:04:28,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1502 to 1502. [2023-11-26 12:04:28,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1502 states, 1502 states have (on average 1.4427430093209055) internal successors, (2167), 1501 states have internal predecessors, (2167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:28,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1502 states to 1502 states and 2167 transitions. [2023-11-26 12:04:28,094 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1502 states and 2167 transitions. [2023-11-26 12:04:28,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:28,095 INFO L428 stractBuchiCegarLoop]: Abstraction has 1502 states and 2167 transitions. [2023-11-26 12:04:28,095 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 12:04:28,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1502 states and 2167 transitions. [2023-11-26 12:04:28,103 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 668 [2023-11-26 12:04:28,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:28,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:28,124 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:28,124 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:28,125 INFO L748 eck$LassoCheckResult]: Stem: 16363#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 16364#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 16406#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16464#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 16443#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 16444#L137-2 ~b0_req_up~0 := 0; 16521#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 16534#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 16365#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 16366#L152-2 ~b1_req_up~0 := 0; 16324#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 16325#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 16335#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 16336#L167-2 ~d0_req_up~0 := 0; 16358#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 16407#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 16408#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 16344#L182-2 ~d1_req_up~0 := 0; 16345#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 16449#L233-1 assume !(1 == ~z_req_up~0); 16451#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16326#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 16327#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16452#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 16453#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 16352#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 16353#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 16297#L336-1 assume !(0 == ~z_ev~0); 16298#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 16532#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 16342#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 16474#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 16475#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 16490#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16525#L354 assume !(1 == ~b0_ev~0); 16398#L354-2 assume !(1 == ~b1_ev~0); 16399#L359-1 assume !(1 == ~d0_ev~0); 16404#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 16405#L369-1 assume !(1 == ~z_ev~0); 16496#L374-1 assume { :end_inline_reset_delta_events } true; 16497#L432-2 assume !false; 16660#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 16293#L295 [2023-11-26 12:04:28,125 INFO L750 eck$LassoCheckResult]: Loop: 16293#L295 assume !false; 16294#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 16346#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 16347#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 16316#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16317#L290 assume 0 != eval_~tmp___0~0#1; 16522#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 16523#L299 assume !(0 != eval_~tmp~0#1); 16293#L295 [2023-11-26 12:04:28,126 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:28,126 INFO L85 PathProgramCache]: Analyzing trace with hash -1127262488, now seen corresponding path program 1 times [2023-11-26 12:04:28,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:28,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246262948] [2023-11-26 12:04:28,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:28,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:28,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:28,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:28,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:28,169 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246262948] [2023-11-26 12:04:28,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246262948] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:28,169 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:28,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:28,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743851568] [2023-11-26 12:04:28,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:28,171 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:28,172 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:28,172 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 4 times [2023-11-26 12:04:28,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:28,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191714174] [2023-11-26 12:04:28,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:28,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:28,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,177 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:28,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,185 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:28,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:28,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:28,223 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:28,224 INFO L87 Difference]: Start difference. First operand 1502 states and 2167 transitions. cyclomatic complexity: 674 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:28,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:28,259 INFO L93 Difference]: Finished difference Result 1632 states and 2327 transitions. [2023-11-26 12:04:28,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1632 states and 2327 transitions. [2023-11-26 12:04:28,274 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 702 [2023-11-26 12:04:28,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1632 states to 1592 states and 2260 transitions. [2023-11-26 12:04:28,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 760 [2023-11-26 12:04:28,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 760 [2023-11-26 12:04:28,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1592 states and 2260 transitions. [2023-11-26 12:04:28,290 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:28,291 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1592 states and 2260 transitions. [2023-11-26 12:04:28,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1592 states and 2260 transitions. [2023-11-26 12:04:28,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1592 to 1592. [2023-11-26 12:04:28,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1592 states, 1592 states have (on average 1.4195979899497488) internal successors, (2260), 1591 states have internal predecessors, (2260), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:28,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1592 states to 1592 states and 2260 transitions. [2023-11-26 12:04:28,334 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1592 states and 2260 transitions. [2023-11-26 12:04:28,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:28,335 INFO L428 stractBuchiCegarLoop]: Abstraction has 1592 states and 2260 transitions. [2023-11-26 12:04:28,335 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 12:04:28,335 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1592 states and 2260 transitions. [2023-11-26 12:04:28,344 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 702 [2023-11-26 12:04:28,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:28,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:28,345 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:28,345 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:28,345 INFO L748 eck$LassoCheckResult]: Stem: 19499#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 19500#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 19536#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19594#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 19570#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 19571#L137-2 ~b0_req_up~0 := 0; 19643#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 19654#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 19501#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 19502#L152-2 ~b1_req_up~0 := 0; 19463#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 19464#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 19473#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 19474#L167-2 ~d0_req_up~0 := 0; 19494#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 19537#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 19538#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 19479#L182-2 ~d1_req_up~0 := 0; 19480#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 19576#L233-1 assume !(1 == ~z_req_up~0); 19578#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19465#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 19466#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19579#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 19580#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 19488#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 19489#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 19437#L336-1 assume !(0 == ~z_ev~0); 19438#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 19651#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 19639#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 19602#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 19603#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 19617#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19646#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 20578#L354-2 assume !(1 == ~b1_ev~0); 20577#L359-1 assume !(1 == ~d0_ev~0); 19534#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 19535#L369-1 assume !(1 == ~z_ev~0); 19621#L374-1 assume { :end_inline_reset_delta_events } true; 19622#L432-2 assume !false; 20667#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 20346#L295 [2023-11-26 12:04:28,345 INFO L750 eck$LassoCheckResult]: Loop: 20346#L295 assume !false; 20356#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 20355#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 19934#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 19935#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20350#L290 assume 0 != eval_~tmp___0~0#1; 20348#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 20345#L299 assume !(0 != eval_~tmp~0#1); 20346#L295 [2023-11-26 12:04:28,346 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:28,346 INFO L85 PathProgramCache]: Analyzing trace with hash -317915862, now seen corresponding path program 1 times [2023-11-26 12:04:28,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:28,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273227161] [2023-11-26 12:04:28,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:28,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:28,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:28,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:28,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:28,379 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1273227161] [2023-11-26 12:04:28,380 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1273227161] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:28,380 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:28,380 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:28,380 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927594684] [2023-11-26 12:04:28,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:28,381 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:28,381 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:28,381 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 5 times [2023-11-26 12:04:28,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:28,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013625384] [2023-11-26 12:04:28,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:28,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:28,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,386 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:28,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:28,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:28,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:28,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:28,426 INFO L87 Difference]: Start difference. First operand 1592 states and 2260 transitions. cyclomatic complexity: 677 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:28,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:28,458 INFO L93 Difference]: Finished difference Result 1827 states and 2578 transitions. [2023-11-26 12:04:28,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1827 states and 2578 transitions. [2023-11-26 12:04:28,471 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 792 [2023-11-26 12:04:28,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1827 states to 1827 states and 2578 transitions. [2023-11-26 12:04:28,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 852 [2023-11-26 12:04:28,487 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 852 [2023-11-26 12:04:28,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1827 states and 2578 transitions. [2023-11-26 12:04:28,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:28,488 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1827 states and 2578 transitions. [2023-11-26 12:04:28,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1827 states and 2578 transitions. [2023-11-26 12:04:28,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1827 to 1827. [2023-11-26 12:04:28,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1827 states, 1827 states have (on average 1.411056376573618) internal successors, (2578), 1826 states have internal predecessors, (2578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:28,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1827 states to 1827 states and 2578 transitions. [2023-11-26 12:04:28,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1827 states and 2578 transitions. [2023-11-26 12:04:28,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:28,535 INFO L428 stractBuchiCegarLoop]: Abstraction has 1827 states and 2578 transitions. [2023-11-26 12:04:28,535 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 12:04:28,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1827 states and 2578 transitions. [2023-11-26 12:04:28,542 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 792 [2023-11-26 12:04:28,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:28,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:28,543 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:28,543 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:28,544 INFO L748 eck$LassoCheckResult]: Stem: 22925#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 22926#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 22964#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23029#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 23004#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 23005#L137-2 ~b0_req_up~0 := 0; 23086#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 23098#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 22927#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 22928#L152-2 ~b1_req_up~0 := 0; 22890#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 22891#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 22900#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 22901#L167-2 ~d0_req_up~0 := 0; 22920#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 22965#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 22966#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 22905#L182-2 ~d1_req_up~0 := 0; 22906#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 23010#L233-1 assume !(1 == ~z_req_up~0); 23012#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22892#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 22893#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23013#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 23014#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 22914#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 22915#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 22862#L336-1 assume !(0 == ~z_ev~0); 22863#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 23093#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 23082#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 23038#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 23039#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 23055#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22989#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 22990#L354-2 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 23053#L359-1 assume !(1 == ~d0_ev~0); 23054#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 22971#L369-1 assume !(1 == ~z_ev~0); 22972#L374-1 assume { :end_inline_reset_delta_events } true; 23341#L432-2 assume !false; 23343#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 22858#L295 [2023-11-26 12:04:28,544 INFO L750 eck$LassoCheckResult]: Loop: 22858#L295 assume !false; 22859#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 22907#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 22908#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 23105#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23106#L290 assume 0 != eval_~tmp___0~0#1; 23383#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 23880#L299 assume !(0 != eval_~tmp~0#1); 22858#L295 [2023-11-26 12:04:28,544 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:28,544 INFO L85 PathProgramCache]: Analyzing trace with hash -2092923224, now seen corresponding path program 1 times [2023-11-26 12:04:28,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:28,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969563281] [2023-11-26 12:04:28,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:28,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:28,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:04:28,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:04:28,572 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:04:28,572 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969563281] [2023-11-26 12:04:28,572 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969563281] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:04:28,572 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:04:28,572 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:04:28,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351692370] [2023-11-26 12:04:28,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:04:28,573 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:04:28,573 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:28,574 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 6 times [2023-11-26 12:04:28,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:28,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188799285] [2023-11-26 12:04:28,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:28,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:28,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,577 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:28,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,581 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:28,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:04:28,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:04:28,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:04:28,618 INFO L87 Difference]: Start difference. First operand 1827 states and 2578 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:28,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:04:28,650 INFO L93 Difference]: Finished difference Result 2264 states and 3192 transitions. [2023-11-26 12:04:28,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2264 states and 3192 transitions. [2023-11-26 12:04:28,662 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 960 [2023-11-26 12:04:28,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2264 states to 2264 states and 3192 transitions. [2023-11-26 12:04:28,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1024 [2023-11-26 12:04:28,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1024 [2023-11-26 12:04:28,681 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2264 states and 3192 transitions. [2023-11-26 12:04:28,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-26 12:04:28,681 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2264 states and 3192 transitions. [2023-11-26 12:04:28,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2264 states and 3192 transitions. [2023-11-26 12:04:28,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2264 to 2264. [2023-11-26 12:04:28,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2264 states, 2264 states have (on average 1.4098939929328622) internal successors, (3192), 2263 states have internal predecessors, (3192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:04:28,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2264 states to 2264 states and 3192 transitions. [2023-11-26 12:04:28,732 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2264 states and 3192 transitions. [2023-11-26 12:04:28,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:04:28,732 INFO L428 stractBuchiCegarLoop]: Abstraction has 2264 states and 3192 transitions. [2023-11-26 12:04:28,733 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 12:04:28,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2264 states and 3192 transitions. [2023-11-26 12:04:28,741 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 960 [2023-11-26 12:04:28,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:04:28,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:04:28,742 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:28,742 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:04:28,743 INFO L748 eck$LassoCheckResult]: Stem: 27022#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 27023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 27058#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27120#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 27098#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 27099#L137-2 ~b0_req_up~0 := 0; 27175#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 27186#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 27024#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 27025#L152-2 ~b1_req_up~0 := 0; 26985#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 26986#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 26996#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 26997#L167-2 ~d0_req_up~0 := 0; 27017#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 27059#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 27060#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 27002#L182-2 ~d1_req_up~0 := 0; 27003#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 27104#L233-1 assume !(1 == ~z_req_up~0); 27106#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26987#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 26988#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27107#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 27108#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 27011#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 27012#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 26959#L336-1 assume !(0 == ~z_ev~0); 26960#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 27183#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 27171#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 27130#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 27131#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 27145#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27178#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 27050#L354-2 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 27051#L359-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 27056#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 27057#L369-1 assume !(1 == ~z_ev~0); 27152#L374-1 assume { :end_inline_reset_delta_events } true; 27153#L432-2 assume !false; 27330#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 26955#L295 [2023-11-26 12:04:28,743 INFO L750 eck$LassoCheckResult]: Loop: 26955#L295 assume !false; 26956#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 27004#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 27005#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 27195#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27192#L290 assume 0 != eval_~tmp___0~0#1; 27176#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 27044#L299 assume !(0 != eval_~tmp~0#1); 26955#L295 [2023-11-26 12:04:28,743 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:28,744 INFO L85 PathProgramCache]: Analyzing trace with hash 2144785770, now seen corresponding path program 1 times [2023-11-26 12:04:28,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:28,744 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [80978180] [2023-11-26 12:04:28,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:28,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:28,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,753 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:28,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,766 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:28,767 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:28,767 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 7 times [2023-11-26 12:04:28,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:28,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099874914] [2023-11-26 12:04:28,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:28,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:28,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,771 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:28,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,774 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:28,775 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:04:28,775 INFO L85 PathProgramCache]: Analyzing trace with hash 109674101, now seen corresponding path program 1 times [2023-11-26 12:04:28,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:04:28,775 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704128766] [2023-11-26 12:04:28,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:04:28,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:04:28,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,785 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:28,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:28,799 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:04:30,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:30,158 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:04:30,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:04:30,307 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.11 12:04:30 BoogieIcfgContainer [2023-11-26 12:04:30,307 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-26 12:04:30,308 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-26 12:04:30,308 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-26 12:04:30,308 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-26 12:04:30,309 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:04:19" (3/4) ... [2023-11-26 12:04:30,311 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-26 12:04:30,383 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/witness.graphml [2023-11-26 12:04:30,383 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-26 12:04:30,384 INFO L158 Benchmark]: Toolchain (without parser) took 11716.10ms. Allocated memory was 178.3MB in the beginning and 270.5MB in the end (delta: 92.3MB). Free memory was 136.1MB in the beginning and 79.3MB in the end (delta: 56.7MB). Peak memory consumption was 151.5MB. Max. memory is 16.1GB. [2023-11-26 12:04:30,384 INFO L158 Benchmark]: CDTParser took 0.29ms. Allocated memory is still 117.4MB. Free memory is still 67.1MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 12:04:30,384 INFO L158 Benchmark]: CACSL2BoogieTranslator took 361.63ms. Allocated memory is still 178.3MB. Free memory was 136.1MB in the beginning and 122.4MB in the end (delta: 13.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-26 12:04:30,385 INFO L158 Benchmark]: Boogie Procedure Inliner took 53.87ms. Allocated memory is still 178.3MB. Free memory was 122.4MB in the beginning and 120.3MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-26 12:04:30,385 INFO L158 Benchmark]: Boogie Preprocessor took 85.26ms. Allocated memory is still 178.3MB. Free memory was 119.8MB in the beginning and 117.2MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-26 12:04:30,386 INFO L158 Benchmark]: RCFGBuilder took 761.20ms. Allocated memory is still 178.3MB. Free memory was 117.2MB in the beginning and 95.7MB in the end (delta: 21.5MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2023-11-26 12:04:30,386 INFO L158 Benchmark]: BuchiAutomizer took 10372.50ms. Allocated memory was 178.3MB in the beginning and 270.5MB in the end (delta: 92.3MB). Free memory was 95.6MB in the beginning and 85.6MB in the end (delta: 10.0MB). Peak memory consumption was 105.4MB. Max. memory is 16.1GB. [2023-11-26 12:04:30,386 INFO L158 Benchmark]: Witness Printer took 75.33ms. Allocated memory is still 270.5MB. Free memory was 85.6MB in the beginning and 79.3MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-26 12:04:30,388 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29ms. Allocated memory is still 117.4MB. Free memory is still 67.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 361.63ms. Allocated memory is still 178.3MB. Free memory was 136.1MB in the beginning and 122.4MB in the end (delta: 13.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 53.87ms. Allocated memory is still 178.3MB. Free memory was 122.4MB in the beginning and 120.3MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 85.26ms. Allocated memory is still 178.3MB. Free memory was 119.8MB in the beginning and 117.2MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 761.20ms. Allocated memory is still 178.3MB. Free memory was 117.2MB in the beginning and 95.7MB in the end (delta: 21.5MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 10372.50ms. Allocated memory was 178.3MB in the beginning and 270.5MB in the end (delta: 92.3MB). Free memory was 95.6MB in the beginning and 85.6MB in the end (delta: 10.0MB). Peak memory consumption was 105.4MB. Max. memory is 16.1GB. * Witness Printer took 75.33ms. Allocated memory is still 270.5MB. Free memory was 85.6MB in the beginning and 79.3MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (18 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function ((-1 * z_ev) + 1) and consists of 3 locations. One deterministic module has affine ranking function ((-1 * b0_ev) + 1) and consists of 3 locations. 18 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2264 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 10.2s and 19 iterations. TraceHistogramMax:1. Analysis of lassos took 7.6s. Construction of modules took 0.3s. Büchi inclusion checks took 1.9s. Highest rank in rank-based complementation 3. Minimization of det autom 8. Minimization of nondet autom 12. Automata minimization 0.4s AutomataMinimizationTime, 20 MinimizatonAttempts, 129 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 910 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 908 mSDsluCounter, 7860 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4316 mSDsCounter, 50 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 277 IncrementalHoareTripleChecker+Invalid, 327 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 50 mSolverCounterUnsat, 3544 mSDtfsCounter, 277 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN6 SILU0 SILI10 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital77 mio100 ax100 hnf100 lsp12 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 47ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 9 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.4s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, __retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, tmp=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, kernel_st=0, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, __retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, tmp=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, kernel_st=0, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-26 12:04:30,497 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_da46d460-418a-4cb9-8a47-dbf31a8ca5c7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)