./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:52:49,901 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:52:49,993 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:52:49,999 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:52:50,000 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:52:50,036 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:52:50,037 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:52:50,037 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:52:50,038 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:52:50,043 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:52:50,044 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:52:50,044 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:52:50,045 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:52:50,047 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:52:50,047 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:52:50,048 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:52:50,048 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:52:50,049 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:52:50,050 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:52:50,050 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:52:50,050 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:52:50,051 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:52:50,051 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:52:50,052 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:52:50,052 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:52:50,053 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:52:50,053 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:52:50,054 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:52:50,054 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:52:50,054 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:52:50,056 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:52:50,056 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:52:50,056 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:52:50,057 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:52:50,057 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:52:50,057 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:52:50,058 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:52:50,058 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:52:50,058 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2023-11-26 11:52:50,404 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:52:50,433 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:52:50,436 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:52:50,438 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:52:50,438 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:52:50,440 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2023-11-26 11:52:53,698 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:52:54,067 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:52:54,068 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2023-11-26 11:52:54,086 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/data/99320d0f2/bda0012d514b4e499a26276018841ebb/FLAG250735919 [2023-11-26 11:52:54,103 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/data/99320d0f2/bda0012d514b4e499a26276018841ebb [2023-11-26 11:52:54,108 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:52:54,112 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:52:54,117 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:52:54,118 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:52:54,124 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:52:54,125 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,126 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2cec36ca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54, skipping insertion in model container [2023-11-26 11:52:54,126 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,184 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:52:54,430 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:52:54,444 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:52:54,485 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:52:54,503 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:52:54,503 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54 WrapperNode [2023-11-26 11:52:54,504 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:52:54,505 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:52:54,505 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:52:54,505 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:52:54,513 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,525 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,564 INFO L138 Inliner]: procedures = 29, calls = 32, calls flagged for inlining = 27, calls inlined = 29, statements flattened = 307 [2023-11-26 11:52:54,565 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:52:54,566 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:52:54,566 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:52:54,566 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:52:54,578 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,578 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,589 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,604 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 11:52:54,604 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,616 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,622 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,629 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,631 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,633 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,636 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:52:54,637 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:52:54,637 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:52:54,638 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:52:54,639 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (1/1) ... [2023-11-26 11:52:54,645 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:52:54,659 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:52:54,672 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:52:54,675 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:52:54,711 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:52:54,711 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:52:54,711 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:52:54,711 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:52:54,801 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:52:54,803 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:52:55,163 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:52:55,175 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:52:55,177 INFO L309 CfgBuilder]: Removed 4 assume(true) statements. [2023-11-26 11:52:55,179 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:52:55 BoogieIcfgContainer [2023-11-26 11:52:55,179 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:52:55,180 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:52:55,181 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:52:55,186 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:52:55,187 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:52:55,187 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:52:54" (1/3) ... [2023-11-26 11:52:55,189 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1b9e763c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:52:55, skipping insertion in model container [2023-11-26 11:52:55,189 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:52:55,191 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:52:54" (2/3) ... [2023-11-26 11:52:55,192 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1b9e763c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:52:55, skipping insertion in model container [2023-11-26 11:52:55,192 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:52:55,192 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:52:55" (3/3) ... [2023-11-26 11:52:55,194 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2023-11-26 11:52:55,281 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:52:55,281 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:52:55,282 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:52:55,282 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:52:55,282 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:52:55,282 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:52:55,282 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:52:55,282 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:52:55,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:55,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2023-11-26 11:52:55,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:55,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:55,338 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:55,338 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:55,339 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:52:55,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:55,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2023-11-26 11:52:55,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:55,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:55,349 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:55,349 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:55,359 INFO L748 eck$LassoCheckResult]: Stem: 19#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 31#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 101#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64#L222true assume !(1 == ~q_req_up~0); 9#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 32#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 39#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L275true assume !(0 == ~q_read_ev~0); 93#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 106#L65true assume !(1 == ~p_dw_pc~0); 30#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 56#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 74#is_do_write_p_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 36#L315true assume !(0 != activate_threads_~tmp~1#1); 62#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 96#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 68#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 21#is_do_read_c_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4#L323true assume !(0 != activate_threads_~tmp___0~1#1); 47#L323-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97#L293true assume !(1 == ~q_read_ev~0); 2#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 37#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2023-11-26 11:52:55,360 INFO L750 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 102#L364true assume !true; 65#eval_returnLabel#1true havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83#L222-3true assume !(1 == ~q_req_up~0); 33#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 41#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 54#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 61#L65-3true assume !(1 == ~p_dw_pc~0); 17#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 94#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 55#is_do_write_p_triggered_returnLabel#2true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 42#L315-3true assume !(0 != activate_threads_~tmp~1#1); 84#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 59#L84-3true assume 1 == ~c_dr_pc~0; 44#L85-1true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 78#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 29#is_do_read_c_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 104#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 77#L323-5true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 5#L293-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 53#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 75#exists_runnable_thread_returnLabel#2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 13#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 7#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2023-11-26 11:52:55,367 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:55,367 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2023-11-26 11:52:55,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:55,378 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904614708] [2023-11-26 11:52:55,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:55,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:55,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:55,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:55,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:55,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904614708] [2023-11-26 11:52:55,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904614708] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:55,589 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:55,589 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:52:55,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331342370] [2023-11-26 11:52:55,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:55,596 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:52:55,597 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:55,597 INFO L85 PathProgramCache]: Analyzing trace with hash -573197680, now seen corresponding path program 1 times [2023-11-26 11:52:55,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:55,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695717299] [2023-11-26 11:52:55,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:55,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:55,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:55,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:55,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:55,629 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [695717299] [2023-11-26 11:52:55,629 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [695717299] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:55,629 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:55,630 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:52:55,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [526665132] [2023-11-26 11:52:55,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:55,631 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:55,632 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:55,665 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:52:55,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:52:55,668 INFO L87 Difference]: Start difference. First operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:55,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:55,701 INFO L93 Difference]: Finished difference Result 101 states and 144 transitions. [2023-11-26 11:52:55,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 144 transitions. [2023-11-26 11:52:55,707 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2023-11-26 11:52:55,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 95 states and 138 transitions. [2023-11-26 11:52:55,715 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2023-11-26 11:52:55,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2023-11-26 11:52:55,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 138 transitions. [2023-11-26 11:52:55,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:55,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2023-11-26 11:52:55,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 138 transitions. [2023-11-26 11:52:55,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2023-11-26 11:52:55,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4526315789473685) internal successors, (138), 94 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:55,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 138 transitions. [2023-11-26 11:52:55,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2023-11-26 11:52:55,764 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:52:55,768 INFO L428 stractBuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2023-11-26 11:52:55,769 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:52:55,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 138 transitions. [2023-11-26 11:52:55,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2023-11-26 11:52:55,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:55,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:55,773 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:55,773 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:55,774 INFO L748 eck$LassoCheckResult]: Stem: 272#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 297#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 250#L222 assume !(1 == ~q_req_up~0); 239#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 240#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 280#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 301#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 299#L275 assume !(0 == ~q_read_ev~0); 300#L275-2 assume !(0 == ~q_write_ev~0); 286#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 287#L65 assume !(1 == ~p_dw_pc~0); 283#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 282#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 267#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 268#L315 assume !(0 != activate_threads_~tmp~1#1); 245#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 246#L84 assume 1 == ~c_dr_pc~0; 292#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 259#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 260#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 222#L323 assume !(0 != activate_threads_~tmp___0~1#1); 223#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 308#L293 assume !(1 == ~q_read_ev~0); 215#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 216#L298-1 assume { :end_inline_reset_delta_events } true; 241#L419-2 [2023-11-26 11:52:55,774 INFO L750 eck$LassoCheckResult]: Loop: 241#L419-2 assume !false; 242#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 256#L364 assume !false; 288#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 252#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 218#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 237#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 238#L344 assume !(0 != eval_~tmp___1~0#1); 253#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 254#L222-3 assume !(1 == ~q_req_up~0); 285#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 278#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 279#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 306#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 228#L65-3 assume !(1 == ~p_dw_pc~0); 229#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 263#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 305#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 307#L315-3 assume !(0 != activate_threads_~tmp~1#1); 295#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 219#L84-3 assume 1 == ~c_dr_pc~0; 220#L85-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 276#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 277#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 294#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 274#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 275#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 226#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 227#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 289#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 290#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 269#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 247#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 233#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 234#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 293#L436 assume !(0 != start_simulation_~tmp~4#1); 241#L419-2 [2023-11-26 11:52:55,775 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:55,775 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2023-11-26 11:52:55,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:55,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54645214] [2023-11-26 11:52:55,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:55,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:55,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:55,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:55,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:55,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54645214] [2023-11-26 11:52:55,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54645214] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:55,926 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:55,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 11:52:55,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254714840] [2023-11-26 11:52:55,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:55,927 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:52:55,927 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:55,927 INFO L85 PathProgramCache]: Analyzing trace with hash -1808359021, now seen corresponding path program 1 times [2023-11-26 11:52:55,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:55,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916509102] [2023-11-26 11:52:55,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:55,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:55,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:56,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:56,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:56,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916509102] [2023-11-26 11:52:56,093 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1916509102] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:56,093 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:56,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:52:56,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1002469123] [2023-11-26 11:52:56,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:56,094 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:56,094 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:56,095 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:52:56,095 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:52:56,096 INFO L87 Difference]: Start difference. First operand 95 states and 138 transitions. cyclomatic complexity: 44 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:56,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:56,195 INFO L93 Difference]: Finished difference Result 211 states and 299 transitions. [2023-11-26 11:52:56,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211 states and 299 transitions. [2023-11-26 11:52:56,200 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 177 [2023-11-26 11:52:56,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211 states to 211 states and 299 transitions. [2023-11-26 11:52:56,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 211 [2023-11-26 11:52:56,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 211 [2023-11-26 11:52:56,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 211 states and 299 transitions. [2023-11-26 11:52:56,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:56,206 INFO L218 hiAutomatonCegarLoop]: Abstraction has 211 states and 299 transitions. [2023-11-26 11:52:56,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states and 299 transitions. [2023-11-26 11:52:56,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 196. [2023-11-26 11:52:56,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.4285714285714286) internal successors, (280), 195 states have internal predecessors, (280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:56,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 280 transitions. [2023-11-26 11:52:56,223 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196 states and 280 transitions. [2023-11-26 11:52:56,223 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:52:56,224 INFO L428 stractBuchiCegarLoop]: Abstraction has 196 states and 280 transitions. [2023-11-26 11:52:56,225 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:52:56,225 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 280 transitions. [2023-11-26 11:52:56,228 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 164 [2023-11-26 11:52:56,228 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:56,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:56,229 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:56,230 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:56,230 INFO L748 eck$LassoCheckResult]: Stem: 589#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 590#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 614#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 567#L222 assume !(1 == ~q_req_up~0); 554#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 555#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 600#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 619#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 617#L275 assume !(0 == ~q_read_ev~0); 618#L275-2 assume !(0 == ~q_write_ev~0); 603#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 604#L65 assume !(1 == ~p_dw_pc~0); 611#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 612#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 587#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 588#L315 assume !(0 != activate_threads_~tmp~1#1); 562#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 563#L84 assume !(1 == ~c_dr_pc~0); 582#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 577#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 578#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 540#L323 assume !(0 != activate_threads_~tmp___0~1#1); 541#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 627#L293 assume !(1 == ~q_read_ev~0); 534#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 535#L298-1 assume { :end_inline_reset_delta_events } true; 558#L419-2 [2023-11-26 11:52:56,230 INFO L750 eck$LassoCheckResult]: Loop: 558#L419-2 assume !false; 559#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 573#L364 assume !false; 605#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 569#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 537#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 556#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 557#L344 assume !(0 != eval_~tmp___1~0#1); 570#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 571#L222-3 assume !(1 == ~q_req_up~0); 602#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 598#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 599#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 625#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 546#L65-3 assume !(1 == ~p_dw_pc~0); 547#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 581#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 624#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 626#L315-3 assume !(0 != activate_threads_~tmp~1#1); 613#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 538#L84-3 assume !(1 == ~c_dr_pc~0); 539#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 596#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 597#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 610#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 594#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 595#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 623#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 635#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 636#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 719#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 718#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 564#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 548#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 549#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 609#L436 assume !(0 != start_simulation_~tmp~4#1); 558#L419-2 [2023-11-26 11:52:56,231 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:56,231 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2023-11-26 11:52:56,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:56,232 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480015605] [2023-11-26 11:52:56,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:56,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:56,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:56,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:56,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:56,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480015605] [2023-11-26 11:52:56,392 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [480015605] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:56,392 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:56,393 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 11:52:56,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395659187] [2023-11-26 11:52:56,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:56,394 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:52:56,394 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:56,395 INFO L85 PathProgramCache]: Analyzing trace with hash -631754702, now seen corresponding path program 1 times [2023-11-26 11:52:56,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:56,395 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220219221] [2023-11-26 11:52:56,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:56,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:56,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:56,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:56,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:56,476 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220219221] [2023-11-26 11:52:56,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [220219221] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:56,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:56,477 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:52:56,477 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [844917168] [2023-11-26 11:52:56,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:56,478 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:56,478 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:56,478 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:52:56,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:52:56,479 INFO L87 Difference]: Start difference. First operand 196 states and 280 transitions. cyclomatic complexity: 86 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:56,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:56,594 INFO L93 Difference]: Finished difference Result 449 states and 621 transitions. [2023-11-26 11:52:56,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 621 transitions. [2023-11-26 11:52:56,602 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 375 [2023-11-26 11:52:56,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 621 transitions. [2023-11-26 11:52:56,612 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2023-11-26 11:52:56,613 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2023-11-26 11:52:56,614 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 621 transitions. [2023-11-26 11:52:56,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:56,621 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 621 transitions. [2023-11-26 11:52:56,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 621 transitions. [2023-11-26 11:52:56,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2023-11-26 11:52:56,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.3830734966592428) internal successors, (621), 448 states have internal predecessors, (621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:56,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 621 transitions. [2023-11-26 11:52:56,670 INFO L240 hiAutomatonCegarLoop]: Abstraction has 449 states and 621 transitions. [2023-11-26 11:52:56,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:52:56,678 INFO L428 stractBuchiCegarLoop]: Abstraction has 449 states and 621 transitions. [2023-11-26 11:52:56,678 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:52:56,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 621 transitions. [2023-11-26 11:52:56,683 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 375 [2023-11-26 11:52:56,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:56,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:56,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:56,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:56,689 INFO L748 eck$LassoCheckResult]: Stem: 1254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1283#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1227#L222 assume !(1 == ~q_req_up~0); 1229#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1266#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1267#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1295#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1296#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1287#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1299#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1344#L65 assume !(1 == ~p_dw_pc~0); 1343#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1342#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1341#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1340#L315 assume !(0 != activate_threads_~tmp~1#1); 1339#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1338#L84 assume !(1 == ~c_dr_pc~0); 1337#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1336#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1335#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1334#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1333#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1332#L293 assume !(1 == ~q_read_ev~0); 1331#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1193#L298-1 assume { :end_inline_reset_delta_events } true; 1219#L419-2 [2023-11-26 11:52:56,694 INFO L750 eck$LassoCheckResult]: Loop: 1219#L419-2 assume !false; 1220#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1382#L364 assume !false; 1377#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1230#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1197#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1215#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1216#L344 assume !(0 != eval_~tmp___1~0#1); 1257#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1552#L222-3 assume !(1 == ~q_req_up~0); 1549#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1548#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1543#L275-5 assume !(0 == ~q_write_ev~0); 1541#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1539#L65-3 assume !(1 == ~p_dw_pc~0); 1537#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 1535#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1533#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1531#L315-3 assume !(0 != activate_threads_~tmp~1#1); 1529#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1527#L84-3 assume !(1 == ~c_dr_pc~0); 1525#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 1523#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1521#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1519#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1518#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1517#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1516#L293-5 assume !(1 == ~q_write_ev~0); 1514#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1438#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1421#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1398#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1395#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1392#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1317#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1278#L436 assume !(0 != start_simulation_~tmp~4#1); 1219#L419-2 [2023-11-26 11:52:56,695 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:56,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2023-11-26 11:52:56,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:56,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610872934] [2023-11-26 11:52:56,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:56,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:56,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:56,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:56,787 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:56,788 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1610872934] [2023-11-26 11:52:56,788 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1610872934] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:56,788 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:56,788 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:52:56,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1807911538] [2023-11-26 11:52:56,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:56,794 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:52:56,796 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:56,796 INFO L85 PathProgramCache]: Analyzing trace with hash -85709838, now seen corresponding path program 1 times [2023-11-26 11:52:56,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:56,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101919713] [2023-11-26 11:52:56,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:56,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:56,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:56,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:56,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:56,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101919713] [2023-11-26 11:52:56,884 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101919713] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:56,884 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:56,884 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:52:56,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [581497558] [2023-11-26 11:52:56,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:56,885 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:56,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:56,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:52:56,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:52:56,887 INFO L87 Difference]: Start difference. First operand 449 states and 621 transitions. cyclomatic complexity: 176 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:56,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:56,928 INFO L93 Difference]: Finished difference Result 701 states and 951 transitions. [2023-11-26 11:52:56,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 701 states and 951 transitions. [2023-11-26 11:52:56,936 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 586 [2023-11-26 11:52:56,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 701 states to 701 states and 951 transitions. [2023-11-26 11:52:56,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 701 [2023-11-26 11:52:56,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 701 [2023-11-26 11:52:56,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 701 states and 951 transitions. [2023-11-26 11:52:56,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:56,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 701 states and 951 transitions. [2023-11-26 11:52:56,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states and 951 transitions. [2023-11-26 11:52:56,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 510. [2023-11-26 11:52:56,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 510 states, 510 states have (on average 1.3588235294117648) internal successors, (693), 509 states have internal predecessors, (693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:56,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 510 states to 510 states and 693 transitions. [2023-11-26 11:52:56,976 INFO L240 hiAutomatonCegarLoop]: Abstraction has 510 states and 693 transitions. [2023-11-26 11:52:56,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:52:56,978 INFO L428 stractBuchiCegarLoop]: Abstraction has 510 states and 693 transitions. [2023-11-26 11:52:56,978 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:52:56,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 510 states and 693 transitions. [2023-11-26 11:52:56,981 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 422 [2023-11-26 11:52:56,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:56,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:56,983 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:56,983 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:56,983 INFO L748 eck$LassoCheckResult]: Stem: 2411#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 2412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2439#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2386#L222 assume !(1 == ~q_req_up~0); 2371#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2372#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2421#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2444#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2441#L275 assume !(0 == ~q_read_ev~0); 2442#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2452#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2493#L65 assume !(1 == ~p_dw_pc~0); 2491#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 2489#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2487#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2485#L315 assume !(0 != activate_threads_~tmp~1#1); 2483#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2481#L84 assume !(1 == ~c_dr_pc~0); 2479#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 2477#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2475#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2473#L323 assume !(0 != activate_threads_~tmp___0~1#1); 2471#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2469#L293 assume !(1 == ~q_read_ev~0); 2466#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2352#L298-1 assume { :end_inline_reset_delta_events } true; 2377#L419-2 [2023-11-26 11:52:56,984 INFO L750 eck$LassoCheckResult]: Loop: 2377#L419-2 assume !false; 2378#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2392#L364 assume !false; 2426#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2388#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2356#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2373#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2374#L344 assume !(0 != eval_~tmp___1~0#1); 2414#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2823#L222-3 assume !(1 == ~q_req_up~0); 2820#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2819#L275-3 assume !(0 == ~q_read_ev~0); 2817#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2816#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2815#L65-3 assume !(1 == ~p_dw_pc~0); 2814#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 2813#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2812#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2811#L315-3 assume !(0 != activate_threads_~tmp~1#1); 2810#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2809#L84-3 assume !(1 == ~c_dr_pc~0); 2808#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2807#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2806#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2805#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2804#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2803#L293-3 assume !(1 == ~q_read_ev~0); 2726#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2802#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2563#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2560#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2406#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2407#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2367#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2368#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2433#L436 assume !(0 != start_simulation_~tmp~4#1); 2377#L419-2 [2023-11-26 11:52:56,984 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:56,984 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2023-11-26 11:52:56,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:56,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743574829] [2023-11-26 11:52:56,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:56,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:56,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:57,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:57,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:57,027 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743574829] [2023-11-26 11:52:57,027 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743574829] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:57,027 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:57,027 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 11:52:57,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [980395833] [2023-11-26 11:52:57,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:57,028 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:52:57,029 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:57,029 INFO L85 PathProgramCache]: Analyzing trace with hash -884233102, now seen corresponding path program 1 times [2023-11-26 11:52:57,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:57,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229769240] [2023-11-26 11:52:57,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:57,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:57,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:57,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:57,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:57,076 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229769240] [2023-11-26 11:52:57,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1229769240] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:57,076 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:57,076 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:52:57,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1479383430] [2023-11-26 11:52:57,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:57,077 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:57,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:57,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:52:57,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:52:57,079 INFO L87 Difference]: Start difference. First operand 510 states and 693 transitions. cyclomatic complexity: 185 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:57,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:57,154 INFO L93 Difference]: Finished difference Result 745 states and 1002 transitions. [2023-11-26 11:52:57,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 745 states and 1002 transitions. [2023-11-26 11:52:57,161 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 622 [2023-11-26 11:52:57,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 745 states to 745 states and 1002 transitions. [2023-11-26 11:52:57,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 745 [2023-11-26 11:52:57,169 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 745 [2023-11-26 11:52:57,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 745 states and 1002 transitions. [2023-11-26 11:52:57,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:57,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 745 states and 1002 transitions. [2023-11-26 11:52:57,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 745 states and 1002 transitions. [2023-11-26 11:52:57,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 745 to 563. [2023-11-26 11:52:57,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 563 states, 563 states have (on average 1.3481349911190053) internal successors, (759), 562 states have internal predecessors, (759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:57,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 759 transitions. [2023-11-26 11:52:57,188 INFO L240 hiAutomatonCegarLoop]: Abstraction has 563 states and 759 transitions. [2023-11-26 11:52:57,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-26 11:52:57,189 INFO L428 stractBuchiCegarLoop]: Abstraction has 563 states and 759 transitions. [2023-11-26 11:52:57,189 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:52:57,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 563 states and 759 transitions. [2023-11-26 11:52:57,193 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 458 [2023-11-26 11:52:57,193 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:57,193 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:57,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:57,195 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:57,195 INFO L748 eck$LassoCheckResult]: Stem: 3680#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3705#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3653#L222 assume !(1 == ~q_req_up~0); 3641#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3642#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3781#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3719#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3707#L275 assume !(0 == ~q_read_ev~0); 3708#L275-2 assume !(0 == ~q_write_ev~0); 3693#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3694#L65 assume !(1 == ~p_dw_pc~0); 3701#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3702#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3675#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3676#L315 assume !(0 != activate_threads_~tmp~1#1); 3647#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3648#L84 assume !(1 == ~c_dr_pc~0); 3670#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3663#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3664#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3624#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3625#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3725#L293 assume !(1 == ~q_read_ev~0); 3618#L293-2 assume !(1 == ~q_write_ev~0); 3619#L298-1 assume { :end_inline_reset_delta_events } true; 3718#L419-2 [2023-11-26 11:52:57,195 INFO L750 eck$LassoCheckResult]: Loop: 3718#L419-2 assume !false; 3834#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3831#L364 assume !false; 3829#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3827#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3669#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3639#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3640#L344 assume !(0 != eval_~tmp___1~0#1); 3679#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4100#L222-3 assume !(1 == ~q_req_up~0); 4101#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4164#L275-3 assume !(0 == ~q_read_ev~0); 3721#L275-5 assume !(0 == ~q_write_ev~0); 3722#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3630#L65-3 assume !(1 == ~p_dw_pc~0); 3631#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 4176#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4175#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4174#L315-3 assume !(0 != activate_threads_~tmp~1#1); 4173#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4172#L84-3 assume !(1 == ~c_dr_pc~0); 4171#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 4170#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4169#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4168#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 4166#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4165#L293-3 assume !(1 == ~q_read_ev~0); 3628#L293-5 assume !(1 == ~q_write_ev~0); 3629#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3695#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3696#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3674#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3649#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3634#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3635#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3731#L436 assume !(0 != start_simulation_~tmp~4#1); 3718#L419-2 [2023-11-26 11:52:57,196 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:57,196 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2023-11-26 11:52:57,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:57,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774877151] [2023-11-26 11:52:57,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:57,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:57,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:57,206 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:57,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:57,236 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:57,236 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:57,237 INFO L85 PathProgramCache]: Analyzing trace with hash -338188238, now seen corresponding path program 1 times [2023-11-26 11:52:57,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:57,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536163371] [2023-11-26 11:52:57,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:57,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:57,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:57,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:57,281 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:57,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536163371] [2023-11-26 11:52:57,282 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [536163371] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:57,282 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:57,282 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:52:57,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717921971] [2023-11-26 11:52:57,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:57,283 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:57,283 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:57,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:52:57,284 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:52:57,284 INFO L87 Difference]: Start difference. First operand 563 states and 759 transitions. cyclomatic complexity: 198 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:57,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:57,364 INFO L93 Difference]: Finished difference Result 763 states and 1023 transitions. [2023-11-26 11:52:57,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 763 states and 1023 transitions. [2023-11-26 11:52:57,381 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 654 [2023-11-26 11:52:57,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 763 states to 763 states and 1023 transitions. [2023-11-26 11:52:57,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 763 [2023-11-26 11:52:57,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 763 [2023-11-26 11:52:57,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 763 states and 1023 transitions. [2023-11-26 11:52:57,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:57,391 INFO L218 hiAutomatonCegarLoop]: Abstraction has 763 states and 1023 transitions. [2023-11-26 11:52:57,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 763 states and 1023 transitions. [2023-11-26 11:52:57,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 763 to 581. [2023-11-26 11:52:57,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 581 states, 581 states have (on average 1.3373493975903614) internal successors, (777), 580 states have internal predecessors, (777), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:57,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 581 states to 581 states and 777 transitions. [2023-11-26 11:52:57,408 INFO L240 hiAutomatonCegarLoop]: Abstraction has 581 states and 777 transitions. [2023-11-26 11:52:57,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 11:52:57,410 INFO L428 stractBuchiCegarLoop]: Abstraction has 581 states and 777 transitions. [2023-11-26 11:52:57,410 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:52:57,411 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 581 states and 777 transitions. [2023-11-26 11:52:57,414 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 476 [2023-11-26 11:52:57,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:57,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:57,416 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:57,416 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:57,419 INFO L748 eck$LassoCheckResult]: Stem: 5022#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 5023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 5054#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4997#L222 assume !(1 == ~q_req_up~0); 4999#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5140#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5138#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5066#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5057#L275 assume !(0 == ~q_read_ev~0); 5058#L275-2 assume !(0 == ~q_write_ev~0); 5039#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5040#L65 assume !(1 == ~p_dw_pc~0); 5148#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 5088#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5019#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5020#L315 assume !(0 != activate_threads_~tmp~1#1); 4991#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4992#L84 assume !(1 == ~c_dr_pc~0); 5014#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 5008#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5009#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4968#L323 assume !(0 != activate_threads_~tmp___0~1#1); 4969#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5074#L293 assume !(1 == ~q_read_ev~0); 5075#L293-2 assume !(1 == ~q_write_ev~0); 5063#L298-1 assume { :end_inline_reset_delta_events } true; 4987#L419-2 [2023-11-26 11:52:57,421 INFO L750 eck$LassoCheckResult]: Loop: 4987#L419-2 assume !false; 4988#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5045#L364 assume !false; 5084#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5418#L255 assume !(0 == ~p_dw_st~0); 5414#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5412#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5410#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5408#L344 assume !(0 != eval_~tmp___1~0#1); 5004#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5005#L222-3 assume !(1 == ~q_req_up~0); 5038#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5034#L275-3 assume !(0 == ~q_read_ev~0); 5035#L275-5 assume !(0 == ~q_write_ev~0); 5070#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4974#L65-3 assume !(1 == ~p_dw_pc~0); 4975#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5013#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5069#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5072#L315-3 assume !(0 != activate_threads_~tmp~1#1); 5053#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4966#L84-3 assume !(1 == ~c_dr_pc~0); 4967#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 5032#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5033#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5050#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5028#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5029#L293-3 assume !(1 == ~q_read_ev~0); 5065#L293-5 assume !(1 == ~q_write_ev~0); 5085#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5086#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5527#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5526#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5525#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5524#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5087#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5049#L436 assume !(0 != start_simulation_~tmp~4#1); 4987#L419-2 [2023-11-26 11:52:57,422 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:57,423 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2023-11-26 11:52:57,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:57,423 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597533542] [2023-11-26 11:52:57,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:57,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:57,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:57,442 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:57,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:57,460 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:57,461 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:57,461 INFO L85 PathProgramCache]: Analyzing trace with hash 22665520, now seen corresponding path program 1 times [2023-11-26 11:52:57,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:57,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076314338] [2023-11-26 11:52:57,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:57,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:57,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:57,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:57,493 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:57,493 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076314338] [2023-11-26 11:52:57,494 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2076314338] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:57,494 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:57,494 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:52:57,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458027423] [2023-11-26 11:52:57,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:57,496 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:57,496 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:57,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:52:57,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:52:57,498 INFO L87 Difference]: Start difference. First operand 581 states and 777 transitions. cyclomatic complexity: 198 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:57,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:57,533 INFO L93 Difference]: Finished difference Result 905 states and 1173 transitions. [2023-11-26 11:52:57,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 905 states and 1173 transitions. [2023-11-26 11:52:57,541 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 722 [2023-11-26 11:52:57,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 905 states to 905 states and 1173 transitions. [2023-11-26 11:52:57,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 905 [2023-11-26 11:52:57,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 905 [2023-11-26 11:52:57,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 905 states and 1173 transitions. [2023-11-26 11:52:57,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:57,551 INFO L218 hiAutomatonCegarLoop]: Abstraction has 905 states and 1173 transitions. [2023-11-26 11:52:57,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 905 states and 1173 transitions. [2023-11-26 11:52:57,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 905 to 905. [2023-11-26 11:52:57,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 905 states, 905 states have (on average 1.296132596685083) internal successors, (1173), 904 states have internal predecessors, (1173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:57,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 905 states to 905 states and 1173 transitions. [2023-11-26 11:52:57,577 INFO L240 hiAutomatonCegarLoop]: Abstraction has 905 states and 1173 transitions. [2023-11-26 11:52:57,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:52:57,579 INFO L428 stractBuchiCegarLoop]: Abstraction has 905 states and 1173 transitions. [2023-11-26 11:52:57,579 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:52:57,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 905 states and 1173 transitions. [2023-11-26 11:52:57,585 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 722 [2023-11-26 11:52:57,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:57,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:57,586 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:57,586 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:57,587 INFO L748 eck$LassoCheckResult]: Stem: 6520#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6549#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6490#L222 assume !(1 == ~q_req_up~0); 6492#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6723#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 6722#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6721#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6720#L275 assume !(0 == ~q_read_ev~0); 6672#L275-2 assume !(0 == ~q_write_ev~0); 6667#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6661#L65 assume !(1 == ~p_dw_pc~0); 6655#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6649#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6643#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6634#L315 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 6630#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6628#L84 assume !(1 == ~c_dr_pc~0); 6626#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6624#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6622#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6620#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6618#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6616#L293 assume !(1 == ~q_read_ev~0); 6615#L293-2 assume !(1 == ~q_write_ev~0); 6932#L298-1 assume { :end_inline_reset_delta_events } true; 6931#L419-2 [2023-11-26 11:52:57,587 INFO L750 eck$LassoCheckResult]: Loop: 6931#L419-2 assume !false; 6606#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6603#L364 assume !false; 6599#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6600#L255 assume !(0 == ~p_dw_st~0); 6813#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6809#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6805#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6799#L344 assume !(0 != eval_~tmp___1~0#1); 6795#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6789#L222-3 assume !(1 == ~q_req_up~0); 6790#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6924#L275-3 assume !(0 == ~q_read_ev~0); 6921#L275-5 assume !(0 == ~q_write_ev~0); 6769#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6917#L65-3 assume !(1 == ~p_dw_pc~0); 6914#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6839#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6828#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6823#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 6817#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6812#L84-3 assume !(1 == ~c_dr_pc~0); 6808#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6804#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6798#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6794#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6788#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6782#L293-3 assume !(1 == ~q_read_ev~0); 6781#L293-5 assume !(1 == ~q_write_ev~0); 6868#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6865#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6866#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6937#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6936#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6935#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6934#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6933#L436 assume !(0 != start_simulation_~tmp~4#1); 6931#L419-2 [2023-11-26 11:52:57,588 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:57,588 INFO L85 PathProgramCache]: Analyzing trace with hash -1896010065, now seen corresponding path program 1 times [2023-11-26 11:52:57,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:57,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510784017] [2023-11-26 11:52:57,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:57,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:57,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:57,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:57,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:57,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510784017] [2023-11-26 11:52:57,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510784017] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:57,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:57,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:52:57,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389740586] [2023-11-26 11:52:57,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:57,646 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:52:57,646 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:57,646 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 1 times [2023-11-26 11:52:57,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:57,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572598847] [2023-11-26 11:52:57,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:57,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:57,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:57,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:57,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:57,725 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572598847] [2023-11-26 11:52:57,725 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572598847] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:57,725 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:57,725 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:52:57,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680859477] [2023-11-26 11:52:57,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:57,726 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:57,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:57,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:52:57,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:52:57,727 INFO L87 Difference]: Start difference. First operand 905 states and 1173 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:57,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:57,737 INFO L93 Difference]: Finished difference Result 827 states and 1075 transitions. [2023-11-26 11:52:57,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 827 states and 1075 transitions. [2023-11-26 11:52:57,744 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 722 [2023-11-26 11:52:57,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 827 states to 827 states and 1075 transitions. [2023-11-26 11:52:57,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 827 [2023-11-26 11:52:57,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 827 [2023-11-26 11:52:57,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 827 states and 1075 transitions. [2023-11-26 11:52:57,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:57,753 INFO L218 hiAutomatonCegarLoop]: Abstraction has 827 states and 1075 transitions. [2023-11-26 11:52:57,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 827 states and 1075 transitions. [2023-11-26 11:52:57,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 827 to 827. [2023-11-26 11:52:57,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 827 states, 827 states have (on average 1.2998790810157195) internal successors, (1075), 826 states have internal predecessors, (1075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:57,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 827 states to 827 states and 1075 transitions. [2023-11-26 11:52:57,772 INFO L240 hiAutomatonCegarLoop]: Abstraction has 827 states and 1075 transitions. [2023-11-26 11:52:57,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:52:57,773 INFO L428 stractBuchiCegarLoop]: Abstraction has 827 states and 1075 transitions. [2023-11-26 11:52:57,773 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 11:52:57,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 827 states and 1075 transitions. [2023-11-26 11:52:57,778 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 722 [2023-11-26 11:52:57,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:57,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:57,779 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:57,779 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:57,780 INFO L748 eck$LassoCheckResult]: Stem: 8259#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8260#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8288#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8232#L222 assume !(1 == ~q_req_up~0); 8234#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8270#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8271#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8293#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8380#L275 assume !(0 == ~q_read_ev~0); 8379#L275-2 assume !(0 == ~q_write_ev~0); 8354#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8321#L65 assume !(1 == ~p_dw_pc~0); 8284#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8285#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8377#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8376#L315 assume !(0 != activate_threads_~tmp~1#1); 8375#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8374#L84 assume !(1 == ~c_dr_pc~0); 8373#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 8243#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8244#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8201#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8202#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8309#L293 assume !(1 == ~q_read_ev~0); 8310#L293-2 assume !(1 == ~q_write_ev~0); 8297#L298-1 assume { :end_inline_reset_delta_events } true; 8298#L419-2 [2023-11-26 11:52:57,780 INFO L750 eck$LassoCheckResult]: Loop: 8298#L419-2 assume !false; 8427#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8425#L364 assume !false; 8420#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8421#L255 assume !(0 == ~p_dw_st~0); 8519#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8515#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8511#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8505#L344 assume !(0 != eval_~tmp___1~0#1); 8501#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8495#L222-3 assume !(1 == ~q_req_up~0); 8496#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8541#L275-3 assume !(0 == ~q_read_ev~0); 8539#L275-5 assume !(0 == ~q_write_ev~0); 8475#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8537#L65-3 assume !(1 == ~p_dw_pc~0); 8535#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 8533#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8531#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8528#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 8523#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8518#L84-3 assume !(1 == ~c_dr_pc~0); 8514#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 8510#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8504#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8500#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 8494#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8488#L293-3 assume !(1 == ~q_read_ev~0); 8440#L293-5 assume !(1 == ~q_write_ev~0); 8438#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8436#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8434#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8435#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8561#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8559#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8558#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8428#L436 assume !(0 != start_simulation_~tmp~4#1); 8298#L419-2 [2023-11-26 11:52:57,780 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:57,781 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2023-11-26 11:52:57,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:57,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746573201] [2023-11-26 11:52:57,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:57,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:57,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:57,793 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:57,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:57,810 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:57,811 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:57,811 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 2 times [2023-11-26 11:52:57,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:57,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590037607] [2023-11-26 11:52:57,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:57,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:57,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:57,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:57,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:57,877 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590037607] [2023-11-26 11:52:57,877 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590037607] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:57,877 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:57,877 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:52:57,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599457797] [2023-11-26 11:52:57,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:57,878 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:52:57,878 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:57,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:52:57,879 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:52:57,879 INFO L87 Difference]: Start difference. First operand 827 states and 1075 transitions. cyclomatic complexity: 250 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:57,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:57,928 INFO L93 Difference]: Finished difference Result 1043 states and 1357 transitions. [2023-11-26 11:52:57,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1043 states and 1357 transitions. [2023-11-26 11:52:57,938 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 922 [2023-11-26 11:52:57,946 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1043 states to 1043 states and 1357 transitions. [2023-11-26 11:52:57,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1043 [2023-11-26 11:52:57,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1043 [2023-11-26 11:52:57,948 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1043 states and 1357 transitions. [2023-11-26 11:52:57,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:57,950 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1043 states and 1357 transitions. [2023-11-26 11:52:57,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1043 states and 1357 transitions. [2023-11-26 11:52:57,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1043 to 754. [2023-11-26 11:52:57,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 754 states, 754 states have (on average 1.2877984084880636) internal successors, (971), 753 states have internal predecessors, (971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:57,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 754 states to 754 states and 971 transitions. [2023-11-26 11:52:57,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 754 states and 971 transitions. [2023-11-26 11:52:57,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:52:57,971 INFO L428 stractBuchiCegarLoop]: Abstraction has 754 states and 971 transitions. [2023-11-26 11:52:57,971 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 11:52:57,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 754 states and 971 transitions. [2023-11-26 11:52:57,975 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2023-11-26 11:52:57,976 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:57,976 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:57,977 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:57,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:57,977 INFO L748 eck$LassoCheckResult]: Stem: 10137#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 10138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10168#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10112#L222 assume !(1 == ~q_req_up~0); 10098#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10099#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 10262#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10183#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10172#L275 assume !(0 == ~q_read_ev~0); 10173#L275-2 assume !(0 == ~q_write_ev~0); 10155#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10156#L65 assume !(1 == ~p_dw_pc~0); 10267#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 10213#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10134#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10135#L315 assume !(0 != activate_threads_~tmp~1#1); 10106#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10107#L84 assume !(1 == ~c_dr_pc~0); 10263#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 10121#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10122#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10083#L323 assume !(0 != activate_threads_~tmp___0~1#1); 10084#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10193#L293 assume !(1 == ~q_read_ev~0); 10194#L293-2 assume !(1 == ~q_write_ev~0); 10180#L298-1 assume { :end_inline_reset_delta_events } true; 10181#L419-2 assume !false; 10388#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10385#L364 [2023-11-26 11:52:57,978 INFO L750 eck$LassoCheckResult]: Loop: 10385#L364 assume !false; 10374#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10375#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10463#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10460#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10457#L344 assume 0 != eval_~tmp___1~0#1; 10452#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 10450#L353 assume !(0 != eval_~tmp~2#1); 10384#L349 assume !(0 == ~c_dr_st~0); 10385#L364 [2023-11-26 11:52:57,978 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:57,978 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 1 times [2023-11-26 11:52:57,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:57,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117942170] [2023-11-26 11:52:57,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:57,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:57,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:57,989 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:57,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:58,003 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:58,003 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:58,004 INFO L85 PathProgramCache]: Analyzing trace with hash -479000197, now seen corresponding path program 1 times [2023-11-26 11:52:58,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:58,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1060121078] [2023-11-26 11:52:58,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:58,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:58,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:58,008 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:58,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:58,012 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:58,012 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:58,013 INFO L85 PathProgramCache]: Analyzing trace with hash 519639659, now seen corresponding path program 1 times [2023-11-26 11:52:58,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:58,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516854236] [2023-11-26 11:52:58,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:58,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:58,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:52:58,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:52:58,058 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:52:58,058 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516854236] [2023-11-26 11:52:58,058 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516854236] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:52:58,058 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:52:58,058 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:52:58,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180042695] [2023-11-26 11:52:58,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:52:58,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:52:58,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:52:58,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:52:58,133 INFO L87 Difference]: Start difference. First operand 754 states and 971 transitions. cyclomatic complexity: 221 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:58,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:52:58,168 INFO L93 Difference]: Finished difference Result 844 states and 1081 transitions. [2023-11-26 11:52:58,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 844 states and 1081 transitions. [2023-11-26 11:52:58,175 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 735 [2023-11-26 11:52:58,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 844 states to 844 states and 1081 transitions. [2023-11-26 11:52:58,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 844 [2023-11-26 11:52:58,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 844 [2023-11-26 11:52:58,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 844 states and 1081 transitions. [2023-11-26 11:52:58,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:52:58,184 INFO L218 hiAutomatonCegarLoop]: Abstraction has 844 states and 1081 transitions. [2023-11-26 11:52:58,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 844 states and 1081 transitions. [2023-11-26 11:52:58,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 844 to 824. [2023-11-26 11:52:58,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 824 states, 824 states have (on average 1.2851941747572815) internal successors, (1059), 823 states have internal predecessors, (1059), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:52:58,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 824 states to 824 states and 1059 transitions. [2023-11-26 11:52:58,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 824 states and 1059 transitions. [2023-11-26 11:52:58,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:52:58,204 INFO L428 stractBuchiCegarLoop]: Abstraction has 824 states and 1059 transitions. [2023-11-26 11:52:58,204 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 11:52:58,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 824 states and 1059 transitions. [2023-11-26 11:52:58,209 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 715 [2023-11-26 11:52:58,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:52:58,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:52:58,210 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:58,210 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:52:58,210 INFO L748 eck$LassoCheckResult]: Stem: 11743#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 11744#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 11770#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11719#L222 assume !(1 == ~q_req_up~0); 11721#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11867#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 11865#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 11788#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11776#L275 assume !(0 == ~q_read_ev~0); 11777#L275-2 assume !(0 == ~q_write_ev~0); 11789#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 11815#L65 assume !(1 == ~p_dw_pc~0); 11767#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 11768#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 11877#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11874#L315 assume !(0 != activate_threads_~tmp~1#1); 11873#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 11795#L84 assume !(1 == ~c_dr_pc~0); 11734#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 11729#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 11730#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11688#L323 assume !(0 != activate_threads_~tmp___0~1#1); 11689#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11797#L293 assume !(1 == ~q_read_ev~0); 11798#L293-2 assume !(1 == ~q_write_ev~0); 12316#L298-1 assume { :end_inline_reset_delta_events } true; 12313#L419-2 assume !false; 12311#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 12308#L364 [2023-11-26 11:52:58,210 INFO L750 eck$LassoCheckResult]: Loop: 12308#L364 assume !false; 12306#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12304#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12302#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12300#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 12298#L344 assume 0 != eval_~tmp___1~0#1; 12296#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 12254#L353 assume !(0 != eval_~tmp~2#1); 12142#L349 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 12143#L368 assume !(0 != eval_~tmp___0~2#1); 12308#L364 [2023-11-26 11:52:58,211 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:58,211 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 2 times [2023-11-26 11:52:58,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:58,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440967268] [2023-11-26 11:52:58,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:58,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:58,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:58,219 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:58,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:58,229 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:58,230 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:58,230 INFO L85 PathProgramCache]: Analyzing trace with hash -1964105996, now seen corresponding path program 1 times [2023-11-26 11:52:58,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:58,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362196575] [2023-11-26 11:52:58,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:58,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:58,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:58,234 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:58,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:58,238 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:58,238 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:52:58,239 INFO L85 PathProgramCache]: Analyzing trace with hash -1071041532, now seen corresponding path program 1 times [2023-11-26 11:52:58,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:52:58,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948069826] [2023-11-26 11:52:58,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:52:58,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:52:58,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:58,248 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:58,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:58,258 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 11:52:59,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:59,104 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 11:52:59,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 11:52:59,201 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.11 11:52:59 BoogieIcfgContainer [2023-11-26 11:52:59,201 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-26 11:52:59,202 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-26 11:52:59,202 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-26 11:52:59,202 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-26 11:52:59,203 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:52:55" (3/4) ... [2023-11-26 11:52:59,204 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-26 11:52:59,281 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/witness.graphml [2023-11-26 11:52:59,281 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-26 11:52:59,282 INFO L158 Benchmark]: Toolchain (without parser) took 5170.10ms. Allocated memory was 134.2MB in the beginning and 165.7MB in the end (delta: 31.5MB). Free memory was 102.5MB in the beginning and 96.1MB in the end (delta: 6.5MB). Peak memory consumption was 39.1MB. Max. memory is 16.1GB. [2023-11-26 11:52:59,282 INFO L158 Benchmark]: CDTParser took 0.28ms. Allocated memory is still 100.7MB. Free memory is still 52.1MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 11:52:59,283 INFO L158 Benchmark]: CACSL2BoogieTranslator took 386.87ms. Allocated memory is still 134.2MB. Free memory was 102.2MB in the beginning and 89.3MB in the end (delta: 12.9MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2023-11-26 11:52:59,283 INFO L158 Benchmark]: Boogie Procedure Inliner took 60.12ms. Allocated memory is still 134.2MB. Free memory was 89.3MB in the beginning and 87.2MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-26 11:52:59,283 INFO L158 Benchmark]: Boogie Preprocessor took 70.70ms. Allocated memory is still 134.2MB. Free memory was 87.2MB in the beginning and 84.5MB in the end (delta: 2.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 11:52:59,284 INFO L158 Benchmark]: RCFGBuilder took 542.30ms. Allocated memory is still 134.2MB. Free memory was 84.5MB in the beginning and 66.4MB in the end (delta: 18.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-26 11:52:59,284 INFO L158 Benchmark]: BuchiAutomizer took 4020.90ms. Allocated memory was 134.2MB in the beginning and 165.7MB in the end (delta: 31.5MB). Free memory was 66.1MB in the beginning and 100.3MB in the end (delta: -34.2MB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 11:52:59,285 INFO L158 Benchmark]: Witness Printer took 79.50ms. Allocated memory is still 165.7MB. Free memory was 100.3MB in the beginning and 96.1MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 11:52:59,287 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.28ms. Allocated memory is still 100.7MB. Free memory is still 52.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 386.87ms. Allocated memory is still 134.2MB. Free memory was 102.2MB in the beginning and 89.3MB in the end (delta: 12.9MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 60.12ms. Allocated memory is still 134.2MB. Free memory was 89.3MB in the beginning and 87.2MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 70.70ms. Allocated memory is still 134.2MB. Free memory was 87.2MB in the beginning and 84.5MB in the end (delta: 2.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 542.30ms. Allocated memory is still 134.2MB. Free memory was 84.5MB in the beginning and 66.4MB in the end (delta: 18.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 4020.90ms. Allocated memory was 134.2MB in the beginning and 165.7MB in the end (delta: 31.5MB). Free memory was 66.1MB in the beginning and 100.3MB in the end (delta: -34.2MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 79.50ms. Allocated memory is still 165.7MB. Free memory was 100.3MB in the beginning and 96.1MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 824 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.8s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 2.6s. Construction of modules took 0.2s. Büchi inclusion checks took 0.8s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 10 MinimizatonAttempts, 879 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1588 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1588 mSDsluCounter, 2930 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1463 mSDsCounter, 68 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 241 IncrementalHoareTripleChecker+Invalid, 309 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 68 mSolverCounterUnsat, 1467 mSDtfsCounter, 241 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 339]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0, tmp___0=0] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0, tmp___0=0] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-26 11:52:59,352 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347e58be-7d23-4f23-9f48-b6283bbad82d/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)