./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 12:02:38,317 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 12:02:38,386 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 12:02:38,392 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 12:02:38,393 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 12:02:38,418 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 12:02:38,419 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 12:02:38,420 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 12:02:38,421 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 12:02:38,421 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 12:02:38,422 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 12:02:38,423 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 12:02:38,424 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 12:02:38,424 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 12:02:38,425 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 12:02:38,426 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 12:02:38,426 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 12:02:38,427 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 12:02:38,427 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 12:02:38,428 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 12:02:38,429 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 12:02:38,429 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 12:02:38,430 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 12:02:38,430 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 12:02:38,431 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 12:02:38,431 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 12:02:38,432 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 12:02:38,432 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 12:02:38,433 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 12:02:38,433 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 12:02:38,434 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 12:02:38,434 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 12:02:38,435 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 12:02:38,435 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 12:02:38,436 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 12:02:38,436 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 12:02:38,436 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 12:02:38,437 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 12:02:38,437 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2023-11-26 12:02:38,721 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 12:02:38,764 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 12:02:38,767 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 12:02:38,769 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 12:02:38,770 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 12:02:38,771 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2023-11-26 12:02:42,009 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 12:02:42,233 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 12:02:42,234 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2023-11-26 12:02:42,246 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/data/8b95bd13b/55c2001d1f984b3c8b24e17221f69722/FLAG07453dad4 [2023-11-26 12:02:42,261 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/data/8b95bd13b/55c2001d1f984b3c8b24e17221f69722 [2023-11-26 12:02:42,264 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 12:02:42,266 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 12:02:42,267 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 12:02:42,268 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 12:02:42,273 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 12:02:42,274 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,275 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@186ee067 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42, skipping insertion in model container [2023-11-26 12:02:42,276 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,316 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 12:02:42,555 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:02:42,569 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 12:02:42,629 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:02:42,649 INFO L206 MainTranslator]: Completed translation [2023-11-26 12:02:42,649 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42 WrapperNode [2023-11-26 12:02:42,650 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 12:02:42,651 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 12:02:42,651 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 12:02:42,651 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 12:02:42,660 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,673 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,731 INFO L138 Inliner]: procedures = 31, calls = 36, calls flagged for inlining = 31, calls inlined = 35, statements flattened = 410 [2023-11-26 12:02:42,731 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 12:02:42,732 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 12:02:42,732 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 12:02:42,733 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 12:02:42,747 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,749 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,766 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,797 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 12:02:42,797 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,798 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,806 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,813 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,815 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,817 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,822 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 12:02:42,823 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 12:02:42,823 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 12:02:42,823 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 12:02:42,824 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (1/1) ... [2023-11-26 12:02:42,830 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:02:42,847 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:02:42,867 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:02:42,893 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 12:02:42,917 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 12:02:42,918 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 12:02:42,918 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 12:02:42,918 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 12:02:43,045 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 12:02:43,048 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 12:02:43,571 INFO L775 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##104: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2023-11-26 12:02:43,571 INFO L775 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##105: assume !(1 == ~q_free~0); [2023-11-26 12:02:43,572 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 12:02:43,591 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 12:02:43,591 INFO L309 CfgBuilder]: Removed 4 assume(true) statements. [2023-11-26 12:02:43,593 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:02:43 BoogieIcfgContainer [2023-11-26 12:02:43,593 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 12:02:43,594 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 12:02:43,594 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 12:02:43,598 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 12:02:43,599 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:02:43,599 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 12:02:42" (1/3) ... [2023-11-26 12:02:43,600 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71701c97 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:02:43, skipping insertion in model container [2023-11-26 12:02:43,600 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:02:43,601 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:02:42" (2/3) ... [2023-11-26 12:02:43,601 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71701c97 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:02:43, skipping insertion in model container [2023-11-26 12:02:43,601 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:02:43,602 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:02:43" (3/3) ... [2023-11-26 12:02:43,603 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2023-11-26 12:02:43,671 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 12:02:43,671 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 12:02:43,671 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 12:02:43,671 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 12:02:43,672 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 12:02:43,672 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 12:02:43,672 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 12:02:43,672 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 12:02:43,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 144 states, 143 states have (on average 1.5524475524475525) internal successors, (222), 143 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:43,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 104 [2023-11-26 12:02:43,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:43,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:43,721 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:43,721 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:43,721 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 12:02:43,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 144 states, 143 states have (on average 1.5524475524475525) internal successors, (222), 143 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:43,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 104 [2023-11-26 12:02:43,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:43,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:43,744 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:43,744 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:43,750 INFO L748 eck$LassoCheckResult]: Stem: 22#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 36#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 140#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25#L258true assume !(1 == ~q_req_up~0); 69#L258-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60#L273true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 114#L273-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 101#L278-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47#L311true assume !(0 == ~q_read_ev~0); 102#L311-2true assume !(0 == ~q_write_ev~0); 78#L316-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 31#L66true assume 1 == ~p_dw_pc~0; 131#L67true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 55#L87true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 98#is_do_write_p_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 53#L387true assume !(0 != activate_threads_~tmp~1#1); 106#L387-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 86#L95true assume 1 == ~c_dr_pc~0; 120#L96true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 21#L116true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 27#is_do_read_c_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 79#L395true assume !(0 != activate_threads_~tmp___0~1#1); 11#L395-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28#L329true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 56#L329-2true assume !(1 == ~q_write_ev~0); 33#L334-1true assume { :end_inline_reset_delta_events } true; 128#L491-2true [2023-11-26 12:02:43,752 INFO L750 eck$LassoCheckResult]: Loop: 128#L491-2true assume !false; 129#L492true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 97#L435true assume !true; 82#eval_returnLabel#1true havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59#L258-3true assume !(1 == ~q_req_up~0); 109#L258-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132#L311-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 115#L311-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 70#L316-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 113#L66-3true assume 1 == ~p_dw_pc~0; 94#L67-1true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 8#L87-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 63#is_do_write_p_triggered_returnLabel#2true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 124#L387-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 32#L387-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 126#L95-3true assume 1 == ~c_dr_pc~0; 65#L96-1true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 104#L116-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 35#is_do_read_c_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 133#L395-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 16#L395-5true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41#L329-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 90#L329-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 142#L334-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 51#L291-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 105#L303-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 100#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 80#L510true assume !(0 == start_simulation_~tmp~4#1); 6#L510-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 75#L291-2true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 93#L303-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 143#L465true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 29#L472true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 145#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 77#L523true assume !(0 != start_simulation_~tmp___0~3#1); 128#L491-2true [2023-11-26 12:02:43,759 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:43,759 INFO L85 PathProgramCache]: Analyzing trace with hash 854607455, now seen corresponding path program 1 times [2023-11-26 12:02:43,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:43,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2055998553] [2023-11-26 12:02:43,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:43,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:43,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:44,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:44,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:44,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2055998553] [2023-11-26 12:02:44,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2055998553] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:44,034 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:44,034 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:02:44,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [392015285] [2023-11-26 12:02:44,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:44,042 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:02:44,043 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:44,043 INFO L85 PathProgramCache]: Analyzing trace with hash 1919014688, now seen corresponding path program 1 times [2023-11-26 12:02:44,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:44,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643012477] [2023-11-26 12:02:44,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:44,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:44,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:44,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:44,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:44,076 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643012477] [2023-11-26 12:02:44,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643012477] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:44,076 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:44,076 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:02:44,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [387549568] [2023-11-26 12:02:44,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:44,078 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:02:44,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:02:44,113 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:02:44,114 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:02:44,116 INFO L87 Difference]: Start difference. First operand has 144 states, 143 states have (on average 1.5524475524475525) internal successors, (222), 143 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:44,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:02:44,148 INFO L93 Difference]: Finished difference Result 140 states and 207 transitions. [2023-11-26 12:02:44,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 207 transitions. [2023-11-26 12:02:44,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2023-11-26 12:02:44,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 134 states and 201 transitions. [2023-11-26 12:02:44,162 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134 [2023-11-26 12:02:44,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134 [2023-11-26 12:02:44,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134 states and 201 transitions. [2023-11-26 12:02:44,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:02:44,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 134 states and 201 transitions. [2023-11-26 12:02:44,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states and 201 transitions. [2023-11-26 12:02:44,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2023-11-26 12:02:44,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:44,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 201 transitions. [2023-11-26 12:02:44,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134 states and 201 transitions. [2023-11-26 12:02:44,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:02:44,210 INFO L428 stractBuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2023-11-26 12:02:44,210 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 12:02:44,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 201 transitions. [2023-11-26 12:02:44,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2023-11-26 12:02:44,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:44,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:44,216 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:44,216 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:44,216 INFO L748 eck$LassoCheckResult]: Stem: 334#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 335#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 359#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 339#L258 assume !(1 == ~q_req_up~0); 341#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 393#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 394#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 418#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 372#L311 assume !(0 == ~q_read_ev~0); 373#L311-2 assume !(0 == ~q_write_ev~0); 405#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 348#L66 assume 1 == ~p_dw_pc~0; 350#L67 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 386#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 387#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 382#L387 assume !(0 != activate_threads_~tmp~1#1); 383#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 411#L95 assume 1 == ~c_dr_pc~0; 413#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 330#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 331#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 342#L395 assume !(0 != activate_threads_~tmp___0~1#1); 308#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 345#L329-2 assume !(1 == ~q_write_ev~0); 353#L334-1 assume { :end_inline_reset_delta_events } true; 354#L491-2 [2023-11-26 12:02:44,217 INFO L750 eck$LassoCheckResult]: Loop: 354#L491-2 assume !false; 426#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 356#L435 assume !false; 388#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 389#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 299#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 312#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 313#L415 assume !(0 != eval_~tmp___1~0#1); 409#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 390#L258-3 assume !(1 == ~q_req_up~0); 392#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 420#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 424#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 402#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 403#L66-3 assume 1 == ~p_dw_pc~0; 416#L67-1 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 303#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 305#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 396#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 351#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 352#L95-3 assume 1 == ~c_dr_pc~0; 397#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 398#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 357#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 358#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 318#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 366#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 414#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 379#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 381#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 417#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 406#L510 assume !(0 == start_simulation_~tmp~4#1); 300#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 301#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 333#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 346#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 347#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 343#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 344#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 404#L523 assume !(0 != start_simulation_~tmp___0~3#1); 354#L491-2 [2023-11-26 12:02:44,219 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:44,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1672255905, now seen corresponding path program 1 times [2023-11-26 12:02:44,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:44,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666748953] [2023-11-26 12:02:44,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:44,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:44,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:44,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:44,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:44,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666748953] [2023-11-26 12:02:44,379 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [666748953] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:44,379 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:44,379 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:02:44,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774305914] [2023-11-26 12:02:44,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:44,380 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:02:44,381 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:44,381 INFO L85 PathProgramCache]: Analyzing trace with hash -848315206, now seen corresponding path program 1 times [2023-11-26 12:02:44,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:44,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376976191] [2023-11-26 12:02:44,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:44,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:44,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:44,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:44,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:44,568 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [376976191] [2023-11-26 12:02:44,569 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [376976191] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:44,569 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:44,569 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:02:44,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2054140100] [2023-11-26 12:02:44,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:44,570 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:02:44,570 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:02:44,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:02:44,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:02:44,572 INFO L87 Difference]: Start difference. First operand 134 states and 201 transitions. cyclomatic complexity: 68 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:44,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:02:44,645 INFO L93 Difference]: Finished difference Result 221 states and 321 transitions. [2023-11-26 12:02:44,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 221 states and 321 transitions. [2023-11-26 12:02:44,649 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 186 [2023-11-26 12:02:44,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 221 states to 221 states and 321 transitions. [2023-11-26 12:02:44,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2023-11-26 12:02:44,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2023-11-26 12:02:44,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 221 states and 321 transitions. [2023-11-26 12:02:44,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:02:44,656 INFO L218 hiAutomatonCegarLoop]: Abstraction has 221 states and 321 transitions. [2023-11-26 12:02:44,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states and 321 transitions. [2023-11-26 12:02:44,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 219. [2023-11-26 12:02:44,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219 states, 219 states have (on average 1.45662100456621) internal successors, (319), 218 states have internal predecessors, (319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:44,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 319 transitions. [2023-11-26 12:02:44,670 INFO L240 hiAutomatonCegarLoop]: Abstraction has 219 states and 319 transitions. [2023-11-26 12:02:44,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:02:44,676 INFO L428 stractBuchiCegarLoop]: Abstraction has 219 states and 319 transitions. [2023-11-26 12:02:44,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 12:02:44,677 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 219 states and 319 transitions. [2023-11-26 12:02:44,679 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 184 [2023-11-26 12:02:44,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:44,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:44,681 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:44,681 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:44,682 INFO L748 eck$LassoCheckResult]: Stem: 699#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 700#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 723#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 704#L258 assume !(1 == ~q_req_up~0); 706#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 757#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 758#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 787#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 737#L311 assume !(0 == ~q_read_ev~0); 738#L311-2 assume !(0 == ~q_write_ev~0); 770#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 715#L66 assume !(1 == ~p_dw_pc~0); 716#L66-2 assume !(2 == ~p_dw_pc~0); 729#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 750#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 751#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 746#L387 assume !(0 != activate_threads_~tmp~1#1); 747#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 779#L95 assume 1 == ~c_dr_pc~0; 781#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 695#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 696#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 707#L395 assume !(0 != activate_threads_~tmp___0~1#1); 674#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 675#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 710#L329-2 assume !(1 == ~q_write_ev~0); 717#L334-1 assume { :end_inline_reset_delta_events } true; 718#L491-2 [2023-11-26 12:02:44,682 INFO L750 eck$LassoCheckResult]: Loop: 718#L491-2 assume !false; 817#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 815#L435 assume !false; 812#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 809#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 807#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 806#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 804#L415 assume !(0 != eval_~tmp___1~0#1); 805#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 872#L258-3 assume !(1 == ~q_req_up~0); 870#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 869#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 868#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 766#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 767#L66-3 assume !(1 == ~p_dw_pc~0); 739#L66-5 assume !(2 == ~p_dw_pc~0); 666#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 667#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 668#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 760#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 713#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 714#L95-3 assume 1 == ~c_dr_pc~0; 761#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 762#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 721#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 722#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 683#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 684#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 728#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 782#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 743#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 745#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 786#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 771#L510 assume !(0 == start_simulation_~tmp~4#1); 664#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 665#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 698#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 712#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 799#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 828#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 825#L523 assume !(0 != start_simulation_~tmp___0~3#1); 718#L491-2 [2023-11-26 12:02:44,683 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:44,683 INFO L85 PathProgramCache]: Analyzing trace with hash -841270075, now seen corresponding path program 1 times [2023-11-26 12:02:44,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:44,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477709880] [2023-11-26 12:02:44,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:44,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:44,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:44,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:44,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:44,817 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477709880] [2023-11-26 12:02:44,817 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477709880] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:44,817 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:44,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:02:44,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [387184236] [2023-11-26 12:02:44,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:44,820 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:02:44,821 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:44,822 INFO L85 PathProgramCache]: Analyzing trace with hash 54589687, now seen corresponding path program 1 times [2023-11-26 12:02:44,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:44,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986780466] [2023-11-26 12:02:44,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:44,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:44,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:44,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:44,911 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:44,911 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986780466] [2023-11-26 12:02:44,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986780466] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:44,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:44,912 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:02:44,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278219471] [2023-11-26 12:02:44,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:44,913 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:02:44,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:02:44,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:02:44,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:02:44,914 INFO L87 Difference]: Start difference. First operand 219 states and 319 transitions. cyclomatic complexity: 102 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:45,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:02:45,045 INFO L93 Difference]: Finished difference Result 471 states and 676 transitions. [2023-11-26 12:02:45,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 471 states and 676 transitions. [2023-11-26 12:02:45,050 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 425 [2023-11-26 12:02:45,055 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 471 states to 471 states and 676 transitions. [2023-11-26 12:02:45,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 471 [2023-11-26 12:02:45,057 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 471 [2023-11-26 12:02:45,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 471 states and 676 transitions. [2023-11-26 12:02:45,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:02:45,060 INFO L218 hiAutomatonCegarLoop]: Abstraction has 471 states and 676 transitions. [2023-11-26 12:02:45,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states and 676 transitions. [2023-11-26 12:02:45,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 377. [2023-11-26 12:02:45,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 377 states, 377 states have (on average 1.4456233421750664) internal successors, (545), 376 states have internal predecessors, (545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:45,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 377 states to 377 states and 545 transitions. [2023-11-26 12:02:45,083 INFO L240 hiAutomatonCegarLoop]: Abstraction has 377 states and 545 transitions. [2023-11-26 12:02:45,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:02:45,085 INFO L428 stractBuchiCegarLoop]: Abstraction has 377 states and 545 transitions. [2023-11-26 12:02:45,085 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 12:02:45,085 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 377 states and 545 transitions. [2023-11-26 12:02:45,088 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 342 [2023-11-26 12:02:45,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:45,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:45,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:45,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:45,091 INFO L748 eck$LassoCheckResult]: Stem: 1402#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 1403#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1426#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1407#L258 assume !(1 == ~q_req_up~0); 1409#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1461#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1462#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1498#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1440#L311 assume !(0 == ~q_read_ev~0); 1441#L311-2 assume !(0 == ~q_write_ev~0); 1479#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1418#L66 assume !(1 == ~p_dw_pc~0); 1419#L66-2 assume !(2 == ~p_dw_pc~0); 1432#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 1456#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1457#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1450#L387 assume !(0 != activate_threads_~tmp~1#1); 1451#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1489#L95 assume !(1 == ~c_dr_pc~0); 1490#L95-2 assume 2 == ~c_dr_pc~0; 1502#L106 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1398#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1399#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1410#L395 assume !(0 != activate_threads_~tmp___0~1#1); 1377#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1378#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1413#L329-2 assume !(1 == ~q_write_ev~0); 1422#L334-1 assume { :end_inline_reset_delta_events } true; 1423#L491-2 [2023-11-26 12:02:45,091 INFO L750 eck$LassoCheckResult]: Loop: 1423#L491-2 assume !false; 1510#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1421#L435 assume !false; 1454#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1455#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1366#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1379#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1380#L415 assume !(0 != eval_~tmp___1~0#1); 1483#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1458#L258-3 assume !(1 == ~q_req_up~0); 1460#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1505#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1508#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1472#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1473#L66-3 assume !(1 == ~p_dw_pc~0); 1442#L66-5 assume !(2 == ~p_dw_pc~0); 1369#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 1370#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1371#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1464#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 1416#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1417#L95-3 assume !(1 == ~c_dr_pc~0); 1360#L95-5 assume 2 == ~c_dr_pc~0; 1361#L106-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1499#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1424#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1425#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1385#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1386#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1431#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1491#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1446#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1448#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1480#L510 assume !(0 == start_simulation_~tmp~4#1); 1367#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1368#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1401#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1415#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1411#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1412#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1478#L523 assume !(0 != start_simulation_~tmp___0~3#1); 1423#L491-2 [2023-11-26 12:02:45,091 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:45,092 INFO L85 PathProgramCache]: Analyzing trace with hash -1943531092, now seen corresponding path program 1 times [2023-11-26 12:02:45,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:45,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613058183] [2023-11-26 12:02:45,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:45,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:45,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:45,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:45,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:45,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613058183] [2023-11-26 12:02:45,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613058183] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:45,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:45,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-26 12:02:45,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1015573909] [2023-11-26 12:02:45,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:45,163 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:02:45,163 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:45,163 INFO L85 PathProgramCache]: Analyzing trace with hash 2126410793, now seen corresponding path program 1 times [2023-11-26 12:02:45,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:45,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [939847125] [2023-11-26 12:02:45,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:45,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:45,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:45,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:45,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:45,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [939847125] [2023-11-26 12:02:45,224 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [939847125] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:45,224 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:45,224 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:02:45,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381506565] [2023-11-26 12:02:45,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:45,225 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:02:45,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:02:45,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:02:45,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:02:45,226 INFO L87 Difference]: Start difference. First operand 377 states and 545 transitions. cyclomatic complexity: 170 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:45,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:02:45,342 INFO L93 Difference]: Finished difference Result 555 states and 772 transitions. [2023-11-26 12:02:45,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 555 states and 772 transitions. [2023-11-26 12:02:45,349 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 488 [2023-11-26 12:02:45,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 555 states to 555 states and 772 transitions. [2023-11-26 12:02:45,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 555 [2023-11-26 12:02:45,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 555 [2023-11-26 12:02:45,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 555 states and 772 transitions. [2023-11-26 12:02:45,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:02:45,357 INFO L218 hiAutomatonCegarLoop]: Abstraction has 555 states and 772 transitions. [2023-11-26 12:02:45,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states and 772 transitions. [2023-11-26 12:02:45,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 551. [2023-11-26 12:02:45,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.3938294010889292) internal successors, (768), 550 states have internal predecessors, (768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:45,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 768 transitions. [2023-11-26 12:02:45,393 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 768 transitions. [2023-11-26 12:02:45,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:02:45,396 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 768 transitions. [2023-11-26 12:02:45,396 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 12:02:45,398 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 768 transitions. [2023-11-26 12:02:45,403 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 488 [2023-11-26 12:02:45,403 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:45,408 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:45,411 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:45,411 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:45,412 INFO L748 eck$LassoCheckResult]: Stem: 2341#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 2342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2367#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2346#L258 assume !(1 == ~q_req_up~0); 2348#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2404#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2405#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2458#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2382#L311 assume !(0 == ~q_read_ev~0); 2383#L311-2 assume !(0 == ~q_write_ev~0); 2449#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2484#L66 assume !(1 == ~p_dw_pc~0); 2372#L66-2 assume !(2 == ~p_dw_pc~0); 2373#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 2395#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2396#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2391#L387 assume !(0 != activate_threads_~tmp~1#1); 2392#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2433#L95 assume !(1 == ~c_dr_pc~0); 2434#L95-2 assume !(2 == ~c_dr_pc~0); 2481#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 2337#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2338#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2423#L395 assume !(0 != activate_threads_~tmp___0~1#1); 2424#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2353#L329 assume !(1 == ~q_read_ev~0); 2354#L329-2 assume !(1 == ~q_write_ev~0); 2822#L334-1 assume { :end_inline_reset_delta_events } true; 2820#L491-2 [2023-11-26 12:02:45,414 INFO L750 eck$LassoCheckResult]: Loop: 2820#L491-2 assume !false; 2819#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2637#L435 assume !false; 2674#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2669#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2667#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2666#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2662#L415 assume !(0 != eval_~tmp___1~0#1); 2663#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2813#L258-3 assume !(1 == ~q_req_up~0); 2808#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2806#L311-3 assume !(0 == ~q_read_ev~0); 2804#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2802#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2800#L66-3 assume !(1 == ~p_dw_pc~0); 2798#L66-5 assume !(2 == ~p_dw_pc~0); 2796#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 2794#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2792#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2790#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2788#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2786#L95-3 assume !(1 == ~c_dr_pc~0); 2302#L95-5 assume !(2 == ~c_dr_pc~0); 2303#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 2448#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2365#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2366#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2325#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2326#L329-3 assume !(1 == ~q_read_ev~0); 2371#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2838#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2837#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2834#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2833#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2832#L510 assume !(0 == start_simulation_~tmp~4#1); 2830#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2829#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2827#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2826#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2825#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2824#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2823#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2821#L523 assume !(0 != start_simulation_~tmp___0~3#1); 2820#L491-2 [2023-11-26 12:02:45,414 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:45,415 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 1 times [2023-11-26 12:02:45,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:45,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278645276] [2023-11-26 12:02:45,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:45,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:45,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:45,442 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:02:45,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:45,488 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:02:45,489 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:45,489 INFO L85 PathProgramCache]: Analyzing trace with hash 147817770, now seen corresponding path program 1 times [2023-11-26 12:02:45,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:45,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059331495] [2023-11-26 12:02:45,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:45,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:45,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:45,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:45,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:45,552 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059331495] [2023-11-26 12:02:45,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059331495] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:45,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:45,553 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:02:45,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [970462687] [2023-11-26 12:02:45,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:45,553 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:02:45,554 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:02:45,554 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 12:02:45,555 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 12:02:45,555 INFO L87 Difference]: Start difference. First operand 551 states and 768 transitions. cyclomatic complexity: 221 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:45,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:02:45,669 INFO L93 Difference]: Finished difference Result 886 states and 1210 transitions. [2023-11-26 12:02:45,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 886 states and 1210 transitions. [2023-11-26 12:02:45,679 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 818 [2023-11-26 12:02:45,690 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 886 states to 886 states and 1210 transitions. [2023-11-26 12:02:45,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 886 [2023-11-26 12:02:45,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 886 [2023-11-26 12:02:45,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 886 states and 1210 transitions. [2023-11-26 12:02:45,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:02:45,693 INFO L218 hiAutomatonCegarLoop]: Abstraction has 886 states and 1210 transitions. [2023-11-26 12:02:45,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886 states and 1210 transitions. [2023-11-26 12:02:45,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886 to 569. [2023-11-26 12:02:45,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 569 states, 569 states have (on average 1.3813708260105448) internal successors, (786), 568 states have internal predecessors, (786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:45,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 786 transitions. [2023-11-26 12:02:45,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 569 states and 786 transitions. [2023-11-26 12:02:45,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 12:02:45,712 INFO L428 stractBuchiCegarLoop]: Abstraction has 569 states and 786 transitions. [2023-11-26 12:02:45,712 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 12:02:45,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 569 states and 786 transitions. [2023-11-26 12:02:45,716 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 506 [2023-11-26 12:02:45,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:45,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:45,719 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:45,719 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:45,720 INFO L748 eck$LassoCheckResult]: Stem: 3795#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 3796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3823#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3802#L258 assume !(1 == ~q_req_up~0); 3804#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3871#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3922#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3923#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3839#L311 assume !(0 == ~q_read_ev~0); 3840#L311-2 assume !(0 == ~q_write_ev~0); 3877#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3878#L66 assume !(1 == ~p_dw_pc~0); 3827#L66-2 assume !(2 == ~p_dw_pc~0); 3828#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 3851#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3852#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3847#L387 assume !(0 != activate_threads_~tmp~1#1); 3848#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3890#L95 assume !(1 == ~c_dr_pc~0); 3891#L95-2 assume !(2 == ~c_dr_pc~0); 3862#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 3863#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3805#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3806#L395 assume !(0 != activate_threads_~tmp___0~1#1); 3772#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3773#L329 assume !(1 == ~q_read_ev~0); 3807#L329-2 assume !(1 == ~q_write_ev~0); 3816#L334-1 assume { :end_inline_reset_delta_events } true; 3817#L491-2 [2023-11-26 12:02:45,721 INFO L750 eck$LassoCheckResult]: Loop: 3817#L491-2 assume !false; 3936#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3820#L435 assume !false; 3855#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3856#L291 assume !(0 == ~p_dw_st~0); 3760#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 3762#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3939#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 4142#L415 assume !(0 != eval_~tmp___1~0#1); 3884#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3885#L258-3 assume !(1 == ~q_req_up~0); 3915#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3916#L311-3 assume !(0 == ~q_read_ev~0); 3924#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3925#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3920#L66-3 assume !(1 == ~p_dw_pc~0); 3921#L66-5 assume !(2 == ~p_dw_pc~0); 4241#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 4240#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4237#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4236#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 4235#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4234#L95-3 assume !(1 == ~c_dr_pc~0); 4233#L95-5 assume !(2 == ~c_dr_pc~0); 4232#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 4231#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4230#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4229#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 4227#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3829#L329-3 assume !(1 == ~q_read_ev~0); 3830#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 4311#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3844#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3846#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3903#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3881#L510 assume !(0 == start_simulation_~tmp~4#1); 3763#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3764#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4302#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4301#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4300#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3808#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3809#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3876#L523 assume !(0 != start_simulation_~tmp___0~3#1); 3817#L491-2 [2023-11-26 12:02:45,721 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:45,722 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 2 times [2023-11-26 12:02:45,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:45,722 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867886806] [2023-11-26 12:02:45,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:45,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:45,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:45,744 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:02:45,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:45,764 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:02:45,765 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:45,765 INFO L85 PathProgramCache]: Analyzing trace with hash 657647766, now seen corresponding path program 1 times [2023-11-26 12:02:45,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:45,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130869160] [2023-11-26 12:02:45,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:45,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:45,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:45,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:45,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:45,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [130869160] [2023-11-26 12:02:45,887 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [130869160] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:45,887 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:45,887 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:02:45,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915103834] [2023-11-26 12:02:45,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:45,888 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:02:45,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:02:45,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 12:02:45,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 12:02:45,889 INFO L87 Difference]: Start difference. First operand 569 states and 786 transitions. cyclomatic complexity: 221 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:45,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:02:45,966 INFO L93 Difference]: Finished difference Result 861 states and 1170 transitions. [2023-11-26 12:02:45,966 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 861 states and 1170 transitions. [2023-11-26 12:02:45,974 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 797 [2023-11-26 12:02:45,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 861 states to 861 states and 1170 transitions. [2023-11-26 12:02:45,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 861 [2023-11-26 12:02:45,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 861 [2023-11-26 12:02:45,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 861 states and 1170 transitions. [2023-11-26 12:02:45,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:02:45,985 INFO L218 hiAutomatonCegarLoop]: Abstraction has 861 states and 1170 transitions. [2023-11-26 12:02:45,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 861 states and 1170 transitions. [2023-11-26 12:02:45,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 861 to 587. [2023-11-26 12:02:45,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 587 states, 587 states have (on average 1.3560477001703577) internal successors, (796), 586 states have internal predecessors, (796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:46,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 587 states and 796 transitions. [2023-11-26 12:02:46,000 INFO L240 hiAutomatonCegarLoop]: Abstraction has 587 states and 796 transitions. [2023-11-26 12:02:46,001 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 12:02:46,001 INFO L428 stractBuchiCegarLoop]: Abstraction has 587 states and 796 transitions. [2023-11-26 12:02:46,002 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 12:02:46,002 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 587 states and 796 transitions. [2023-11-26 12:02:46,006 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 524 [2023-11-26 12:02:46,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:46,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:46,007 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:46,007 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:46,007 INFO L748 eck$LassoCheckResult]: Stem: 5235#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 5236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 5262#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5242#L258 assume !(1 == ~q_req_up~0); 5244#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5309#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5361#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5362#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5277#L311 assume !(0 == ~q_read_ev~0); 5278#L311-2 assume !(0 == ~q_write_ev~0); 5317#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5318#L66 assume !(1 == ~p_dw_pc~0); 5266#L66-2 assume !(2 == ~p_dw_pc~0); 5267#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 5290#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5291#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5286#L387 assume !(0 != activate_threads_~tmp~1#1); 5287#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5331#L95 assume !(1 == ~c_dr_pc~0); 5332#L95-2 assume !(2 == ~c_dr_pc~0); 5300#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 5301#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5245#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5246#L395 assume !(0 != activate_threads_~tmp___0~1#1); 5213#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5214#L329 assume !(1 == ~q_read_ev~0); 5247#L329-2 assume !(1 == ~q_write_ev~0); 5292#L334-1 assume { :end_inline_reset_delta_events } true; 5524#L491-2 [2023-11-26 12:02:46,007 INFO L750 eck$LassoCheckResult]: Loop: 5524#L491-2 assume !false; 5523#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5487#L435 assume !false; 5522#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5519#L291 assume !(0 == ~p_dw_st~0); 5520#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5521#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5515#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5516#L415 assume !(0 != eval_~tmp___1~0#1); 5608#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5603#L258-3 assume !(1 == ~q_req_up~0); 5604#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5714#L311-3 assume !(0 == ~q_read_ev~0); 5713#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 5310#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5311#L66-3 assume !(1 == ~p_dw_pc~0); 5575#L66-5 assume !(2 == ~p_dw_pc~0); 5572#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 5570#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5568#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5567#L387-3 assume !(0 != activate_threads_~tmp~1#1); 5565#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5563#L95-3 assume !(1 == ~c_dr_pc~0); 5561#L95-5 assume !(2 == ~c_dr_pc~0); 5559#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 5557#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5555#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5553#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5551#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5549#L329-3 assume !(1 == ~q_read_ev~0); 5547#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 5545#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5543#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5540#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5538#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5535#L510 assume !(0 == start_simulation_~tmp~4#1); 5533#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5532#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5530#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5529#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5528#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5527#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5526#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5525#L523 assume !(0 != start_simulation_~tmp___0~3#1); 5524#L491-2 [2023-11-26 12:02:46,008 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:46,008 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 3 times [2023-11-26 12:02:46,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:46,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534419818] [2023-11-26 12:02:46,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:46,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:46,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,018 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:02:46,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,029 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:02:46,030 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:46,030 INFO L85 PathProgramCache]: Analyzing trace with hash 523634260, now seen corresponding path program 1 times [2023-11-26 12:02:46,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:46,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711779128] [2023-11-26 12:02:46,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:46,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:46,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:46,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:46,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:46,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1711779128] [2023-11-26 12:02:46,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1711779128] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:46,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:46,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:02:46,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031042262] [2023-11-26 12:02:46,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:46,091 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:02:46,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:02:46,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:02:46,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:02:46,092 INFO L87 Difference]: Start difference. First operand 587 states and 796 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:46,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:02:46,135 INFO L93 Difference]: Finished difference Result 850 states and 1119 transitions. [2023-11-26 12:02:46,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 850 states and 1119 transitions. [2023-11-26 12:02:46,143 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2023-11-26 12:02:46,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 850 states to 850 states and 1119 transitions. [2023-11-26 12:02:46,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 850 [2023-11-26 12:02:46,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 850 [2023-11-26 12:02:46,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 850 states and 1119 transitions. [2023-11-26 12:02:46,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:02:46,155 INFO L218 hiAutomatonCegarLoop]: Abstraction has 850 states and 1119 transitions. [2023-11-26 12:02:46,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 850 states and 1119 transitions. [2023-11-26 12:02:46,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 850 to 850. [2023-11-26 12:02:46,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 850 states, 850 states have (on average 1.316470588235294) internal successors, (1119), 849 states have internal predecessors, (1119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:46,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 850 states to 850 states and 1119 transitions. [2023-11-26 12:02:46,177 INFO L240 hiAutomatonCegarLoop]: Abstraction has 850 states and 1119 transitions. [2023-11-26 12:02:46,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:02:46,179 INFO L428 stractBuchiCegarLoop]: Abstraction has 850 states and 1119 transitions. [2023-11-26 12:02:46,180 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 12:02:46,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 850 states and 1119 transitions. [2023-11-26 12:02:46,186 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2023-11-26 12:02:46,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:46,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:46,187 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:46,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:46,189 INFO L748 eck$LassoCheckResult]: Stem: 6680#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 6681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6704#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6685#L258 assume !(1 == ~q_req_up~0); 6687#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6737#L273 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 6738#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6771#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6719#L311 assume !(0 == ~q_read_ev~0); 6720#L311-2 assume !(0 == ~q_write_ev~0); 6752#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6696#L66 assume !(1 == ~p_dw_pc~0); 6697#L66-2 assume !(2 == ~p_dw_pc~0); 6710#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 6732#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6733#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6726#L387 assume !(0 != activate_threads_~tmp~1#1); 6727#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6763#L95 assume !(1 == ~c_dr_pc~0); 6764#L95-2 assume !(2 == ~c_dr_pc~0); 6740#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 6676#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6677#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6688#L395 assume !(0 != activate_threads_~tmp___0~1#1); 6656#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6657#L329 assume !(1 == ~q_read_ev~0); 6691#L329-2 assume !(1 == ~q_write_ev~0); 6700#L334-1 assume { :end_inline_reset_delta_events } true; 6701#L491-2 [2023-11-26 12:02:46,190 INFO L750 eck$LassoCheckResult]: Loop: 6701#L491-2 assume !false; 6785#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6699#L435 assume !false; 6730#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6731#L291 assume !(0 == ~p_dw_st~0); 6645#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6647#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6788#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 7202#L415 assume !(0 != eval_~tmp___1~0#1); 6756#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6734#L258-3 assume !(1 == ~q_req_up~0); 6736#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6776#L311-3 assume !(0 == ~q_read_ev~0); 7417#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 6749#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6750#L66-3 assume !(1 == ~p_dw_pc~0); 6721#L66-5 assume !(2 == ~p_dw_pc~0); 6650#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 6651#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6652#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6741#L387-3 assume !(0 != activate_threads_~tmp~1#1); 6694#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6695#L95-3 assume !(1 == ~c_dr_pc~0); 6641#L95-5 assume !(2 == ~c_dr_pc~0); 6642#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 6789#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 7407#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7406#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 7405#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6708#L329-3 assume !(1 == ~q_read_ev~0); 6709#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 6765#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6724#L291-1 assume !(0 == ~p_dw_st~0); 6725#L295-1 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6772#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6770#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6753#L510 assume !(0 == start_simulation_~tmp~4#1); 6648#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6649#L291-2 assume !(0 == ~p_dw_st~0); 6678#L295-2 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6679#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6692#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6693#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6689#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6690#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6751#L523 assume !(0 != start_simulation_~tmp___0~3#1); 6701#L491-2 [2023-11-26 12:02:46,190 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:46,191 INFO L85 PathProgramCache]: Analyzing trace with hash -1649319439, now seen corresponding path program 1 times [2023-11-26 12:02:46,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:46,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183358686] [2023-11-26 12:02:46,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:46,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:46,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:46,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:46,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:46,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [183358686] [2023-11-26 12:02:46,230 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [183358686] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:46,230 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:46,230 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:02:46,231 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066998368] [2023-11-26 12:02:46,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:46,231 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:02:46,232 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:46,232 INFO L85 PathProgramCache]: Analyzing trace with hash -1954829134, now seen corresponding path program 1 times [2023-11-26 12:02:46,232 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:46,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184317808] [2023-11-26 12:02:46,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:46,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:46,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:46,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:46,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:46,339 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184317808] [2023-11-26 12:02:46,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184317808] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:46,339 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:46,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:02:46,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389265188] [2023-11-26 12:02:46,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:46,340 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:02:46,341 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:02:46,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:02:46,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:02:46,341 INFO L87 Difference]: Start difference. First operand 850 states and 1119 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:46,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:02:46,353 INFO L93 Difference]: Finished difference Result 806 states and 1065 transitions. [2023-11-26 12:02:46,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 806 states and 1065 transitions. [2023-11-26 12:02:46,360 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2023-11-26 12:02:46,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 806 states to 806 states and 1065 transitions. [2023-11-26 12:02:46,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 806 [2023-11-26 12:02:46,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 806 [2023-11-26 12:02:46,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 806 states and 1065 transitions. [2023-11-26 12:02:46,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:02:46,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 806 states and 1065 transitions. [2023-11-26 12:02:46,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 806 states and 1065 transitions. [2023-11-26 12:02:46,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 806 to 806. [2023-11-26 12:02:46,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 806 states, 806 states have (on average 1.3213399503722085) internal successors, (1065), 805 states have internal predecessors, (1065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:46,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 806 states to 806 states and 1065 transitions. [2023-11-26 12:02:46,390 INFO L240 hiAutomatonCegarLoop]: Abstraction has 806 states and 1065 transitions. [2023-11-26 12:02:46,390 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:02:46,391 INFO L428 stractBuchiCegarLoop]: Abstraction has 806 states and 1065 transitions. [2023-11-26 12:02:46,391 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 12:02:46,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 806 states and 1065 transitions. [2023-11-26 12:02:46,396 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2023-11-26 12:02:46,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:46,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:46,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:46,398 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:46,398 INFO L748 eck$LassoCheckResult]: Stem: 8342#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 8343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8370#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8349#L258 assume !(1 == ~q_req_up~0); 8351#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8409#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8410#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8469#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8387#L311 assume !(0 == ~q_read_ev~0); 8388#L311-2 assume !(0 == ~q_write_ev~0); 8456#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8360#L66 assume !(1 == ~p_dw_pc~0); 8361#L66-2 assume !(2 == ~p_dw_pc~0); 8476#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 8477#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8450#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8451#L387 assume !(0 != activate_threads_~tmp~1#1); 8460#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8461#L95 assume !(1 == ~c_dr_pc~0); 8462#L95-2 assume !(2 == ~c_dr_pc~0); 8463#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 8340#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8341#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8431#L395 assume !(0 != activate_threads_~tmp___0~1#1); 8432#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8354#L329 assume !(1 == ~q_read_ev~0); 8355#L329-2 assume !(1 == ~q_write_ev~0); 8402#L334-1 assume { :end_inline_reset_delta_events } true; 8931#L491-2 assume !false; 8755#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8753#L435 [2023-11-26 12:02:46,398 INFO L750 eck$LassoCheckResult]: Loop: 8753#L435 assume !false; 8751#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8748#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8745#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8744#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8743#L415 assume 0 != eval_~tmp___1~0#1; 8742#L415-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 8736#L424 assume !(0 != eval_~tmp~2#1); 8737#L420 assume !(0 == ~c_dr_st~0); 8753#L435 [2023-11-26 12:02:46,399 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:46,399 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 1 times [2023-11-26 12:02:46,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:46,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57306583] [2023-11-26 12:02:46,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:46,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:46,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,408 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:02:46,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:02:46,424 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:46,424 INFO L85 PathProgramCache]: Analyzing trace with hash 1094877041, now seen corresponding path program 1 times [2023-11-26 12:02:46,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:46,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112069439] [2023-11-26 12:02:46,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:46,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:46,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,430 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:02:46,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,436 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:02:46,436 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:46,437 INFO L85 PathProgramCache]: Analyzing trace with hash -1470124191, now seen corresponding path program 1 times [2023-11-26 12:02:46,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:46,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28723880] [2023-11-26 12:02:46,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:46,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:46,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:02:46,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:02:46,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:02:46,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [28723880] [2023-11-26 12:02:46,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [28723880] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:02:46,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:02:46,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:02:46,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884809894] [2023-11-26 12:02:46,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:02:46,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:02:46,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:02:46,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:02:46,534 INFO L87 Difference]: Start difference. First operand 806 states and 1065 transitions. cyclomatic complexity: 266 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:46,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:02:46,573 INFO L93 Difference]: Finished difference Result 922 states and 1209 transitions. [2023-11-26 12:02:46,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 922 states and 1209 transitions. [2023-11-26 12:02:46,581 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 850 [2023-11-26 12:02:46,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 922 states to 922 states and 1209 transitions. [2023-11-26 12:02:46,588 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 922 [2023-11-26 12:02:46,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 922 [2023-11-26 12:02:46,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 922 states and 1209 transitions. [2023-11-26 12:02:46,591 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:02:46,591 INFO L218 hiAutomatonCegarLoop]: Abstraction has 922 states and 1209 transitions. [2023-11-26 12:02:46,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 922 states and 1209 transitions. [2023-11-26 12:02:46,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 922 to 814. [2023-11-26 12:02:46,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 814 states, 814 states have (on average 1.3194103194103195) internal successors, (1074), 813 states have internal predecessors, (1074), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:02:46,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 814 states to 814 states and 1074 transitions. [2023-11-26 12:02:46,611 INFO L240 hiAutomatonCegarLoop]: Abstraction has 814 states and 1074 transitions. [2023-11-26 12:02:46,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:02:46,612 INFO L428 stractBuchiCegarLoop]: Abstraction has 814 states and 1074 transitions. [2023-11-26 12:02:46,612 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 12:02:46,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 814 states and 1074 transitions. [2023-11-26 12:02:46,617 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 743 [2023-11-26 12:02:46,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:02:46,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:02:46,618 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:46,619 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:02:46,619 INFO L748 eck$LassoCheckResult]: Stem: 10078#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 10079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10104#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10085#L258 assume !(1 == ~q_req_up~0); 10087#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10141#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 10142#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10204#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10118#L311 assume !(0 == ~q_read_ev~0); 10119#L311-2 assume !(0 == ~q_write_ev~0); 10188#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10095#L66 assume !(1 == ~p_dw_pc~0); 10096#L66-2 assume !(2 == ~p_dw_pc~0); 10238#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 10131#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10132#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10127#L387 assume !(0 != activate_threads_~tmp~1#1); 10128#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10173#L95 assume !(1 == ~c_dr_pc~0); 10174#L95-2 assume !(2 == ~c_dr_pc~0); 10143#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 10144#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10088#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10089#L395 assume !(0 != activate_threads_~tmp___0~1#1); 10056#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10057#L329 assume !(1 == ~q_read_ev~0); 10090#L329-2 assume !(1 == ~q_write_ev~0); 10400#L334-1 assume { :end_inline_reset_delta_events } true; 10399#L491-2 assume !false; 10397#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10377#L435 [2023-11-26 12:02:46,619 INFO L750 eck$LassoCheckResult]: Loop: 10377#L435 assume !false; 10395#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10393#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10391#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10389#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10387#L415 assume 0 != eval_~tmp___1~0#1; 10385#L415-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 10382#L424 assume !(0 != eval_~tmp~2#1); 10380#L420 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 10376#L439 assume !(0 != eval_~tmp___0~2#1); 10377#L435 [2023-11-26 12:02:46,620 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:46,620 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 2 times [2023-11-26 12:02:46,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:46,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294183326] [2023-11-26 12:02:46,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:46,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:46,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,628 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:02:46,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:02:46,641 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:46,641 INFO L85 PathProgramCache]: Analyzing trace with hash -418551845, now seen corresponding path program 1 times [2023-11-26 12:02:46,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:46,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2129168595] [2023-11-26 12:02:46,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:46,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:46,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,646 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:02:46,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:02:46,650 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:02:46,651 INFO L85 PathProgramCache]: Analyzing trace with hash 1670788587, now seen corresponding path program 1 times [2023-11-26 12:02:46,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:02:46,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043550175] [2023-11-26 12:02:46,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:02:46,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:02:46,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,660 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:02:46,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:46,689 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:02:47,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:47,781 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:02:47,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:02:47,944 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.11 12:02:47 BoogieIcfgContainer [2023-11-26 12:02:47,946 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-26 12:02:47,947 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-26 12:02:47,947 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-26 12:02:47,947 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-26 12:02:47,948 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:02:43" (3/4) ... [2023-11-26 12:02:47,951 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-26 12:02:48,062 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/witness.graphml [2023-11-26 12:02:48,062 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-26 12:02:48,063 INFO L158 Benchmark]: Toolchain (without parser) took 5796.87ms. Allocated memory was 119.5MB in the beginning and 184.5MB in the end (delta: 65.0MB). Free memory was 74.9MB in the beginning and 128.7MB in the end (delta: -53.7MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2023-11-26 12:02:48,063 INFO L158 Benchmark]: CDTParser took 0.26ms. Allocated memory is still 119.5MB. Free memory is still 94.5MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 12:02:48,063 INFO L158 Benchmark]: CACSL2BoogieTranslator took 382.79ms. Allocated memory is still 119.5MB. Free memory was 74.7MB in the beginning and 60.9MB in the end (delta: 13.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-26 12:02:48,064 INFO L158 Benchmark]: Boogie Procedure Inliner took 80.67ms. Allocated memory was 119.5MB in the beginning and 153.1MB in the end (delta: 33.6MB). Free memory was 60.9MB in the beginning and 123.6MB in the end (delta: -62.7MB). Peak memory consumption was 6.0MB. Max. memory is 16.1GB. [2023-11-26 12:02:48,064 INFO L158 Benchmark]: Boogie Preprocessor took 90.03ms. Allocated memory is still 153.1MB. Free memory was 123.6MB in the beginning and 123.8MB in the end (delta: -144.7kB). Peak memory consumption was 5.1MB. Max. memory is 16.1GB. [2023-11-26 12:02:48,064 INFO L158 Benchmark]: RCFGBuilder took 770.58ms. Allocated memory is still 153.1MB. Free memory was 123.8MB in the beginning and 101.1MB in the end (delta: 22.7MB). Peak memory consumption was 23.1MB. Max. memory is 16.1GB. [2023-11-26 12:02:48,065 INFO L158 Benchmark]: BuchiAutomizer took 4352.26ms. Allocated memory was 153.1MB in the beginning and 184.5MB in the end (delta: 31.5MB). Free memory was 101.1MB in the beginning and 133.9MB in the end (delta: -32.8MB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 12:02:48,065 INFO L158 Benchmark]: Witness Printer took 114.97ms. Allocated memory is still 184.5MB. Free memory was 132.9MB in the beginning and 128.7MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 12:02:48,069 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.26ms. Allocated memory is still 119.5MB. Free memory is still 94.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 382.79ms. Allocated memory is still 119.5MB. Free memory was 74.7MB in the beginning and 60.9MB in the end (delta: 13.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 80.67ms. Allocated memory was 119.5MB in the beginning and 153.1MB in the end (delta: 33.6MB). Free memory was 60.9MB in the beginning and 123.6MB in the end (delta: -62.7MB). Peak memory consumption was 6.0MB. Max. memory is 16.1GB. * Boogie Preprocessor took 90.03ms. Allocated memory is still 153.1MB. Free memory was 123.6MB in the beginning and 123.8MB in the end (delta: -144.7kB). Peak memory consumption was 5.1MB. Max. memory is 16.1GB. * RCFGBuilder took 770.58ms. Allocated memory is still 153.1MB. Free memory was 123.8MB in the beginning and 101.1MB in the end (delta: 22.7MB). Peak memory consumption was 23.1MB. Max. memory is 16.1GB. * BuchiAutomizer took 4352.26ms. Allocated memory was 153.1MB in the beginning and 184.5MB in the end (delta: 31.5MB). Free memory was 101.1MB in the beginning and 133.9MB in the end (delta: -32.8MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 114.97ms. Allocated memory is still 184.5MB. Free memory was 132.9MB in the beginning and 128.7MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 814 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.1s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 2.9s. Construction of modules took 0.3s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 9 MinimizatonAttempts, 799 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1947 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1947 mSDsluCounter, 3360 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1753 mSDsCounter, 76 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 243 IncrementalHoareTripleChecker+Invalid, 319 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 76 mSolverCounterUnsat, 1607 mSDtfsCounter, 243 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 410]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0, tmp___0=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 410]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0, tmp___0=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-26 12:02:48,151 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fde3f7d9-cd97-4398-a535-ad2aae53c2d1/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)