./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/array-examples/standard_sentinel-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/array-examples/standard_sentinel-2.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 590a845a219659d0ad58521e10c3551f2ec7e80ca70e994a8616abe765f6f296 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 10:43:42,294 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 10:43:42,358 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 10:43:42,363 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 10:43:42,364 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 10:43:42,389 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 10:43:42,390 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 10:43:42,391 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 10:43:42,392 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 10:43:42,392 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 10:43:42,393 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 10:43:42,393 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 10:43:42,394 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 10:43:42,394 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 10:43:42,395 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 10:43:42,395 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 10:43:42,396 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 10:43:42,396 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 10:43:42,397 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 10:43:42,397 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 10:43:42,398 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 10:43:42,398 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 10:43:42,399 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 10:43:42,399 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 10:43:42,399 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 10:43:42,400 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 10:43:42,400 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 10:43:42,401 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 10:43:42,401 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 10:43:42,401 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 10:43:42,402 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 10:43:42,402 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 10:43:42,402 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 10:43:42,403 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 10:43:42,403 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 10:43:42,403 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 10:43:42,404 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 10:43:42,404 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 10:43:42,404 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 590a845a219659d0ad58521e10c3551f2ec7e80ca70e994a8616abe765f6f296 [2023-11-26 10:43:42,692 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 10:43:42,714 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 10:43:42,717 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 10:43:42,718 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 10:43:42,719 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 10:43:42,720 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/array-examples/standard_sentinel-2.i [2023-11-26 10:43:45,929 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 10:43:46,119 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 10:43:46,120 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/sv-benchmarks/c/array-examples/standard_sentinel-2.i [2023-11-26 10:43:46,128 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/data/e70e5de4d/edd0259a4d2d489787c6ca28300d3e78/FLAG79d5fd39a [2023-11-26 10:43:46,141 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/data/e70e5de4d/edd0259a4d2d489787c6ca28300d3e78 [2023-11-26 10:43:46,144 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 10:43:46,145 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 10:43:46,147 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 10:43:46,147 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 10:43:46,153 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 10:43:46,154 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,155 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5b2a15e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46, skipping insertion in model container [2023-11-26 10:43:46,155 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,178 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 10:43:46,357 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:43:46,369 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 10:43:46,388 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:43:46,405 INFO L206 MainTranslator]: Completed translation [2023-11-26 10:43:46,405 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46 WrapperNode [2023-11-26 10:43:46,406 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 10:43:46,409 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 10:43:46,409 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 10:43:46,410 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 10:43:46,418 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,425 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,442 INFO L138 Inliner]: procedures = 16, calls = 14, calls flagged for inlining = 4, calls inlined = 4, statements flattened = 54 [2023-11-26 10:43:46,442 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 10:43:46,443 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 10:43:46,443 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 10:43:46,444 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 10:43:46,454 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,454 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,456 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,470 INFO L175 MemorySlicer]: Split 5 memory accesses to 2 slices as follows [2, 3]. 60 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 2 writes are split as follows [0, 2]. [2023-11-26 10:43:46,470 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,470 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,484 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,488 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,489 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,491 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,493 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 10:43:46,494 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 10:43:46,494 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 10:43:46,494 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 10:43:46,495 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (1/1) ... [2023-11-26 10:43:46,501 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:43:46,517 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:46,530 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:43:46,542 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 10:43:46,576 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 10:43:46,576 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 10:43:46,576 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2023-11-26 10:43:46,576 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2023-11-26 10:43:46,576 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2023-11-26 10:43:46,577 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2023-11-26 10:43:46,577 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 10:43:46,577 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 10:43:46,578 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2023-11-26 10:43:46,578 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2023-11-26 10:43:46,578 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2023-11-26 10:43:46,654 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 10:43:46,658 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 10:43:46,810 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 10:43:46,819 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 10:43:46,820 INFO L309 CfgBuilder]: Removed 2 assume(true) statements. [2023-11-26 10:43:46,821 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:43:46 BoogieIcfgContainer [2023-11-26 10:43:46,822 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 10:43:46,823 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 10:43:46,823 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 10:43:46,828 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 10:43:46,829 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:43:46,829 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 10:43:46" (1/3) ... [2023-11-26 10:43:46,830 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@49d0c7ce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:43:46, skipping insertion in model container [2023-11-26 10:43:46,831 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:43:46,831 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:43:46" (2/3) ... [2023-11-26 10:43:46,832 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@49d0c7ce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:43:46, skipping insertion in model container [2023-11-26 10:43:46,832 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:43:46,832 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:43:46" (3/3) ... [2023-11-26 10:43:46,834 INFO L332 chiAutomizerObserver]: Analyzing ICFG standard_sentinel-2.i [2023-11-26 10:43:46,900 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 10:43:46,900 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 10:43:46,901 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 10:43:46,901 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 10:43:46,901 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 10:43:46,901 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 10:43:46,902 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 10:43:46,902 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 10:43:46,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:46,929 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2023-11-26 10:43:46,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:46,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:46,936 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 10:43:46,936 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 10:43:46,937 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 10:43:46,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:46,939 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2023-11-26 10:43:46,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:46,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:46,941 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-26 10:43:46,941 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 10:43:46,950 INFO L748 eck$LassoCheckResult]: Stem: 14#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2); 5#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~nondet4#1, main_#t~post3#1, main_~i~0#1, main_#t~mem5#1, main_~i~1#1, main_~#a~0#1.base, main_~#a~0#1.offset, main_~marker~0#1, main_~pos~0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_#t~nondet1#1;main_~marker~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;havoc main_#t~nondet2#1;main_~pos~0#1 := main_#t~nondet2#1;havoc main_#t~nondet2#1;main_~i~0#1 := 0; 11#L20-3true [2023-11-26 10:43:46,950 INFO L750 eck$LassoCheckResult]: Loop: 11#L20-3true assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 12#L20-2true main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 11#L20-3true [2023-11-26 10:43:46,957 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:46,958 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2023-11-26 10:43:46,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:46,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131361312] [2023-11-26 10:43:46,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:46,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:47,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:47,074 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:47,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:47,104 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:47,107 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:47,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2023-11-26 10:43:47,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:47,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294505994] [2023-11-26 10:43:47,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:47,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:47,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:47,121 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:47,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:47,131 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:47,133 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:47,134 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2023-11-26 10:43:47,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:47,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213147946] [2023-11-26 10:43:47,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:47,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:47,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:47,169 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:47,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:47,190 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:47,620 INFO L210 LassoAnalysis]: Preferences: [2023-11-26 10:43:47,621 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-26 10:43:47,621 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-26 10:43:47,621 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-26 10:43:47,621 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-26 10:43:47,621 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:43:47,621 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-26 10:43:47,621 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-26 10:43:47,621 INFO L133 ssoRankerPreferences]: Filename of dumped script: standard_sentinel-2.i_Iteration1_Lasso [2023-11-26 10:43:47,622 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-26 10:43:47,622 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-26 10:43:47,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:47,649 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:47,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:47,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:47,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:47,837 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:47,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:47,842 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:47,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:47,848 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:47,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-26 10:43:48,087 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-26 10:43:48,091 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-26 10:43:48,093 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:43:48,094 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:48,104 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:43:48,111 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 10:43:48,124 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-26 10:43:48,125 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 10:43:48,125 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-26 10:43:48,126 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 10:43:48,126 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 10:43:48,126 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 10:43:48,129 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-26 10:43:48,129 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-26 10:43:48,144 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 10:43:48,150 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-26 10:43:48,151 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:43:48,151 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:48,157 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:43:48,206 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-26 10:43:48,209 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 10:43:48,225 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 10:43:48,226 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 10:43:48,226 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 10:43:48,226 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 10:43:48,236 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 10:43:48,237 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 10:43:48,264 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 10:43:48,273 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-26 10:43:48,274 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:43:48,275 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:48,277 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:43:48,314 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-26 10:43:48,315 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 10:43:48,329 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 10:43:48,329 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 10:43:48,330 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 10:43:48,330 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 10:43:48,335 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 10:43:48,335 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 10:43:48,348 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-26 10:43:48,352 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-26 10:43:48,353 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:43:48,353 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:48,354 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:43:48,366 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-26 10:43:48,379 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-26 10:43:48,380 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-26 10:43:48,381 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-26 10:43:48,381 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-26 10:43:48,381 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-26 10:43:48,395 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-26 10:43:48,396 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-26 10:43:48,411 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-26 10:43:48,448 INFO L443 ModelExtractionUtils]: Simplification made 8 calls to the SMT solver. [2023-11-26 10:43:48,449 INFO L444 ModelExtractionUtils]: 0 out of 13 variables were initially zero. Simplification set additionally 10 variables to zero. [2023-11-26 10:43:48,451 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:43:48,451 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:48,479 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:43:48,486 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-26 10:43:48,487 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-26 10:43:48,499 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2023-11-26 10:43:48,499 INFO L513 LassoAnalysis]: Proved termination. [2023-11-26 10:43:48,500 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#a~0#1.base)_1, ULTIMATE.start_main_~i~0#1) = 199999*v_rep(select #length ULTIMATE.start_main_~#a~0#1.base)_1 - 8*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2023-11-26 10:43:48,516 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-26 10:43:48,537 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2023-11-26 10:43:48,545 WARN L1572 BoogieBacktranslator]: Unfinished Backtranslation: ArrayAccessExpression #length[~#a~0!base] could not be translated [2023-11-26 10:43:48,567 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:48,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:48,585 INFO L262 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-26 10:43:48,587 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:43:48,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:48,605 INFO L262 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-26 10:43:48,605 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:43:48,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:48,702 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-26 10:43:48,702 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-26 10:43:48,708 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:48,802 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 49 transitions. Complement of second has 8 states. [2023-11-26 10:43:48,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2023-11-26 10:43:48,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:48,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 24 transitions. [2023-11-26 10:43:48,821 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 24 transitions. Stem has 2 letters. Loop has 2 letters. [2023-11-26 10:43:48,822 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 10:43:48,822 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 24 transitions. Stem has 4 letters. Loop has 2 letters. [2023-11-26 10:43:48,822 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 10:43:48,822 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 24 transitions. Stem has 2 letters. Loop has 4 letters. [2023-11-26 10:43:48,823 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-26 10:43:48,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 49 transitions. [2023-11-26 10:43:48,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:48,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 9 states and 11 transitions. [2023-11-26 10:43:48,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2023-11-26 10:43:48,834 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2023-11-26 10:43:48,834 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 11 transitions. [2023-11-26 10:43:48,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:48,835 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 11 transitions. [2023-11-26 10:43:48,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 11 transitions. [2023-11-26 10:43:48,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2023-11-26 10:43:48,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:48,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 11 transitions. [2023-11-26 10:43:48,867 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 11 transitions. [2023-11-26 10:43:48,867 INFO L428 stractBuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2023-11-26 10:43:48,868 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 10:43:48,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 11 transitions. [2023-11-26 10:43:48,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:48,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:48,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:48,870 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2023-11-26 10:43:48,870 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 10:43:48,871 INFO L748 eck$LassoCheckResult]: Stem: 115#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2); 116#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~nondet4#1, main_#t~post3#1, main_~i~0#1, main_#t~mem5#1, main_~i~1#1, main_~#a~0#1.base, main_~#a~0#1.offset, main_~marker~0#1, main_~pos~0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_#t~nondet1#1;main_~marker~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;havoc main_#t~nondet2#1;main_~pos~0#1 := main_#t~nondet2#1;havoc main_#t~nondet2#1;main_~i~0#1 := 0; 108#L20-3 assume !(main_~i~0#1 < 100000); 109#L20-4 havoc main_~i~0#1; 114#L25 assume main_~pos~0#1 >= 0 && main_~pos~0#1 < 100000;call write~int#1(main_~marker~0#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~pos~0#1, 4);main_~i~1#1 := 0; 113#L28-3 [2023-11-26 10:43:48,871 INFO L750 eck$LassoCheckResult]: Loop: 113#L28-3 call main_#t~mem5#1 := read~int#1(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~1#1, 4); 112#L28-1 assume !!(main_#t~mem5#1 != main_~marker~0#1);havoc main_#t~mem5#1;main_~i~1#1 := 1 + main_~i~1#1; 113#L28-3 [2023-11-26 10:43:48,876 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:48,876 INFO L85 PathProgramCache]: Analyzing trace with hash 28696936, now seen corresponding path program 1 times [2023-11-26 10:43:48,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:48,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456618635] [2023-11-26 10:43:48,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:48,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:48,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:49,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:49,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:49,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456618635] [2023-11-26 10:43:49,020 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456618635] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:43:49,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:43:49,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:43:49,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [478778690] [2023-11-26 10:43:49,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:43:49,027 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:43:49,027 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:49,028 INFO L85 PathProgramCache]: Analyzing trace with hash 1734, now seen corresponding path program 1 times [2023-11-26 10:43:49,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:49,028 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975014373] [2023-11-26 10:43:49,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:49,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:49,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:49,047 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:49,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:49,059 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:49,109 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:49,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:43:49,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:43:49,114 INFO L87 Difference]: Start difference. First operand 9 states and 11 transitions. cyclomatic complexity: 4 Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:49,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:49,130 INFO L93 Difference]: Finished difference Result 10 states and 11 transitions. [2023-11-26 10:43:49,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10 states and 11 transitions. [2023-11-26 10:43:49,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:49,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10 states to 10 states and 11 transitions. [2023-11-26 10:43:49,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-26 10:43:49,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2023-11-26 10:43:49,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 11 transitions. [2023-11-26 10:43:49,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:49,136 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10 states and 11 transitions. [2023-11-26 10:43:49,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 11 transitions. [2023-11-26 10:43:49,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 9. [2023-11-26 10:43:49,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:49,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2023-11-26 10:43:49,139 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2023-11-26 10:43:49,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:43:49,141 INFO L428 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2023-11-26 10:43:49,141 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 10:43:49,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2023-11-26 10:43:49,143 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:49,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:49,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:49,144 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:43:49,144 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 10:43:49,145 INFO L748 eck$LassoCheckResult]: Stem: 140#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2); 141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~nondet4#1, main_#t~post3#1, main_~i~0#1, main_#t~mem5#1, main_~i~1#1, main_~#a~0#1.base, main_~#a~0#1.offset, main_~marker~0#1, main_~pos~0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_#t~nondet1#1;main_~marker~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;havoc main_#t~nondet2#1;main_~pos~0#1 := main_#t~nondet2#1;havoc main_#t~nondet2#1;main_~i~0#1 := 0; 137#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 133#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 134#L20-3 assume !(main_~i~0#1 < 100000); 138#L20-4 havoc main_~i~0#1; 139#L25 assume main_~pos~0#1 >= 0 && main_~pos~0#1 < 100000;call write~int#1(main_~marker~0#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~pos~0#1, 4);main_~i~1#1 := 0; 136#L28-3 [2023-11-26 10:43:49,145 INFO L750 eck$LassoCheckResult]: Loop: 136#L28-3 call main_#t~mem5#1 := read~int#1(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~1#1, 4); 135#L28-1 assume !!(main_#t~mem5#1 != main_~marker~0#1);havoc main_#t~mem5#1;main_~i~1#1 := 1 + main_~i~1#1; 136#L28-3 [2023-11-26 10:43:49,145 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:49,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669542, now seen corresponding path program 1 times [2023-11-26 10:43:49,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:49,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106889155] [2023-11-26 10:43:49,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:49,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:49,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:49,235 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:49,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:49,235 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106889155] [2023-11-26 10:43:49,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106889155] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 10:43:49,236 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [901920701] [2023-11-26 10:43:49,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:49,237 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 10:43:49,237 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:49,238 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 10:43:49,248 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2023-11-26 10:43:49,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:49,307 INFO L262 TraceCheckSpWp]: Trace formula consists of 56 conjuncts, 3 conjunts are in the unsatisfiable core [2023-11-26 10:43:49,309 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:43:49,323 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:49,323 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 10:43:49,344 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:49,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [901920701] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 10:43:49,345 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 10:43:49,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2023-11-26 10:43:49,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870788541] [2023-11-26 10:43:49,346 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 10:43:49,346 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:43:49,347 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:49,347 INFO L85 PathProgramCache]: Analyzing trace with hash 1734, now seen corresponding path program 2 times [2023-11-26 10:43:49,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:49,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136802409] [2023-11-26 10:43:49,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:49,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:49,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:49,353 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:49,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:49,357 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:49,401 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:49,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2023-11-26 10:43:49,402 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2023-11-26 10:43:49,403 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 3 Second operand has 7 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:49,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:49,436 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2023-11-26 10:43:49,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2023-11-26 10:43:49,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:49,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2023-11-26 10:43:49,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-26 10:43:49,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2023-11-26 10:43:49,438 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2023-11-26 10:43:49,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:49,438 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2023-11-26 10:43:49,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2023-11-26 10:43:49,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2023-11-26 10:43:49,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:49,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2023-11-26 10:43:49,441 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2023-11-26 10:43:49,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-26 10:43:49,442 INFO L428 stractBuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2023-11-26 10:43:49,442 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 10:43:49,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2023-11-26 10:43:49,443 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:49,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:49,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:49,446 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1, 1] [2023-11-26 10:43:49,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 10:43:49,447 INFO L748 eck$LassoCheckResult]: Stem: 211#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2); 212#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~nondet4#1, main_#t~post3#1, main_~i~0#1, main_#t~mem5#1, main_~i~1#1, main_~#a~0#1.base, main_~#a~0#1.offset, main_~marker~0#1, main_~pos~0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_#t~nondet1#1;main_~marker~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;havoc main_#t~nondet2#1;main_~pos~0#1 := main_#t~nondet2#1;havoc main_#t~nondet2#1;main_~i~0#1 := 0; 203#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 204#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 205#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 206#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 207#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 217#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 216#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 215#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 214#L20-3 assume !(main_~i~0#1 < 100000); 213#L20-4 havoc main_~i~0#1; 210#L25 assume main_~pos~0#1 >= 0 && main_~pos~0#1 < 100000;call write~int#1(main_~marker~0#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~pos~0#1, 4);main_~i~1#1 := 0; 209#L28-3 [2023-11-26 10:43:49,447 INFO L750 eck$LassoCheckResult]: Loop: 209#L28-3 call main_#t~mem5#1 := read~int#1(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~1#1, 4); 208#L28-1 assume !!(main_#t~mem5#1 != main_~marker~0#1);havoc main_#t~mem5#1;main_~i~1#1 := 1 + main_~i~1#1; 209#L28-3 [2023-11-26 10:43:49,448 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:49,448 INFO L85 PathProgramCache]: Analyzing trace with hash 82232672, now seen corresponding path program 2 times [2023-11-26 10:43:49,448 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:49,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080965197] [2023-11-26 10:43:49,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:49,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:49,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:49,621 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:49,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:49,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080965197] [2023-11-26 10:43:49,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080965197] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 10:43:49,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1556634552] [2023-11-26 10:43:49,622 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-26 10:43:49,622 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 10:43:49,623 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:49,624 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 10:43:49,645 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2023-11-26 10:43:49,697 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-26 10:43:49,697 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 10:43:49,698 INFO L262 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-26 10:43:49,700 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:43:49,733 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:49,734 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 10:43:49,829 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:49,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1556634552] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 10:43:49,829 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 10:43:49,829 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2023-11-26 10:43:49,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269745507] [2023-11-26 10:43:49,830 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 10:43:49,831 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:43:49,832 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:49,832 INFO L85 PathProgramCache]: Analyzing trace with hash 1734, now seen corresponding path program 3 times [2023-11-26 10:43:49,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:49,833 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666058820] [2023-11-26 10:43:49,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:49,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:49,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:49,842 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:49,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:49,848 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:49,912 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:49,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2023-11-26 10:43:49,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2023-11-26 10:43:49,916 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 3 Second operand has 13 states, 13 states have (on average 2.0) internal successors, (26), 13 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:49,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:49,995 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2023-11-26 10:43:49,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2023-11-26 10:43:50,003 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:50,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2023-11-26 10:43:50,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-26 10:43:50,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2023-11-26 10:43:50,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2023-11-26 10:43:50,006 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:50,006 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2023-11-26 10:43:50,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2023-11-26 10:43:50,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2023-11-26 10:43:50,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:50,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2023-11-26 10:43:50,013 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2023-11-26 10:43:50,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-26 10:43:50,017 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2023-11-26 10:43:50,017 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 10:43:50,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2023-11-26 10:43:50,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:50,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:50,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:50,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1, 1] [2023-11-26 10:43:50,021 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 10:43:50,021 INFO L748 eck$LassoCheckResult]: Stem: 341#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2); 342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~nondet4#1, main_#t~post3#1, main_~i~0#1, main_#t~mem5#1, main_~i~1#1, main_~#a~0#1.base, main_~#a~0#1.offset, main_~marker~0#1, main_~pos~0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_#t~nondet1#1;main_~marker~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;havoc main_#t~nondet2#1;main_~pos~0#1 := main_#t~nondet2#1;havoc main_#t~nondet2#1;main_~i~0#1 := 0; 333#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 334#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 335#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 336#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 337#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 359#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 358#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 357#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 356#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 355#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 354#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 353#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 352#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 351#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 350#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 349#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 348#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 347#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 346#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 345#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 344#L20-3 assume !(main_~i~0#1 < 100000); 343#L20-4 havoc main_~i~0#1; 340#L25 assume main_~pos~0#1 >= 0 && main_~pos~0#1 < 100000;call write~int#1(main_~marker~0#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~pos~0#1, 4);main_~i~1#1 := 0; 339#L28-3 [2023-11-26 10:43:50,026 INFO L750 eck$LassoCheckResult]: Loop: 339#L28-3 call main_#t~mem5#1 := read~int#1(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~1#1, 4); 338#L28-1 assume !!(main_#t~mem5#1 != main_~marker~0#1);havoc main_#t~mem5#1;main_~i~1#1 := 1 + main_~i~1#1; 339#L28-3 [2023-11-26 10:43:50,041 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:50,041 INFO L85 PathProgramCache]: Analyzing trace with hash 1520933460, now seen corresponding path program 3 times [2023-11-26 10:43:50,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:50,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997008055] [2023-11-26 10:43:50,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:50,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:50,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:50,425 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:50,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:50,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [997008055] [2023-11-26 10:43:50,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [997008055] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 10:43:50,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1719810893] [2023-11-26 10:43:50,427 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-26 10:43:50,427 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 10:43:50,427 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:50,431 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 10:43:50,468 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2023-11-26 10:43:50,649 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2023-11-26 10:43:50,650 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 10:43:50,652 INFO L262 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 12 conjunts are in the unsatisfiable core [2023-11-26 10:43:50,655 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:43:50,715 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:50,715 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 10:43:51,012 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:51,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1719810893] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 10:43:51,012 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 10:43:51,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 25 [2023-11-26 10:43:51,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [341705541] [2023-11-26 10:43:51,013 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 10:43:51,014 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:43:51,014 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:51,014 INFO L85 PathProgramCache]: Analyzing trace with hash 1734, now seen corresponding path program 4 times [2023-11-26 10:43:51,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:51,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495632068] [2023-11-26 10:43:51,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:51,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:51,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:51,019 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:51,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:51,023 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:51,062 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:51,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2023-11-26 10:43:51,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2023-11-26 10:43:51,064 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 3 Second operand has 25 states, 25 states have (on average 2.0) internal successors, (50), 25 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:51,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:51,174 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions. [2023-11-26 10:43:51,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions. [2023-11-26 10:43:51,176 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:51,177 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions. [2023-11-26 10:43:51,177 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-26 10:43:51,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2023-11-26 10:43:51,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions. [2023-11-26 10:43:51,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:51,178 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2023-11-26 10:43:51,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions. [2023-11-26 10:43:51,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2023-11-26 10:43:51,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:51,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2023-11-26 10:43:51,184 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2023-11-26 10:43:51,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-26 10:43:51,185 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2023-11-26 10:43:51,185 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 10:43:51,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2023-11-26 10:43:51,186 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:51,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:51,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:51,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1, 1] [2023-11-26 10:43:51,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 10:43:51,189 INFO L748 eck$LassoCheckResult]: Stem: 591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2); 592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~nondet4#1, main_#t~post3#1, main_~i~0#1, main_#t~mem5#1, main_~i~1#1, main_~#a~0#1.base, main_~#a~0#1.offset, main_~marker~0#1, main_~pos~0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_#t~nondet1#1;main_~marker~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;havoc main_#t~nondet2#1;main_~pos~0#1 := main_#t~nondet2#1;havoc main_#t~nondet2#1;main_~i~0#1 := 0; 583#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 584#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 585#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 586#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 587#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 633#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 632#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 631#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 630#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 629#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 628#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 627#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 626#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 625#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 624#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 623#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 622#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 621#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 620#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 619#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 618#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 617#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 616#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 615#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 614#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 613#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 612#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 611#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 610#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 609#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 608#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 607#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 606#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 605#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 604#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 603#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 602#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 601#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 600#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 599#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 598#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 597#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 596#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 595#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 594#L20-3 assume !(main_~i~0#1 < 100000); 593#L20-4 havoc main_~i~0#1; 590#L25 assume main_~pos~0#1 >= 0 && main_~pos~0#1 < 100000;call write~int#1(main_~marker~0#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~pos~0#1, 4);main_~i~1#1 := 0; 589#L28-3 [2023-11-26 10:43:51,190 INFO L750 eck$LassoCheckResult]: Loop: 589#L28-3 call main_#t~mem5#1 := read~int#1(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~1#1, 4); 588#L28-1 assume !!(main_#t~mem5#1 != main_~marker~0#1);havoc main_#t~mem5#1;main_~i~1#1 := 1 + main_~i~1#1; 589#L28-3 [2023-11-26 10:43:51,190 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:51,190 INFO L85 PathProgramCache]: Analyzing trace with hash -96806340, now seen corresponding path program 4 times [2023-11-26 10:43:51,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:51,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844140846] [2023-11-26 10:43:51,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:51,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:51,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:52,113 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:52,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:52,114 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1844140846] [2023-11-26 10:43:52,114 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1844140846] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 10:43:52,114 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [679637250] [2023-11-26 10:43:52,114 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-26 10:43:52,114 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 10:43:52,115 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:52,119 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 10:43:52,145 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2023-11-26 10:43:52,266 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-26 10:43:52,266 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 10:43:52,269 INFO L262 TraceCheckSpWp]: Trace formula consists of 287 conjuncts, 24 conjunts are in the unsatisfiable core [2023-11-26 10:43:52,273 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:43:52,405 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:52,406 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 10:43:53,367 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:53,367 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [679637250] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 10:43:53,367 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 10:43:53,367 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 49 [2023-11-26 10:43:53,368 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105405835] [2023-11-26 10:43:53,368 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 10:43:53,368 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:43:53,369 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:53,369 INFO L85 PathProgramCache]: Analyzing trace with hash 1734, now seen corresponding path program 5 times [2023-11-26 10:43:53,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:53,369 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816391594] [2023-11-26 10:43:53,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:53,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:53,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:53,376 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:43:53,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:43:53,381 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:43:53,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:43:53,426 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2023-11-26 10:43:53,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2023-11-26 10:43:53,428 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 3 Second operand has 49 states, 49 states have (on average 2.0) internal successors, (98), 49 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:53,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:43:53,647 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2023-11-26 10:43:53,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions. [2023-11-26 10:43:53,649 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:53,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions. [2023-11-26 10:43:53,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-26 10:43:53,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2023-11-26 10:43:53,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions. [2023-11-26 10:43:53,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:43:53,652 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2023-11-26 10:43:53,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions. [2023-11-26 10:43:53,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2023-11-26 10:43:53,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:43:53,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2023-11-26 10:43:53,664 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2023-11-26 10:43:53,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2023-11-26 10:43:53,668 INFO L428 stractBuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2023-11-26 10:43:53,668 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 10:43:53,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2023-11-26 10:43:53,670 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:43:53,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:43:53,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:43:53,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1, 1] [2023-11-26 10:43:53,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 10:43:53,674 INFO L748 eck$LassoCheckResult]: Stem: 1081#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2); 1082#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~nondet4#1, main_#t~post3#1, main_~i~0#1, main_#t~mem5#1, main_~i~1#1, main_~#a~0#1.base, main_~#a~0#1.offset, main_~marker~0#1, main_~pos~0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_#t~nondet1#1;main_~marker~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;havoc main_#t~nondet2#1;main_~pos~0#1 := main_#t~nondet2#1;havoc main_#t~nondet2#1;main_~i~0#1 := 0; 1073#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1074#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1075#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1076#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1077#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1171#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1170#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1169#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1168#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1167#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1166#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1165#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1164#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1163#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1162#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1161#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1160#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1159#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1158#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1157#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1156#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1155#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1154#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1153#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1152#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1151#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1150#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1149#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1148#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1147#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1146#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1145#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1144#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1143#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1142#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1141#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1140#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1139#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1138#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1137#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1136#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1135#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1134#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1133#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1132#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1131#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1130#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1129#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1128#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1127#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1126#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1125#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1124#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1123#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1122#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1121#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1120#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1119#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1118#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1117#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1116#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1115#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1114#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1113#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1112#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1111#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1110#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1109#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1108#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1107#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1106#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1105#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1104#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1103#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1102#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1101#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1100#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1099#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1098#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1097#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1096#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1095#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1094#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1093#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1092#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1091#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1090#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1089#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1088#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1087#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1086#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 1085#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1084#L20-3 assume !(main_~i~0#1 < 100000); 1083#L20-4 havoc main_~i~0#1; 1080#L25 assume main_~pos~0#1 >= 0 && main_~pos~0#1 < 100000;call write~int#1(main_~marker~0#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~pos~0#1, 4);main_~i~1#1 := 0; 1079#L28-3 [2023-11-26 10:43:53,675 INFO L750 eck$LassoCheckResult]: Loop: 1079#L28-3 call main_#t~mem5#1 := read~int#1(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~1#1, 4); 1078#L28-1 assume !!(main_#t~mem5#1 != main_~marker~0#1);havoc main_#t~mem5#1;main_~i~1#1 := 1 + main_~i~1#1; 1079#L28-3 [2023-11-26 10:43:53,675 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:43:53,675 INFO L85 PathProgramCache]: Analyzing trace with hash -21777908, now seen corresponding path program 5 times [2023-11-26 10:43:53,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:43:53,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582084075] [2023-11-26 10:43:53,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:43:53,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:43:53,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:43:56,424 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:43:56,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:43:56,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582084075] [2023-11-26 10:43:56,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582084075] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 10:43:56,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [966508909] [2023-11-26 10:43:56,425 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-26 10:43:56,425 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 10:43:56,426 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:43:56,429 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 10:43:56,446 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2023-11-26 10:44:01,212 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2023-11-26 10:44:01,212 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-26 10:44:01,220 INFO L262 TraceCheckSpWp]: Trace formula consists of 551 conjuncts, 48 conjunts are in the unsatisfiable core [2023-11-26 10:44:01,226 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-26 10:44:01,411 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:01,412 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-26 10:44:05,078 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:05,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [966508909] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-26 10:44:05,078 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-26 10:44:05,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 97 [2023-11-26 10:44:05,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596250773] [2023-11-26 10:44:05,079 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-26 10:44:05,080 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:05,080 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:05,080 INFO L85 PathProgramCache]: Analyzing trace with hash 1734, now seen corresponding path program 6 times [2023-11-26 10:44:05,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:05,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534751421] [2023-11-26 10:44:05,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:05,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:05,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:05,086 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:05,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:05,090 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:05,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:05,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2023-11-26 10:44:05,139 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2023-11-26 10:44:05,140 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 3 Second operand has 97 states, 97 states have (on average 2.0) internal successors, (194), 97 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:05,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:05,694 INFO L93 Difference]: Finished difference Result 195 states and 196 transitions. [2023-11-26 10:44:05,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 196 transitions. [2023-11-26 10:44:05,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:44:05,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 196 transitions. [2023-11-26 10:44:05,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-26 10:44:05,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2023-11-26 10:44:05,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 196 transitions. [2023-11-26 10:44:05,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:05,702 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2023-11-26 10:44:05,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 196 transitions. [2023-11-26 10:44:05,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2023-11-26 10:44:05,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.005128205128205) internal successors, (196), 194 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:05,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 196 transitions. [2023-11-26 10:44:05,713 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2023-11-26 10:44:05,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2023-11-26 10:44:05,715 INFO L428 stractBuchiCegarLoop]: Abstraction has 195 states and 196 transitions. [2023-11-26 10:44:05,715 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 10:44:05,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 196 transitions. [2023-11-26 10:44:05,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-26 10:44:05,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:05,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:05,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 94, 1, 1, 1, 1, 1] [2023-11-26 10:44:05,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-26 10:44:05,729 INFO L748 eck$LassoCheckResult]: Stem: 2051#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2); 2052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~nondet4#1, main_#t~post3#1, main_~i~0#1, main_#t~mem5#1, main_~i~1#1, main_~#a~0#1.base, main_~#a~0#1.offset, main_~marker~0#1, main_~pos~0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_#t~nondet1#1;main_~marker~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;havoc main_#t~nondet2#1;main_~pos~0#1 := main_#t~nondet2#1;havoc main_#t~nondet2#1;main_~i~0#1 := 0; 2043#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2044#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2045#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2046#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2047#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2237#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2236#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2235#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2234#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2233#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2232#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2231#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2230#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2229#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2228#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2227#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2226#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2225#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2224#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2223#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2222#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2221#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2220#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2219#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2218#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2217#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2216#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2215#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2214#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2213#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2212#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2211#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2210#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2209#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2208#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2207#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2206#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2205#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2204#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2203#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2202#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2201#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2200#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2199#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2198#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2197#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2196#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2195#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2194#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2193#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2192#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2191#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2190#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2189#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2188#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2187#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2186#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2185#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2184#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2183#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2182#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2181#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2180#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2179#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2178#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2177#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2176#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2175#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2174#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2173#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2172#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2171#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2170#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2169#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2168#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2167#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2166#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2165#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2164#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2163#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2162#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2161#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2160#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2159#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2158#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2157#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2156#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2155#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2154#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2153#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2152#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2151#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2150#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2149#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2148#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2147#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2146#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2145#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2144#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2143#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2142#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2141#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2140#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2139#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2138#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2137#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2136#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2135#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2134#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2133#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2132#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2131#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2130#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2129#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2128#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2127#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2126#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2125#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2124#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2123#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2122#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2121#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2120#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2119#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2118#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2117#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2116#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2115#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2114#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2113#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2112#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2111#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2110#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2109#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2108#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2107#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2106#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2105#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2104#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2103#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2102#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2101#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2100#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2099#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2098#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2097#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2096#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2095#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2094#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2093#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2092#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2091#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2090#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2089#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2088#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2087#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2086#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2085#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2084#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2083#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2082#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2081#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2080#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2079#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2078#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2077#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2076#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2075#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2074#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2073#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2072#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2071#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2070#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2069#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2068#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2067#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2066#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2065#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2064#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2063#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2062#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2061#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2060#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2059#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2058#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2057#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2056#L20-3 assume !!(main_~i~0#1 < 100000);havoc main_#t~nondet4#1;call write~int#1(main_#t~nondet4#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet4#1; 2055#L20-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2054#L20-3 assume !(main_~i~0#1 < 100000); 2053#L20-4 havoc main_~i~0#1; 2050#L25 assume main_~pos~0#1 >= 0 && main_~pos~0#1 < 100000;call write~int#1(main_~marker~0#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~pos~0#1, 4);main_~i~1#1 := 0; 2049#L28-3 [2023-11-26 10:44:05,729 INFO L750 eck$LassoCheckResult]: Loop: 2049#L28-3 call main_#t~mem5#1 := read~int#1(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~1#1, 4); 2048#L28-1 assume !!(main_#t~mem5#1 != main_~marker~0#1);havoc main_#t~mem5#1;main_~i~1#1 := 1 + main_~i~1#1; 2049#L28-3 [2023-11-26 10:44:05,730 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:05,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1766769068, now seen corresponding path program 6 times [2023-11-26 10:44:05,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:05,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248935637] [2023-11-26 10:44:05,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:05,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:05,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:14,181 INFO L134 CoverageAnalysis]: Checked inductivity of 8836 backedges. 0 proven. 8836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:14,182 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:14,182 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248935637] [2023-11-26 10:44:14,182 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248935637] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-26 10:44:14,182 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1877659891] [2023-11-26 10:44:14,182 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-26 10:44:14,183 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-26 10:44:14,183 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:44:14,192 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-26 10:44:14,203 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e31ed915-3dfc-4f6b-a6cc-55dbb25b1f62/bin/uautomizer-verify-VRDe98Ueme/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process