./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 12:04:57,028 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 12:04:57,216 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 12:04:57,231 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 12:04:57,232 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 12:04:57,292 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 12:04:57,296 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 12:04:57,297 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 12:04:57,298 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 12:04:57,305 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 12:04:57,306 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 12:04:57,307 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 12:04:57,307 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 12:04:57,310 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 12:04:57,311 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 12:04:57,312 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 12:04:57,312 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 12:04:57,313 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 12:04:57,313 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 12:04:57,314 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 12:04:57,315 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 12:04:57,318 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 12:04:57,319 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 12:04:57,319 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 12:04:57,320 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 12:04:57,321 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 12:04:57,321 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 12:04:57,322 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 12:04:57,322 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 12:04:57,323 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 12:04:57,325 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 12:04:57,325 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 12:04:57,326 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 12:04:57,326 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 12:04:57,326 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 12:04:57,327 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 12:04:57,327 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 12:04:57,328 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 12:04:57,328 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 [2023-11-26 12:04:57,704 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 12:04:57,755 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 12:04:57,759 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 12:04:57,760 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 12:04:57,761 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 12:04:57,763 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2023-11-26 12:05:00,821 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 12:05:01,194 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 12:05:01,195 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2023-11-26 12:05:01,212 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/data/ecbe54c45/4f0b285227984d8db491c96b8a03d89c/FLAG147aa8ab4 [2023-11-26 12:05:01,230 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/data/ecbe54c45/4f0b285227984d8db491c96b8a03d89c [2023-11-26 12:05:01,233 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 12:05:01,235 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 12:05:01,237 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 12:05:01,238 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 12:05:01,244 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 12:05:01,246 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,247 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1b9863ba and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01, skipping insertion in model container [2023-11-26 12:05:01,248 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,301 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 12:05:01,565 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:05:01,586 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 12:05:01,660 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 12:05:01,697 INFO L206 MainTranslator]: Completed translation [2023-11-26 12:05:01,698 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01 WrapperNode [2023-11-26 12:05:01,698 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 12:05:01,700 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 12:05:01,700 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 12:05:01,700 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 12:05:01,710 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,740 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,814 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 63, statements flattened = 822 [2023-11-26 12:05:01,816 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 12:05:01,816 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 12:05:01,817 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 12:05:01,817 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 12:05:01,832 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,834 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,850 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,879 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 12:05:01,880 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,880 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,898 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,914 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,917 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,922 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,929 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 12:05:01,931 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 12:05:01,931 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 12:05:01,931 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 12:05:01,937 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (1/1) ... [2023-11-26 12:05:01,948 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 12:05:01,978 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 12:05:02,008 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 12:05:02,035 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 12:05:02,056 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 12:05:02,056 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 12:05:02,056 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 12:05:02,056 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 12:05:02,151 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 12:05:02,154 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 12:05:03,138 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 12:05:03,178 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 12:05:03,181 INFO L309 CfgBuilder]: Removed 6 assume(true) statements. [2023-11-26 12:05:03,184 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:05:03 BoogieIcfgContainer [2023-11-26 12:05:03,184 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 12:05:03,186 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 12:05:03,186 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 12:05:03,191 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 12:05:03,192 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:05:03,192 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 12:05:01" (1/3) ... [2023-11-26 12:05:03,193 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@332b06cc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:05:03, skipping insertion in model container [2023-11-26 12:05:03,194 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:05:03,196 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:05:01" (2/3) ... [2023-11-26 12:05:03,199 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@332b06cc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 12:05:03, skipping insertion in model container [2023-11-26 12:05:03,200 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 12:05:03,200 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:05:03" (3/3) ... [2023-11-26 12:05:03,203 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-2.c [2023-11-26 12:05:03,288 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 12:05:03,288 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 12:05:03,289 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 12:05:03,289 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 12:05:03,289 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 12:05:03,289 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 12:05:03,289 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 12:05:03,290 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 12:05:03,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:03,342 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 270 [2023-11-26 12:05:03,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:03,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:03,354 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:03,355 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:03,355 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 12:05:03,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:03,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 270 [2023-11-26 12:05:03,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:03,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:03,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:03,381 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:03,390 INFO L748 eck$LassoCheckResult]: Stem: 205#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 222#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 326#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 217#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114#L292true assume !(1 == ~m_i~0);~m_st~0 := 2; 229#L292-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 207#L297-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 190#L302-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 198#L307-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 261#L429true assume !(0 == ~M_E~0); 56#L429-2true assume !(0 == ~T1_E~0); 150#L434-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 230#L439-1true assume !(0 == ~T3_E~0); 174#L444-1true assume !(0 == ~E_M~0); 278#L449-1true assume !(0 == ~E_1~0); 58#L454-1true assume !(0 == ~E_2~0); 304#L459-1true assume !(0 == ~E_3~0); 36#L464-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 297#L208true assume 1 == ~m_pc~0; 302#L209true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 329#L219true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176#is_master_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 50#L531true assume !(0 != activate_threads_~tmp~1#1); 137#L531-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121#L227true assume !(1 == ~t1_pc~0); 49#L227-2true is_transmit1_triggered_~__retres1~1#1 := 0; 199#L238true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 57#L539true assume !(0 != activate_threads_~tmp___0~0#1); 145#L539-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74#L246true assume 1 == ~t2_pc~0; 134#L247true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 156#L257true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 327#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 211#L547true assume !(0 != activate_threads_~tmp___1~0#1); 239#L547-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81#L265true assume !(1 == ~t3_pc~0); 311#L265-2true is_transmit3_triggered_~__retres1~3#1 := 0; 3#L276true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 325#L555true assume !(0 != activate_threads_~tmp___2~0#1); 63#L555-2true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 202#L477true assume !(1 == ~M_E~0); 267#L477-2true assume !(1 == ~T1_E~0); 223#L482-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 172#L487-1true assume !(1 == ~T3_E~0); 257#L492-1true assume !(1 == ~E_M~0); 40#L497-1true assume !(1 == ~E_1~0); 144#L502-1true assume !(1 == ~E_2~0); 30#L507-1true assume !(1 == ~E_3~0); 118#L512-1true assume { :end_inline_reset_delta_events } true; 194#L678-2true [2023-11-26 12:05:03,392 INFO L750 eck$LassoCheckResult]: Loop: 194#L678-2true assume !false; 286#L679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 308#L404-1true assume !true; 106#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 146#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 269#L429-3true assume 0 == ~M_E~0;~M_E~0 := 1; 330#L429-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 192#L434-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 236#L439-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 61#L444-3true assume 0 == ~E_M~0;~E_M~0 := 1; 68#L449-3true assume 0 == ~E_1~0;~E_1~0 := 1; 92#L454-3true assume !(0 == ~E_2~0); 241#L459-3true assume 0 == ~E_3~0;~E_3~0 := 1; 59#L464-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 252#L208-15true assume 1 == ~m_pc~0; 281#L209-5true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 250#L219-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96#is_master_triggered_returnLabel#6true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 158#L531-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69#L531-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 290#L227-15true assume 1 == ~t1_pc~0; 318#L228-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 242#L238-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 208#L539-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 189#L539-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175#L246-15true assume 1 == ~t2_pc~0; 9#L247-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 254#L257-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 279#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 313#L547-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55#L547-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203#L265-15true assume !(1 == ~t3_pc~0); 271#L265-17true is_transmit3_triggered_~__retres1~3#1 := 0; 130#L276-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86#L555-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 218#L555-17true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 260#L477-3true assume 1 == ~M_E~0;~M_E~0 := 2; 180#L477-5true assume !(1 == ~T1_E~0); 266#L482-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 93#L487-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 54#L492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 289#L497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 142#L502-3true assume 1 == ~E_2~0;~E_2~0 := 2; 185#L507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 109#L512-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32#L320-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13#L342-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 282#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 210#L697true assume !(0 == start_simulation_~tmp~3#1); 2#L697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 258#L320-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 79#L342-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 41#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 328#L652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 200#L659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 162#stop_simulation_returnLabel#1true start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 80#L710true assume !(0 != start_simulation_~tmp___0~1#1); 194#L678-2true [2023-11-26 12:05:03,400 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:03,400 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2023-11-26 12:05:03,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:03,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094198806] [2023-11-26 12:05:03,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:03,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:03,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:03,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:03,785 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:03,786 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094198806] [2023-11-26 12:05:03,787 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094198806] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:03,787 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:03,787 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:03,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964489211] [2023-11-26 12:05:03,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:03,797 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:05:03,800 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:03,800 INFO L85 PathProgramCache]: Analyzing trace with hash 1122762879, now seen corresponding path program 1 times [2023-11-26 12:05:03,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:03,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033453487] [2023-11-26 12:05:03,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:03,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:03,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:03,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:03,905 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:03,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033453487] [2023-11-26 12:05:03,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1033453487] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:03,906 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:03,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:05:03,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951622772] [2023-11-26 12:05:03,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:03,909 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:03,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:03,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:03,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:03,969 INFO L87 Difference]: Start difference. First operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:04,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:04,057 INFO L93 Difference]: Finished difference Result 327 states and 485 transitions. [2023-11-26 12:05:04,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 485 transitions. [2023-11-26 12:05:04,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-26 12:05:04,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 322 states and 480 transitions. [2023-11-26 12:05:04,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2023-11-26 12:05:04,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2023-11-26 12:05:04,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 480 transitions. [2023-11-26 12:05:04,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:04,093 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 480 transitions. [2023-11-26 12:05:04,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 480 transitions. [2023-11-26 12:05:04,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2023-11-26 12:05:04,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.4906832298136645) internal successors, (480), 321 states have internal predecessors, (480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:04,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 480 transitions. [2023-11-26 12:05:04,221 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 480 transitions. [2023-11-26 12:05:04,223 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:04,231 INFO L428 stractBuchiCegarLoop]: Abstraction has 322 states and 480 transitions. [2023-11-26 12:05:04,232 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 12:05:04,232 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 480 transitions. [2023-11-26 12:05:04,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-26 12:05:04,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:04,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:04,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:04,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:04,248 INFO L748 eck$LassoCheckResult]: Stem: 949#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 962#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 960#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 867#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 868#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 951#L297-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 937#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 938#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 945#L429 assume !(0 == ~M_E~0); 771#L429-2 assume !(0 == ~T1_E~0); 772#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 899#L439-1 assume !(0 == ~T3_E~0); 920#L444-1 assume !(0 == ~E_M~0); 921#L449-1 assume !(0 == ~E_1~0); 774#L454-1 assume !(0 == ~E_2~0); 775#L459-1 assume !(0 == ~E_3~0); 732#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 733#L208 assume 1 == ~m_pc~0; 984#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 986#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 923#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 759#L531 assume !(0 != activate_threads_~tmp~1#1); 760#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 872#L227 assume !(1 == ~t1_pc~0); 757#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 758#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 745#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 746#L539 assume !(0 != activate_threads_~tmp___0~0#1); 773#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 806#L246 assume 1 == ~t2_pc~0; 807#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 888#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 903#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 954#L547 assume !(0 != activate_threads_~tmp___1~0#1); 955#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 820#L265 assume !(1 == ~t3_pc~0); 694#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 667#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 668#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 695#L555 assume !(0 != activate_threads_~tmp___2~0#1); 788#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 789#L477 assume !(1 == ~M_E~0); 948#L477-2 assume !(1 == ~T1_E~0); 963#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 916#L487-1 assume !(1 == ~T3_E~0); 917#L492-1 assume !(1 == ~E_M~0); 743#L497-1 assume !(1 == ~E_1~0); 744#L502-1 assume !(1 == ~E_2~0); 722#L507-1 assume !(1 == ~E_3~0); 723#L512-1 assume { :end_inline_reset_delta_events } true; 817#L678-2 [2023-11-26 12:05:04,249 INFO L750 eck$LassoCheckResult]: Loop: 817#L678-2 assume !false; 943#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 956#L404-1 assume !false; 871#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 852#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 707#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 696#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 697#L357 assume !(0 != eval_~tmp~0#1); 795#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 858#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 897#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 977#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 939#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 940#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 781#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 782#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 796#L454-3 assume !(0 == ~E_2~0); 835#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 776#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 777#L208-15 assume !(1 == ~m_pc~0); 925#L208-17 is_master_triggered_~__retres1~0#1 := 0; 926#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 842#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 843#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 797#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 798#L227-15 assume !(1 == ~t1_pc~0); 979#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 969#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 804#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 805#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 936#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 922#L246-15 assume 1 == ~t2_pc~0; 675#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 676#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 974#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 981#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 769#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 770#L265-15 assume !(1 == ~t3_pc~0); 849#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 848#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 880#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 825#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 826#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 959#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 927#L477-5 assume !(1 == ~T1_E~0); 928#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 834#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 765#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 766#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 893#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 894#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 860#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 726#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 686#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 687#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 952#L697 assume !(0 == start_simulation_~tmp~3#1); 665#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 666#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 815#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 738#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 739#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 946#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 905#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 816#L710 assume !(0 != start_simulation_~tmp___0~1#1); 817#L678-2 [2023-11-26 12:05:04,249 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:04,250 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2023-11-26 12:05:04,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:04,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715045163] [2023-11-26 12:05:04,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:04,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:04,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:04,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:04,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:04,383 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715045163] [2023-11-26 12:05:04,383 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [715045163] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:04,383 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:04,384 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:04,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247840825] [2023-11-26 12:05:04,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:04,385 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:05:04,385 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:04,386 INFO L85 PathProgramCache]: Analyzing trace with hash 1981164799, now seen corresponding path program 1 times [2023-11-26 12:05:04,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:04,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104710955] [2023-11-26 12:05:04,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:04,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:04,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:04,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:04,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:04,545 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104710955] [2023-11-26 12:05:04,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2104710955] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:04,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:04,546 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:04,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385608362] [2023-11-26 12:05:04,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:04,547 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:04,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:04,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:04,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:04,549 INFO L87 Difference]: Start difference. First operand 322 states and 480 transitions. cyclomatic complexity: 159 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:04,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:04,587 INFO L93 Difference]: Finished difference Result 322 states and 479 transitions. [2023-11-26 12:05:04,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 479 transitions. [2023-11-26 12:05:04,591 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-26 12:05:04,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 322 states and 479 transitions. [2023-11-26 12:05:04,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2023-11-26 12:05:04,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2023-11-26 12:05:04,596 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 479 transitions. [2023-11-26 12:05:04,605 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:04,605 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 479 transitions. [2023-11-26 12:05:04,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 479 transitions. [2023-11-26 12:05:04,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2023-11-26 12:05:04,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.4875776397515528) internal successors, (479), 321 states have internal predecessors, (479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:04,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 479 transitions. [2023-11-26 12:05:04,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 479 transitions. [2023-11-26 12:05:04,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:04,641 INFO L428 stractBuchiCegarLoop]: Abstraction has 322 states and 479 transitions. [2023-11-26 12:05:04,642 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 12:05:04,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 479 transitions. [2023-11-26 12:05:04,645 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-26 12:05:04,645 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:04,645 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:04,647 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:04,647 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:04,648 INFO L748 eck$LassoCheckResult]: Stem: 1600#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1614#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1611#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1520#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 1521#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1602#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1588#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1589#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1596#L429 assume !(0 == ~M_E~0); 1422#L429-2 assume !(0 == ~T1_E~0); 1423#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1550#L439-1 assume !(0 == ~T3_E~0); 1571#L444-1 assume !(0 == ~E_M~0); 1572#L449-1 assume !(0 == ~E_1~0); 1427#L454-1 assume !(0 == ~E_2~0); 1428#L459-1 assume !(0 == ~E_3~0); 1383#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1384#L208 assume 1 == ~m_pc~0; 1635#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1637#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1574#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1410#L531 assume !(0 != activate_threads_~tmp~1#1); 1411#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1524#L227 assume !(1 == ~t1_pc~0); 1408#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1409#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1399#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1400#L539 assume !(0 != activate_threads_~tmp___0~0#1); 1424#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1455#L246 assume 1 == ~t2_pc~0; 1456#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1539#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1554#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1605#L547 assume !(0 != activate_threads_~tmp___1~0#1); 1606#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1469#L265 assume !(1 == ~t3_pc~0); 1345#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1318#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1319#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1346#L555 assume !(0 != activate_threads_~tmp___2~0#1); 1436#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1437#L477 assume !(1 == ~M_E~0); 1599#L477-2 assume !(1 == ~T1_E~0); 1613#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1567#L487-1 assume !(1 == ~T3_E~0); 1568#L492-1 assume !(1 == ~E_M~0); 1389#L497-1 assume !(1 == ~E_1~0); 1390#L502-1 assume !(1 == ~E_2~0); 1373#L507-1 assume !(1 == ~E_3~0); 1374#L512-1 assume { :end_inline_reset_delta_events } true; 1468#L678-2 [2023-11-26 12:05:04,648 INFO L750 eck$LassoCheckResult]: Loop: 1468#L678-2 assume !false; 1592#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1607#L404-1 assume !false; 1522#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1497#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1358#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1347#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1348#L357 assume !(0 != eval_~tmp~0#1); 1444#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1509#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1546#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1628#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1590#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1591#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1432#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1433#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1447#L454-3 assume !(0 == ~E_2~0); 1485#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1425#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1426#L208-15 assume !(1 == ~m_pc~0); 1576#L208-17 is_master_triggered_~__retres1~0#1 := 0; 1577#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1493#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1494#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1448#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1449#L227-15 assume 1 == ~t1_pc~0; 1633#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1620#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1458#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1459#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1587#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1573#L246-15 assume 1 == ~t2_pc~0; 1330#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1331#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1625#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1632#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1420#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1421#L265-15 assume 1 == ~t3_pc~0; 1499#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1500#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1534#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1477#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1478#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1610#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1578#L477-5 assume !(1 == ~T1_E~0); 1579#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1486#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1418#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1419#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1544#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1545#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1511#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1377#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1339#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1604#L697 assume !(0 == start_simulation_~tmp~3#1); 1316#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1317#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1466#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1391#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 1392#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1597#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1556#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1467#L710 assume !(0 != start_simulation_~tmp___0~1#1); 1468#L678-2 [2023-11-26 12:05:04,649 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:04,649 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2023-11-26 12:05:04,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:04,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421501390] [2023-11-26 12:05:04,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:04,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:04,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:04,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:04,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:04,712 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421501390] [2023-11-26 12:05:04,712 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421501390] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:04,712 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:04,712 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:04,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1630187100] [2023-11-26 12:05:04,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:04,714 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:05:04,714 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:04,715 INFO L85 PathProgramCache]: Analyzing trace with hash 315643517, now seen corresponding path program 1 times [2023-11-26 12:05:04,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:04,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940455667] [2023-11-26 12:05:04,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:04,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:04,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:04,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:04,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:04,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1940455667] [2023-11-26 12:05:04,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1940455667] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:04,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:04,782 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:04,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1471505438] [2023-11-26 12:05:04,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:04,783 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:04,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:04,784 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:04,784 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:04,784 INFO L87 Difference]: Start difference. First operand 322 states and 479 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:04,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:04,801 INFO L93 Difference]: Finished difference Result 322 states and 478 transitions. [2023-11-26 12:05:04,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 478 transitions. [2023-11-26 12:05:04,805 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-26 12:05:04,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 322 states and 478 transitions. [2023-11-26 12:05:04,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2023-11-26 12:05:04,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2023-11-26 12:05:04,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 478 transitions. [2023-11-26 12:05:04,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:04,813 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 478 transitions. [2023-11-26 12:05:04,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 478 transitions. [2023-11-26 12:05:04,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2023-11-26 12:05:04,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.484472049689441) internal successors, (478), 321 states have internal predecessors, (478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:04,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 478 transitions. [2023-11-26 12:05:04,827 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 478 transitions. [2023-11-26 12:05:04,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:04,828 INFO L428 stractBuchiCegarLoop]: Abstraction has 322 states and 478 transitions. [2023-11-26 12:05:04,828 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 12:05:04,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 478 transitions. [2023-11-26 12:05:04,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-26 12:05:04,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:04,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:04,834 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:04,834 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:04,834 INFO L748 eck$LassoCheckResult]: Stem: 2251#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2252#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2264#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2261#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2167#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 2168#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2253#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2239#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2240#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2247#L429 assume !(0 == ~M_E~0); 2073#L429-2 assume !(0 == ~T1_E~0); 2074#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2201#L439-1 assume !(0 == ~T3_E~0); 2222#L444-1 assume !(0 == ~E_M~0); 2223#L449-1 assume !(0 == ~E_1~0); 2076#L454-1 assume !(0 == ~E_2~0); 2077#L459-1 assume !(0 == ~E_3~0); 2034#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2035#L208 assume 1 == ~m_pc~0; 2286#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2288#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2225#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2061#L531 assume !(0 != activate_threads_~tmp~1#1); 2062#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2174#L227 assume !(1 == ~t1_pc~0); 2059#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2060#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2047#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2048#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2075#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2106#L246 assume 1 == ~t2_pc~0; 2107#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2190#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2205#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2256#L547 assume !(0 != activate_threads_~tmp___1~0#1); 2257#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2120#L265 assume !(1 == ~t3_pc~0); 1996#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1969#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1970#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1997#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2087#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2088#L477 assume !(1 == ~M_E~0); 2250#L477-2 assume !(1 == ~T1_E~0); 2265#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2218#L487-1 assume !(1 == ~T3_E~0); 2219#L492-1 assume !(1 == ~E_M~0); 2040#L497-1 assume !(1 == ~E_1~0); 2041#L502-1 assume !(1 == ~E_2~0); 2024#L507-1 assume !(1 == ~E_3~0); 2025#L512-1 assume { :end_inline_reset_delta_events } true; 2119#L678-2 [2023-11-26 12:05:04,835 INFO L750 eck$LassoCheckResult]: Loop: 2119#L678-2 assume !false; 2243#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2258#L404-1 assume !false; 2173#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2148#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2009#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1998#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1999#L357 assume !(0 != eval_~tmp~0#1); 2095#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2160#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2197#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2279#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2241#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2242#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2083#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2084#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2098#L454-3 assume !(0 == ~E_2~0); 2136#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2078#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2079#L208-15 assume !(1 == ~m_pc~0); 2227#L208-17 is_master_triggered_~__retres1~0#1 := 0; 2228#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2144#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2145#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2099#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2100#L227-15 assume !(1 == ~t1_pc~0); 2281#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2271#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2109#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2110#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2238#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2224#L246-15 assume 1 == ~t2_pc~0; 1981#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1982#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2276#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2283#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2071#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2072#L265-15 assume 1 == ~t3_pc~0; 2150#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2151#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2185#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2128#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2129#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2262#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2229#L477-5 assume !(1 == ~T1_E~0); 2230#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2137#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2069#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2070#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2195#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2196#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2163#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2028#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1990#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1991#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2255#L697 assume !(0 == start_simulation_~tmp~3#1); 1967#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1968#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2117#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2042#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 2043#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2248#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2207#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2118#L710 assume !(0 != start_simulation_~tmp___0~1#1); 2119#L678-2 [2023-11-26 12:05:04,835 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:04,836 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2023-11-26 12:05:04,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:04,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004386313] [2023-11-26 12:05:04,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:04,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:04,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:04,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:04,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:04,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004386313] [2023-11-26 12:05:04,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1004386313] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:04,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:04,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:04,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848819543] [2023-11-26 12:05:04,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:04,952 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:05:04,953 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:04,953 INFO L85 PathProgramCache]: Analyzing trace with hash -641284866, now seen corresponding path program 1 times [2023-11-26 12:05:04,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:04,954 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841070848] [2023-11-26 12:05:04,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:04,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:04,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:05,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:05,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:05,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841070848] [2023-11-26 12:05:05,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841070848] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:05,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:05,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:05,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1433219513] [2023-11-26 12:05:05,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:05,024 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:05,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:05,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:05:05,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:05:05,026 INFO L87 Difference]: Start difference. First operand 322 states and 478 transitions. cyclomatic complexity: 157 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:05,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:05,180 INFO L93 Difference]: Finished difference Result 559 states and 824 transitions. [2023-11-26 12:05:05,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 559 states and 824 transitions. [2023-11-26 12:05:05,187 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 496 [2023-11-26 12:05:05,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 559 states to 559 states and 824 transitions. [2023-11-26 12:05:05,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 559 [2023-11-26 12:05:05,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 559 [2023-11-26 12:05:05,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 559 states and 824 transitions. [2023-11-26 12:05:05,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:05,197 INFO L218 hiAutomatonCegarLoop]: Abstraction has 559 states and 824 transitions. [2023-11-26 12:05:05,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states and 824 transitions. [2023-11-26 12:05:05,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 559. [2023-11-26 12:05:05,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 559 states, 559 states have (on average 1.4740608228980323) internal successors, (824), 558 states have internal predecessors, (824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:05,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 559 states to 559 states and 824 transitions. [2023-11-26 12:05:05,224 INFO L240 hiAutomatonCegarLoop]: Abstraction has 559 states and 824 transitions. [2023-11-26 12:05:05,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:05:05,228 INFO L428 stractBuchiCegarLoop]: Abstraction has 559 states and 824 transitions. [2023-11-26 12:05:05,230 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 12:05:05,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 559 states and 824 transitions. [2023-11-26 12:05:05,235 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 496 [2023-11-26 12:05:05,235 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:05,235 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:05,239 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:05,246 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:05,249 INFO L748 eck$LassoCheckResult]: Stem: 3157#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3158#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3171#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3167#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3063#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 3064#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3159#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3141#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3142#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3151#L429 assume !(0 == ~M_E~0); 2966#L429-2 assume !(0 == ~T1_E~0); 2967#L434-1 assume !(0 == ~T2_E~0); 3102#L439-1 assume !(0 == ~T3_E~0); 3124#L444-1 assume !(0 == ~E_M~0); 3125#L449-1 assume !(0 == ~E_1~0); 2969#L454-1 assume !(0 == ~E_2~0); 2970#L459-1 assume !(0 == ~E_3~0); 2925#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2926#L208 assume 1 == ~m_pc~0; 3199#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3201#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3127#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2954#L531 assume !(0 != activate_threads_~tmp~1#1); 2955#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3071#L227 assume !(1 == ~t1_pc~0); 2952#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2953#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2939#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2940#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2968#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3000#L246 assume 1 == ~t2_pc~0; 3001#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3090#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3106#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3162#L547 assume !(0 != activate_threads_~tmp___1~0#1); 3163#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3014#L265 assume !(1 == ~t3_pc~0); 2887#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2860#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2861#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2888#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2980#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2981#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 3155#L477-2 assume !(1 == ~T1_E~0); 3172#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3120#L487-1 assume !(1 == ~T3_E~0); 3121#L492-1 assume !(1 == ~E_M~0); 2932#L497-1 assume !(1 == ~E_1~0); 2933#L502-1 assume !(1 == ~E_2~0); 2915#L507-1 assume !(1 == ~E_3~0); 2916#L512-1 assume { :end_inline_reset_delta_events } true; 3228#L678-2 [2023-11-26 12:05:05,250 INFO L750 eck$LassoCheckResult]: Loop: 3228#L678-2 assume !false; 3212#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3211#L404-1 assume !false; 3210#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3208#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2929#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2889#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2890#L357 assume !(0 != eval_~tmp~0#1); 3054#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3055#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3202#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3203#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3392#L434-3 assume !(0 == ~T2_E~0); 3391#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3390#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3389#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3388#L454-3 assume !(0 == ~E_2~0); 3387#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3386#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3385#L208-15 assume !(1 == ~m_pc~0); 3383#L208-17 is_master_triggered_~__retres1~0#1 := 0; 3382#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3381#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3380#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3379#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3378#L227-15 assume 1 == ~t1_pc~0; 3376#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3375#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3374#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3373#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3372#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3371#L246-15 assume !(1 == ~t2_pc~0); 3369#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 3368#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3367#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3366#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3365#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3364#L265-15 assume 1 == ~t3_pc~0; 3362#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3361#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3360#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3359#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3358#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3357#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3188#L477-5 assume !(1 == ~T1_E~0); 3356#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3190#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3355#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3354#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3353#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3352#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3351#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2919#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2881#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2882#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3161#L697 assume !(0 == start_simulation_~tmp~3#1); 2858#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2859#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3011#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 2935#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3152#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3153#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3230#L710 assume !(0 != start_simulation_~tmp___0~1#1); 3228#L678-2 [2023-11-26 12:05:05,250 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:05,251 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2023-11-26 12:05:05,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:05,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872258024] [2023-11-26 12:05:05,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:05,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:05,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:05,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:05,380 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:05,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872258024] [2023-11-26 12:05:05,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872258024] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:05,381 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:05,381 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:05:05,382 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037072003] [2023-11-26 12:05:05,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:05,382 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:05:05,383 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:05,383 INFO L85 PathProgramCache]: Analyzing trace with hash 277425788, now seen corresponding path program 1 times [2023-11-26 12:05:05,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:05,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186734377] [2023-11-26 12:05:05,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:05,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:05,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:05,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:05,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:05,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [186734377] [2023-11-26 12:05:05,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [186734377] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:05,479 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:05,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:05,480 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101695856] [2023-11-26 12:05:05,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:05,481 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:05,482 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:05,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:05,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:05,483 INFO L87 Difference]: Start difference. First operand 559 states and 824 transitions. cyclomatic complexity: 267 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:05,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:05,554 INFO L93 Difference]: Finished difference Result 1039 states and 1509 transitions. [2023-11-26 12:05:05,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1039 states and 1509 transitions. [2023-11-26 12:05:05,565 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 973 [2023-11-26 12:05:05,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1039 states to 1039 states and 1509 transitions. [2023-11-26 12:05:05,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1039 [2023-11-26 12:05:05,577 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1039 [2023-11-26 12:05:05,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1039 states and 1509 transitions. [2023-11-26 12:05:05,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:05,579 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1039 states and 1509 transitions. [2023-11-26 12:05:05,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1039 states and 1509 transitions. [2023-11-26 12:05:05,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1039 to 985. [2023-11-26 12:05:05,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 985 states, 985 states have (on average 1.4568527918781726) internal successors, (1435), 984 states have internal predecessors, (1435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:05,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 985 states to 985 states and 1435 transitions. [2023-11-26 12:05:05,613 INFO L240 hiAutomatonCegarLoop]: Abstraction has 985 states and 1435 transitions. [2023-11-26 12:05:05,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:05,617 INFO L428 stractBuchiCegarLoop]: Abstraction has 985 states and 1435 transitions. [2023-11-26 12:05:05,617 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 12:05:05,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 985 states and 1435 transitions. [2023-11-26 12:05:05,624 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 919 [2023-11-26 12:05:05,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:05,625 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:05,627 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:05,627 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:05,627 INFO L748 eck$LassoCheckResult]: Stem: 4787#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4788#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4807#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4679#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 4680#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4789#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4768#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4769#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4781#L429 assume !(0 == ~M_E~0); 4574#L429-2 assume !(0 == ~T1_E~0); 4575#L434-1 assume !(0 == ~T2_E~0); 4719#L439-1 assume !(0 == ~T3_E~0); 4744#L444-1 assume !(0 == ~E_M~0); 4745#L449-1 assume !(0 == ~E_1~0); 4579#L454-1 assume !(0 == ~E_2~0); 4580#L459-1 assume !(0 == ~E_3~0); 4533#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4534#L208 assume !(1 == ~m_pc~0); 4866#L208-2 is_master_triggered_~__retres1~0#1 := 0; 4867#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4747#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4562#L531 assume !(0 != activate_threads_~tmp~1#1); 4563#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4685#L227 assume !(1 == ~t1_pc~0); 4560#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4561#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4548#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4549#L539 assume !(0 != activate_threads_~tmp___0~0#1); 4576#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4609#L246 assume 1 == ~t2_pc~0; 4610#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4704#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4724#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4794#L547 assume !(0 != activate_threads_~tmp___1~0#1); 4795#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4624#L265 assume !(1 == ~t3_pc~0); 4493#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4465#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4466#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4494#L555 assume !(0 != activate_threads_~tmp___2~0#1); 4593#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4594#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 4784#L477-2 assume !(1 == ~T1_E~0); 4808#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4740#L487-1 assume !(1 == ~T3_E~0); 4741#L492-1 assume !(1 == ~E_M~0); 4546#L497-1 assume !(1 == ~E_1~0); 4547#L502-1 assume !(1 == ~E_2~0); 4521#L507-1 assume !(1 == ~E_3~0); 4522#L512-1 assume { :end_inline_reset_delta_events } true; 5277#L678-2 [2023-11-26 12:05:05,629 INFO L750 eck$LassoCheckResult]: Loop: 5277#L678-2 assume !false; 5274#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5273#L404-1 assume !false; 4683#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4684#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4539#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4540#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5269#L357 assume !(0 != eval_~tmp~0#1); 4667#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4668#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5267#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5268#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5422#L434-3 assume !(0 == ~T2_E~0); 5421#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5420#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5419#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5418#L454-3 assume !(0 == ~E_2~0); 5417#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5416#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5415#L208-15 assume !(1 == ~m_pc~0); 5414#L208-17 is_master_triggered_~__retres1~0#1 := 0; 5413#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5412#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5411#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5410#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5409#L227-15 assume 1 == ~t1_pc~0; 4883#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4825#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4607#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4608#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4766#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4767#L246-15 assume !(1 == ~t2_pc~0); 5399#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 5397#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4847#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4848#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4572#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4573#L265-15 assume !(1 == ~t3_pc~0); 4657#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 4656#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4696#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4828#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5375#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5373#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4835#L477-5 assume !(1 == ~T1_E~0); 5371#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4838#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5370#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5369#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5368#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5367#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5366#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5006#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5003#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4852#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4853#L697 assume !(0 == start_simulation_~tmp~3#1); 4463#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4464#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4618#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4541#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 4542#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4782#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4726#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4727#L710 assume !(0 != start_simulation_~tmp___0~1#1); 5277#L678-2 [2023-11-26 12:05:05,630 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:05,630 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2023-11-26 12:05:05,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:05,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171556154] [2023-11-26 12:05:05,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:05,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:05,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:05,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:05,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:05,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171556154] [2023-11-26 12:05:05,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [171556154] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:05,687 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:05,687 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:05:05,687 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1671661710] [2023-11-26 12:05:05,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:05,688 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:05:05,688 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:05,689 INFO L85 PathProgramCache]: Analyzing trace with hash -1395091843, now seen corresponding path program 1 times [2023-11-26 12:05:05,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:05,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [382867256] [2023-11-26 12:05:05,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:05,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:05,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:05,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:05,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:05,730 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [382867256] [2023-11-26 12:05:05,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [382867256] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:05,731 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:05,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:05,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1131806180] [2023-11-26 12:05:05,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:05,732 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:05,732 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:05,733 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:05,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:05,733 INFO L87 Difference]: Start difference. First operand 985 states and 1435 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:05,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:05,806 INFO L93 Difference]: Finished difference Result 1769 states and 2555 transitions. [2023-11-26 12:05:05,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1769 states and 2555 transitions. [2023-11-26 12:05:05,824 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1692 [2023-11-26 12:05:05,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1769 states to 1769 states and 2555 transitions. [2023-11-26 12:05:05,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1769 [2023-11-26 12:05:05,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1769 [2023-11-26 12:05:05,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1769 states and 2555 transitions. [2023-11-26 12:05:05,849 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:05,849 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1769 states and 2555 transitions. [2023-11-26 12:05:05,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1769 states and 2555 transitions. [2023-11-26 12:05:05,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1769 to 1761. [2023-11-26 12:05:05,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1761 states, 1761 states have (on average 1.4463373083475297) internal successors, (2547), 1760 states have internal predecessors, (2547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:05,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1761 states to 1761 states and 2547 transitions. [2023-11-26 12:05:05,902 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1761 states and 2547 transitions. [2023-11-26 12:05:05,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:05,903 INFO L428 stractBuchiCegarLoop]: Abstraction has 1761 states and 2547 transitions. [2023-11-26 12:05:05,903 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 12:05:05,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1761 states and 2547 transitions. [2023-11-26 12:05:05,917 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1684 [2023-11-26 12:05:05,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:05,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:05,919 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:05,919 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:05,920 INFO L748 eck$LassoCheckResult]: Stem: 7524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7546#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7539#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7431#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 7432#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7527#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7510#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7511#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7519#L429 assume !(0 == ~M_E~0); 7331#L429-2 assume !(0 == ~T1_E~0); 7332#L434-1 assume !(0 == ~T2_E~0); 7465#L439-1 assume !(0 == ~T3_E~0); 7490#L444-1 assume !(0 == ~E_M~0); 7491#L449-1 assume !(0 == ~E_1~0); 7334#L454-1 assume !(0 == ~E_2~0); 7335#L459-1 assume !(0 == ~E_3~0); 7292#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7293#L208 assume !(1 == ~m_pc~0); 7594#L208-2 is_master_triggered_~__retres1~0#1 := 0; 7595#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7493#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7319#L531 assume !(0 != activate_threads_~tmp~1#1); 7320#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7437#L227 assume !(1 == ~t1_pc~0); 7317#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7318#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7305#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7306#L539 assume !(0 != activate_threads_~tmp___0~0#1); 7333#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7366#L246 assume !(1 == ~t2_pc~0); 7367#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7471#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7472#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7532#L547 assume !(0 != activate_threads_~tmp___1~0#1); 7533#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7379#L265 assume !(1 == ~t3_pc~0); 7255#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7226#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7227#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7256#L555 assume !(0 != activate_threads_~tmp___2~0#1); 7345#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7346#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 7522#L477-2 assume !(1 == ~T1_E~0); 7547#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7548#L487-1 assume !(1 == ~T3_E~0); 8251#L492-1 assume !(1 == ~E_M~0); 7298#L497-1 assume !(1 == ~E_1~0); 7299#L502-1 assume !(1 == ~E_2~0); 8239#L507-1 assume !(1 == ~E_3~0); 8235#L512-1 assume { :end_inline_reset_delta_events } true; 8231#L678-2 [2023-11-26 12:05:05,920 INFO L750 eck$LassoCheckResult]: Loop: 8231#L678-2 assume !false; 8226#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8224#L404-1 assume !false; 8222#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8219#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8215#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8211#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8208#L357 assume !(0 != eval_~tmp~0#1); 8209#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8378#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8377#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8376#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8375#L434-3 assume !(0 == ~T2_E~0); 8374#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8373#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8372#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8371#L454-3 assume !(0 == ~E_2~0); 8370#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8369#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8368#L208-15 assume !(1 == ~m_pc~0); 8367#L208-17 is_master_triggered_~__retres1~0#1 := 0; 8366#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8365#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8364#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8363#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8362#L227-15 assume 1 == ~t1_pc~0; 8360#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8358#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8356#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8354#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8353#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8350#L246-15 assume !(1 == ~t2_pc~0); 8349#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 8347#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8345#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8343#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8341#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8338#L265-15 assume 1 == ~t3_pc~0; 8334#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8331#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8328#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8325#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8322#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8318#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7570#L477-5 assume !(1 == ~T1_E~0); 8312#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7573#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8305#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8301#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8297#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8293#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8289#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8285#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8277#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8273#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 8269#L697 assume !(0 == start_simulation_~tmp~3#1); 8264#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8261#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8255#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8252#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 8248#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8243#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8240#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 8236#L710 assume !(0 != start_simulation_~tmp___0~1#1); 8231#L678-2 [2023-11-26 12:05:05,921 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:05,921 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2023-11-26 12:05:05,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:05,921 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380107612] [2023-11-26 12:05:05,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:05,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:05,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:06,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:06,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:06,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380107612] [2023-11-26 12:05:06,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380107612] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:06,008 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:06,008 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:05:06,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381149939] [2023-11-26 12:05:06,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:06,009 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:05:06,010 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:06,010 INFO L85 PathProgramCache]: Analyzing trace with hash 277425788, now seen corresponding path program 2 times [2023-11-26 12:05:06,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:06,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706627263] [2023-11-26 12:05:06,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:06,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:06,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:06,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:06,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:06,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706627263] [2023-11-26 12:05:06,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706627263] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:06,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:06,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:06,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [216922861] [2023-11-26 12:05:06,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:06,055 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:06,055 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:06,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:06,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:06,056 INFO L87 Difference]: Start difference. First operand 1761 states and 2547 transitions. cyclomatic complexity: 794 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:06,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:06,105 INFO L93 Difference]: Finished difference Result 2567 states and 3710 transitions. [2023-11-26 12:05:06,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2567 states and 3710 transitions. [2023-11-26 12:05:06,132 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2484 [2023-11-26 12:05:06,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2567 states to 2567 states and 3710 transitions. [2023-11-26 12:05:06,158 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2567 [2023-11-26 12:05:06,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2567 [2023-11-26 12:05:06,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2567 states and 3710 transitions. [2023-11-26 12:05:06,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:06,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2567 states and 3710 transitions. [2023-11-26 12:05:06,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2567 states and 3710 transitions. [2023-11-26 12:05:06,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2567 to 1785. [2023-11-26 12:05:06,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4492997198879551) internal successors, (2587), 1784 states have internal predecessors, (2587), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:06,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2587 transitions. [2023-11-26 12:05:06,219 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2587 transitions. [2023-11-26 12:05:06,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:06,221 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2587 transitions. [2023-11-26 12:05:06,221 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 12:05:06,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2587 transitions. [2023-11-26 12:05:06,234 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1716 [2023-11-26 12:05:06,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:06,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:06,235 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:06,235 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:06,236 INFO L748 eck$LassoCheckResult]: Stem: 11857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 11858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 11872#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11869#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11764#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 11765#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11860#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11843#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11844#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11853#L429 assume !(0 == ~M_E~0); 11664#L429-2 assume !(0 == ~T1_E~0); 11665#L434-1 assume !(0 == ~T2_E~0); 11797#L439-1 assume !(0 == ~T3_E~0); 11822#L444-1 assume !(0 == ~E_M~0); 11823#L449-1 assume !(0 == ~E_1~0); 11667#L454-1 assume !(0 == ~E_2~0); 11668#L459-1 assume !(0 == ~E_3~0); 11625#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11626#L208 assume !(1 == ~m_pc~0); 11910#L208-2 is_master_triggered_~__retres1~0#1 := 0; 11911#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11826#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11652#L531 assume !(0 != activate_threads_~tmp~1#1); 11653#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11772#L227 assume !(1 == ~t1_pc~0); 11650#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11651#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11638#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11639#L539 assume !(0 != activate_threads_~tmp___0~0#1); 11666#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11697#L246 assume !(1 == ~t2_pc~0); 11698#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11801#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11802#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11863#L547 assume !(0 != activate_threads_~tmp___1~0#1); 11864#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11710#L265 assume !(1 == ~t3_pc~0); 11588#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11561#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11562#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11589#L555 assume !(0 != activate_threads_~tmp___2~0#1); 11678#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11679#L477 assume !(1 == ~M_E~0); 11856#L477-2 assume !(1 == ~T1_E~0); 11873#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11817#L487-1 assume !(1 == ~T3_E~0); 11818#L492-1 assume !(1 == ~E_M~0); 11631#L497-1 assume !(1 == ~E_1~0); 11632#L502-1 assume !(1 == ~E_2~0); 11616#L507-1 assume !(1 == ~E_3~0); 11617#L512-1 assume { :end_inline_reset_delta_events } true; 11770#L678-2 [2023-11-26 12:05:06,236 INFO L750 eck$LassoCheckResult]: Loop: 11770#L678-2 assume !false; 12693#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12690#L404-1 assume !false; 12688#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12684#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12680#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12678#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12676#L357 assume !(0 != eval_~tmp~0#1); 11754#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11755#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11793#L429-3 assume !(0 == ~M_E~0); 11897#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11845#L434-3 assume !(0 == ~T2_E~0); 11846#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11674#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11675#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11689#L454-3 assume !(0 == ~E_2~0); 11728#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11669#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11670#L208-15 assume !(1 == ~m_pc~0); 11828#L208-17 is_master_triggered_~__retres1~0#1 := 0; 11829#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11736#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11737#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11690#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11691#L227-15 assume 1 == ~t1_pc~0; 11908#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11885#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11699#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11700#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11842#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11824#L246-15 assume !(1 == ~t2_pc~0); 11825#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 11890#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11891#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11901#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11662#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11663#L265-15 assume !(1 == ~t3_pc~0); 11745#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 11744#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11782#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11719#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11720#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11870#L477-3 assume !(1 == ~M_E~0); 11831#L477-5 assume !(1 == ~T1_E~0); 11832#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11729#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11660#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11661#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11791#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11792#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11758#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11620#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11582#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11583#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 11862#L697 assume !(0 == start_simulation_~tmp~3#1); 11559#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11560#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11712#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12928#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 12925#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12921#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12918#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 12913#L710 assume !(0 != start_simulation_~tmp___0~1#1); 11770#L678-2 [2023-11-26 12:05:06,237 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:06,237 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2023-11-26 12:05:06,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:06,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405115887] [2023-11-26 12:05:06,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:06,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:06,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:06,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:06,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:06,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405115887] [2023-11-26 12:05:06,297 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1405115887] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:06,297 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:06,298 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:06,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149709776] [2023-11-26 12:05:06,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:06,298 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:05:06,299 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:06,299 INFO L85 PathProgramCache]: Analyzing trace with hash -96371011, now seen corresponding path program 1 times [2023-11-26 12:05:06,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:06,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685325057] [2023-11-26 12:05:06,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:06,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:06,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:06,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:06,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:06,337 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685325057] [2023-11-26 12:05:06,337 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [685325057] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:06,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:06,337 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:06,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397724253] [2023-11-26 12:05:06,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:06,338 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:06,338 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:06,339 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 12:05:06,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 12:05:06,339 INFO L87 Difference]: Start difference. First operand 1785 states and 2587 transitions. cyclomatic complexity: 806 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:06,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:06,410 INFO L93 Difference]: Finished difference Result 2561 states and 3678 transitions. [2023-11-26 12:05:06,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2561 states and 3678 transitions. [2023-11-26 12:05:06,435 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2484 [2023-11-26 12:05:06,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2561 states to 2561 states and 3678 transitions. [2023-11-26 12:05:06,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2561 [2023-11-26 12:05:06,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2561 [2023-11-26 12:05:06,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2561 states and 3678 transitions. [2023-11-26 12:05:06,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:06,467 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2561 states and 3678 transitions. [2023-11-26 12:05:06,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2561 states and 3678 transitions. [2023-11-26 12:05:06,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2561 to 1785. [2023-11-26 12:05:06,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4397759103641457) internal successors, (2570), 1784 states have internal predecessors, (2570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:06,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2570 transitions. [2023-11-26 12:05:06,550 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2570 transitions. [2023-11-26 12:05:06,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 12:05:06,551 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2570 transitions. [2023-11-26 12:05:06,552 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 12:05:06,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2570 transitions. [2023-11-26 12:05:06,566 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1716 [2023-11-26 12:05:06,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:06,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:06,567 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:06,568 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:06,568 INFO L748 eck$LassoCheckResult]: Stem: 16213#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16214#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16229#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16226#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16119#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 16120#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16216#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16199#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16200#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16209#L429 assume !(0 == ~M_E~0); 16021#L429-2 assume !(0 == ~T1_E~0); 16022#L434-1 assume !(0 == ~T2_E~0); 16152#L439-1 assume !(0 == ~T3_E~0); 16178#L444-1 assume !(0 == ~E_M~0); 16179#L449-1 assume !(0 == ~E_1~0); 16024#L454-1 assume !(0 == ~E_2~0); 16025#L459-1 assume !(0 == ~E_3~0); 15982#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15983#L208 assume !(1 == ~m_pc~0); 16268#L208-2 is_master_triggered_~__retres1~0#1 := 0; 16269#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16181#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16009#L531 assume !(0 != activate_threads_~tmp~1#1); 16010#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16127#L227 assume !(1 == ~t1_pc~0); 16007#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16008#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15995#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15996#L539 assume !(0 != activate_threads_~tmp___0~0#1); 16023#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16054#L246 assume !(1 == ~t2_pc~0); 16055#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16157#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16158#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16220#L547 assume !(0 != activate_threads_~tmp___1~0#1); 16221#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16067#L265 assume !(1 == ~t3_pc~0); 15945#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15917#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15918#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15946#L555 assume !(0 != activate_threads_~tmp___2~0#1); 16035#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16036#L477 assume !(1 == ~M_E~0); 16212#L477-2 assume !(1 == ~T1_E~0); 16230#L482-1 assume !(1 == ~T2_E~0); 16173#L487-1 assume !(1 == ~T3_E~0); 16174#L492-1 assume !(1 == ~E_M~0); 15988#L497-1 assume !(1 == ~E_1~0); 15989#L502-1 assume !(1 == ~E_2~0); 15973#L507-1 assume !(1 == ~E_3~0); 15974#L512-1 assume { :end_inline_reset_delta_events } true; 16125#L678-2 [2023-11-26 12:05:06,569 INFO L750 eck$LassoCheckResult]: Loop: 16125#L678-2 assume !false; 16994#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16911#L404-1 assume !false; 16910#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16427#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16423#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16421#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16418#L357 assume !(0 != eval_~tmp~0#1); 16419#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17187#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17186#L429-3 assume !(0 == ~M_E~0); 17185#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17184#L434-3 assume !(0 == ~T2_E~0); 17183#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17182#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17181#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17180#L454-3 assume !(0 == ~E_2~0); 17179#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17178#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17177#L208-15 assume !(1 == ~m_pc~0); 17176#L208-17 is_master_triggered_~__retres1~0#1 := 0; 17175#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17174#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17173#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17172#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17171#L227-15 assume 1 == ~t1_pc~0; 17169#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17168#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17167#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17166#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17165#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17164#L246-15 assume !(1 == ~t2_pc~0); 17163#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 17162#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17161#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17160#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17159#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17158#L265-15 assume 1 == ~t3_pc~0; 17156#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17155#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17154#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17153#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17152#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17151#L477-3 assume !(1 == ~M_E~0); 16848#L477-5 assume !(1 == ~T1_E~0); 17150#L482-3 assume !(1 == ~T2_E~0); 17149#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17148#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17147#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17146#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16193#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16114#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15977#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 15938#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 15939#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 16218#L697 assume !(0 == start_simulation_~tmp~3#1); 16219#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17014#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17009#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17007#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 17004#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17002#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17000#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 16998#L710 assume !(0 != start_simulation_~tmp___0~1#1); 16125#L678-2 [2023-11-26 12:05:06,569 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:06,569 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2023-11-26 12:05:06,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:06,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960694364] [2023-11-26 12:05:06,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:06,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:06,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:06,582 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:06,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:06,623 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:06,624 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:06,624 INFO L85 PathProgramCache]: Analyzing trace with hash -112797122, now seen corresponding path program 1 times [2023-11-26 12:05:06,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:06,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722183164] [2023-11-26 12:05:06,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:06,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:06,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:06,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:06,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:06,671 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722183164] [2023-11-26 12:05:06,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [722183164] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:06,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:06,672 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:06,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125860900] [2023-11-26 12:05:06,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:06,673 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:06,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:06,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:06,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:06,674 INFO L87 Difference]: Start difference. First operand 1785 states and 2570 transitions. cyclomatic complexity: 789 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:06,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:06,721 INFO L93 Difference]: Finished difference Result 2108 states and 3030 transitions. [2023-11-26 12:05:06,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2108 states and 3030 transitions. [2023-11-26 12:05:06,741 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2004 [2023-11-26 12:05:06,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2108 states to 2108 states and 3030 transitions. [2023-11-26 12:05:06,763 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2108 [2023-11-26 12:05:06,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2108 [2023-11-26 12:05:06,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2108 states and 3030 transitions. [2023-11-26 12:05:06,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:06,771 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2108 states and 3030 transitions. [2023-11-26 12:05:06,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2108 states and 3030 transitions. [2023-11-26 12:05:06,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2108 to 2108. [2023-11-26 12:05:06,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2108 states, 2108 states have (on average 1.4373814041745732) internal successors, (3030), 2107 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:06,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2108 states to 2108 states and 3030 transitions. [2023-11-26 12:05:06,827 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2108 states and 3030 transitions. [2023-11-26 12:05:06,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:06,828 INFO L428 stractBuchiCegarLoop]: Abstraction has 2108 states and 3030 transitions. [2023-11-26 12:05:06,828 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 12:05:06,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2108 states and 3030 transitions. [2023-11-26 12:05:06,838 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2004 [2023-11-26 12:05:06,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:06,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:06,840 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:06,840 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:06,841 INFO L748 eck$LassoCheckResult]: Stem: 20124#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 20125#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20143#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20139#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20023#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 20024#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20127#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20111#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20112#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20120#L429 assume !(0 == ~M_E~0); 19919#L429-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19920#L434-1 assume !(0 == ~T2_E~0); 20067#L439-1 assume !(0 == ~T3_E~0); 20092#L444-1 assume !(0 == ~E_M~0); 20093#L449-1 assume !(0 == ~E_1~0); 20216#L454-1 assume !(0 == ~E_2~0); 20181#L459-1 assume !(0 == ~E_3~0); 20182#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20215#L208 assume !(1 == ~m_pc~0); 20178#L208-2 is_master_triggered_~__retres1~0#1 := 0; 20179#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20096#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19907#L531 assume !(0 != activate_threads_~tmp~1#1); 19908#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20032#L227 assume !(1 == ~t1_pc~0); 19905#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19906#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19893#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19894#L539 assume !(0 != activate_threads_~tmp___0~0#1); 19922#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20203#L246 assume !(1 == ~t2_pc~0); 20202#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20201#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20200#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20199#L547 assume !(0 != activate_threads_~tmp___1~0#1); 20198#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20197#L265 assume !(1 == ~t3_pc~0); 19843#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19816#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19817#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19844#L555 assume !(0 != activate_threads_~tmp___2~0#1); 19934#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19935#L477 assume !(1 == ~M_E~0); 20123#L477-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20144#L482-1 assume !(1 == ~T2_E~0); 20087#L487-1 assume !(1 == ~T3_E~0); 20088#L492-1 assume !(1 == ~E_M~0); 19886#L497-1 assume !(1 == ~E_1~0); 19887#L502-1 assume !(1 == ~E_2~0); 19871#L507-1 assume !(1 == ~E_3~0); 19872#L512-1 assume { :end_inline_reset_delta_events } true; 20030#L678-2 [2023-11-26 12:05:06,841 INFO L750 eck$LassoCheckResult]: Loop: 20030#L678-2 assume !false; 20908#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20904#L404-1 assume !false; 20900#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20895#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20889#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20883#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20877#L357 assume !(0 != eval_~tmp~0#1); 20878#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21197#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21195#L429-3 assume !(0 == ~M_E~0); 21193#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21190#L434-3 assume !(0 == ~T2_E~0); 21186#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21182#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21178#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21174#L454-3 assume !(0 == ~E_2~0); 21170#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21166#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21162#L208-15 assume !(1 == ~m_pc~0); 21158#L208-17 is_master_triggered_~__retres1~0#1 := 0; 21154#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21150#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21146#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21142#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21138#L227-15 assume 1 == ~t1_pc~0; 21132#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21126#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21122#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21118#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21113#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21108#L246-15 assume !(1 == ~t2_pc~0); 21103#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 21098#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21092#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21087#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21082#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21078#L265-15 assume 1 == ~t3_pc~0; 21067#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21058#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21052#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21046#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21040#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21033#L477-3 assume !(1 == ~M_E~0); 21024#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21020#L482-3 assume !(1 == ~T2_E~0); 21016#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21011#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21005#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21000#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20995#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20990#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20985#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20976#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20971#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 20966#L697 assume !(0 == start_simulation_~tmp~3#1); 20960#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20956#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20949#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20945#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 20939#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20932#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20927#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 20922#L710 assume !(0 != start_simulation_~tmp___0~1#1); 20030#L678-2 [2023-11-26 12:05:06,842 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:06,842 INFO L85 PathProgramCache]: Analyzing trace with hash 1665536133, now seen corresponding path program 1 times [2023-11-26 12:05:06,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:06,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648844583] [2023-11-26 12:05:06,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:06,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:06,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:06,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:06,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:06,887 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648844583] [2023-11-26 12:05:06,887 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1648844583] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:06,887 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:06,887 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:05:06,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96641414] [2023-11-26 12:05:06,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:06,889 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:05:06,889 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:06,890 INFO L85 PathProgramCache]: Analyzing trace with hash 704851328, now seen corresponding path program 1 times [2023-11-26 12:05:06,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:06,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085456351] [2023-11-26 12:05:06,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:06,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:06,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:06,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:06,964 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:06,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085456351] [2023-11-26 12:05:06,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085456351] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:06,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:06,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:05:06,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1460967309] [2023-11-26 12:05:06,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:06,969 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:06,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:06,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:06,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:06,971 INFO L87 Difference]: Start difference. First operand 2108 states and 3030 transitions. cyclomatic complexity: 926 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:07,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:07,002 INFO L93 Difference]: Finished difference Result 1785 states and 2544 transitions. [2023-11-26 12:05:07,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2544 transitions. [2023-11-26 12:05:07,014 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1716 [2023-11-26 12:05:07,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2544 transitions. [2023-11-26 12:05:07,030 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2023-11-26 12:05:07,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2023-11-26 12:05:07,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2544 transitions. [2023-11-26 12:05:07,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:07,039 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2544 transitions. [2023-11-26 12:05:07,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2544 transitions. [2023-11-26 12:05:07,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2023-11-26 12:05:07,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4252100840336135) internal successors, (2544), 1784 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:07,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2544 transitions. [2023-11-26 12:05:07,116 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2544 transitions. [2023-11-26 12:05:07,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:07,119 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2544 transitions. [2023-11-26 12:05:07,120 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 12:05:07,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2544 transitions. [2023-11-26 12:05:07,128 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1716 [2023-11-26 12:05:07,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:07,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:07,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:07,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:07,130 INFO L748 eck$LassoCheckResult]: Stem: 24015#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 24016#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 24032#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24029#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23918#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 23919#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24020#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24002#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24003#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24010#L429 assume !(0 == ~M_E~0); 23822#L429-2 assume !(0 == ~T1_E~0); 23823#L434-1 assume !(0 == ~T2_E~0); 23958#L439-1 assume !(0 == ~T3_E~0); 23982#L444-1 assume !(0 == ~E_M~0); 23983#L449-1 assume !(0 == ~E_1~0); 23825#L454-1 assume !(0 == ~E_2~0); 23826#L459-1 assume !(0 == ~E_3~0); 23783#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23784#L208 assume !(1 == ~m_pc~0); 24068#L208-2 is_master_triggered_~__retres1~0#1 := 0; 24069#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23986#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23810#L531 assume !(0 != activate_threads_~tmp~1#1); 23811#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23926#L227 assume !(1 == ~t1_pc~0); 23808#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23809#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23796#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23797#L539 assume !(0 != activate_threads_~tmp___0~0#1); 23824#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23856#L246 assume !(1 == ~t2_pc~0); 23857#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23962#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23963#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24023#L547 assume !(0 != activate_threads_~tmp___1~0#1); 24024#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23869#L265 assume !(1 == ~t3_pc~0); 23745#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23718#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23719#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23746#L555 assume !(0 != activate_threads_~tmp___2~0#1); 23836#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23837#L477 assume !(1 == ~M_E~0); 24013#L477-2 assume !(1 == ~T1_E~0); 24033#L482-1 assume !(1 == ~T2_E~0); 23977#L487-1 assume !(1 == ~T3_E~0); 23978#L492-1 assume !(1 == ~E_M~0); 23789#L497-1 assume !(1 == ~E_1~0); 23790#L502-1 assume !(1 == ~E_2~0); 23773#L507-1 assume !(1 == ~E_3~0); 23774#L512-1 assume { :end_inline_reset_delta_events } true; 23924#L678-2 [2023-11-26 12:05:07,130 INFO L750 eck$LassoCheckResult]: Loop: 23924#L678-2 assume !false; 24796#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24795#L404-1 assume !false; 24794#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24792#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24789#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24788#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23843#L357 assume !(0 != eval_~tmp~0#1); 23845#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25499#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25497#L429-3 assume !(0 == ~M_E~0); 25495#L429-5 assume !(0 == ~T1_E~0); 25493#L434-3 assume !(0 == ~T2_E~0); 25491#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25489#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25487#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25485#L454-3 assume !(0 == ~E_2~0); 25483#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25481#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25479#L208-15 assume !(1 == ~m_pc~0); 25477#L208-17 is_master_triggered_~__retres1~0#1 := 0; 25475#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25473#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25471#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25469#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25467#L227-15 assume 1 == ~t1_pc~0; 25465#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24041#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23858#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23859#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24001#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23984#L246-15 assume !(1 == ~t2_pc~0); 23985#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 25446#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25443#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25440#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23820#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23821#L265-15 assume 1 == ~t3_pc~0; 25429#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23938#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23939#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23877#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23878#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24030#L477-3 assume !(1 == ~M_E~0); 23990#L477-5 assume !(1 == ~T1_E~0); 23991#L482-3 assume !(1 == ~T2_E~0); 23886#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23818#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23819#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24063#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24828#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24827#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24825#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24820#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24818#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 24817#L697 assume !(0 == start_simulation_~tmp~3#1); 24815#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24814#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24810#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24809#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 24807#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24805#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24803#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 24801#L710 assume !(0 != start_simulation_~tmp___0~1#1); 23924#L678-2 [2023-11-26 12:05:07,131 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:07,131 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2023-11-26 12:05:07,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:07,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949353019] [2023-11-26 12:05:07,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:07,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:07,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:07,145 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:07,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:07,173 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:07,173 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:07,173 INFO L85 PathProgramCache]: Analyzing trace with hash 331103552, now seen corresponding path program 1 times [2023-11-26 12:05:07,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:07,174 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102186380] [2023-11-26 12:05:07,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:07,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:07,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:07,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:07,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:07,249 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102186380] [2023-11-26 12:05:07,249 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [102186380] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:07,249 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:07,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:05:07,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172256841] [2023-11-26 12:05:07,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:07,250 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:07,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:07,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 12:05:07,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 12:05:07,252 INFO L87 Difference]: Start difference. First operand 1785 states and 2544 transitions. cyclomatic complexity: 763 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:07,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:07,403 INFO L93 Difference]: Finished difference Result 3125 states and 4384 transitions. [2023-11-26 12:05:07,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3125 states and 4384 transitions. [2023-11-26 12:05:07,424 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3040 [2023-11-26 12:05:07,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3125 states to 3125 states and 4384 transitions. [2023-11-26 12:05:07,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3125 [2023-11-26 12:05:07,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3125 [2023-11-26 12:05:07,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3125 states and 4384 transitions. [2023-11-26 12:05:07,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:07,467 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3125 states and 4384 transitions. [2023-11-26 12:05:07,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3125 states and 4384 transitions. [2023-11-26 12:05:07,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3125 to 1809. [2023-11-26 12:05:07,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1809 states, 1809 states have (on average 1.4195688225538972) internal successors, (2568), 1808 states have internal predecessors, (2568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:07,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1809 states to 1809 states and 2568 transitions. [2023-11-26 12:05:07,520 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1809 states and 2568 transitions. [2023-11-26 12:05:07,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 12:05:07,522 INFO L428 stractBuchiCegarLoop]: Abstraction has 1809 states and 2568 transitions. [2023-11-26 12:05:07,522 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 12:05:07,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1809 states and 2568 transitions. [2023-11-26 12:05:07,530 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1740 [2023-11-26 12:05:07,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:07,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:07,532 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:07,532 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:07,532 INFO L748 eck$LassoCheckResult]: Stem: 28953#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 28954#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 28972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28968#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28849#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 28850#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28956#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28938#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28939#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28946#L429 assume !(0 == ~M_E~0); 28749#L429-2 assume !(0 == ~T1_E~0); 28750#L434-1 assume !(0 == ~T2_E~0); 28889#L439-1 assume !(0 == ~T3_E~0); 28914#L444-1 assume !(0 == ~E_M~0); 28915#L449-1 assume !(0 == ~E_1~0); 28752#L454-1 assume !(0 == ~E_2~0); 28753#L459-1 assume !(0 == ~E_3~0); 28709#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28710#L208 assume !(1 == ~m_pc~0); 29028#L208-2 is_master_triggered_~__retres1~0#1 := 0; 29029#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28918#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28737#L531 assume !(0 != activate_threads_~tmp~1#1); 28738#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28856#L227 assume !(1 == ~t1_pc~0); 28735#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28736#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28723#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28724#L539 assume !(0 != activate_threads_~tmp___0~0#1); 28751#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28783#L246 assume !(1 == ~t2_pc~0); 28784#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28894#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28895#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28962#L547 assume !(0 != activate_threads_~tmp___1~0#1); 28963#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28796#L265 assume !(1 == ~t3_pc~0); 28672#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28645#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28646#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28673#L555 assume !(0 != activate_threads_~tmp___2~0#1); 28763#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28764#L477 assume !(1 == ~M_E~0); 28949#L477-2 assume !(1 == ~T1_E~0); 28973#L482-1 assume !(1 == ~T2_E~0); 28910#L487-1 assume !(1 == ~T3_E~0); 28911#L492-1 assume !(1 == ~E_M~0); 28716#L497-1 assume !(1 == ~E_1~0); 28717#L502-1 assume !(1 == ~E_2~0); 28700#L507-1 assume !(1 == ~E_3~0); 28701#L512-1 assume { :end_inline_reset_delta_events } true; 28795#L678-2 [2023-11-26 12:05:07,533 INFO L750 eck$LassoCheckResult]: Loop: 28795#L678-2 assume !false; 28942#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28965#L404-1 assume !false; 28855#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28826#L320 assume !(0 == ~m_st~0); 28683#L324 assume !(0 == ~t1_st~0); 28684#L328 assume !(0 == ~t2_st~0); 28948#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 28713#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28674#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28675#L357 assume !(0 != eval_~tmp~0#1); 28839#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29006#L429-3 assume !(0 == ~M_E~0); 29007#L429-5 assume !(0 == ~T1_E~0); 28940#L434-3 assume !(0 == ~T2_E~0); 28941#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28759#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28760#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28812#L454-3 assume !(0 == ~E_2~0); 28813#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30385#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28990#L208-15 assume !(1 == ~m_pc~0); 28991#L208-17 is_master_triggered_~__retres1~0#1 := 0; 28987#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28988#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28897#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28898#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29022#L227-15 assume !(1 == ~t1_pc~0); 29024#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 28981#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28982#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28957#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28958#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28916#L246-15 assume !(1 == ~t2_pc~0); 28917#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 28995#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28996#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29038#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29039#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28950#L265-15 assume 1 == ~t3_pc~0; 28951#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28867#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28868#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28804#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28805#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28998#L477-3 assume !(1 == ~M_E~0); 28999#L477-5 assume !(1 == ~T1_E~0); 29003#L482-3 assume !(1 == ~T2_E~0); 29004#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28745#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28746#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28878#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28879#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28843#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28844#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30426#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30424#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 30423#L697 assume !(0 == start_simulation_~tmp~3#1); 30421#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28997#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28793#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28718#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 28719#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28947#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28899#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 28794#L710 assume !(0 != start_simulation_~tmp___0~1#1); 28795#L678-2 [2023-11-26 12:05:07,533 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:07,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2023-11-26 12:05:07,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:07,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736491525] [2023-11-26 12:05:07,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:07,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:07,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:07,551 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:07,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:07,580 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:07,583 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:07,583 INFO L85 PathProgramCache]: Analyzing trace with hash 1044594375, now seen corresponding path program 1 times [2023-11-26 12:05:07,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:07,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475688540] [2023-11-26 12:05:07,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:07,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:07,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:07,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:07,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:07,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475688540] [2023-11-26 12:05:07,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475688540] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:07,682 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:07,683 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 12:05:07,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986799256] [2023-11-26 12:05:07,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:07,683 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:07,684 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:07,684 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 12:05:07,686 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 12:05:07,686 INFO L87 Difference]: Start difference. First operand 1809 states and 2568 transitions. cyclomatic complexity: 763 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:07,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:07,910 INFO L93 Difference]: Finished difference Result 3133 states and 4387 transitions. [2023-11-26 12:05:07,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3133 states and 4387 transitions. [2023-11-26 12:05:07,929 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3060 [2023-11-26 12:05:07,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3133 states to 3133 states and 4387 transitions. [2023-11-26 12:05:07,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3133 [2023-11-26 12:05:07,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3133 [2023-11-26 12:05:07,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3133 states and 4387 transitions. [2023-11-26 12:05:07,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:07,989 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3133 states and 4387 transitions. [2023-11-26 12:05:07,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3133 states and 4387 transitions. [2023-11-26 12:05:08,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3133 to 1869. [2023-11-26 12:05:08,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1869 states, 1869 states have (on average 1.3970037453183521) internal successors, (2611), 1868 states have internal predecessors, (2611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:08,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1869 states to 1869 states and 2611 transitions. [2023-11-26 12:05:08,053 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1869 states and 2611 transitions. [2023-11-26 12:05:08,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 12:05:08,055 INFO L428 stractBuchiCegarLoop]: Abstraction has 1869 states and 2611 transitions. [2023-11-26 12:05:08,055 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 12:05:08,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1869 states and 2611 transitions. [2023-11-26 12:05:08,065 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1800 [2023-11-26 12:05:08,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:08,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:08,067 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:08,067 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:08,067 INFO L748 eck$LassoCheckResult]: Stem: 33904#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 33905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 33927#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33924#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33805#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 33806#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33908#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33890#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33891#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33899#L429 assume !(0 == ~M_E~0); 33704#L429-2 assume !(0 == ~T1_E~0); 33705#L434-1 assume !(0 == ~T2_E~0); 33842#L439-1 assume !(0 == ~T3_E~0); 33868#L444-1 assume !(0 == ~E_M~0); 33869#L449-1 assume !(0 == ~E_1~0); 33709#L454-1 assume !(0 == ~E_2~0); 33710#L459-1 assume !(0 == ~E_3~0); 33664#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33665#L208 assume !(1 == ~m_pc~0); 33966#L208-2 is_master_triggered_~__retres1~0#1 := 0; 33967#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33872#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33692#L531 assume !(0 != activate_threads_~tmp~1#1); 33693#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33813#L227 assume !(1 == ~t1_pc~0); 33690#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33691#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33681#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33682#L539 assume !(0 != activate_threads_~tmp___0~0#1); 33706#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33739#L246 assume !(1 == ~t2_pc~0); 33740#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33848#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33849#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33914#L547 assume !(0 != activate_threads_~tmp___1~0#1); 33915#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33750#L265 assume !(1 == ~t3_pc~0); 33626#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33599#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33600#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33629#L555 assume !(0 != activate_threads_~tmp___2~0#1); 33723#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33724#L477 assume !(1 == ~M_E~0); 33903#L477-2 assume !(1 == ~T1_E~0); 33928#L482-1 assume !(1 == ~T2_E~0); 33866#L487-1 assume !(1 == ~T3_E~0); 33867#L492-1 assume !(1 == ~E_M~0); 33671#L497-1 assume !(1 == ~E_1~0); 33672#L502-1 assume !(1 == ~E_2~0); 33656#L507-1 assume !(1 == ~E_3~0); 33657#L512-1 assume { :end_inline_reset_delta_events } true; 33810#L678-2 [2023-11-26 12:05:08,068 INFO L750 eck$LassoCheckResult]: Loop: 33810#L678-2 assume !false; 34701#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34700#L404-1 assume !false; 34699#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34697#L320 assume !(0 == ~m_st~0); 34698#L324 assume !(0 == ~t1_st~0); 34694#L328 assume !(0 == ~t2_st~0); 34696#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 34693#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34549#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34550#L357 assume !(0 != eval_~tmp~0#1); 34786#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34785#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34784#L429-3 assume !(0 == ~M_E~0); 34783#L429-5 assume !(0 == ~T1_E~0); 34782#L434-3 assume !(0 == ~T2_E~0); 34781#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34780#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34779#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34778#L454-3 assume !(0 == ~E_2~0); 34777#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33707#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33708#L208-15 assume !(1 == ~m_pc~0); 33874#L208-17 is_master_triggered_~__retres1~0#1 := 0; 33875#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33773#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33774#L531-15 assume !(0 != activate_threads_~tmp~1#1); 33729#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33730#L227-15 assume !(1 == ~t1_pc~0); 33954#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 33939#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33737#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33738#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33887#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33870#L246-15 assume !(1 == ~t2_pc~0); 33871#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 35431#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35430#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35429#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35428#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35427#L265-15 assume 1 == ~t3_pc~0; 35425#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35424#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33942#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33759#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33760#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33923#L477-3 assume !(1 == ~M_E~0); 33876#L477-5 assume !(1 == ~T1_E~0); 33877#L482-3 assume !(1 == ~T2_E~0); 33769#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33698#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33699#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33833#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33834#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33798#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 33658#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 33618#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 33619#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 33911#L697 assume !(0 == start_simulation_~tmp~3#1); 33913#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34722#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34717#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34715#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 34713#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34710#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34708#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 34706#L710 assume !(0 != start_simulation_~tmp___0~1#1); 33810#L678-2 [2023-11-26 12:05:08,069 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:08,069 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 4 times [2023-11-26 12:05:08,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:08,069 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [276868670] [2023-11-26 12:05:08,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:08,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:08,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:08,083 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:08,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:08,103 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:08,104 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:08,104 INFO L85 PathProgramCache]: Analyzing trace with hash 1468241097, now seen corresponding path program 1 times [2023-11-26 12:05:08,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:08,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136606938] [2023-11-26 12:05:08,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:08,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:08,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:08,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:08,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:08,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136606938] [2023-11-26 12:05:08,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136606938] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:08,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:08,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:08,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821155805] [2023-11-26 12:05:08,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:08,148 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 12:05:08,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:08,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:08,150 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:08,150 INFO L87 Difference]: Start difference. First operand 1869 states and 2611 transitions. cyclomatic complexity: 746 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:08,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:08,208 INFO L93 Difference]: Finished difference Result 2878 states and 3964 transitions. [2023-11-26 12:05:08,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2878 states and 3964 transitions. [2023-11-26 12:05:08,224 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2805 [2023-11-26 12:05:08,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2878 states to 2878 states and 3964 transitions. [2023-11-26 12:05:08,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2878 [2023-11-26 12:05:08,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2878 [2023-11-26 12:05:08,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2878 states and 3964 transitions. [2023-11-26 12:05:08,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:08,250 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2878 states and 3964 transitions. [2023-11-26 12:05:08,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2878 states and 3964 transitions. [2023-11-26 12:05:08,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2878 to 2788. [2023-11-26 12:05:08,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2788 states, 2788 states have (on average 1.3780487804878048) internal successors, (3842), 2787 states have internal predecessors, (3842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:08,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2788 states to 2788 states and 3842 transitions. [2023-11-26 12:05:08,321 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2788 states and 3842 transitions. [2023-11-26 12:05:08,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:08,322 INFO L428 stractBuchiCegarLoop]: Abstraction has 2788 states and 3842 transitions. [2023-11-26 12:05:08,323 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 12:05:08,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2788 states and 3842 transitions. [2023-11-26 12:05:08,335 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2715 [2023-11-26 12:05:08,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:08,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:08,337 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:08,337 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:08,337 INFO L748 eck$LassoCheckResult]: Stem: 38667#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 38668#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 38685#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38682#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38566#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 38567#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38670#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38651#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38652#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38660#L429 assume !(0 == ~M_E~0); 38457#L429-2 assume !(0 == ~T1_E~0); 38458#L434-1 assume !(0 == ~T2_E~0); 38605#L439-1 assume !(0 == ~T3_E~0); 38632#L444-1 assume !(0 == ~E_M~0); 38633#L449-1 assume !(0 == ~E_1~0); 38462#L454-1 assume !(0 == ~E_2~0); 38463#L459-1 assume !(0 == ~E_3~0); 38416#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38417#L208 assume !(1 == ~m_pc~0); 38724#L208-2 is_master_triggered_~__retres1~0#1 := 0; 38725#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38636#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38445#L531 assume !(0 != activate_threads_~tmp~1#1); 38446#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38571#L227 assume !(1 == ~t1_pc~0); 38443#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38444#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38434#L539 assume !(0 != activate_threads_~tmp___0~0#1); 38459#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38493#L246 assume !(1 == ~t2_pc~0); 38494#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38611#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38612#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38674#L547 assume !(0 != activate_threads_~tmp___1~0#1); 38675#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38506#L265 assume !(1 == ~t3_pc~0); 38379#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38352#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38353#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38382#L555 assume !(0 != activate_threads_~tmp___2~0#1); 38476#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38477#L477 assume !(1 == ~M_E~0); 38666#L477-2 assume !(1 == ~T1_E~0); 38686#L482-1 assume !(1 == ~T2_E~0); 38630#L487-1 assume !(1 == ~T3_E~0); 38631#L492-1 assume !(1 == ~E_M~0); 38428#L497-1 assume !(1 == ~E_1~0); 38429#L502-1 assume !(1 == ~E_2~0); 38409#L507-1 assume !(1 == ~E_3~0); 38410#L512-1 assume { :end_inline_reset_delta_events } true; 38568#L678-2 assume !false; 39383#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39384#L404-1 [2023-11-26 12:05:08,338 INFO L750 eck$LassoCheckResult]: Loop: 39384#L404-1 assume !false; 39356#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 39357#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 39582#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 39578#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 39573#L357 assume 0 != eval_~tmp~0#1; 39566#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 39561#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 39559#L365-2 havoc eval_~tmp_ndt_1~0#1; 39555#L362-1 assume !(0 == ~t1_st~0); 39550#L376-1 assume !(0 == ~t2_st~0); 39386#L390-1 assume !(0 == ~t3_st~0); 39384#L404-1 [2023-11-26 12:05:08,338 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:08,339 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2023-11-26 12:05:08,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:08,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2045043343] [2023-11-26 12:05:08,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:08,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:08,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:08,350 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:08,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:08,373 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:08,375 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:08,376 INFO L85 PathProgramCache]: Analyzing trace with hash -616621386, now seen corresponding path program 1 times [2023-11-26 12:05:08,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:08,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246585381] [2023-11-26 12:05:08,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:08,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:08,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:08,382 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:08,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:08,387 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:08,388 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:08,388 INFO L85 PathProgramCache]: Analyzing trace with hash 945603068, now seen corresponding path program 1 times [2023-11-26 12:05:08,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:08,388 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943013867] [2023-11-26 12:05:08,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:08,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:08,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:08,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:08,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:08,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1943013867] [2023-11-26 12:05:08,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1943013867] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:08,435 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:08,435 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:08,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1985605907] [2023-11-26 12:05:08,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:08,554 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:08,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:08,555 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:08,555 INFO L87 Difference]: Start difference. First operand 2788 states and 3842 transitions. cyclomatic complexity: 1060 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:08,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:08,630 INFO L93 Difference]: Finished difference Result 5000 states and 6813 transitions. [2023-11-26 12:05:08,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5000 states and 6813 transitions. [2023-11-26 12:05:08,681 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4860 [2023-11-26 12:05:08,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5000 states to 5000 states and 6813 transitions. [2023-11-26 12:05:08,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5000 [2023-11-26 12:05:08,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5000 [2023-11-26 12:05:08,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5000 states and 6813 transitions. [2023-11-26 12:05:08,723 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:08,723 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5000 states and 6813 transitions. [2023-11-26 12:05:08,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5000 states and 6813 transitions. [2023-11-26 12:05:08,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5000 to 4755. [2023-11-26 12:05:08,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4755 states, 4755 states have (on average 1.3665615141955836) internal successors, (6498), 4754 states have internal predecessors, (6498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:08,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4755 states to 4755 states and 6498 transitions. [2023-11-26 12:05:08,833 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4755 states and 6498 transitions. [2023-11-26 12:05:08,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:08,835 INFO L428 stractBuchiCegarLoop]: Abstraction has 4755 states and 6498 transitions. [2023-11-26 12:05:08,835 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 12:05:08,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4755 states and 6498 transitions. [2023-11-26 12:05:08,854 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4615 [2023-11-26 12:05:08,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:08,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:08,855 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:08,855 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:08,856 INFO L748 eck$LassoCheckResult]: Stem: 46485#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 46486#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 46504#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46501#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46361#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 46362#L292-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 46511#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46465#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46466#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46527#L429 assume !(0 == ~M_E~0); 46528#L429-2 assume !(0 == ~T1_E~0); 46412#L434-1 assume !(0 == ~T2_E~0); 46413#L439-1 assume !(0 == ~T3_E~0); 46442#L444-1 assume !(0 == ~E_M~0); 46443#L449-1 assume !(0 == ~E_1~0); 46260#L454-1 assume !(0 == ~E_2~0); 46261#L459-1 assume !(0 == ~E_3~0); 46215#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46216#L208 assume !(1 == ~m_pc~0); 46559#L208-2 is_master_triggered_~__retres1~0#1 := 0; 46560#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46445#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 46446#L531 assume !(0 != activate_threads_~tmp~1#1); 46397#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46398#L227 assume !(1 == ~t1_pc~0); 46242#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46243#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46229#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 46230#L539 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46259#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46292#L246 assume !(1 == ~t2_pc~0); 46293#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46420#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46421#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46495#L547 assume !(0 != activate_threads_~tmp___1~0#1); 46496#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46305#L265 assume !(1 == ~t3_pc~0); 46306#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46148#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46149#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46570#L555 assume !(0 != activate_threads_~tmp___2~0#1); 46571#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46483#L477 assume !(1 == ~M_E~0); 46484#L477-2 assume !(1 == ~T1_E~0); 46505#L482-1 assume !(1 == ~T2_E~0); 46506#L487-1 assume !(1 == ~T3_E~0); 46525#L492-1 assume !(1 == ~E_M~0); 46526#L497-1 assume !(1 == ~E_1~0); 46404#L502-1 assume !(1 == ~E_2~0); 46405#L507-1 assume !(1 == ~E_3~0); 46368#L512-1 assume { :end_inline_reset_delta_events } true; 46369#L678-2 assume !false; 47910#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47908#L404-1 [2023-11-26 12:05:08,856 INFO L750 eck$LassoCheckResult]: Loop: 47908#L404-1 assume !false; 47906#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 47902#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 47900#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 47898#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 47896#L357 assume 0 != eval_~tmp~0#1; 47893#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 47883#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 47879#L365-2 havoc eval_~tmp_ndt_1~0#1; 47874#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 47810#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 47859#L379-2 havoc eval_~tmp_ndt_2~0#1; 47854#L376-1 assume !(0 == ~t2_st~0); 47855#L390-1 assume !(0 == ~t3_st~0); 47908#L404-1 [2023-11-26 12:05:08,857 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:08,857 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2023-11-26 12:05:08,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:08,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749233153] [2023-11-26 12:05:08,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:08,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:08,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:08,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:08,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:08,884 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749233153] [2023-11-26 12:05:08,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [749233153] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:08,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:08,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:08,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944353719] [2023-11-26 12:05:08,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:08,886 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 12:05:08,886 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:08,886 INFO L85 PathProgramCache]: Analyzing trace with hash 6018452, now seen corresponding path program 1 times [2023-11-26 12:05:08,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:08,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040527063] [2023-11-26 12:05:08,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:08,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:08,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:08,891 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:08,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:08,895 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:08,970 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:08,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:08,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:08,971 INFO L87 Difference]: Start difference. First operand 4755 states and 6498 transitions. cyclomatic complexity: 1749 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:09,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:09,001 INFO L93 Difference]: Finished difference Result 4706 states and 6431 transitions. [2023-11-26 12:05:09,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4706 states and 6431 transitions. [2023-11-26 12:05:09,027 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4615 [2023-11-26 12:05:09,045 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4706 states to 4706 states and 6431 transitions. [2023-11-26 12:05:09,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4706 [2023-11-26 12:05:09,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4706 [2023-11-26 12:05:09,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4706 states and 6431 transitions. [2023-11-26 12:05:09,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:09,059 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4706 states and 6431 transitions. [2023-11-26 12:05:09,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4706 states and 6431 transitions. [2023-11-26 12:05:09,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4706 to 4706. [2023-11-26 12:05:09,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4706 states, 4706 states have (on average 1.3665533361665958) internal successors, (6431), 4705 states have internal predecessors, (6431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:09,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4706 states to 4706 states and 6431 transitions. [2023-11-26 12:05:09,240 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4706 states and 6431 transitions. [2023-11-26 12:05:09,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:09,241 INFO L428 stractBuchiCegarLoop]: Abstraction has 4706 states and 6431 transitions. [2023-11-26 12:05:09,242 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 12:05:09,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4706 states and 6431 transitions. [2023-11-26 12:05:09,264 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4615 [2023-11-26 12:05:09,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:09,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:09,266 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:09,266 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:09,266 INFO L748 eck$LassoCheckResult]: Stem: 55927#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 55928#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 55943#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55940#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55821#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 55822#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55930#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55913#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55914#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55921#L429 assume !(0 == ~M_E~0); 55721#L429-2 assume !(0 == ~T1_E~0); 55722#L434-1 assume !(0 == ~T2_E~0); 55865#L439-1 assume !(0 == ~T3_E~0); 55893#L444-1 assume !(0 == ~E_M~0); 55894#L449-1 assume !(0 == ~E_1~0); 55724#L454-1 assume !(0 == ~E_2~0); 55725#L459-1 assume !(0 == ~E_3~0); 55680#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55681#L208 assume !(1 == ~m_pc~0); 55984#L208-2 is_master_triggered_~__retres1~0#1 := 0; 55985#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55896#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 55709#L531 assume !(0 != activate_threads_~tmp~1#1); 55710#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55831#L227 assume !(1 == ~t1_pc~0); 55707#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55708#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55694#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 55695#L539 assume !(0 != activate_threads_~tmp___0~0#1); 55723#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55755#L246 assume !(1 == ~t2_pc~0); 55756#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55869#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55870#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55935#L547 assume !(0 != activate_threads_~tmp___1~0#1); 55936#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55768#L265 assume !(1 == ~t3_pc~0); 55644#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55615#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55616#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55645#L555 assume !(0 != activate_threads_~tmp___2~0#1); 55735#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55736#L477 assume !(1 == ~M_E~0); 55926#L477-2 assume !(1 == ~T1_E~0); 55944#L482-1 assume !(1 == ~T2_E~0); 55888#L487-1 assume !(1 == ~T3_E~0); 55889#L492-1 assume !(1 == ~E_M~0); 55687#L497-1 assume !(1 == ~E_1~0); 55688#L502-1 assume !(1 == ~E_2~0); 55671#L507-1 assume !(1 == ~E_3~0); 55672#L512-1 assume { :end_inline_reset_delta_events } true; 55829#L678-2 assume !false; 57419#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57417#L404-1 [2023-11-26 12:05:09,267 INFO L750 eck$LassoCheckResult]: Loop: 57417#L404-1 assume !false; 57415#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 57412#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 57410#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 57408#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 57406#L357 assume 0 != eval_~tmp~0#1; 57402#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 57399#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 57397#L365-2 havoc eval_~tmp_ndt_1~0#1; 57395#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 57328#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 57393#L379-2 havoc eval_~tmp_ndt_2~0#1; 57391#L376-1 assume !(0 == ~t2_st~0); 57392#L390-1 assume !(0 == ~t3_st~0); 57417#L404-1 [2023-11-26 12:05:09,267 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:09,268 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2023-11-26 12:05:09,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:09,268 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336820174] [2023-11-26 12:05:09,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:09,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:09,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:09,281 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:09,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:09,298 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:09,299 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:09,299 INFO L85 PathProgramCache]: Analyzing trace with hash 6018452, now seen corresponding path program 2 times [2023-11-26 12:05:09,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:09,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719197626] [2023-11-26 12:05:09,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:09,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:09,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:09,305 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:09,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:09,310 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:09,311 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:09,311 INFO L85 PathProgramCache]: Analyzing trace with hash -1934834854, now seen corresponding path program 1 times [2023-11-26 12:05:09,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:09,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411352234] [2023-11-26 12:05:09,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:09,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:09,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:09,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:09,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:09,362 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411352234] [2023-11-26 12:05:09,363 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411352234] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:09,363 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:09,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 12:05:09,363 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755175918] [2023-11-26 12:05:09,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:09,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:09,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:09,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:09,447 INFO L87 Difference]: Start difference. First operand 4706 states and 6431 transitions. cyclomatic complexity: 1731 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:09,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:09,532 INFO L93 Difference]: Finished difference Result 5299 states and 7206 transitions. [2023-11-26 12:05:09,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5299 states and 7206 transitions. [2023-11-26 12:05:09,559 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5216 [2023-11-26 12:05:09,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5299 states to 5299 states and 7206 transitions. [2023-11-26 12:05:09,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5299 [2023-11-26 12:05:09,587 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5299 [2023-11-26 12:05:09,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5299 states and 7206 transitions. [2023-11-26 12:05:09,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:09,595 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5299 states and 7206 transitions. [2023-11-26 12:05:09,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5299 states and 7206 transitions. [2023-11-26 12:05:09,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5299 to 5145. [2023-11-26 12:05:09,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5145 states, 5145 states have (on average 1.3624878522837707) internal successors, (7010), 5144 states have internal predecessors, (7010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:09,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5145 states to 5145 states and 7010 transitions. [2023-11-26 12:05:09,691 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5145 states and 7010 transitions. [2023-11-26 12:05:09,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:09,692 INFO L428 stractBuchiCegarLoop]: Abstraction has 5145 states and 7010 transitions. [2023-11-26 12:05:09,692 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 12:05:09,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5145 states and 7010 transitions. [2023-11-26 12:05:09,711 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5062 [2023-11-26 12:05:09,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:09,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:09,712 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:09,712 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:09,713 INFO L748 eck$LassoCheckResult]: Stem: 65952#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 65953#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 65970#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65967#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65842#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 65843#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65955#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65936#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65937#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65946#L429 assume !(0 == ~M_E~0); 65734#L429-2 assume !(0 == ~T1_E~0); 65735#L434-1 assume !(0 == ~T2_E~0); 65885#L439-1 assume !(0 == ~T3_E~0); 65914#L444-1 assume !(0 == ~E_M~0); 65915#L449-1 assume !(0 == ~E_1~0); 65737#L454-1 assume !(0 == ~E_2~0); 65738#L459-1 assume !(0 == ~E_3~0); 65692#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65693#L208 assume !(1 == ~m_pc~0); 66021#L208-2 is_master_triggered_~__retres1~0#1 := 0; 66022#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65917#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 65722#L531 assume !(0 != activate_threads_~tmp~1#1); 65723#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65852#L227 assume !(1 == ~t1_pc~0); 65720#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65721#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65706#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 65707#L539 assume !(0 != activate_threads_~tmp___0~0#1); 65736#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65770#L246 assume !(1 == ~t2_pc~0); 65771#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 65890#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65891#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 65959#L547 assume !(0 != activate_threads_~tmp___1~0#1); 65960#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65783#L265 assume !(1 == ~t3_pc~0); 65656#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 65628#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65629#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65657#L555 assume !(0 != activate_threads_~tmp___2~0#1); 65748#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65749#L477 assume !(1 == ~M_E~0); 65951#L477-2 assume !(1 == ~T1_E~0); 65971#L482-1 assume !(1 == ~T2_E~0); 65910#L487-1 assume !(1 == ~T3_E~0); 65911#L492-1 assume !(1 == ~E_M~0); 65699#L497-1 assume !(1 == ~E_1~0); 65700#L502-1 assume !(1 == ~E_2~0); 65683#L507-1 assume !(1 == ~E_3~0); 65684#L512-1 assume { :end_inline_reset_delta_events } true; 65849#L678-2 assume !false; 67789#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67784#L404-1 [2023-11-26 12:05:09,713 INFO L750 eck$LassoCheckResult]: Loop: 67784#L404-1 assume !false; 67779#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 67772#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 67767#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 67762#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 67754#L357 assume 0 != eval_~tmp~0#1; 67749#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 67744#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 67739#L365-2 havoc eval_~tmp_ndt_1~0#1; 67733#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 67521#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 67728#L379-2 havoc eval_~tmp_ndt_2~0#1; 67852#L376-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 67849#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 67801#L393-2 havoc eval_~tmp_ndt_3~0#1; 67791#L390-1 assume !(0 == ~t3_st~0); 67784#L404-1 [2023-11-26 12:05:09,714 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:09,714 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2023-11-26 12:05:09,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:09,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019064478] [2023-11-26 12:05:09,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:09,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:09,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:09,725 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:09,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:09,741 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:09,741 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:09,741 INFO L85 PathProgramCache]: Analyzing trace with hash 1484720438, now seen corresponding path program 1 times [2023-11-26 12:05:09,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:09,742 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646338151] [2023-11-26 12:05:09,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:09,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:09,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:09,747 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:09,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:09,751 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:09,752 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:09,752 INFO L85 PathProgramCache]: Analyzing trace with hash 340499836, now seen corresponding path program 1 times [2023-11-26 12:05:09,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:09,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244758843] [2023-11-26 12:05:09,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:09,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:09,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 12:05:09,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 12:05:09,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 12:05:09,795 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [244758843] [2023-11-26 12:05:09,796 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [244758843] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 12:05:09,796 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 12:05:09,796 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 12:05:09,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224727931] [2023-11-26 12:05:09,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 12:05:09,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 12:05:09,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 12:05:09,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 12:05:09,998 INFO L87 Difference]: Start difference. First operand 5145 states and 7010 transitions. cyclomatic complexity: 1871 Second operand has 3 states, 2 states have (on average 34.5) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:10,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 12:05:10,096 INFO L93 Difference]: Finished difference Result 8657 states and 11688 transitions. [2023-11-26 12:05:10,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8657 states and 11688 transitions. [2023-11-26 12:05:10,137 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8546 [2023-11-26 12:05:10,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8657 states to 8657 states and 11688 transitions. [2023-11-26 12:05:10,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8657 [2023-11-26 12:05:10,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8657 [2023-11-26 12:05:10,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8657 states and 11688 transitions. [2023-11-26 12:05:10,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 12:05:10,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8657 states and 11688 transitions. [2023-11-26 12:05:10,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8657 states and 11688 transitions. [2023-11-26 12:05:10,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8657 to 8513. [2023-11-26 12:05:10,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8513 states, 8513 states have (on average 1.35604369787384) internal successors, (11544), 8512 states have internal predecessors, (11544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 12:05:10,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8513 states to 8513 states and 11544 transitions. [2023-11-26 12:05:10,356 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8513 states and 11544 transitions. [2023-11-26 12:05:10,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 12:05:10,357 INFO L428 stractBuchiCegarLoop]: Abstraction has 8513 states and 11544 transitions. [2023-11-26 12:05:10,357 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 12:05:10,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8513 states and 11544 transitions. [2023-11-26 12:05:10,426 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8402 [2023-11-26 12:05:10,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 12:05:10,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 12:05:10,427 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:10,428 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 12:05:10,428 INFO L748 eck$LassoCheckResult]: Stem: 79759#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 79760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 79777#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 79774#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79644#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 79645#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79762#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79745#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79746#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 79754#L429 assume !(0 == ~M_E~0); 79541#L429-2 assume !(0 == ~T1_E~0); 79542#L434-1 assume !(0 == ~T2_E~0); 79691#L439-1 assume !(0 == ~T3_E~0); 79724#L444-1 assume !(0 == ~E_M~0); 79725#L449-1 assume !(0 == ~E_1~0); 79544#L454-1 assume !(0 == ~E_2~0); 79545#L459-1 assume !(0 == ~E_3~0); 79501#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79502#L208 assume !(1 == ~m_pc~0); 79824#L208-2 is_master_triggered_~__retres1~0#1 := 0; 79825#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79727#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 79529#L531 assume !(0 != activate_threads_~tmp~1#1); 79530#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79654#L227 assume !(1 == ~t1_pc~0); 79527#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 79528#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79514#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 79515#L539 assume !(0 != activate_threads_~tmp___0~0#1); 79543#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79575#L246 assume !(1 == ~t2_pc~0); 79576#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 79698#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79699#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 79768#L547 assume !(0 != activate_threads_~tmp___1~0#1); 79769#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79587#L265 assume !(1 == ~t3_pc~0); 79465#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 79438#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79439#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 79466#L555 assume !(0 != activate_threads_~tmp___2~0#1); 79555#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79556#L477 assume !(1 == ~M_E~0); 79758#L477-2 assume !(1 == ~T1_E~0); 79778#L482-1 assume !(1 == ~T2_E~0); 79719#L487-1 assume !(1 == ~T3_E~0); 79720#L492-1 assume !(1 == ~E_M~0); 79507#L497-1 assume !(1 == ~E_1~0); 79508#L502-1 assume !(1 == ~E_2~0); 79492#L507-1 assume !(1 == ~E_3~0); 79493#L512-1 assume { :end_inline_reset_delta_events } true; 79651#L678-2 assume !false; 84621#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84619#L404-1 [2023-11-26 12:05:10,428 INFO L750 eck$LassoCheckResult]: Loop: 84619#L404-1 assume !false; 84617#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 84614#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 84612#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 84610#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 84608#L357 assume 0 != eval_~tmp~0#1; 84605#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 84602#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 84600#L365-2 havoc eval_~tmp_ndt_1~0#1; 84598#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 84542#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 84596#L379-2 havoc eval_~tmp_ndt_2~0#1; 84633#L376-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 84631#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 84629#L393-2 havoc eval_~tmp_ndt_3~0#1; 84627#L390-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 82758#L407 assume !(0 != eval_~tmp_ndt_4~0#1); 84622#L407-2 havoc eval_~tmp_ndt_4~0#1; 84619#L404-1 [2023-11-26 12:05:10,429 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:10,429 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2023-11-26 12:05:10,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:10,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113555908] [2023-11-26 12:05:10,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:10,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:10,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:10,442 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:10,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:10,457 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:10,459 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:10,459 INFO L85 PathProgramCache]: Analyzing trace with hash 887098260, now seen corresponding path program 1 times [2023-11-26 12:05:10,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:10,460 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117420756] [2023-11-26 12:05:10,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:10,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:10,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:10,465 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:10,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:10,470 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:10,471 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 12:05:10,471 INFO L85 PathProgramCache]: Analyzing trace with hash 802727514, now seen corresponding path program 1 times [2023-11-26 12:05:10,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 12:05:10,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168381851] [2023-11-26 12:05:10,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 12:05:10,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 12:05:10,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:10,484 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:10,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:10,507 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 12:05:11,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:11,929 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 12:05:11,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 12:05:12,144 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.11 12:05:12 BoogieIcfgContainer [2023-11-26 12:05:12,144 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-26 12:05:12,144 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-26 12:05:12,145 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-26 12:05:12,145 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-26 12:05:12,145 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:05:03" (3/4) ... [2023-11-26 12:05:12,148 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-26 12:05:12,249 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/witness.graphml [2023-11-26 12:05:12,249 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-26 12:05:12,250 INFO L158 Benchmark]: Toolchain (without parser) took 11014.71ms. Allocated memory was 136.3MB in the beginning and 243.3MB in the end (delta: 107.0MB). Free memory was 104.7MB in the beginning and 88.1MB in the end (delta: 16.6MB). Peak memory consumption was 126.4MB. Max. memory is 16.1GB. [2023-11-26 12:05:12,250 INFO L158 Benchmark]: CDTParser took 0.36ms. Allocated memory is still 136.3MB. Free memory is still 95.8MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 12:05:12,251 INFO L158 Benchmark]: CACSL2BoogieTranslator took 461.58ms. Allocated memory is still 136.3MB. Free memory was 104.5MB in the beginning and 89.9MB in the end (delta: 14.6MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-26 12:05:12,251 INFO L158 Benchmark]: Boogie Procedure Inliner took 116.07ms. Allocated memory is still 136.3MB. Free memory was 89.9MB in the beginning and 86.1MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 12:05:12,252 INFO L158 Benchmark]: Boogie Preprocessor took 113.35ms. Allocated memory is still 136.3MB. Free memory was 86.1MB in the beginning and 81.7MB in the end (delta: 4.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 12:05:12,252 INFO L158 Benchmark]: RCFGBuilder took 1253.67ms. Allocated memory was 136.3MB in the beginning and 167.8MB in the end (delta: 31.5MB). Free memory was 81.7MB in the beginning and 114.3MB in the end (delta: -32.6MB). Peak memory consumption was 22.8MB. Max. memory is 16.1GB. [2023-11-26 12:05:12,253 INFO L158 Benchmark]: BuchiAutomizer took 8958.37ms. Allocated memory was 167.8MB in the beginning and 243.3MB in the end (delta: 75.5MB). Free memory was 114.3MB in the beginning and 95.4MB in the end (delta: 18.9MB). Peak memory consumption was 95.2MB. Max. memory is 16.1GB. [2023-11-26 12:05:12,253 INFO L158 Benchmark]: Witness Printer took 104.70ms. Allocated memory is still 243.3MB. Free memory was 95.4MB in the beginning and 88.1MB in the end (delta: 7.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-26 12:05:12,256 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.36ms. Allocated memory is still 136.3MB. Free memory is still 95.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 461.58ms. Allocated memory is still 136.3MB. Free memory was 104.5MB in the beginning and 89.9MB in the end (delta: 14.6MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 116.07ms. Allocated memory is still 136.3MB. Free memory was 89.9MB in the beginning and 86.1MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 113.35ms. Allocated memory is still 136.3MB. Free memory was 86.1MB in the beginning and 81.7MB in the end (delta: 4.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1253.67ms. Allocated memory was 136.3MB in the beginning and 167.8MB in the end (delta: 31.5MB). Free memory was 81.7MB in the beginning and 114.3MB in the end (delta: -32.6MB). Peak memory consumption was 22.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 8958.37ms. Allocated memory was 167.8MB in the beginning and 243.3MB in the end (delta: 75.5MB). Free memory was 114.3MB in the beginning and 95.4MB in the end (delta: 18.9MB). Peak memory consumption was 95.2MB. Max. memory is 16.1GB. * Witness Printer took 104.70ms. Allocated memory is still 243.3MB. Free memory was 95.4MB in the beginning and 88.1MB in the end (delta: 7.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 8513 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.7s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 4.6s. Construction of modules took 0.5s. Büchi inclusion checks took 3.0s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 1.2s AutomataMinimizationTime, 17 MinimizatonAttempts, 4833 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.6s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 8140 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 8140 mSDsluCounter, 15042 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6667 mSDsCounter, 143 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 348 IncrementalHoareTripleChecker+Invalid, 491 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 143 mSolverCounterUnsat, 8375 mSDtfsCounter, 348 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 352]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L434] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L439] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L444] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L449] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L454] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L459] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L464] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L208] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L218] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L227] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L237] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L246] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L256] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L265] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L275] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L482] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L487] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L492] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L497] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L502] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L507] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L512] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L675] RET reset_delta_events() [L678] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L362-L373] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L376-L387] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L390-L401] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L404-L415] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 352]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L434] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L439] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L444] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L449] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L454] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L459] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L464] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L208] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L218] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L227] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L237] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L246] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L256] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L265] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L275] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L482] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L487] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L492] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L497] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L502] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L507] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L512] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L675] RET reset_delta_events() [L678] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L362-L373] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L376-L387] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L390-L401] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L404-L415] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-26 12:05:12,381 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c4197b7-5e63-4007-ac55-2d904cb6ebb1/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)